1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * pinmux driver shared headfile for CSR SiRFsoc
4 *
5 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6 */
7
8#ifndef __PINMUX_SIRF_H__
9#define __PINMUX_SIRF_H__
10
11#define SIRFSOC_NUM_PADS		622
12#define SIRFSOC_RSC_USB_UART_SHARE	0
13#define SIRFSOC_RSC_PIN_MUX		0x4
14
15#define SIRFSOC_GPIO_PAD_EN(g)		((g)*0x100 + 0x84)
16#define SIRFSOC_GPIO_PAD_EN_CLR(g)	((g)*0x100 + 0x90)
17#define SIRFSOC_GPIO_CTRL(g, i)			((g)*0x100 + (i)*4)
18#define SIRFSOC_GPIO_DSP_EN0			(0x80)
19#define SIRFSOC_GPIO_INT_STATUS(g)		((g)*0x100 + 0x8C)
20
21#define SIRFSOC_GPIO_CTL_INTR_LOW_MASK		0x1
22#define SIRFSOC_GPIO_CTL_INTR_HIGH_MASK		0x2
23#define SIRFSOC_GPIO_CTL_INTR_TYPE_MASK		0x4
24#define SIRFSOC_GPIO_CTL_INTR_EN_MASK		0x8
25#define SIRFSOC_GPIO_CTL_INTR_STS_MASK		0x10
26#define SIRFSOC_GPIO_CTL_OUT_EN_MASK		0x20
27#define SIRFSOC_GPIO_CTL_DATAOUT_MASK		0x40
28#define SIRFSOC_GPIO_CTL_DATAIN_MASK		0x80
29#define SIRFSOC_GPIO_CTL_PULL_MASK		0x100
30#define SIRFSOC_GPIO_CTL_PULL_HIGH		0x200
31#define SIRFSOC_GPIO_CTL_DSP_INT		0x400
32
33#define SIRFSOC_GPIO_NO_OF_BANKS        5
34#define SIRFSOC_GPIO_BANK_SIZE          32
35#define SIRFSOC_GPIO_NUM(bank, index)	(((bank)*(32)) + (index))
36
37/**
38 * @dev: a pointer back to containing device
39 * @virtbase: the offset to the controller in virtual memory
40 */
41struct sirfsoc_pmx {
42	struct device *dev;
43	struct pinctrl_dev *pmx;
44	void __iomem *gpio_virtbase;
45	void __iomem *rsc_virtbase;
46	u32 gpio_regs[SIRFSOC_GPIO_NO_OF_BANKS][SIRFSOC_GPIO_BANK_SIZE];
47	u32 ints_regs[SIRFSOC_GPIO_NO_OF_BANKS];
48	u32 paden_regs[SIRFSOC_GPIO_NO_OF_BANKS];
49	u32 dspen_regs;
50	u32 rsc_regs[3];
51};
52
53/* SIRFSOC_GPIO_PAD_EN set */
54struct sirfsoc_muxmask {
55	unsigned long group;
56	unsigned long mask;
57};
58
59struct sirfsoc_padmux {
60	unsigned long muxmask_counts;
61	const struct sirfsoc_muxmask *muxmask;
62	/* RSC_PIN_MUX set */
63	unsigned long ctrlreg;
64	unsigned long funcmask;
65	unsigned long funcval;
66};
67
68 /**
69 * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
70 * @name: the name of this specific pin group
71 * @pins: an array of discrete physical pins used in this group, taken
72 *	from the driver-local pin enumeration space
73 * @num_pins: the number of pins in this group array, i.e. the number of
74 *	elements in .pins so we can iterate over that array
75 */
76struct sirfsoc_pin_group {
77	const char *name;
78	const unsigned int *pins;
79	const unsigned num_pins;
80};
81
82#define SIRFSOC_PIN_GROUP(n, p)  \
83	{			\
84		.name = n,	\
85		.pins = p,	\
86		.num_pins = ARRAY_SIZE(p),	\
87	}
88
89struct sirfsoc_pmx_func {
90	const char *name;
91	const char * const *groups;
92	const unsigned num_groups;
93	const struct sirfsoc_padmux *padmux;
94};
95
96#define SIRFSOC_PMX_FUNCTION(n, g, m)		\
97	{					\
98		.name = n,			\
99		.groups = g,			\
100		.num_groups = ARRAY_SIZE(g),	\
101		.padmux = &m,			\
102	}
103
104struct sirfsoc_pinctrl_data {
105	struct pinctrl_pin_desc *pads;
106	int pads_cnt;
107	struct sirfsoc_pin_group *grps;
108	int grps_cnt;
109	struct sirfsoc_pmx_func *funcs;
110	int funcs_cnt;
111};
112
113extern struct sirfsoc_pinctrl_data prima2_pinctrl_data;
114extern struct sirfsoc_pinctrl_data atlas6_pinctrl_data;
115
116#endif
117