1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * pinctrl pads, groups, functions for CSR SiRFatlasVI 4 * 5 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group 6 * company. 7 */ 8 9#include <linux/pinctrl/pinctrl.h> 10#include <linux/bitops.h> 11 12#include "pinctrl-sirf.h" 13 14/* 15 * pad list for the pinmux subsystem 16 * refer to atlasVI_io_table_v0.93.xls 17 */ 18static const struct pinctrl_pin_desc sirfsoc_pads[] = { 19 PINCTRL_PIN(0, "gpio0-0"), 20 PINCTRL_PIN(1, "gpio0-1"), 21 PINCTRL_PIN(2, "gpio0-2"), 22 PINCTRL_PIN(3, "gpio0-3"), 23 PINCTRL_PIN(4, "pwm0"), 24 PINCTRL_PIN(5, "pwm1"), 25 PINCTRL_PIN(6, "pwm2"), 26 PINCTRL_PIN(7, "pwm3"), 27 PINCTRL_PIN(8, "warm_rst_b"), 28 PINCTRL_PIN(9, "odo_0"), 29 PINCTRL_PIN(10, "odo_1"), 30 PINCTRL_PIN(11, "dr_dir"), 31 PINCTRL_PIN(12, "rts_0"), 32 PINCTRL_PIN(13, "scl_1"), 33 PINCTRL_PIN(14, "ntrst"), 34 PINCTRL_PIN(15, "sda_1"), 35 PINCTRL_PIN(16, "x_ldd[16]"), 36 PINCTRL_PIN(17, "x_ldd[17]"), 37 PINCTRL_PIN(18, "x_ldd[18]"), 38 PINCTRL_PIN(19, "x_ldd[19]"), 39 PINCTRL_PIN(20, "x_ldd[20]"), 40 PINCTRL_PIN(21, "x_ldd[21]"), 41 PINCTRL_PIN(22, "x_ldd[22]"), 42 PINCTRL_PIN(23, "x_ldd[23]"), 43 PINCTRL_PIN(24, "gps_sgn"), 44 PINCTRL_PIN(25, "gps_mag"), 45 PINCTRL_PIN(26, "gps_clk"), 46 PINCTRL_PIN(27, "sd_cd_b_2"), 47 PINCTRL_PIN(28, "sd_vcc_on_2"), 48 PINCTRL_PIN(29, "sd_wp_b_2"), 49 PINCTRL_PIN(30, "sd_clk_3"), 50 PINCTRL_PIN(31, "sd_cmd_3"), 51 52 PINCTRL_PIN(32, "x_sd_dat_3[0]"), 53 PINCTRL_PIN(33, "x_sd_dat_3[1]"), 54 PINCTRL_PIN(34, "x_sd_dat_3[2]"), 55 PINCTRL_PIN(35, "x_sd_dat_3[3]"), 56 PINCTRL_PIN(36, "usb_clk"), 57 PINCTRL_PIN(37, "usb_dir"), 58 PINCTRL_PIN(38, "usb_nxt"), 59 PINCTRL_PIN(39, "usb_stp"), 60 PINCTRL_PIN(40, "usb_dat[7]"), 61 PINCTRL_PIN(41, "usb_dat[6]"), 62 PINCTRL_PIN(42, "x_cko_1"), 63 PINCTRL_PIN(43, "spi_clk_1"), 64 PINCTRL_PIN(44, "spi_dout_1"), 65 PINCTRL_PIN(45, "spi_din_1"), 66 PINCTRL_PIN(46, "spi_en_1"), 67 PINCTRL_PIN(47, "x_txd_1"), 68 PINCTRL_PIN(48, "x_txd_2"), 69 PINCTRL_PIN(49, "x_rxd_1"), 70 PINCTRL_PIN(50, "x_rxd_2"), 71 PINCTRL_PIN(51, "x_usclk_0"), 72 PINCTRL_PIN(52, "x_utxd_0"), 73 PINCTRL_PIN(53, "x_urxd_0"), 74 PINCTRL_PIN(54, "x_utfs_0"), 75 PINCTRL_PIN(55, "x_urfs_0"), 76 PINCTRL_PIN(56, "usb_dat5"), 77 PINCTRL_PIN(57, "usb_dat4"), 78 PINCTRL_PIN(58, "usb_dat3"), 79 PINCTRL_PIN(59, "usb_dat2"), 80 PINCTRL_PIN(60, "usb_dat1"), 81 PINCTRL_PIN(61, "usb_dat0"), 82 PINCTRL_PIN(62, "x_ldd[14]"), 83 PINCTRL_PIN(63, "x_ldd[15]"), 84 85 PINCTRL_PIN(64, "x_gps_gpio"), 86 PINCTRL_PIN(65, "x_ldd[13]"), 87 PINCTRL_PIN(66, "x_df_we_b"), 88 PINCTRL_PIN(67, "x_df_re_b"), 89 PINCTRL_PIN(68, "x_txd_0"), 90 PINCTRL_PIN(69, "x_rxd_0"), 91 PINCTRL_PIN(70, "x_l_lck"), 92 PINCTRL_PIN(71, "x_l_fck"), 93 PINCTRL_PIN(72, "x_l_de"), 94 PINCTRL_PIN(73, "x_ldd[0]"), 95 PINCTRL_PIN(74, "x_ldd[1]"), 96 PINCTRL_PIN(75, "x_ldd[2]"), 97 PINCTRL_PIN(76, "x_ldd[3]"), 98 PINCTRL_PIN(77, "x_ldd[4]"), 99 PINCTRL_PIN(78, "x_cko_0"), 100 PINCTRL_PIN(79, "x_ldd[5]"), 101 PINCTRL_PIN(80, "x_ldd[6]"), 102 PINCTRL_PIN(81, "x_ldd[7]"), 103 PINCTRL_PIN(82, "x_ldd[8]"), 104 PINCTRL_PIN(83, "x_ldd[9]"), 105 PINCTRL_PIN(84, "x_ldd[10]"), 106 PINCTRL_PIN(85, "x_ldd[11]"), 107 PINCTRL_PIN(86, "x_ldd[12]"), 108 PINCTRL_PIN(87, "x_vip_vsync"), 109 PINCTRL_PIN(88, "x_vip_hsync"), 110 PINCTRL_PIN(89, "x_vip_pxclk"), 111 PINCTRL_PIN(90, "x_sda_0"), 112 PINCTRL_PIN(91, "x_scl_0"), 113 PINCTRL_PIN(92, "x_df_ry_by"), 114 PINCTRL_PIN(93, "x_df_cs_b[1]"), 115 PINCTRL_PIN(94, "x_df_cs_b[0]"), 116 PINCTRL_PIN(95, "x_l_pclk"), 117 118 PINCTRL_PIN(96, "x_df_dqs"), 119 PINCTRL_PIN(97, "x_df_wp_b"), 120 PINCTRL_PIN(98, "ac97_sync"), 121 PINCTRL_PIN(99, "ac97_bit_clk "), 122 PINCTRL_PIN(100, "ac97_dout"), 123 PINCTRL_PIN(101, "ac97_din"), 124 PINCTRL_PIN(102, "x_rtc_io"), 125 126 PINCTRL_PIN(103, "x_usb1_dp"), 127 PINCTRL_PIN(104, "x_usb1_dn"), 128}; 129 130static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = { 131 { 132 .group = 1, 133 .mask = BIT(30) | BIT(31), 134 }, { 135 .group = 2, 136 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | 137 BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) | 138 BIT(16) | BIT(17) | BIT(18) | BIT(19) | 139 BIT(20) | BIT(21) | BIT(22) | BIT(31), 140 }, 141}; 142 143static const struct sirfsoc_padmux lcd_16bits_padmux = { 144 .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask), 145 .muxmask = lcd_16bits_sirfsoc_muxmask, 146 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 147 .funcmask = BIT(4), 148 .funcval = 0, 149}; 150 151static const unsigned lcd_16bits_pins[] = { 62, 63, 65, 70, 71, 72, 73, 74, 75, 152 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 }; 153 154static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = { 155 { 156 .group = 2, 157 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | 158 BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) | 159 BIT(16) | BIT(17) | BIT(18) | BIT(19) | 160 BIT(20) | BIT(21) | BIT(22) | BIT(31), 161 }, { 162 .group = 1, 163 .mask = BIT(30) | BIT(31), 164 }, { 165 .group = 0, 166 .mask = BIT(16) | BIT(17), 167 }, 168}; 169 170static const struct sirfsoc_padmux lcd_18bits_padmux = { 171 .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask), 172 .muxmask = lcd_18bits_muxmask, 173 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 174 .funcmask = BIT(4) | BIT(15), 175 .funcval = 0, 176}; 177 178static const unsigned lcd_18bits_pins[] = { 16, 17, 62, 63, 65, 70, 71, 72, 73, 179 74, 75, 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 }; 180 181static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = { 182 { 183 .group = 2, 184 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | 185 BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) | 186 BIT(16) | BIT(17) | BIT(18) | BIT(19) | 187 BIT(20) | BIT(21) | BIT(22) | BIT(31), 188 }, { 189 .group = 1, 190 .mask = BIT(30) | BIT(31), 191 }, { 192 .group = 0, 193 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | 194 BIT(21) | BIT(22) | BIT(23), 195 }, 196}; 197 198static const struct sirfsoc_padmux lcd_24bits_padmux = { 199 .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask), 200 .muxmask = lcd_24bits_muxmask, 201 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 202 .funcmask = BIT(4) | BIT(15), 203 .funcval = 0, 204}; 205 206static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 62, 207 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, 84, 208 85, 86, 95}; 209 210static const struct sirfsoc_muxmask lcdrom_muxmask[] = { 211 { 212 .group = 2, 213 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | 214 BIT(11) | BIT(12) | BIT(13) | BIT(15) | BIT(16) | 215 BIT(17) | BIT(18) | BIT(19) | 216 BIT(20) | BIT(21) | BIT(22) | BIT(31), 217 }, { 218 .group = 1, 219 .mask = BIT(30) | BIT(31), 220 }, { 221 .group = 0, 222 .mask = BIT(8), 223 }, 224}; 225 226static const struct sirfsoc_padmux lcdrom_padmux = { 227 .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask), 228 .muxmask = lcdrom_muxmask, 229 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 230 .funcmask = BIT(4), 231 .funcval = BIT(4), 232}; 233 234static const unsigned lcdrom_pins[] = { 8, 62, 63, 65, 70, 71, 72, 73, 74, 75, 235 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95}; 236 237static const struct sirfsoc_muxmask uart0_muxmask[] = { 238 { 239 .group = 0, 240 .mask = BIT(12), 241 }, { 242 .group = 1, 243 .mask = BIT(23), 244 }, { 245 .group = 2, 246 .mask = BIT(4) | BIT(5), 247 }, 248}; 249 250static const struct sirfsoc_padmux uart0_padmux = { 251 .muxmask_counts = ARRAY_SIZE(uart0_muxmask), 252 .muxmask = uart0_muxmask, 253 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 254 .funcmask = BIT(9), 255 .funcval = BIT(9), 256}; 257 258static const unsigned uart0_pins[] = { 12, 55, 68, 69 }; 259 260static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = { 261 { 262 .group = 2, 263 .mask = BIT(4) | BIT(5), 264 }, 265}; 266 267static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = { 268 .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask), 269 .muxmask = uart0_nostreamctrl_muxmask, 270}; 271 272static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 }; 273 274static const struct sirfsoc_muxmask uart1_muxmask[] = { 275 { 276 .group = 1, 277 .mask = BIT(15) | BIT(17), 278 }, 279}; 280 281static const struct sirfsoc_padmux uart1_padmux = { 282 .muxmask_counts = ARRAY_SIZE(uart1_muxmask), 283 .muxmask = uart1_muxmask, 284}; 285 286static const unsigned uart1_pins[] = { 47, 49 }; 287 288static const struct sirfsoc_muxmask uart2_muxmask[] = { 289 { 290 .group = 0, 291 .mask = BIT(10) | BIT(14), 292 }, { 293 .group = 1, 294 .mask = BIT(16) | BIT(18), 295 }, 296}; 297 298static const struct sirfsoc_padmux uart2_padmux = { 299 .muxmask_counts = ARRAY_SIZE(uart2_muxmask), 300 .muxmask = uart2_muxmask, 301 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 302 .funcmask = BIT(10), 303 .funcval = BIT(10), 304}; 305 306static const unsigned uart2_pins[] = { 10, 14, 48, 50 }; 307 308static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = { 309 { 310 .group = 1, 311 .mask = BIT(16) | BIT(18), 312 }, 313}; 314 315static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = { 316 .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask), 317 .muxmask = uart2_nostreamctrl_muxmask, 318}; 319 320static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 }; 321 322static const struct sirfsoc_muxmask sdmmc3_muxmask[] = { 323 { 324 .group = 0, 325 .mask = BIT(30) | BIT(31), 326 }, { 327 .group = 1, 328 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3), 329 }, 330}; 331 332static const struct sirfsoc_padmux sdmmc3_padmux = { 333 .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask), 334 .muxmask = sdmmc3_muxmask, 335 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 336 .funcmask = BIT(7), 337 .funcval = 0, 338}; 339 340static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 }; 341 342static const struct sirfsoc_muxmask spi0_muxmask[] = { 343 { 344 .group = 0, 345 .mask = BIT(30), 346 }, { 347 .group = 1, 348 .mask = BIT(0) | BIT(2) | BIT(3), 349 }, 350}; 351 352static const struct sirfsoc_padmux spi0_padmux = { 353 .muxmask_counts = ARRAY_SIZE(spi0_muxmask), 354 .muxmask = spi0_muxmask, 355 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 356 .funcmask = BIT(7), 357 .funcval = BIT(7), 358}; 359 360static const unsigned spi0_pins[] = { 30, 32, 34, 35 }; 361 362static const struct sirfsoc_muxmask cko1_muxmask[] = { 363 { 364 .group = 1, 365 .mask = BIT(10), 366 }, 367}; 368 369static const struct sirfsoc_padmux cko1_padmux = { 370 .muxmask_counts = ARRAY_SIZE(cko1_muxmask), 371 .muxmask = cko1_muxmask, 372 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 373 .funcmask = BIT(3), 374 .funcval = 0, 375}; 376 377static const unsigned cko1_pins[] = { 42 }; 378 379static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = { 380 { 381 .group = 1, 382 .mask = BIT(10), 383 }, 384}; 385 386static const struct sirfsoc_padmux i2s_mclk_padmux = { 387 .muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask), 388 .muxmask = i2s_mclk_muxmask, 389 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 390 .funcmask = BIT(3), 391 .funcval = BIT(3), 392}; 393 394static const unsigned i2s_mclk_pins[] = { 42 }; 395 396static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = { 397 { 398 .group = 1, 399 .mask = BIT(19), 400 }, 401}; 402 403static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = { 404 .muxmask_counts = ARRAY_SIZE(i2s_ext_clk_input_muxmask), 405 .muxmask = i2s_ext_clk_input_muxmask, 406 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 407 .funcmask = BIT(2), 408 .funcval = BIT(2), 409}; 410 411static const unsigned i2s_ext_clk_input_pins[] = { 51 }; 412 413static const struct sirfsoc_muxmask i2s_muxmask[] = { 414 { 415 .group = 3, 416 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5), 417 }, 418}; 419 420static const struct sirfsoc_padmux i2s_padmux = { 421 .muxmask_counts = ARRAY_SIZE(i2s_muxmask), 422 .muxmask = i2s_muxmask, 423 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 424}; 425 426static const unsigned i2s_pins[] = { 98, 99, 100, 101 }; 427 428static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = { 429 { 430 .group = 3, 431 .mask = BIT(2) | BIT(3) | BIT(4), 432 }, 433}; 434 435static const struct sirfsoc_padmux i2s_no_din_padmux = { 436 .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask), 437 .muxmask = i2s_no_din_muxmask, 438 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 439}; 440 441static const unsigned i2s_no_din_pins[] = { 98, 99, 100 }; 442 443static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = { 444 { 445 .group = 3, 446 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5), 447 }, 448}; 449 450static const struct sirfsoc_padmux i2s_6chn_padmux = { 451 .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask), 452 .muxmask = i2s_6chn_muxmask, 453 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 454 .funcmask = BIT(1) | BIT(9), 455 .funcval = BIT(1) | BIT(9), 456}; 457 458static const unsigned i2s_6chn_pins[] = { 52, 55, 98, 99, 100, 101 }; 459 460static const struct sirfsoc_muxmask ac97_muxmask[] = { 461 { 462 .group = 3, 463 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5), 464 }, 465}; 466 467static const struct sirfsoc_padmux ac97_padmux = { 468 .muxmask_counts = ARRAY_SIZE(ac97_muxmask), 469 .muxmask = ac97_muxmask, 470}; 471 472static const unsigned ac97_pins[] = { 98, 99, 100, 101 }; 473 474static const struct sirfsoc_muxmask spi1_muxmask[] = { 475 { 476 .group = 1, 477 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), 478 }, 479}; 480 481static const struct sirfsoc_padmux spi1_padmux = { 482 .muxmask_counts = ARRAY_SIZE(spi1_muxmask), 483 .muxmask = spi1_muxmask, 484 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 485 .funcmask = BIT(16), 486 .funcval = 0, 487}; 488 489static const unsigned spi1_pins[] = { 43, 44, 45, 46 }; 490 491static const struct sirfsoc_muxmask sdmmc1_muxmask[] = { 492 { 493 .group = 2, 494 .mask = BIT(2) | BIT(3), 495 }, 496}; 497 498static const struct sirfsoc_padmux sdmmc1_padmux = { 499 .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask), 500 .muxmask = sdmmc1_muxmask, 501 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 502 .funcmask = BIT(5), 503 .funcval = BIT(5), 504}; 505 506static const unsigned sdmmc1_pins[] = { 66, 67 }; 507 508static const struct sirfsoc_muxmask gps_muxmask[] = { 509 { 510 .group = 0, 511 .mask = BIT(24) | BIT(25) | BIT(26), 512 }, 513}; 514 515static const struct sirfsoc_padmux gps_padmux = { 516 .muxmask_counts = ARRAY_SIZE(gps_muxmask), 517 .muxmask = gps_muxmask, 518 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 519 .funcmask = BIT(13), 520 .funcval = 0, 521}; 522 523static const unsigned gps_pins[] = { 24, 25, 26 }; 524 525static const struct sirfsoc_muxmask sdmmc5_muxmask[] = { 526 { 527 .group = 0, 528 .mask = BIT(24) | BIT(25) | BIT(26), 529 }, 530}; 531 532static const struct sirfsoc_padmux sdmmc5_padmux = { 533 .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask), 534 .muxmask = sdmmc5_muxmask, 535 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 536 .funcmask = BIT(13), 537 .funcval = BIT(13), 538}; 539 540static const unsigned sdmmc5_pins[] = { 24, 25, 26 }; 541 542static const struct sirfsoc_muxmask usp0_muxmask[] = { 543 { 544 .group = 1, 545 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23), 546 }, 547}; 548 549static const struct sirfsoc_padmux usp0_padmux = { 550 .muxmask_counts = ARRAY_SIZE(usp0_muxmask), 551 .muxmask = usp0_muxmask, 552 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 553 .funcmask = BIT(1) | BIT(2) | BIT(9), 554 .funcval = 0, 555}; 556 557static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 }; 558 559static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = { 560 { 561 .group = 1, 562 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22), 563 }, 564}; 565 566static const struct sirfsoc_padmux usp0_only_utfs_padmux = { 567 .muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask), 568 .muxmask = usp0_only_utfs_muxmask, 569 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 570 .funcmask = BIT(1) | BIT(2) | BIT(6), 571 .funcval = 0, 572}; 573 574static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 }; 575 576static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = { 577 { 578 .group = 1, 579 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(23), 580 }, 581}; 582 583static const struct sirfsoc_padmux usp0_only_urfs_padmux = { 584 .muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask), 585 .muxmask = usp0_only_urfs_muxmask, 586 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 587 .funcmask = BIT(1) | BIT(2) | BIT(9), 588 .funcval = 0, 589}; 590 591static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 }; 592 593static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = { 594 { 595 .group = 1, 596 .mask = BIT(20) | BIT(21), 597 }, 598}; 599 600static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = { 601 .muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask), 602 .muxmask = usp0_uart_nostreamctrl_muxmask, 603}; 604 605static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 }; 606static const struct sirfsoc_muxmask usp1_muxmask[] = { 607 { 608 .group = 0, 609 .mask = BIT(15), 610 }, { 611 .group = 1, 612 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), 613 }, 614}; 615 616static const struct sirfsoc_padmux usp1_padmux = { 617 .muxmask_counts = ARRAY_SIZE(usp1_muxmask), 618 .muxmask = usp1_muxmask, 619 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 620 .funcmask = BIT(16), 621 .funcval = BIT(16), 622}; 623 624static const unsigned usp1_pins[] = { 15, 43, 44, 45, 46 }; 625 626static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = { 627 { 628 .group = 1, 629 .mask = BIT(12) | BIT(13), 630 }, 631}; 632 633static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = { 634 .muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask), 635 .muxmask = usp1_uart_nostreamctrl_muxmask, 636 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 637 .funcmask = BIT(16), 638 .funcval = BIT(16), 639}; 640 641static const unsigned usp1_uart_nostreamctrl_pins[] = { 44, 45 }; 642 643static const struct sirfsoc_muxmask nand_muxmask[] = { 644 { 645 .group = 2, 646 .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30), 647 }, { 648 .group = 3, 649 .mask = BIT(0) | BIT(1), 650 }, 651}; 652 653static const struct sirfsoc_padmux nand_padmux = { 654 .muxmask_counts = ARRAY_SIZE(nand_muxmask), 655 .muxmask = nand_muxmask, 656 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 657 .funcmask = BIT(5) | BIT(19), 658 .funcval = 0, 659}; 660 661static const unsigned nand_pins[] = { 66, 67, 92, 93, 94, 96, 97 }; 662 663static const struct sirfsoc_muxmask sdmmc0_muxmask[] = { 664 { 665 .group = 3, 666 .mask = BIT(1), 667 }, 668}; 669 670static const struct sirfsoc_padmux sdmmc0_padmux = { 671 .muxmask_counts = ARRAY_SIZE(sdmmc0_muxmask), 672 .muxmask = sdmmc0_muxmask, 673 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 674 .funcmask = BIT(5) | BIT(19), 675 .funcval = BIT(19), 676}; 677 678static const unsigned sdmmc0_pins[] = { 97 }; 679 680static const struct sirfsoc_muxmask sdmmc2_muxmask[] = { 681 { 682 .group = 0, 683 .mask = BIT(27) | BIT(28) | BIT(29), 684 }, 685}; 686 687static const struct sirfsoc_padmux sdmmc2_padmux = { 688 .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask), 689 .muxmask = sdmmc2_muxmask, 690 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 691 .funcmask = BIT(11), 692 .funcval = 0, 693}; 694 695static const unsigned sdmmc2_pins[] = { 27, 28, 29 }; 696 697static const struct sirfsoc_muxmask sdmmc2_nowp_muxmask[] = { 698 { 699 .group = 0, 700 .mask = BIT(27) | BIT(28), 701 }, 702}; 703 704static const struct sirfsoc_padmux sdmmc2_nowp_padmux = { 705 .muxmask_counts = ARRAY_SIZE(sdmmc2_nowp_muxmask), 706 .muxmask = sdmmc2_nowp_muxmask, 707 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 708 .funcmask = BIT(11), 709 .funcval = 0, 710}; 711 712static const unsigned sdmmc2_nowp_pins[] = { 27, 28 }; 713 714static const struct sirfsoc_muxmask cko0_muxmask[] = { 715 { 716 .group = 2, 717 .mask = BIT(14), 718 }, 719}; 720 721static const struct sirfsoc_padmux cko0_padmux = { 722 .muxmask_counts = ARRAY_SIZE(cko0_muxmask), 723 .muxmask = cko0_muxmask, 724}; 725 726static const unsigned cko0_pins[] = { 78 }; 727 728static const struct sirfsoc_muxmask vip_muxmask[] = { 729 { 730 .group = 1, 731 .mask = BIT(4) | BIT(5) | BIT(6) | BIT(8) | BIT(9) 732 | BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28) | 733 BIT(29), 734 }, 735}; 736 737static const struct sirfsoc_padmux vip_padmux = { 738 .muxmask_counts = ARRAY_SIZE(vip_muxmask), 739 .muxmask = vip_muxmask, 740 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 741 .funcmask = BIT(18), 742 .funcval = BIT(18), 743}; 744 745static const unsigned vip_pins[] = { 36, 37, 38, 40, 41, 56, 57, 58, 59, 746 60, 61 }; 747 748static const struct sirfsoc_muxmask vip_noupli_muxmask[] = { 749 { 750 .group = 0, 751 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) 752 | BIT(21) | BIT(22) | BIT(23), 753 }, { 754 .group = 2, 755 .mask = BIT(23) | BIT(24) | BIT(25), 756 }, 757}; 758 759static const struct sirfsoc_padmux vip_noupli_padmux = { 760 .muxmask_counts = ARRAY_SIZE(vip_noupli_muxmask), 761 .muxmask = vip_noupli_muxmask, 762 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 763 .funcmask = BIT(15), 764 .funcval = BIT(15), 765}; 766 767static const unsigned vip_noupli_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 768 87, 88, 89 }; 769 770static const struct sirfsoc_muxmask i2c0_muxmask[] = { 771 { 772 .group = 2, 773 .mask = BIT(26) | BIT(27), 774 }, 775}; 776 777static const struct sirfsoc_padmux i2c0_padmux = { 778 .muxmask_counts = ARRAY_SIZE(i2c0_muxmask), 779 .muxmask = i2c0_muxmask, 780}; 781 782static const unsigned i2c0_pins[] = { 90, 91 }; 783 784static const struct sirfsoc_muxmask i2c1_muxmask[] = { 785 { 786 .group = 0, 787 .mask = BIT(13) | BIT(15), 788 }, 789}; 790 791static const struct sirfsoc_padmux i2c1_padmux = { 792 .muxmask_counts = ARRAY_SIZE(i2c1_muxmask), 793 .muxmask = i2c1_muxmask, 794 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 795 .funcmask = BIT(16), 796 .funcval = 0, 797}; 798 799static const unsigned i2c1_pins[] = { 13, 15 }; 800 801static const struct sirfsoc_muxmask pwm0_muxmask[] = { 802 { 803 .group = 0, 804 .mask = BIT(4), 805 }, 806}; 807 808static const struct sirfsoc_padmux pwm0_padmux = { 809 .muxmask_counts = ARRAY_SIZE(pwm0_muxmask), 810 .muxmask = pwm0_muxmask, 811 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 812 .funcmask = BIT(12), 813 .funcval = 0, 814}; 815 816static const unsigned pwm0_pins[] = { 4 }; 817 818static const struct sirfsoc_muxmask pwm1_muxmask[] = { 819 { 820 .group = 0, 821 .mask = BIT(5), 822 }, 823}; 824 825static const struct sirfsoc_padmux pwm1_padmux = { 826 .muxmask_counts = ARRAY_SIZE(pwm1_muxmask), 827 .muxmask = pwm1_muxmask, 828}; 829 830static const unsigned pwm1_pins[] = { 5 }; 831 832static const struct sirfsoc_muxmask pwm2_muxmask[] = { 833 { 834 .group = 0, 835 .mask = BIT(6), 836 }, 837}; 838 839static const struct sirfsoc_padmux pwm2_padmux = { 840 .muxmask_counts = ARRAY_SIZE(pwm2_muxmask), 841 .muxmask = pwm2_muxmask, 842}; 843 844static const unsigned pwm2_pins[] = { 6 }; 845 846static const struct sirfsoc_muxmask pwm3_muxmask[] = { 847 { 848 .group = 0, 849 .mask = BIT(7), 850 }, 851}; 852 853static const struct sirfsoc_padmux pwm3_padmux = { 854 .muxmask_counts = ARRAY_SIZE(pwm3_muxmask), 855 .muxmask = pwm3_muxmask, 856}; 857 858static const unsigned pwm3_pins[] = { 7 }; 859 860static const struct sirfsoc_muxmask pwm4_muxmask[] = { 861 { 862 .group = 2, 863 .mask = BIT(14), 864 }, 865}; 866 867static const struct sirfsoc_padmux pwm4_padmux = { 868 .muxmask_counts = ARRAY_SIZE(pwm4_muxmask), 869 .muxmask = pwm4_muxmask, 870}; 871 872static const unsigned pwm4_pins[] = { 78 }; 873 874static const struct sirfsoc_muxmask warm_rst_muxmask[] = { 875 { 876 .group = 0, 877 .mask = BIT(8), 878 }, 879}; 880 881static const struct sirfsoc_padmux warm_rst_padmux = { 882 .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask), 883 .muxmask = warm_rst_muxmask, 884 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 885 .funcmask = BIT(4), 886 .funcval = 0, 887}; 888 889static const unsigned warm_rst_pins[] = { 8 }; 890 891static const struct sirfsoc_muxmask usb0_upli_drvbus_muxmask[] = { 892 { 893 .group = 1, 894 .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) 895 | BIT(9) | BIT(24) | BIT(25) | BIT(26) | 896 BIT(27) | BIT(28) | BIT(29), 897 }, 898}; 899static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = { 900 .muxmask_counts = ARRAY_SIZE(usb0_upli_drvbus_muxmask), 901 .muxmask = usb0_upli_drvbus_muxmask, 902 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 903 .funcmask = BIT(18), 904 .funcval = 0, 905}; 906 907static const unsigned usb0_upli_drvbus_pins[] = { 36, 37, 38, 39, 40, 908 41, 56, 57, 58, 59, 60, 61 }; 909 910static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = { 911 { 912 .group = 0, 913 .mask = BIT(28), 914 }, 915}; 916 917static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = { 918 .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask), 919 .muxmask = usb1_utmi_drvbus_muxmask, 920 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 921 .funcmask = BIT(11), 922 .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */ 923}; 924 925static const unsigned usb1_utmi_drvbus_pins[] = { 28 }; 926 927static const struct sirfsoc_padmux usb1_dp_dn_padmux = { 928 .muxmask_counts = 0, 929 .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE, 930 .funcmask = BIT(2), 931 .funcval = BIT(2), 932}; 933 934static const unsigned usb1_dp_dn_pins[] = { 103, 104 }; 935 936static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = { 937 .muxmask_counts = 0, 938 .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE, 939 .funcmask = BIT(2), 940 .funcval = 0, 941}; 942 943static const unsigned uart1_route_io_usb1_pins[] = { 103, 104 }; 944 945static const struct sirfsoc_muxmask pulse_count_muxmask[] = { 946 { 947 .group = 0, 948 .mask = BIT(9) | BIT(10) | BIT(11), 949 }, 950}; 951 952static const struct sirfsoc_padmux pulse_count_padmux = { 953 .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask), 954 .muxmask = pulse_count_muxmask, 955}; 956 957static const unsigned pulse_count_pins[] = { 9, 10, 11 }; 958 959static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { 960 SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins), 961 SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins), 962 SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins), 963 SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins), 964 SIRFSOC_PIN_GROUP("uart0grp", uart0_pins), 965 SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins), 966 SIRFSOC_PIN_GROUP("uart1grp", uart1_pins), 967 SIRFSOC_PIN_GROUP("uart2grp", uart2_pins), 968 SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins), 969 SIRFSOC_PIN_GROUP("usp0grp", usp0_pins), 970 SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp", 971 usp0_uart_nostreamctrl_pins), 972 SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins), 973 SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins), 974 SIRFSOC_PIN_GROUP("usp1grp", usp1_pins), 975 SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp", 976 usp1_uart_nostreamctrl_pins), 977 SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins), 978 SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins), 979 SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins), 980 SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins), 981 SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins), 982 SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins), 983 SIRFSOC_PIN_GROUP("pwm4grp", pwm4_pins), 984 SIRFSOC_PIN_GROUP("vipgrp", vip_pins), 985 SIRFSOC_PIN_GROUP("vip_noupligrp", vip_noupli_pins), 986 SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins), 987 SIRFSOC_PIN_GROUP("cko0grp", cko0_pins), 988 SIRFSOC_PIN_GROUP("cko1grp", cko1_pins), 989 SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins), 990 SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins), 991 SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins), 992 SIRFSOC_PIN_GROUP("sdmmc2_nowpgrp", sdmmc2_nowp_pins), 993 SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins), 994 SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins), 995 SIRFSOC_PIN_GROUP("usb0_upli_drvbusgrp", usb0_upli_drvbus_pins), 996 SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins), 997 SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins), 998 SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins), 999 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins), 1000 SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins), 1001 SIRFSOC_PIN_GROUP("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins), 1002 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins), 1003 SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins), 1004 SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins), 1005 SIRFSOC_PIN_GROUP("ac97grp", ac97_pins), 1006 SIRFSOC_PIN_GROUP("nandgrp", nand_pins), 1007 SIRFSOC_PIN_GROUP("spi0grp", spi0_pins), 1008 SIRFSOC_PIN_GROUP("spi1grp", spi1_pins), 1009 SIRFSOC_PIN_GROUP("gpsgrp", gps_pins), 1010}; 1011 1012static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" }; 1013static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" }; 1014static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" }; 1015static const char * const lcdromgrp[] = { "lcdromgrp" }; 1016static const char * const uart0grp[] = { "uart0grp" }; 1017static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" }; 1018static const char * const uart1grp[] = { "uart1grp" }; 1019static const char * const uart2grp[] = { "uart2grp" }; 1020static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" }; 1021static const char * const usp0_uart_nostreamctrl_grp[] = { 1022 "usp0_uart_nostreamctrl_grp" }; 1023static const char * const usp0grp[] = { "usp0grp" }; 1024static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" }; 1025static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" }; 1026 1027static const char * const usp1grp[] = { "usp1grp" }; 1028static const char * const usp1_uart_nostreamctrl_grp[] = { 1029 "usp1_uart_nostreamctrl_grp" }; 1030static const char * const i2c0grp[] = { "i2c0grp" }; 1031static const char * const i2c1grp[] = { "i2c1grp" }; 1032static const char * const pwm0grp[] = { "pwm0grp" }; 1033static const char * const pwm1grp[] = { "pwm1grp" }; 1034static const char * const pwm2grp[] = { "pwm2grp" }; 1035static const char * const pwm3grp[] = { "pwm3grp" }; 1036static const char * const pwm4grp[] = { "pwm4grp" }; 1037static const char * const vipgrp[] = { "vipgrp" }; 1038static const char * const vip_noupligrp[] = { "vip_noupligrp" }; 1039static const char * const warm_rstgrp[] = { "warm_rstgrp" }; 1040static const char * const cko0grp[] = { "cko0grp" }; 1041static const char * const cko1grp[] = { "cko1grp" }; 1042static const char * const sdmmc0grp[] = { "sdmmc0grp" }; 1043static const char * const sdmmc1grp[] = { "sdmmc1grp" }; 1044static const char * const sdmmc2grp[] = { "sdmmc2grp" }; 1045static const char * const sdmmc3grp[] = { "sdmmc3grp" }; 1046static const char * const sdmmc5grp[] = { "sdmmc5grp" }; 1047static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" }; 1048static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" }; 1049static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" }; 1050static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" }; 1051static const char * const 1052 uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" }; 1053static const char * const pulse_countgrp[] = { "pulse_countgrp" }; 1054static const char * const i2smclkgrp[] = { "i2smclkgrp" }; 1055static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" }; 1056static const char * const i2sgrp[] = { "i2sgrp" }; 1057static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" }; 1058static const char * const i2s_6chngrp[] = { "i2s_6chngrp" }; 1059static const char * const ac97grp[] = { "ac97grp" }; 1060static const char * const nandgrp[] = { "nandgrp" }; 1061static const char * const spi0grp[] = { "spi0grp" }; 1062static const char * const spi1grp[] = { "spi1grp" }; 1063static const char * const gpsgrp[] = { "gpsgrp" }; 1064 1065static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { 1066 SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux), 1067 SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux), 1068 SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux), 1069 SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux), 1070 SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux), 1071 SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp, 1072 uart0_nostreamctrl_padmux), 1073 SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux), 1074 SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux), 1075 SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", 1076 uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux), 1077 SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux), 1078 SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl", 1079 usp0_uart_nostreamctrl_grp, 1080 usp0_uart_nostreamctrl_padmux), 1081 SIRFSOC_PMX_FUNCTION("usp0_only_utfs", usp0_only_utfs_grp, 1082 usp0_only_utfs_padmux), 1083 SIRFSOC_PMX_FUNCTION("usp0_only_urfs", usp0_only_urfs_grp, 1084 usp0_only_urfs_padmux), 1085 SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux), 1086 SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl", 1087 usp1_uart_nostreamctrl_grp, 1088 usp1_uart_nostreamctrl_padmux), 1089 SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux), 1090 SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux), 1091 SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux), 1092 SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux), 1093 SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux), 1094 SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux), 1095 SIRFSOC_PMX_FUNCTION("pwm4", pwm4grp, pwm4_padmux), 1096 SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux), 1097 SIRFSOC_PMX_FUNCTION("vip_noupli", vip_noupligrp, vip_noupli_padmux), 1098 SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux), 1099 SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux), 1100 SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux), 1101 SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux), 1102 SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux), 1103 SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux), 1104 SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux), 1105 SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux), 1106 SIRFSOC_PMX_FUNCTION("sdmmc2_nowp", 1107 sdmmc2_nowpgrp, sdmmc2_nowp_padmux), 1108 SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus", 1109 usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux), 1110 SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", 1111 usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux), 1112 SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux), 1113 SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", 1114 uart1_route_io_usb1grp, uart1_route_io_usb1_padmux), 1115 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux), 1116 SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux), 1117 SIRFSOC_PMX_FUNCTION("i2s_ext_clk_input", i2s_ext_clk_inputgrp, 1118 i2s_ext_clk_input_padmux), 1119 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux), 1120 SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux), 1121 SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux), 1122 SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux), 1123 SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux), 1124 SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux), 1125 SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux), 1126 SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux), 1127}; 1128 1129struct sirfsoc_pinctrl_data atlas6_pinctrl_data = { 1130 (struct pinctrl_pin_desc *)sirfsoc_pads, 1131 ARRAY_SIZE(sirfsoc_pads), 1132 (struct sirfsoc_pin_group *)sirfsoc_pin_groups, 1133 ARRAY_SIZE(sirfsoc_pin_groups), 1134 (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions, 1135 ARRAY_SIZE(sirfsoc_pmx_functions), 1136}; 1137 1138