18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0+ */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Exynos specific definitions for Samsung pinctrl and gpiolib driver. 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright (c) 2012 Samsung Electronics Co., Ltd. 68c2ecf20Sopenharmony_ci * http://www.samsung.com 78c2ecf20Sopenharmony_ci * Copyright (c) 2012 Linaro Ltd 88c2ecf20Sopenharmony_ci * http://www.linaro.org 98c2ecf20Sopenharmony_ci * 108c2ecf20Sopenharmony_ci * This file contains the Exynos specific definitions for the Samsung 118c2ecf20Sopenharmony_ci * pinctrl/gpiolib interface drivers. 128c2ecf20Sopenharmony_ci * 138c2ecf20Sopenharmony_ci * Author: Thomas Abraham <thomas.ab@samsung.com> 148c2ecf20Sopenharmony_ci */ 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci#ifndef __PINCTRL_SAMSUNG_EXYNOS_H 178c2ecf20Sopenharmony_ci#define __PINCTRL_SAMSUNG_EXYNOS_H 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ci/* External GPIO and wakeup interrupt related definitions */ 208c2ecf20Sopenharmony_ci#define EXYNOS_GPIO_ECON_OFFSET 0x700 218c2ecf20Sopenharmony_ci#define EXYNOS_GPIO_EFLTCON_OFFSET 0x800 228c2ecf20Sopenharmony_ci#define EXYNOS_GPIO_EMASK_OFFSET 0x900 238c2ecf20Sopenharmony_ci#define EXYNOS_GPIO_EPEND_OFFSET 0xA00 248c2ecf20Sopenharmony_ci#define EXYNOS_WKUP_ECON_OFFSET 0xE00 258c2ecf20Sopenharmony_ci#define EXYNOS_WKUP_EMASK_OFFSET 0xF00 268c2ecf20Sopenharmony_ci#define EXYNOS_WKUP_EPEND_OFFSET 0xF40 278c2ecf20Sopenharmony_ci#define EXYNOS7_WKUP_ECON_OFFSET 0x700 288c2ecf20Sopenharmony_ci#define EXYNOS7_WKUP_EMASK_OFFSET 0x900 298c2ecf20Sopenharmony_ci#define EXYNOS7_WKUP_EPEND_OFFSET 0xA00 308c2ecf20Sopenharmony_ci#define EXYNOS_SVC_OFFSET 0xB08 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_ci/* helpers to access interrupt service register */ 338c2ecf20Sopenharmony_ci#define EXYNOS_SVC_GROUP_SHIFT 3 348c2ecf20Sopenharmony_ci#define EXYNOS_SVC_GROUP_MASK 0x1f 358c2ecf20Sopenharmony_ci#define EXYNOS_SVC_NUM_MASK 7 368c2ecf20Sopenharmony_ci#define EXYNOS_SVC_GROUP(x) ((x >> EXYNOS_SVC_GROUP_SHIFT) & \ 378c2ecf20Sopenharmony_ci EXYNOS_SVC_GROUP_MASK) 388c2ecf20Sopenharmony_ci 398c2ecf20Sopenharmony_ci/* Exynos specific external interrupt trigger types */ 408c2ecf20Sopenharmony_ci#define EXYNOS_EINT_LEVEL_LOW 0 418c2ecf20Sopenharmony_ci#define EXYNOS_EINT_LEVEL_HIGH 1 428c2ecf20Sopenharmony_ci#define EXYNOS_EINT_EDGE_FALLING 2 438c2ecf20Sopenharmony_ci#define EXYNOS_EINT_EDGE_RISING 3 448c2ecf20Sopenharmony_ci#define EXYNOS_EINT_EDGE_BOTH 4 458c2ecf20Sopenharmony_ci#define EXYNOS_EINT_CON_MASK 0xF 468c2ecf20Sopenharmony_ci#define EXYNOS_EINT_CON_LEN 4 478c2ecf20Sopenharmony_ci 488c2ecf20Sopenharmony_ci#define EXYNOS_EINT_MAX_PER_BANK 8 498c2ecf20Sopenharmony_ci#define EXYNOS_EINT_NR_WKUP_EINT 508c2ecf20Sopenharmony_ci 518c2ecf20Sopenharmony_ci#define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ 528c2ecf20Sopenharmony_ci { \ 538c2ecf20Sopenharmony_ci .type = &bank_type_off, \ 548c2ecf20Sopenharmony_ci .pctl_offset = reg, \ 558c2ecf20Sopenharmony_ci .nr_pins = pins, \ 568c2ecf20Sopenharmony_ci .eint_type = EINT_TYPE_NONE, \ 578c2ecf20Sopenharmony_ci .name = id \ 588c2ecf20Sopenharmony_ci } 598c2ecf20Sopenharmony_ci 608c2ecf20Sopenharmony_ci#define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs) \ 618c2ecf20Sopenharmony_ci { \ 628c2ecf20Sopenharmony_ci .type = &bank_type_off, \ 638c2ecf20Sopenharmony_ci .pctl_offset = reg, \ 648c2ecf20Sopenharmony_ci .nr_pins = pins, \ 658c2ecf20Sopenharmony_ci .eint_type = EINT_TYPE_GPIO, \ 668c2ecf20Sopenharmony_ci .eint_offset = offs, \ 678c2ecf20Sopenharmony_ci .name = id \ 688c2ecf20Sopenharmony_ci } 698c2ecf20Sopenharmony_ci 708c2ecf20Sopenharmony_ci#define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs) \ 718c2ecf20Sopenharmony_ci { \ 728c2ecf20Sopenharmony_ci .type = &bank_type_alive, \ 738c2ecf20Sopenharmony_ci .pctl_offset = reg, \ 748c2ecf20Sopenharmony_ci .nr_pins = pins, \ 758c2ecf20Sopenharmony_ci .eint_type = EINT_TYPE_WKUP, \ 768c2ecf20Sopenharmony_ci .eint_offset = offs, \ 778c2ecf20Sopenharmony_ci .name = id \ 788c2ecf20Sopenharmony_ci } 798c2ecf20Sopenharmony_ci 808c2ecf20Sopenharmony_ci#define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs) \ 818c2ecf20Sopenharmony_ci { \ 828c2ecf20Sopenharmony_ci .type = &exynos5433_bank_type_off, \ 838c2ecf20Sopenharmony_ci .pctl_offset = reg, \ 848c2ecf20Sopenharmony_ci .nr_pins = pins, \ 858c2ecf20Sopenharmony_ci .eint_type = EINT_TYPE_GPIO, \ 868c2ecf20Sopenharmony_ci .eint_offset = offs, \ 878c2ecf20Sopenharmony_ci .name = id \ 888c2ecf20Sopenharmony_ci } 898c2ecf20Sopenharmony_ci 908c2ecf20Sopenharmony_ci#define EXYNOS5433_PIN_BANK_EINTW(pins, reg, id, offs) \ 918c2ecf20Sopenharmony_ci { \ 928c2ecf20Sopenharmony_ci .type = &exynos5433_bank_type_alive, \ 938c2ecf20Sopenharmony_ci .pctl_offset = reg, \ 948c2ecf20Sopenharmony_ci .nr_pins = pins, \ 958c2ecf20Sopenharmony_ci .eint_type = EINT_TYPE_WKUP, \ 968c2ecf20Sopenharmony_ci .eint_offset = offs, \ 978c2ecf20Sopenharmony_ci .name = id \ 988c2ecf20Sopenharmony_ci } 998c2ecf20Sopenharmony_ci 1008c2ecf20Sopenharmony_ci#define EXYNOS5433_PIN_BANK_EINTW_EXT(pins, reg, id, offs, pctl_idx) \ 1018c2ecf20Sopenharmony_ci { \ 1028c2ecf20Sopenharmony_ci .type = &exynos5433_bank_type_off, \ 1038c2ecf20Sopenharmony_ci .pctl_offset = reg, \ 1048c2ecf20Sopenharmony_ci .nr_pins = pins, \ 1058c2ecf20Sopenharmony_ci .eint_type = EINT_TYPE_WKUP, \ 1068c2ecf20Sopenharmony_ci .eint_offset = offs, \ 1078c2ecf20Sopenharmony_ci .name = id, \ 1088c2ecf20Sopenharmony_ci .pctl_res_idx = pctl_idx, \ 1098c2ecf20Sopenharmony_ci } \ 1108c2ecf20Sopenharmony_ci 1118c2ecf20Sopenharmony_ci/** 1128c2ecf20Sopenharmony_ci * struct exynos_weint_data: irq specific data for all the wakeup interrupts 1138c2ecf20Sopenharmony_ci * generated by the external wakeup interrupt controller. 1148c2ecf20Sopenharmony_ci * @irq: interrupt number within the domain. 1158c2ecf20Sopenharmony_ci * @bank: bank responsible for this interrupt 1168c2ecf20Sopenharmony_ci */ 1178c2ecf20Sopenharmony_cistruct exynos_weint_data { 1188c2ecf20Sopenharmony_ci unsigned int irq; 1198c2ecf20Sopenharmony_ci struct samsung_pin_bank *bank; 1208c2ecf20Sopenharmony_ci}; 1218c2ecf20Sopenharmony_ci 1228c2ecf20Sopenharmony_ci/** 1238c2ecf20Sopenharmony_ci * struct exynos_muxed_weint_data: irq specific data for muxed wakeup interrupts 1248c2ecf20Sopenharmony_ci * generated by the external wakeup interrupt controller. 1258c2ecf20Sopenharmony_ci * @nr_banks: count of banks being part of the mux 1268c2ecf20Sopenharmony_ci * @banks: array of banks being part of the mux 1278c2ecf20Sopenharmony_ci */ 1288c2ecf20Sopenharmony_cistruct exynos_muxed_weint_data { 1298c2ecf20Sopenharmony_ci unsigned int nr_banks; 1308c2ecf20Sopenharmony_ci struct samsung_pin_bank *banks[]; 1318c2ecf20Sopenharmony_ci}; 1328c2ecf20Sopenharmony_ci 1338c2ecf20Sopenharmony_ciint exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d); 1348c2ecf20Sopenharmony_ciint exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d); 1358c2ecf20Sopenharmony_civoid exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata); 1368c2ecf20Sopenharmony_civoid exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata); 1378c2ecf20Sopenharmony_cistruct samsung_retention_ctrl * 1388c2ecf20Sopenharmony_ciexynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, 1398c2ecf20Sopenharmony_ci const struct samsung_retention_data *data); 1408c2ecf20Sopenharmony_ci 1418c2ecf20Sopenharmony_ci#endif /* __PINCTRL_SAMSUNG_EXYNOS_H */ 142