1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SuperH Pin Function Controller pinmux support. 4 * 5 * Copyright (C) 2012 Paul Mundt 6 */ 7 8#define DRV_NAME "sh-pfc" 9 10#include <linux/device.h> 11#include <linux/err.h> 12#include <linux/init.h> 13#include <linux/module.h> 14#include <linux/of.h> 15#include <linux/pinctrl/consumer.h> 16#include <linux/pinctrl/machine.h> 17#include <linux/pinctrl/pinconf.h> 18#include <linux/pinctrl/pinconf-generic.h> 19#include <linux/pinctrl/pinctrl.h> 20#include <linux/pinctrl/pinmux.h> 21#include <linux/slab.h> 22#include <linux/spinlock.h> 23 24#include "core.h" 25#include "../core.h" 26#include "../pinconf.h" 27 28struct sh_pfc_pin_config { 29 unsigned int mux_mark; 30 bool mux_set; 31 bool gpio_enabled; 32}; 33 34struct sh_pfc_pinctrl { 35 struct pinctrl_dev *pctl; 36 struct pinctrl_desc pctl_desc; 37 38 struct sh_pfc *pfc; 39 40 struct pinctrl_pin_desc *pins; 41 struct sh_pfc_pin_config *configs; 42 43 const char *func_prop_name; 44 const char *groups_prop_name; 45 const char *pins_prop_name; 46}; 47 48static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev) 49{ 50 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 51 52 return pmx->pfc->info->nr_groups; 53} 54 55static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev, 56 unsigned selector) 57{ 58 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 59 60 return pmx->pfc->info->groups[selector].name; 61} 62 63static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 64 const unsigned **pins, unsigned *num_pins) 65{ 66 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 67 68 *pins = pmx->pfc->info->groups[selector].pins; 69 *num_pins = pmx->pfc->info->groups[selector].nr_pins; 70 71 return 0; 72} 73 74static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 75 unsigned offset) 76{ 77 seq_puts(s, DRV_NAME); 78} 79 80#ifdef CONFIG_OF 81static int sh_pfc_map_add_config(struct pinctrl_map *map, 82 const char *group_or_pin, 83 enum pinctrl_map_type type, 84 unsigned long *configs, 85 unsigned int num_configs) 86{ 87 unsigned long *cfgs; 88 89 cfgs = kmemdup(configs, num_configs * sizeof(*cfgs), 90 GFP_KERNEL); 91 if (cfgs == NULL) 92 return -ENOMEM; 93 94 map->type = type; 95 map->data.configs.group_or_pin = group_or_pin; 96 map->data.configs.configs = cfgs; 97 map->data.configs.num_configs = num_configs; 98 99 return 0; 100} 101 102static int sh_pfc_dt_subnode_to_map(struct pinctrl_dev *pctldev, 103 struct device_node *np, 104 struct pinctrl_map **map, 105 unsigned int *num_maps, unsigned int *index) 106{ 107 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 108 struct device *dev = pmx->pfc->dev; 109 struct pinctrl_map *maps = *map; 110 unsigned int nmaps = *num_maps; 111 unsigned int idx = *index; 112 unsigned int num_configs; 113 const char *function = NULL; 114 unsigned long *configs; 115 struct property *prop; 116 unsigned int num_groups; 117 unsigned int num_pins; 118 const char *group; 119 const char *pin; 120 int ret; 121 122 /* Support both the old Renesas-specific properties and the new standard 123 * properties. Mixing old and new properties isn't allowed, neither 124 * inside a subnode nor across subnodes. 125 */ 126 if (!pmx->func_prop_name) { 127 if (of_find_property(np, "groups", NULL) || 128 of_find_property(np, "pins", NULL)) { 129 pmx->func_prop_name = "function"; 130 pmx->groups_prop_name = "groups"; 131 pmx->pins_prop_name = "pins"; 132 } else { 133 pmx->func_prop_name = "renesas,function"; 134 pmx->groups_prop_name = "renesas,groups"; 135 pmx->pins_prop_name = "renesas,pins"; 136 } 137 } 138 139 /* Parse the function and configuration properties. At least a function 140 * or one configuration must be specified. 141 */ 142 ret = of_property_read_string(np, pmx->func_prop_name, &function); 143 if (ret < 0 && ret != -EINVAL) { 144 dev_err(dev, "Invalid function in DT\n"); 145 return ret; 146 } 147 148 ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs); 149 if (ret < 0) 150 return ret; 151 152 if (!function && num_configs == 0) { 153 dev_err(dev, 154 "DT node must contain at least a function or config\n"); 155 ret = -ENODEV; 156 goto done; 157 } 158 159 /* Count the number of pins and groups and reallocate mappings. */ 160 ret = of_property_count_strings(np, pmx->pins_prop_name); 161 if (ret == -EINVAL) { 162 num_pins = 0; 163 } else if (ret < 0) { 164 dev_err(dev, "Invalid pins list in DT\n"); 165 goto done; 166 } else { 167 num_pins = ret; 168 } 169 170 ret = of_property_count_strings(np, pmx->groups_prop_name); 171 if (ret == -EINVAL) { 172 num_groups = 0; 173 } else if (ret < 0) { 174 dev_err(dev, "Invalid pin groups list in DT\n"); 175 goto done; 176 } else { 177 num_groups = ret; 178 } 179 180 if (!num_pins && !num_groups) { 181 dev_err(dev, "No pin or group provided in DT node\n"); 182 ret = -ENODEV; 183 goto done; 184 } 185 186 if (function) 187 nmaps += num_groups; 188 if (configs) 189 nmaps += num_pins + num_groups; 190 191 maps = krealloc(maps, sizeof(*maps) * nmaps, GFP_KERNEL); 192 if (maps == NULL) { 193 ret = -ENOMEM; 194 goto done; 195 } 196 197 *map = maps; 198 *num_maps = nmaps; 199 200 /* Iterate over pins and groups and create the mappings. */ 201 of_property_for_each_string(np, pmx->groups_prop_name, prop, group) { 202 if (function) { 203 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; 204 maps[idx].data.mux.group = group; 205 maps[idx].data.mux.function = function; 206 idx++; 207 } 208 209 if (configs) { 210 ret = sh_pfc_map_add_config(&maps[idx], group, 211 PIN_MAP_TYPE_CONFIGS_GROUP, 212 configs, num_configs); 213 if (ret < 0) 214 goto done; 215 216 idx++; 217 } 218 } 219 220 if (!configs) { 221 ret = 0; 222 goto done; 223 } 224 225 of_property_for_each_string(np, pmx->pins_prop_name, prop, pin) { 226 ret = sh_pfc_map_add_config(&maps[idx], pin, 227 PIN_MAP_TYPE_CONFIGS_PIN, 228 configs, num_configs); 229 if (ret < 0) 230 goto done; 231 232 idx++; 233 } 234 235done: 236 *index = idx; 237 kfree(configs); 238 return ret; 239} 240 241static void sh_pfc_dt_free_map(struct pinctrl_dev *pctldev, 242 struct pinctrl_map *map, unsigned num_maps) 243{ 244 unsigned int i; 245 246 if (map == NULL) 247 return; 248 249 for (i = 0; i < num_maps; ++i) { 250 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || 251 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 252 kfree(map[i].data.configs.configs); 253 } 254 255 kfree(map); 256} 257 258static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev, 259 struct device_node *np, 260 struct pinctrl_map **map, unsigned *num_maps) 261{ 262 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 263 struct device *dev = pmx->pfc->dev; 264 struct device_node *child; 265 unsigned int index; 266 int ret; 267 268 *map = NULL; 269 *num_maps = 0; 270 index = 0; 271 272 for_each_child_of_node(np, child) { 273 ret = sh_pfc_dt_subnode_to_map(pctldev, child, map, num_maps, 274 &index); 275 if (ret < 0) { 276 of_node_put(child); 277 goto done; 278 } 279 } 280 281 /* If no mapping has been found in child nodes try the config node. */ 282 if (*num_maps == 0) { 283 ret = sh_pfc_dt_subnode_to_map(pctldev, np, map, num_maps, 284 &index); 285 if (ret < 0) 286 goto done; 287 } 288 289 if (*num_maps) 290 return 0; 291 292 dev_err(dev, "no mapping found in node %pOF\n", np); 293 ret = -EINVAL; 294 295done: 296 if (ret < 0) 297 sh_pfc_dt_free_map(pctldev, *map, *num_maps); 298 299 return ret; 300} 301#endif /* CONFIG_OF */ 302 303static const struct pinctrl_ops sh_pfc_pinctrl_ops = { 304 .get_groups_count = sh_pfc_get_groups_count, 305 .get_group_name = sh_pfc_get_group_name, 306 .get_group_pins = sh_pfc_get_group_pins, 307 .pin_dbg_show = sh_pfc_pin_dbg_show, 308#ifdef CONFIG_OF 309 .dt_node_to_map = sh_pfc_dt_node_to_map, 310 .dt_free_map = sh_pfc_dt_free_map, 311#endif 312}; 313 314static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev) 315{ 316 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 317 318 return pmx->pfc->info->nr_functions; 319} 320 321static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev, 322 unsigned selector) 323{ 324 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 325 326 return pmx->pfc->info->functions[selector].name; 327} 328 329static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, 330 unsigned selector, 331 const char * const **groups, 332 unsigned * const num_groups) 333{ 334 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 335 336 *groups = pmx->pfc->info->functions[selector].groups; 337 *num_groups = pmx->pfc->info->functions[selector].nr_groups; 338 339 return 0; 340} 341 342static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector, 343 unsigned group) 344{ 345 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 346 struct sh_pfc *pfc = pmx->pfc; 347 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group]; 348 unsigned long flags; 349 unsigned int i; 350 int ret = 0; 351 352 dev_dbg(pctldev->dev, "Configuring pin group %s\n", grp->name); 353 354 spin_lock_irqsave(&pfc->lock, flags); 355 356 for (i = 0; i < grp->nr_pins; ++i) { 357 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); 358 struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; 359 360 /* 361 * This driver cannot manage both gpio and mux when the gpio 362 * pin is already enabled. So, this function fails. 363 */ 364 if (cfg->gpio_enabled) { 365 ret = -EBUSY; 366 goto done; 367 } 368 369 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION); 370 if (ret < 0) 371 goto done; 372 } 373 374 /* All group pins are configured, mark the pins as mux_set */ 375 for (i = 0; i < grp->nr_pins; ++i) { 376 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); 377 struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; 378 379 cfg->mux_set = true; 380 cfg->mux_mark = grp->mux[i]; 381 } 382 383done: 384 spin_unlock_irqrestore(&pfc->lock, flags); 385 return ret; 386} 387 388static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, 389 struct pinctrl_gpio_range *range, 390 unsigned offset) 391{ 392 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 393 struct sh_pfc *pfc = pmx->pfc; 394 int idx = sh_pfc_get_pin_index(pfc, offset); 395 struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; 396 unsigned long flags; 397 int ret; 398 399 spin_lock_irqsave(&pfc->lock, flags); 400 401 if (!pfc->gpio) { 402 /* If GPIOs are handled externally the pin mux type need to be 403 * set to GPIO here. 404 */ 405 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; 406 407 ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO); 408 if (ret < 0) 409 goto done; 410 } 411 412 cfg->gpio_enabled = true; 413 414 ret = 0; 415 416done: 417 spin_unlock_irqrestore(&pfc->lock, flags); 418 419 return ret; 420} 421 422static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, 423 struct pinctrl_gpio_range *range, 424 unsigned offset) 425{ 426 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 427 struct sh_pfc *pfc = pmx->pfc; 428 int idx = sh_pfc_get_pin_index(pfc, offset); 429 struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; 430 unsigned long flags; 431 432 spin_lock_irqsave(&pfc->lock, flags); 433 cfg->gpio_enabled = false; 434 /* If mux is already set, this configures it here */ 435 if (cfg->mux_set) 436 sh_pfc_config_mux(pfc, cfg->mux_mark, PINMUX_TYPE_FUNCTION); 437 spin_unlock_irqrestore(&pfc->lock, flags); 438} 439 440static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, 441 struct pinctrl_gpio_range *range, 442 unsigned offset, bool input) 443{ 444 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 445 struct sh_pfc *pfc = pmx->pfc; 446 int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT; 447 int idx = sh_pfc_get_pin_index(pfc, offset); 448 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; 449 unsigned long flags; 450 unsigned int dir; 451 int ret; 452 453 /* Check if the requested direction is supported by the pin. Not all SoC 454 * provide pin config data, so perform the check conditionally. 455 */ 456 if (pin->configs) { 457 dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT; 458 if (!(pin->configs & dir)) 459 return -EINVAL; 460 } 461 462 spin_lock_irqsave(&pfc->lock, flags); 463 464 ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type); 465 if (ret < 0) 466 goto done; 467 468done: 469 spin_unlock_irqrestore(&pfc->lock, flags); 470 return ret; 471} 472 473static const struct pinmux_ops sh_pfc_pinmux_ops = { 474 .get_functions_count = sh_pfc_get_functions_count, 475 .get_function_name = sh_pfc_get_function_name, 476 .get_function_groups = sh_pfc_get_function_groups, 477 .set_mux = sh_pfc_func_set_mux, 478 .gpio_request_enable = sh_pfc_gpio_request_enable, 479 .gpio_disable_free = sh_pfc_gpio_disable_free, 480 .gpio_set_direction = sh_pfc_gpio_set_direction, 481}; 482 483static u32 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, 484 unsigned int pin, unsigned int *offset, unsigned int *size) 485{ 486 const struct pinmux_drive_reg_field *field; 487 const struct pinmux_drive_reg *reg; 488 unsigned int i; 489 490 for (reg = pfc->info->drive_regs; reg->reg; ++reg) { 491 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) { 492 field = ®->fields[i]; 493 494 if (field->size && field->pin == pin) { 495 *offset = field->offset; 496 *size = field->size; 497 498 return reg->reg; 499 } 500 } 501 } 502 503 return 0; 504} 505 506static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc, 507 unsigned int pin) 508{ 509 unsigned long flags; 510 unsigned int offset; 511 unsigned int size; 512 u32 reg; 513 u32 val; 514 515 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size); 516 if (!reg) 517 return -EINVAL; 518 519 spin_lock_irqsave(&pfc->lock, flags); 520 val = sh_pfc_read(pfc, reg); 521 spin_unlock_irqrestore(&pfc->lock, flags); 522 523 val = (val >> offset) & GENMASK(size - 1, 0); 524 525 /* Convert the value to mA based on a full drive strength value of 24mA. 526 * We can make the full value configurable later if needed. 527 */ 528 return (val + 1) * (size == 2 ? 6 : 3); 529} 530 531static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc, 532 unsigned int pin, u16 strength) 533{ 534 unsigned long flags; 535 unsigned int offset; 536 unsigned int size; 537 unsigned int step; 538 u32 reg; 539 u32 val; 540 541 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size); 542 if (!reg) 543 return -EINVAL; 544 545 step = size == 2 ? 6 : 3; 546 547 if (strength < step || strength > 24) 548 return -EINVAL; 549 550 /* Convert the value from mA based on a full drive strength value of 551 * 24mA. We can make the full value configurable later if needed. 552 */ 553 strength = strength / step - 1; 554 555 spin_lock_irqsave(&pfc->lock, flags); 556 557 val = sh_pfc_read(pfc, reg); 558 val &= ~GENMASK(offset + size - 1, offset); 559 val |= strength << offset; 560 561 sh_pfc_write(pfc, reg, val); 562 563 spin_unlock_irqrestore(&pfc->lock, flags); 564 565 return 0; 566} 567 568/* Check whether the requested parameter is supported for a pin. */ 569static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin, 570 enum pin_config_param param) 571{ 572 int idx = sh_pfc_get_pin_index(pfc, _pin); 573 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; 574 575 switch (param) { 576 case PIN_CONFIG_BIAS_DISABLE: 577 return pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN; 578 579 case PIN_CONFIG_BIAS_PULL_UP: 580 return pin->configs & SH_PFC_PIN_CFG_PULL_UP; 581 582 case PIN_CONFIG_BIAS_PULL_DOWN: 583 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN; 584 585 case PIN_CONFIG_DRIVE_STRENGTH: 586 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH; 587 588 case PIN_CONFIG_POWER_SOURCE: 589 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE; 590 591 default: 592 return false; 593 } 594} 595 596static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, 597 unsigned long *config) 598{ 599 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 600 struct sh_pfc *pfc = pmx->pfc; 601 enum pin_config_param param = pinconf_to_config_param(*config); 602 unsigned long flags; 603 unsigned int arg; 604 605 if (!sh_pfc_pinconf_validate(pfc, _pin, param)) 606 return -ENOTSUPP; 607 608 switch (param) { 609 case PIN_CONFIG_BIAS_DISABLE: 610 case PIN_CONFIG_BIAS_PULL_UP: 611 case PIN_CONFIG_BIAS_PULL_DOWN: { 612 unsigned int bias; 613 614 if (!pfc->info->ops || !pfc->info->ops->get_bias) 615 return -ENOTSUPP; 616 617 spin_lock_irqsave(&pfc->lock, flags); 618 bias = pfc->info->ops->get_bias(pfc, _pin); 619 spin_unlock_irqrestore(&pfc->lock, flags); 620 621 if (bias != param) 622 return -EINVAL; 623 624 arg = 0; 625 break; 626 } 627 628 case PIN_CONFIG_DRIVE_STRENGTH: { 629 int ret; 630 631 ret = sh_pfc_pinconf_get_drive_strength(pfc, _pin); 632 if (ret < 0) 633 return ret; 634 635 arg = ret; 636 break; 637 } 638 639 case PIN_CONFIG_POWER_SOURCE: { 640 u32 pocctrl, val; 641 int bit; 642 643 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl) 644 return -ENOTSUPP; 645 646 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl); 647 if (WARN(bit < 0, "invalid pin %#x", _pin)) 648 return bit; 649 650 spin_lock_irqsave(&pfc->lock, flags); 651 val = sh_pfc_read(pfc, pocctrl); 652 spin_unlock_irqrestore(&pfc->lock, flags); 653 654 arg = (val & BIT(bit)) ? 3300 : 1800; 655 break; 656 } 657 658 default: 659 return -ENOTSUPP; 660 } 661 662 *config = pinconf_to_config_packed(param, arg); 663 return 0; 664} 665 666static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin, 667 unsigned long *configs, unsigned num_configs) 668{ 669 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 670 struct sh_pfc *pfc = pmx->pfc; 671 enum pin_config_param param; 672 unsigned long flags; 673 unsigned int i; 674 675 for (i = 0; i < num_configs; i++) { 676 param = pinconf_to_config_param(configs[i]); 677 678 if (!sh_pfc_pinconf_validate(pfc, _pin, param)) 679 return -ENOTSUPP; 680 681 switch (param) { 682 case PIN_CONFIG_BIAS_PULL_UP: 683 case PIN_CONFIG_BIAS_PULL_DOWN: 684 case PIN_CONFIG_BIAS_DISABLE: 685 if (!pfc->info->ops || !pfc->info->ops->set_bias) 686 return -ENOTSUPP; 687 688 spin_lock_irqsave(&pfc->lock, flags); 689 pfc->info->ops->set_bias(pfc, _pin, param); 690 spin_unlock_irqrestore(&pfc->lock, flags); 691 692 break; 693 694 case PIN_CONFIG_DRIVE_STRENGTH: { 695 unsigned int arg = 696 pinconf_to_config_argument(configs[i]); 697 int ret; 698 699 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg); 700 if (ret < 0) 701 return ret; 702 703 break; 704 } 705 706 case PIN_CONFIG_POWER_SOURCE: { 707 unsigned int mV = pinconf_to_config_argument(configs[i]); 708 u32 pocctrl, val; 709 int bit; 710 711 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl) 712 return -ENOTSUPP; 713 714 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl); 715 if (WARN(bit < 0, "invalid pin %#x", _pin)) 716 return bit; 717 718 if (mV != 1800 && mV != 3300) 719 return -EINVAL; 720 721 spin_lock_irqsave(&pfc->lock, flags); 722 val = sh_pfc_read(pfc, pocctrl); 723 if (mV == 3300) 724 val |= BIT(bit); 725 else 726 val &= ~BIT(bit); 727 sh_pfc_write(pfc, pocctrl, val); 728 spin_unlock_irqrestore(&pfc->lock, flags); 729 730 break; 731 } 732 733 default: 734 return -ENOTSUPP; 735 } 736 } /* for each config */ 737 738 return 0; 739} 740 741static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 742 unsigned long *configs, 743 unsigned num_configs) 744{ 745 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 746 const unsigned int *pins; 747 unsigned int num_pins; 748 unsigned int i, ret; 749 750 pins = pmx->pfc->info->groups[group].pins; 751 num_pins = pmx->pfc->info->groups[group].nr_pins; 752 753 for (i = 0; i < num_pins; ++i) { 754 ret = sh_pfc_pinconf_set(pctldev, pins[i], configs, num_configs); 755 if (ret) 756 return ret; 757 } 758 759 return 0; 760} 761 762static const struct pinconf_ops sh_pfc_pinconf_ops = { 763 .is_generic = true, 764 .pin_config_get = sh_pfc_pinconf_get, 765 .pin_config_set = sh_pfc_pinconf_set, 766 .pin_config_group_set = sh_pfc_pinconf_group_set, 767 .pin_config_config_dbg_show = pinconf_generic_dump_config, 768}; 769 770/* PFC ranges -> pinctrl pin descs */ 771static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) 772{ 773 unsigned int i; 774 775 /* Allocate and initialize the pins and configs arrays. */ 776 pmx->pins = devm_kcalloc(pfc->dev, 777 pfc->info->nr_pins, sizeof(*pmx->pins), 778 GFP_KERNEL); 779 if (unlikely(!pmx->pins)) 780 return -ENOMEM; 781 782 pmx->configs = devm_kcalloc(pfc->dev, 783 pfc->info->nr_pins, sizeof(*pmx->configs), 784 GFP_KERNEL); 785 if (unlikely(!pmx->configs)) 786 return -ENOMEM; 787 788 for (i = 0; i < pfc->info->nr_pins; ++i) { 789 const struct sh_pfc_pin *info = &pfc->info->pins[i]; 790 struct pinctrl_pin_desc *pin = &pmx->pins[i]; 791 792 /* If the pin number is equal to -1 all pins are considered */ 793 pin->number = info->pin != (u16)-1 ? info->pin : i; 794 pin->name = info->name; 795 } 796 797 return 0; 798} 799 800int sh_pfc_register_pinctrl(struct sh_pfc *pfc) 801{ 802 struct sh_pfc_pinctrl *pmx; 803 int ret; 804 805 pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL); 806 if (unlikely(!pmx)) 807 return -ENOMEM; 808 809 pmx->pfc = pfc; 810 811 ret = sh_pfc_map_pins(pfc, pmx); 812 if (ret < 0) 813 return ret; 814 815 pmx->pctl_desc.name = DRV_NAME; 816 pmx->pctl_desc.owner = THIS_MODULE; 817 pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops; 818 pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops; 819 pmx->pctl_desc.confops = &sh_pfc_pinconf_ops; 820 pmx->pctl_desc.pins = pmx->pins; 821 pmx->pctl_desc.npins = pfc->info->nr_pins; 822 823 ret = devm_pinctrl_register_and_init(pfc->dev, &pmx->pctl_desc, pmx, 824 &pmx->pctl); 825 if (ret) { 826 dev_err(pfc->dev, "could not register: %i\n", ret); 827 828 return ret; 829 } 830 831 return pinctrl_enable(pmx->pctl); 832} 833