1// SPDX-License-Identifier: GPL-2.0 2/* 3 * R8A7796 (R-Car M3-W/W+) support - PFC hardware block. 4 * 5 * Copyright (C) 2016-2019 Renesas Electronics Corp. 6 * 7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c 8 * 9 * R-Car Gen3 processor support - PFC hardware block. 10 * 11 * Copyright (C) 2015 Renesas Electronics Corporation 12 */ 13 14#include <linux/errno.h> 15#include <linux/kernel.h> 16 17#include "core.h" 18#include "sh_pfc.h" 19 20#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) 21 22#define CPU_ALL_GP(fn, sfx) \ 23 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ 24 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ 25 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ 26 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 27 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ 28 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ 29 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ 30 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ 31 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 32 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ 33 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ 34 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) 35 36#define CPU_ALL_NOGP(fn) \ 37 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ 38 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ 39 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \ 40 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \ 41 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \ 42 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \ 43 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \ 44 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \ 45 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ 46 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ 47 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ 48 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ 49 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ 50 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \ 51 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ 52 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \ 53 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \ 54 PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \ 55 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ 56 PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \ 57 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ 58 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \ 59 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \ 60 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \ 61 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \ 62 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \ 63 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \ 64 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \ 65 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \ 66 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \ 67 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \ 68 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \ 69 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \ 70 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \ 71 PIN_NOGP_CFG(PRESET_N, "PRESET#", fn, SH_PFC_PIN_CFG_PULL_DOWN),\ 72 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \ 73 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \ 74 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \ 75 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 76 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 77 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ 78 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ 79 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) 80 81/* 82 * F_() : just information 83 * FM() : macro for FN_xxx / xxx_MARK 84 */ 85 86/* GPSR0 */ 87#define GPSR0_15 F_(D15, IP7_11_8) 88#define GPSR0_14 F_(D14, IP7_7_4) 89#define GPSR0_13 F_(D13, IP7_3_0) 90#define GPSR0_12 F_(D12, IP6_31_28) 91#define GPSR0_11 F_(D11, IP6_27_24) 92#define GPSR0_10 F_(D10, IP6_23_20) 93#define GPSR0_9 F_(D9, IP6_19_16) 94#define GPSR0_8 F_(D8, IP6_15_12) 95#define GPSR0_7 F_(D7, IP6_11_8) 96#define GPSR0_6 F_(D6, IP6_7_4) 97#define GPSR0_5 F_(D5, IP6_3_0) 98#define GPSR0_4 F_(D4, IP5_31_28) 99#define GPSR0_3 F_(D3, IP5_27_24) 100#define GPSR0_2 F_(D2, IP5_23_20) 101#define GPSR0_1 F_(D1, IP5_19_16) 102#define GPSR0_0 F_(D0, IP5_15_12) 103 104/* GPSR1 */ 105#define GPSR1_28 FM(CLKOUT) 106#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8) 107#define GPSR1_26 F_(WE1_N, IP5_7_4) 108#define GPSR1_25 F_(WE0_N, IP5_3_0) 109#define GPSR1_24 F_(RD_WR_N, IP4_31_28) 110#define GPSR1_23 F_(RD_N, IP4_27_24) 111#define GPSR1_22 F_(BS_N, IP4_23_20) 112#define GPSR1_21 F_(CS1_N, IP4_19_16) 113#define GPSR1_20 F_(CS0_N, IP4_15_12) 114#define GPSR1_19 F_(A19, IP4_11_8) 115#define GPSR1_18 F_(A18, IP4_7_4) 116#define GPSR1_17 F_(A17, IP4_3_0) 117#define GPSR1_16 F_(A16, IP3_31_28) 118#define GPSR1_15 F_(A15, IP3_27_24) 119#define GPSR1_14 F_(A14, IP3_23_20) 120#define GPSR1_13 F_(A13, IP3_19_16) 121#define GPSR1_12 F_(A12, IP3_15_12) 122#define GPSR1_11 F_(A11, IP3_11_8) 123#define GPSR1_10 F_(A10, IP3_7_4) 124#define GPSR1_9 F_(A9, IP3_3_0) 125#define GPSR1_8 F_(A8, IP2_31_28) 126#define GPSR1_7 F_(A7, IP2_27_24) 127#define GPSR1_6 F_(A6, IP2_23_20) 128#define GPSR1_5 F_(A5, IP2_19_16) 129#define GPSR1_4 F_(A4, IP2_15_12) 130#define GPSR1_3 F_(A3, IP2_11_8) 131#define GPSR1_2 F_(A2, IP2_7_4) 132#define GPSR1_1 F_(A1, IP2_3_0) 133#define GPSR1_0 F_(A0, IP1_31_28) 134 135/* GPSR2 */ 136#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20) 137#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16) 138#define GPSR2_12 F_(AVB_LINK, IP0_15_12) 139#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8) 140#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4) 141#define GPSR2_9 F_(AVB_MDC, IP0_3_0) 142#define GPSR2_8 F_(PWM2_A, IP1_27_24) 143#define GPSR2_7 F_(PWM1_A, IP1_23_20) 144#define GPSR2_6 F_(PWM0, IP1_19_16) 145#define GPSR2_5 F_(IRQ5, IP1_15_12) 146#define GPSR2_4 F_(IRQ4, IP1_11_8) 147#define GPSR2_3 F_(IRQ3, IP1_7_4) 148#define GPSR2_2 F_(IRQ2, IP1_3_0) 149#define GPSR2_1 F_(IRQ1, IP0_31_28) 150#define GPSR2_0 F_(IRQ0, IP0_27_24) 151 152/* GPSR3 */ 153#define GPSR3_15 F_(SD1_WP, IP11_23_20) 154#define GPSR3_14 F_(SD1_CD, IP11_19_16) 155#define GPSR3_13 F_(SD0_WP, IP11_15_12) 156#define GPSR3_12 F_(SD0_CD, IP11_11_8) 157#define GPSR3_11 F_(SD1_DAT3, IP8_31_28) 158#define GPSR3_10 F_(SD1_DAT2, IP8_27_24) 159#define GPSR3_9 F_(SD1_DAT1, IP8_23_20) 160#define GPSR3_8 F_(SD1_DAT0, IP8_19_16) 161#define GPSR3_7 F_(SD1_CMD, IP8_15_12) 162#define GPSR3_6 F_(SD1_CLK, IP8_11_8) 163#define GPSR3_5 F_(SD0_DAT3, IP8_7_4) 164#define GPSR3_4 F_(SD0_DAT2, IP8_3_0) 165#define GPSR3_3 F_(SD0_DAT1, IP7_31_28) 166#define GPSR3_2 F_(SD0_DAT0, IP7_27_24) 167#define GPSR3_1 F_(SD0_CMD, IP7_23_20) 168#define GPSR3_0 F_(SD0_CLK, IP7_19_16) 169 170/* GPSR4 */ 171#define GPSR4_17 F_(SD3_DS, IP11_7_4) 172#define GPSR4_16 F_(SD3_DAT7, IP11_3_0) 173#define GPSR4_15 F_(SD3_DAT6, IP10_31_28) 174#define GPSR4_14 F_(SD3_DAT5, IP10_27_24) 175#define GPSR4_13 F_(SD3_DAT4, IP10_23_20) 176#define GPSR4_12 F_(SD3_DAT3, IP10_19_16) 177#define GPSR4_11 F_(SD3_DAT2, IP10_15_12) 178#define GPSR4_10 F_(SD3_DAT1, IP10_11_8) 179#define GPSR4_9 F_(SD3_DAT0, IP10_7_4) 180#define GPSR4_8 F_(SD3_CMD, IP10_3_0) 181#define GPSR4_7 F_(SD3_CLK, IP9_31_28) 182#define GPSR4_6 F_(SD2_DS, IP9_27_24) 183#define GPSR4_5 F_(SD2_DAT3, IP9_23_20) 184#define GPSR4_4 F_(SD2_DAT2, IP9_19_16) 185#define GPSR4_3 F_(SD2_DAT1, IP9_15_12) 186#define GPSR4_2 F_(SD2_DAT0, IP9_11_8) 187#define GPSR4_1 F_(SD2_CMD, IP9_7_4) 188#define GPSR4_0 F_(SD2_CLK, IP9_3_0) 189 190/* GPSR5 */ 191#define GPSR5_25 F_(MLB_DAT, IP14_19_16) 192#define GPSR5_24 F_(MLB_SIG, IP14_15_12) 193#define GPSR5_23 F_(MLB_CLK, IP14_11_8) 194#define GPSR5_22 FM(MSIOF0_RXD) 195#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4) 196#define GPSR5_20 FM(MSIOF0_TXD) 197#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0) 198#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28) 199#define GPSR5_17 FM(MSIOF0_SCK) 200#define GPSR5_16 F_(HRTS0_N, IP13_27_24) 201#define GPSR5_15 F_(HCTS0_N, IP13_23_20) 202#define GPSR5_14 F_(HTX0, IP13_19_16) 203#define GPSR5_13 F_(HRX0, IP13_15_12) 204#define GPSR5_12 F_(HSCK0, IP13_11_8) 205#define GPSR5_11 F_(RX2_A, IP13_7_4) 206#define GPSR5_10 F_(TX2_A, IP13_3_0) 207#define GPSR5_9 F_(SCK2, IP12_31_28) 208#define GPSR5_8 F_(RTS1_N, IP12_27_24) 209#define GPSR5_7 F_(CTS1_N, IP12_23_20) 210#define GPSR5_6 F_(TX1_A, IP12_19_16) 211#define GPSR5_5 F_(RX1_A, IP12_15_12) 212#define GPSR5_4 F_(RTS0_N, IP12_11_8) 213#define GPSR5_3 F_(CTS0_N, IP12_7_4) 214#define GPSR5_2 F_(TX0, IP12_3_0) 215#define GPSR5_1 F_(RX0, IP11_31_28) 216#define GPSR5_0 F_(SCK0, IP11_27_24) 217 218/* GPSR6 */ 219#define GPSR6_31 F_(GP6_31, IP18_7_4) 220#define GPSR6_30 F_(GP6_30, IP18_3_0) 221#define GPSR6_29 F_(USB30_OVC, IP17_31_28) 222#define GPSR6_28 F_(USB30_PWEN, IP17_27_24) 223#define GPSR6_27 F_(USB1_OVC, IP17_23_20) 224#define GPSR6_26 F_(USB1_PWEN, IP17_19_16) 225#define GPSR6_25 F_(USB0_OVC, IP17_15_12) 226#define GPSR6_24 F_(USB0_PWEN, IP17_11_8) 227#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4) 228#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0) 229#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28) 230#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24) 231#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20) 232#define GPSR6_18 F_(SSI_WS78, IP16_19_16) 233#define GPSR6_17 F_(SSI_SCK78, IP16_15_12) 234#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8) 235#define GPSR6_15 F_(SSI_WS6, IP16_7_4) 236#define GPSR6_14 F_(SSI_SCK6, IP16_3_0) 237#define GPSR6_13 FM(SSI_SDATA5) 238#define GPSR6_12 FM(SSI_WS5) 239#define GPSR6_11 FM(SSI_SCK5) 240#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28) 241#define GPSR6_9 F_(SSI_WS4, IP15_27_24) 242#define GPSR6_8 F_(SSI_SCK4, IP15_23_20) 243#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16) 244#define GPSR6_6 F_(SSI_WS349, IP15_15_12) 245#define GPSR6_5 F_(SSI_SCK349, IP15_11_8) 246#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4) 247#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0) 248#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28) 249#define GPSR6_1 F_(SSI_WS01239, IP14_27_24) 250#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20) 251 252/* GPSR7 */ 253#define GPSR7_3 FM(GP7_03) 254#define GPSR7_2 FM(GP7_02) 255#define GPSR7_1 FM(AVS2) 256#define GPSR7_0 FM(AVS1) 257 258 259/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 260#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 261#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 262#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 263#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 264#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 265#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 266#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 269#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 274#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 275#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 276#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 277#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 278#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 279#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 280#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 281#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 282#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 283#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 284#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 285#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 286#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 287 288/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 289#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 290#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 291#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 292#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 293#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 294#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 295#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 296#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 297#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 298#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 299#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 300#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 301#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 302#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 303#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 304#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 305#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 306#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 307#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 308#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 309#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 310#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 311#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 312#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 313#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 314#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 315#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 316#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 317#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 318 319/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 320#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 321#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 322#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 323#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 324#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 325#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 326#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 327#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 328#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 329#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 330#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 331#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 332#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 333#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 334#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 335#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 336#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 337#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 338#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 339#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 340#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 341#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 342#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 343#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 344#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 345#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 346#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 347#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 348#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 349#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 350#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 351#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 352#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 353#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 354 355/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 356#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 357#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 358#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 359#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 360#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 361#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 362#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 363#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 364#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 365#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 366#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 367#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 368#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 369#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 370#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 371#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 372#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 373#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 374#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 375#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 376#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0) 377#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 378#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 379#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 380#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 381#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 382#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 383#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 384 385/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 386#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 387#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 388#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 389#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 390#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 391#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 392#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 393#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 394#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 395#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 396#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 397#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 398#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 399#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 400#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 401#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 402#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 403#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 404#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 405#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) 406#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) 407#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0) 408#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0) 409#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0) 410#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 411#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0) 412#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0) 413 414#define PINMUX_GPSR \ 415\ 416 GPSR6_31 \ 417 GPSR6_30 \ 418 GPSR6_29 \ 419 GPSR1_28 GPSR6_28 \ 420 GPSR1_27 GPSR6_27 \ 421 GPSR1_26 GPSR6_26 \ 422 GPSR1_25 GPSR5_25 GPSR6_25 \ 423 GPSR1_24 GPSR5_24 GPSR6_24 \ 424 GPSR1_23 GPSR5_23 GPSR6_23 \ 425 GPSR1_22 GPSR5_22 GPSR6_22 \ 426 GPSR1_21 GPSR5_21 GPSR6_21 \ 427 GPSR1_20 GPSR5_20 GPSR6_20 \ 428 GPSR1_19 GPSR5_19 GPSR6_19 \ 429 GPSR1_18 GPSR5_18 GPSR6_18 \ 430 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \ 431 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \ 432GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \ 433GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \ 434GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \ 435GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \ 436GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \ 437GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \ 438GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ 439GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ 440GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ 441GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ 442GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ 443GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ 444GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \ 445GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \ 446GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \ 447GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 448 449#define PINMUX_IPSR \ 450\ 451FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ 452FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ 453FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ 454FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ 455FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ 456FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ 457FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 458FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ 459\ 460FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ 461FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ 462FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ 463FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \ 464FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ 465FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ 466FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 467FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 468\ 469FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ 470FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ 471FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ 472FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ 473FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ 474FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ 475FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ 476FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ 477\ 478FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \ 479FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \ 480FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \ 481FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \ 482FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \ 483FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \ 484FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ 485FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \ 486\ 487FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \ 488FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \ 489FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \ 490FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \ 491FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \ 492FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \ 493FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \ 494FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 495 496/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 497#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0) 498#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3) 499#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0) 500#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1) 501#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1) 502#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1) 503#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1) 504#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) 505#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) 506#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) 507#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0) 508#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) 509#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) 510#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) 511#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) 512#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) 513#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) 514#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3) 515 516/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 517#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) 518#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0) 519#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) 520#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3) 521#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0) 522#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1) 523#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1) 524#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3) 525#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1) 526#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0) 527#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) 528#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) 529#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) 530#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1) 531#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) 532#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1) 533#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1) 534#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1) 535#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1) 536#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1) 537#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1) 538#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1) 539 540/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 541#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1) 542#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1) 543#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1) 544#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) 545#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) 546#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 547#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1) 548#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) 549#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) 550#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) 551#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1) 552#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1) 553#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) 554 555#define PINMUX_MOD_SELS \ 556\ 557MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \ 558 MOD_SEL2_30 \ 559 MOD_SEL1_29_28_27 MOD_SEL2_29 \ 560MOD_SEL0_28_27 MOD_SEL2_28_27 \ 561MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \ 562 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \ 563MOD_SEL0_23 MOD_SEL1_23_22_21 \ 564MOD_SEL0_22 MOD_SEL2_22 \ 565MOD_SEL0_21 MOD_SEL2_21 \ 566MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \ 567MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \ 568MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \ 569 MOD_SEL2_17 \ 570MOD_SEL0_16 MOD_SEL1_16 \ 571 MOD_SEL1_15_14 \ 572MOD_SEL0_14_13 \ 573 MOD_SEL1_13 \ 574MOD_SEL0_12 MOD_SEL1_12 \ 575MOD_SEL0_11 MOD_SEL1_11 \ 576MOD_SEL0_10 MOD_SEL1_10 \ 577MOD_SEL0_9_8 MOD_SEL1_9 \ 578MOD_SEL0_7_6 \ 579 MOD_SEL1_6 \ 580MOD_SEL0_5 MOD_SEL1_5 \ 581MOD_SEL0_4_3 MOD_SEL1_4 \ 582 MOD_SEL1_3 \ 583 MOD_SEL1_2 \ 584 MOD_SEL1_1 \ 585 MOD_SEL1_0 MOD_SEL2_0 586 587/* 588 * These pins are not able to be muxed but have other properties 589 * that can be set, such as drive-strength or pull-up/pull-down enable. 590 */ 591#define PINMUX_STATIC \ 592 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \ 593 FM(QSPI0_IO2) FM(QSPI0_IO3) \ 594 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \ 595 FM(QSPI1_IO2) FM(QSPI1_IO3) \ 596 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \ 597 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \ 598 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \ 599 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ 600 FM(PRESETOUT) \ 601 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \ 602 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) 603 604#define PINMUX_PHYS \ 605 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5) 606 607enum { 608 PINMUX_RESERVED = 0, 609 610 PINMUX_DATA_BEGIN, 611 GP_ALL(DATA), 612 PINMUX_DATA_END, 613 614#define F_(x, y) 615#define FM(x) FN_##x, 616 PINMUX_FUNCTION_BEGIN, 617 GP_ALL(FN), 618 PINMUX_GPSR 619 PINMUX_IPSR 620 PINMUX_MOD_SELS 621 PINMUX_FUNCTION_END, 622#undef F_ 623#undef FM 624 625#define F_(x, y) 626#define FM(x) x##_MARK, 627 PINMUX_MARK_BEGIN, 628 PINMUX_GPSR 629 PINMUX_IPSR 630 PINMUX_MOD_SELS 631 PINMUX_STATIC 632 PINMUX_PHYS 633 PINMUX_MARK_END, 634#undef F_ 635#undef FM 636}; 637 638static const u16 pinmux_data[] = { 639 PINMUX_DATA_GP_ALL(), 640 641 PINMUX_SINGLE(AVS1), 642 PINMUX_SINGLE(AVS2), 643 PINMUX_SINGLE(CLKOUT), 644 PINMUX_SINGLE(GP7_03), 645 PINMUX_SINGLE(GP7_02), 646 PINMUX_SINGLE(MSIOF0_RXD), 647 PINMUX_SINGLE(MSIOF0_SCK), 648 PINMUX_SINGLE(MSIOF0_TXD), 649 PINMUX_SINGLE(SSI_SCK5), 650 PINMUX_SINGLE(SSI_SDATA5), 651 PINMUX_SINGLE(SSI_WS5), 652 653 /* IPSR0 */ 654 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC), 655 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2), 656 657 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC), 658 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2), 659 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0), 660 661 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT), 662 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2), 663 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0), 664 665 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK), 666 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), 667 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), 668 669 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), 670 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), 671 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), 672 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1), 673 674 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), 675 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), 676 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), 677 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), 678 679 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), 680 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), 681 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE), 682 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1), 683 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1), 684 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1), 685 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4), 686 687 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1), 688 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA), 689 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP), 690 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1), 691 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1), 692 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1), 693 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4), 694 695 /* IPSR1 */ 696 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2), 697 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE), 698 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE), 699 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1), 700 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1), 701 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4), 702 703 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3), 704 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE), 705 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1), 706 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1), 707 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1), 708 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4), 709 710 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), 711 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS), 712 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC), 713 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1), 714 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1), 715 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4), 716 717 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5), 718 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE), 719 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC), 720 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1), 721 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1), 722 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4), 723 724 PINMUX_IPSR_GPSR(IP1_19_16, PWM0), 725 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS), 726 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), 727 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), 728 729 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), 730 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), 731 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), 732 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), 733 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1), 734 735 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), 736 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), 737 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), 738 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), 739 740 PINMUX_IPSR_GPSR(IP1_31_28, A0), 741 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), 742 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1), 743 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8), 744 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0), 745 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0), 746 747 /* IPSR2 */ 748 PINMUX_IPSR_GPSR(IP2_3_0, A1), 749 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17), 750 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1), 751 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9), 752 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1), 753 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0), 754 755 PINMUX_IPSR_GPSR(IP2_7_4, A2), 756 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18), 757 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1), 758 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10), 759 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2), 760 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0), 761 762 PINMUX_IPSR_GPSR(IP2_11_8, A3), 763 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19), 764 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1), 765 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11), 766 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3), 767 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0), 768 769 PINMUX_IPSR_GPSR(IP2_15_12, A4), 770 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20), 771 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1), 772 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12), 773 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12), 774 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4), 775 776 PINMUX_IPSR_GPSR(IP2_19_16, A5), 777 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21), 778 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1), 779 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1), 780 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13), 781 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13), 782 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5), 783 784 PINMUX_IPSR_GPSR(IP2_23_20, A6), 785 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22), 786 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0), 787 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1), 788 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14), 789 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14), 790 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6), 791 792 PINMUX_IPSR_GPSR(IP2_27_24, A7), 793 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23), 794 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0), 795 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1), 796 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15), 797 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15), 798 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7), 799 800 PINMUX_IPSR_GPSR(IP2_31_28, A8), 801 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1), 802 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0), 803 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1), 804 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0), 805 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1), 806 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1), 807 808 /* IPSR3 */ 809 PINMUX_IPSR_GPSR(IP3_3_0, A9), 810 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0), 811 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1), 812 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N), 813 814 PINMUX_IPSR_GPSR(IP3_7_4, A10), 815 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), 816 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1), 817 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), 818 819 PINMUX_IPSR_GPSR(IP3_11_8, A11), 820 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1), 821 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0), 822 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1), 823 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4), 824 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD), 825 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0), 826 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1), 827 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1), 828 829 PINMUX_IPSR_GPSR(IP3_15_12, A12), 830 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12), 831 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2), 832 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0), 833 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8), 834 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4), 835 836 PINMUX_IPSR_GPSR(IP3_19_16, A13), 837 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13), 838 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2), 839 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0), 840 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9), 841 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5), 842 843 PINMUX_IPSR_GPSR(IP3_23_20, A14), 844 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14), 845 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2), 846 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N), 847 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10), 848 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6), 849 850 PINMUX_IPSR_GPSR(IP3_27_24, A15), 851 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15), 852 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2), 853 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N), 854 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11), 855 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7), 856 857 PINMUX_IPSR_GPSR(IP3_31_28, A16), 858 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8), 859 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD), 860 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0), 861 862 /* IPSR4 */ 863 PINMUX_IPSR_GPSR(IP4_3_0, A17), 864 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9), 865 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N), 866 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1), 867 868 PINMUX_IPSR_GPSR(IP4_7_4, A18), 869 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10), 870 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N), 871 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2), 872 873 PINMUX_IPSR_GPSR(IP4_11_8, A19), 874 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11), 875 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB), 876 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3), 877 878 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N), 879 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB), 880 881 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N), 882 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK), 883 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1), 884 885 PINMUX_IPSR_GPSR(IP4_23_20, BS_N), 886 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS), 887 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3), 888 PINMUX_IPSR_GPSR(IP4_23_20, SCK3), 889 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3), 890 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX), 891 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX), 892 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0), 893 894 PINMUX_IPSR_GPSR(IP4_27_24, RD_N), 895 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3), 896 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0), 897 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0), 898 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0), 899 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0), 900 901 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N), 902 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3), 903 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0), 904 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0), 905 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0), 906 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0), 907 908 /* IPSR5 */ 909 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N), 910 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3), 911 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N), 912 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N), 913 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1), 914 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK), 915 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0), 916 917 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), 918 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), 919 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N), 920 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), 921 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), 922 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), 923 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX), 924 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0), 925 926 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0), 927 PINMUX_IPSR_GPSR(IP5_11_8, QCLK), 928 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK), 929 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0), 930 931 PINMUX_IPSR_GPSR(IP5_15_12, D0), 932 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1), 933 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0), 934 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16), 935 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0), 936 937 PINMUX_IPSR_GPSR(IP5_19_16, D1), 938 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1), 939 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0), 940 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17), 941 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1), 942 943 PINMUX_IPSR_GPSR(IP5_23_20, D2), 944 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0), 945 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18), 946 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2), 947 948 PINMUX_IPSR_GPSR(IP5_27_24, D3), 949 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0), 950 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19), 951 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3), 952 953 PINMUX_IPSR_GPSR(IP5_31_28, D4), 954 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1), 955 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20), 956 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4), 957 958 /* IPSR6 */ 959 PINMUX_IPSR_GPSR(IP6_3_0, D5), 960 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), 961 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21), 962 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5), 963 964 PINMUX_IPSR_GPSR(IP6_7_4, D6), 965 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1), 966 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22), 967 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6), 968 969 PINMUX_IPSR_GPSR(IP6_11_8, D7), 970 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1), 971 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23), 972 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7), 973 974 PINMUX_IPSR_GPSR(IP6_15_12, D8), 975 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0), 976 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3), 977 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2), 978 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0), 979 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0), 980 981 PINMUX_IPSR_GPSR(IP6_19_16, D9), 982 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1), 983 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3), 984 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0), 985 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1), 986 987 PINMUX_IPSR_GPSR(IP6_23_20, D10), 988 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2), 989 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3), 990 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1), 991 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0), 992 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2), 993 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2), 994 995 PINMUX_IPSR_GPSR(IP6_27_24, D11), 996 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3), 997 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), 998 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), 999 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), 1000 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2), 1001 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), 1002 1003 PINMUX_IPSR_GPSR(IP6_31_28, D12), 1004 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4), 1005 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3), 1006 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2), 1007 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0), 1008 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4), 1009 1010 /* IPSR7 */ 1011 PINMUX_IPSR_GPSR(IP7_3_0, D13), 1012 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5), 1013 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3), 1014 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2), 1015 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0), 1016 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5), 1017 1018 PINMUX_IPSR_GPSR(IP7_7_4, D14), 1019 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6), 1020 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0), 1021 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2), 1022 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0), 1023 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6), 1024 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2), 1025 1026 PINMUX_IPSR_GPSR(IP7_11_8, D15), 1027 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7), 1028 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0), 1029 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2), 1030 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0), 1031 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7), 1032 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), 1033 1034 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK), 1035 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), 1036 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), 1037 1038 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD), 1039 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4), 1040 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1), 1041 1042 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0), 1043 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4), 1044 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1), 1045 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1), 1046 1047 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1), 1048 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4), 1049 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1), 1050 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1), 1051 1052 /* IPSR8 */ 1053 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2), 1054 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4), 1055 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1), 1056 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1), 1057 1058 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3), 1059 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4), 1060 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1), 1061 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1), 1062 1063 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK), 1064 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6), 1065 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0), 1066 1067 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), 1068 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), 1069 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1), 1070 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), 1071 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), 1072 1073 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), 1074 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), 1075 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), 1076 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1), 1077 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), 1078 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), 1079 1080 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), 1081 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), 1082 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), 1083 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), 1084 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), 1085 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), 1086 1087 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), 1088 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), 1089 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), 1090 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), 1091 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), 1092 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), 1093 1094 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), 1095 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), 1096 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), 1097 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1), 1098 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), 1099 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), 1100 1101 /* IPSR9 */ 1102 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK), 1103 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8), 1104 1105 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD), 1106 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9), 1107 1108 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0), 1109 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10), 1110 1111 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1), 1112 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11), 1113 1114 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2), 1115 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12), 1116 1117 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3), 1118 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13), 1119 1120 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS), 1121 PINMUX_IPSR_GPSR(IP9_27_24, NFALE), 1122 1123 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK), 1124 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N), 1125 1126 /* IPSR10 */ 1127 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD), 1128 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N), 1129 1130 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0), 1131 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0), 1132 1133 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1), 1134 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1), 1135 1136 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2), 1137 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2), 1138 1139 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3), 1140 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3), 1141 1142 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4), 1143 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0), 1144 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4), 1145 1146 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5), 1147 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0), 1148 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5), 1149 1150 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6), 1151 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD), 1152 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6), 1153 1154 /* IPSR11 */ 1155 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7), 1156 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP), 1157 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7), 1158 1159 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS), 1160 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), 1161 1162 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), 1163 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0), 1164 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), 1165 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), 1166 1167 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), 1168 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0), 1169 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), 1170 1171 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0), 1172 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0), 1173 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1174 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1), 1175 1176 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0), 1177 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0), 1178 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1179 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1), 1180 1181 PINMUX_IPSR_GPSR(IP11_27_24, SCK0), 1182 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), 1183 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), 1184 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1), 1185 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), 1186 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), 1187 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), 1188 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1), 1189 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2), 1190 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1), 1191 1192 PINMUX_IPSR_GPSR(IP11_31_28, RX0), 1193 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1), 1194 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2), 1195 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2), 1196 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1), 1197 1198 /* IPSR12 */ 1199 PINMUX_IPSR_GPSR(IP12_3_0, TX0), 1200 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1), 1201 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2), 1202 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2), 1203 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1), 1204 1205 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N), 1206 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1), 1207 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1), 1208 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2), 1209 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2), 1210 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1), 1211 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C), 1212 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP), 1213 1214 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), 1215 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), 1216 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), 1217 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1), 1218 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), 1219 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), 1220 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), 1221 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1), 1222 1223 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0), 1224 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0), 1225 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2), 1226 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2), 1227 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2), 1228 1229 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0), 1230 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0), 1231 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2), 1232 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2), 1233 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2), 1234 1235 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N), 1236 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0), 1237 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1), 1238 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2), 1239 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2), 1240 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1), 1241 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA), 1242 1243 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N), 1244 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0), 1245 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), 1246 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2), 1247 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2), 1248 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1), 1249 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0), 1250 1251 PINMUX_IPSR_GPSR(IP12_31_28, SCK2), 1252 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1), 1253 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), 1254 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2), 1255 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), 1256 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1), 1257 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK), 1258 1259 /* IPSR13 */ 1260 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0), 1261 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1), 1262 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0), 1263 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0), 1264 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2), 1265 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N), 1266 1267 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0), 1268 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1), 1269 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0), 1270 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0), 1271 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2), 1272 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N), 1273 1274 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), 1275 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), 1276 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0), 1277 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), 1278 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), 1279 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), 1280 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2), 1281 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1), 1282 1283 PINMUX_IPSR_GPSR(IP13_15_12, HRX0), 1284 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3), 1285 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1), 1286 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3), 1287 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3), 1288 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2), 1289 1290 PINMUX_IPSR_GPSR(IP13_19_16, HTX0), 1291 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3), 1292 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1), 1293 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3), 1294 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3), 1295 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2), 1296 1297 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N), 1298 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1), 1299 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3), 1300 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0), 1301 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3), 1302 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3), 1303 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2), 1304 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A), 1305 1306 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N), 1307 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1), 1308 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3), 1309 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0), 1310 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3), 1311 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0), 1312 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A), 1313 1314 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC), 1315 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A), 1316 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1), 1317 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3), 1318 1319 /* IPSR14 */ 1320 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), 1321 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), 1322 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0), 1323 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2), 1324 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), 1325 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), 1326 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), 1327 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1), 1328 1329 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), 1330 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), 1331 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), 1332 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0), 1333 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), 1334 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), 1335 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), 1336 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1), 1337 1338 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK), 1339 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5), 1340 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1), 1341 1342 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG), 1343 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1), 1344 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5), 1345 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1), 1346 1347 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT), 1348 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1), 1349 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5), 1350 1351 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239), 1352 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5), 1353 1354 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239), 1355 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5), 1356 1357 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0), 1358 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5), 1359 1360 /* IPSR15 */ 1361 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0), 1362 1363 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0), 1364 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1), 1365 1366 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349), 1367 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), 1368 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0), 1369 1370 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349), 1371 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0), 1372 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0), 1373 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0), 1374 1375 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3), 1376 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), 1377 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0), 1378 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0), 1379 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0), 1380 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0), 1381 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0), 1382 1383 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4), 1384 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0), 1385 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0), 1386 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0), 1387 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0), 1388 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0), 1389 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0), 1390 1391 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4), 1392 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0), 1393 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0), 1394 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0), 1395 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0), 1396 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0), 1397 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0), 1398 1399 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4), 1400 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0), 1401 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0), 1402 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0), 1403 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0), 1404 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0), 1405 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0), 1406 1407 /* IPSR16 */ 1408 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6), 1409 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3), 1410 1411 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6), 1412 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3), 1413 1414 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6), 1415 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3), 1416 1417 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78), 1418 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1), 1419 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2), 1420 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0), 1421 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0), 1422 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0), 1423 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0), 1424 1425 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78), 1426 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1), 1427 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2), 1428 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0), 1429 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0), 1430 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0), 1431 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0), 1432 1433 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7), 1434 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1), 1435 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2), 1436 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0), 1437 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0), 1438 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0), 1439 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0), 1440 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0), 1441 1442 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8), 1443 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1), 1444 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2), 1445 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0), 1446 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0), 1447 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0), 1448 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0), 1449 1450 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0), 1451 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1), 1452 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2), 1453 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0), 1454 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1), 1455 PINMUX_IPSR_GPSR(IP16_31_28, SCK1), 1456 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), 1457 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), 1458 1459 /* IPSR17 */ 1460 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0), 1461 1462 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1), 1463 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), 1464 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), 1465 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), 1466 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0), 1467 1468 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN), 1469 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2), 1470 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3), 1471 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3), 1472 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1), 1473 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1), 1474 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2), 1475 1476 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC), 1477 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2), 1478 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3), 1479 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3), 1480 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1), 1481 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2), 1482 1483 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN), 1484 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2), 1485 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0), 1486 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4), 1487 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4), 1488 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1), 1489 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1), 1490 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0), 1491 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2), 1492 1493 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC), 1494 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2), 1495 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0), 1496 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4), 1497 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4), 1498 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1), 1499 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1), 1500 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1), 1501 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2), 1502 1503 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN), 1504 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B), 1505 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1), 1506 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3), 1507 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3), 1508 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), 1509 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1), 1510 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1), 1511 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0), 1512 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2), 1513 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2), 1514 1515 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC), 1516 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B), 1517 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1), 1518 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3), 1519 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3), 1520 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), 1521 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1), 1522 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N), 1523 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1), 1524 1525 /* IPSR18 */ 1526 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30), 1527 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B), 1528 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1), 1529 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4), 1530 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), 1531 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1), 1532 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2), 1533 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2), 1534 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3), 1535 1536 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31), 1537 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B), 1538 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1), 1539 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), 1540 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), 1541 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1), 1542 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3), 1543 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), 1544 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), 1545 1546/* 1547 * Static pins can not be muxed between different functions but 1548 * still need mark entries in the pinmux list. Add each static 1549 * pin to the list without an associated function. The sh-pfc 1550 * core will do the right thing and skip trying to mux the pin 1551 * while still applying configuration to it. 1552 */ 1553#define FM(x) PINMUX_DATA(x##_MARK, 0), 1554 PINMUX_STATIC 1555#undef FM 1556}; 1557 1558/* 1559 * Pins not associated with a GPIO port. 1560 */ 1561enum { 1562 GP_ASSIGN_LAST(), 1563 NOGP_ALL(), 1564}; 1565 1566static const struct sh_pfc_pin pinmux_pins[] = { 1567 PINMUX_GPIO_GP_ALL(), 1568 PINMUX_NOGP_ALL(), 1569}; 1570 1571/* - AUDIO CLOCK ------------------------------------------------------------ */ 1572static const unsigned int audio_clk_a_a_pins[] = { 1573 /* CLK A */ 1574 RCAR_GP_PIN(6, 22), 1575}; 1576static const unsigned int audio_clk_a_a_mux[] = { 1577 AUDIO_CLKA_A_MARK, 1578}; 1579static const unsigned int audio_clk_a_b_pins[] = { 1580 /* CLK A */ 1581 RCAR_GP_PIN(5, 4), 1582}; 1583static const unsigned int audio_clk_a_b_mux[] = { 1584 AUDIO_CLKA_B_MARK, 1585}; 1586static const unsigned int audio_clk_a_c_pins[] = { 1587 /* CLK A */ 1588 RCAR_GP_PIN(5, 19), 1589}; 1590static const unsigned int audio_clk_a_c_mux[] = { 1591 AUDIO_CLKA_C_MARK, 1592}; 1593static const unsigned int audio_clk_b_a_pins[] = { 1594 /* CLK B */ 1595 RCAR_GP_PIN(5, 12), 1596}; 1597static const unsigned int audio_clk_b_a_mux[] = { 1598 AUDIO_CLKB_A_MARK, 1599}; 1600static const unsigned int audio_clk_b_b_pins[] = { 1601 /* CLK B */ 1602 RCAR_GP_PIN(6, 23), 1603}; 1604static const unsigned int audio_clk_b_b_mux[] = { 1605 AUDIO_CLKB_B_MARK, 1606}; 1607static const unsigned int audio_clk_c_a_pins[] = { 1608 /* CLK C */ 1609 RCAR_GP_PIN(5, 21), 1610}; 1611static const unsigned int audio_clk_c_a_mux[] = { 1612 AUDIO_CLKC_A_MARK, 1613}; 1614static const unsigned int audio_clk_c_b_pins[] = { 1615 /* CLK C */ 1616 RCAR_GP_PIN(5, 0), 1617}; 1618static const unsigned int audio_clk_c_b_mux[] = { 1619 AUDIO_CLKC_B_MARK, 1620}; 1621static const unsigned int audio_clkout_a_pins[] = { 1622 /* CLKOUT */ 1623 RCAR_GP_PIN(5, 18), 1624}; 1625static const unsigned int audio_clkout_a_mux[] = { 1626 AUDIO_CLKOUT_A_MARK, 1627}; 1628static const unsigned int audio_clkout_b_pins[] = { 1629 /* CLKOUT */ 1630 RCAR_GP_PIN(6, 28), 1631}; 1632static const unsigned int audio_clkout_b_mux[] = { 1633 AUDIO_CLKOUT_B_MARK, 1634}; 1635static const unsigned int audio_clkout_c_pins[] = { 1636 /* CLKOUT */ 1637 RCAR_GP_PIN(5, 3), 1638}; 1639static const unsigned int audio_clkout_c_mux[] = { 1640 AUDIO_CLKOUT_C_MARK, 1641}; 1642static const unsigned int audio_clkout_d_pins[] = { 1643 /* CLKOUT */ 1644 RCAR_GP_PIN(5, 21), 1645}; 1646static const unsigned int audio_clkout_d_mux[] = { 1647 AUDIO_CLKOUT_D_MARK, 1648}; 1649static const unsigned int audio_clkout1_a_pins[] = { 1650 /* CLKOUT1 */ 1651 RCAR_GP_PIN(5, 15), 1652}; 1653static const unsigned int audio_clkout1_a_mux[] = { 1654 AUDIO_CLKOUT1_A_MARK, 1655}; 1656static const unsigned int audio_clkout1_b_pins[] = { 1657 /* CLKOUT1 */ 1658 RCAR_GP_PIN(6, 29), 1659}; 1660static const unsigned int audio_clkout1_b_mux[] = { 1661 AUDIO_CLKOUT1_B_MARK, 1662}; 1663static const unsigned int audio_clkout2_a_pins[] = { 1664 /* CLKOUT2 */ 1665 RCAR_GP_PIN(5, 16), 1666}; 1667static const unsigned int audio_clkout2_a_mux[] = { 1668 AUDIO_CLKOUT2_A_MARK, 1669}; 1670static const unsigned int audio_clkout2_b_pins[] = { 1671 /* CLKOUT2 */ 1672 RCAR_GP_PIN(6, 30), 1673}; 1674static const unsigned int audio_clkout2_b_mux[] = { 1675 AUDIO_CLKOUT2_B_MARK, 1676}; 1677 1678static const unsigned int audio_clkout3_a_pins[] = { 1679 /* CLKOUT3 */ 1680 RCAR_GP_PIN(5, 19), 1681}; 1682static const unsigned int audio_clkout3_a_mux[] = { 1683 AUDIO_CLKOUT3_A_MARK, 1684}; 1685static const unsigned int audio_clkout3_b_pins[] = { 1686 /* CLKOUT3 */ 1687 RCAR_GP_PIN(6, 31), 1688}; 1689static const unsigned int audio_clkout3_b_mux[] = { 1690 AUDIO_CLKOUT3_B_MARK, 1691}; 1692 1693/* - EtherAVB --------------------------------------------------------------- */ 1694static const unsigned int avb_link_pins[] = { 1695 /* AVB_LINK */ 1696 RCAR_GP_PIN(2, 12), 1697}; 1698static const unsigned int avb_link_mux[] = { 1699 AVB_LINK_MARK, 1700}; 1701static const unsigned int avb_magic_pins[] = { 1702 /* AVB_MAGIC_ */ 1703 RCAR_GP_PIN(2, 10), 1704}; 1705static const unsigned int avb_magic_mux[] = { 1706 AVB_MAGIC_MARK, 1707}; 1708static const unsigned int avb_phy_int_pins[] = { 1709 /* AVB_PHY_INT */ 1710 RCAR_GP_PIN(2, 11), 1711}; 1712static const unsigned int avb_phy_int_mux[] = { 1713 AVB_PHY_INT_MARK, 1714}; 1715static const unsigned int avb_mdio_pins[] = { 1716 /* AVB_MDC, AVB_MDIO */ 1717 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO, 1718}; 1719static const unsigned int avb_mdio_mux[] = { 1720 AVB_MDC_MARK, AVB_MDIO_MARK, 1721}; 1722static const unsigned int avb_mii_pins[] = { 1723 /* 1724 * AVB_TX_CTL, AVB_TXC, AVB_TD0, 1725 * AVB_TD1, AVB_TD2, AVB_TD3, 1726 * AVB_RX_CTL, AVB_RXC, AVB_RD0, 1727 * AVB_RD1, AVB_RD2, AVB_RD3, 1728 * AVB_TXCREFCLK 1729 */ 1730 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0, 1731 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3, 1732 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0, 1733 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3, 1734 PIN_AVB_TXCREFCLK, 1735}; 1736static const unsigned int avb_mii_mux[] = { 1737 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK, 1738 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK, 1739 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK, 1740 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, 1741 AVB_TXCREFCLK_MARK, 1742}; 1743static const unsigned int avb_avtp_pps_pins[] = { 1744 /* AVB_AVTP_PPS */ 1745 RCAR_GP_PIN(2, 6), 1746}; 1747static const unsigned int avb_avtp_pps_mux[] = { 1748 AVB_AVTP_PPS_MARK, 1749}; 1750static const unsigned int avb_avtp_match_a_pins[] = { 1751 /* AVB_AVTP_MATCH_A */ 1752 RCAR_GP_PIN(2, 13), 1753}; 1754static const unsigned int avb_avtp_match_a_mux[] = { 1755 AVB_AVTP_MATCH_A_MARK, 1756}; 1757static const unsigned int avb_avtp_capture_a_pins[] = { 1758 /* AVB_AVTP_CAPTURE_A */ 1759 RCAR_GP_PIN(2, 14), 1760}; 1761static const unsigned int avb_avtp_capture_a_mux[] = { 1762 AVB_AVTP_CAPTURE_A_MARK, 1763}; 1764static const unsigned int avb_avtp_match_b_pins[] = { 1765 /* AVB_AVTP_MATCH_B */ 1766 RCAR_GP_PIN(1, 8), 1767}; 1768static const unsigned int avb_avtp_match_b_mux[] = { 1769 AVB_AVTP_MATCH_B_MARK, 1770}; 1771static const unsigned int avb_avtp_capture_b_pins[] = { 1772 /* AVB_AVTP_CAPTURE_B */ 1773 RCAR_GP_PIN(1, 11), 1774}; 1775static const unsigned int avb_avtp_capture_b_mux[] = { 1776 AVB_AVTP_CAPTURE_B_MARK, 1777}; 1778 1779/* - CAN ------------------------------------------------------------------ */ 1780static const unsigned int can0_data_a_pins[] = { 1781 /* TX, RX */ 1782 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 1783}; 1784static const unsigned int can0_data_a_mux[] = { 1785 CAN0_TX_A_MARK, CAN0_RX_A_MARK, 1786}; 1787static const unsigned int can0_data_b_pins[] = { 1788 /* TX, RX */ 1789 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1790}; 1791static const unsigned int can0_data_b_mux[] = { 1792 CAN0_TX_B_MARK, CAN0_RX_B_MARK, 1793}; 1794static const unsigned int can1_data_pins[] = { 1795 /* TX, RX */ 1796 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), 1797}; 1798static const unsigned int can1_data_mux[] = { 1799 CAN1_TX_MARK, CAN1_RX_MARK, 1800}; 1801 1802/* - CAN Clock -------------------------------------------------------------- */ 1803static const unsigned int can_clk_pins[] = { 1804 /* CLK */ 1805 RCAR_GP_PIN(1, 25), 1806}; 1807static const unsigned int can_clk_mux[] = { 1808 CAN_CLK_MARK, 1809}; 1810 1811/* - CAN FD --------------------------------------------------------------- */ 1812static const unsigned int canfd0_data_a_pins[] = { 1813 /* TX, RX */ 1814 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 1815}; 1816static const unsigned int canfd0_data_a_mux[] = { 1817 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, 1818}; 1819static const unsigned int canfd0_data_b_pins[] = { 1820 /* TX, RX */ 1821 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1822}; 1823static const unsigned int canfd0_data_b_mux[] = { 1824 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, 1825}; 1826static const unsigned int canfd1_data_pins[] = { 1827 /* TX, RX */ 1828 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), 1829}; 1830static const unsigned int canfd1_data_mux[] = { 1831 CANFD1_TX_MARK, CANFD1_RX_MARK, 1832}; 1833 1834/* - DRIF0 --------------------------------------------------------------- */ 1835static const unsigned int drif0_ctrl_a_pins[] = { 1836 /* CLK, SYNC */ 1837 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 1838}; 1839static const unsigned int drif0_ctrl_a_mux[] = { 1840 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK, 1841}; 1842static const unsigned int drif0_data0_a_pins[] = { 1843 /* D0 */ 1844 RCAR_GP_PIN(6, 10), 1845}; 1846static const unsigned int drif0_data0_a_mux[] = { 1847 RIF0_D0_A_MARK, 1848}; 1849static const unsigned int drif0_data1_a_pins[] = { 1850 /* D1 */ 1851 RCAR_GP_PIN(6, 7), 1852}; 1853static const unsigned int drif0_data1_a_mux[] = { 1854 RIF0_D1_A_MARK, 1855}; 1856static const unsigned int drif0_ctrl_b_pins[] = { 1857 /* CLK, SYNC */ 1858 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 1859}; 1860static const unsigned int drif0_ctrl_b_mux[] = { 1861 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK, 1862}; 1863static const unsigned int drif0_data0_b_pins[] = { 1864 /* D0 */ 1865 RCAR_GP_PIN(5, 1), 1866}; 1867static const unsigned int drif0_data0_b_mux[] = { 1868 RIF0_D0_B_MARK, 1869}; 1870static const unsigned int drif0_data1_b_pins[] = { 1871 /* D1 */ 1872 RCAR_GP_PIN(5, 2), 1873}; 1874static const unsigned int drif0_data1_b_mux[] = { 1875 RIF0_D1_B_MARK, 1876}; 1877static const unsigned int drif0_ctrl_c_pins[] = { 1878 /* CLK, SYNC */ 1879 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15), 1880}; 1881static const unsigned int drif0_ctrl_c_mux[] = { 1882 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK, 1883}; 1884static const unsigned int drif0_data0_c_pins[] = { 1885 /* D0 */ 1886 RCAR_GP_PIN(5, 13), 1887}; 1888static const unsigned int drif0_data0_c_mux[] = { 1889 RIF0_D0_C_MARK, 1890}; 1891static const unsigned int drif0_data1_c_pins[] = { 1892 /* D1 */ 1893 RCAR_GP_PIN(5, 14), 1894}; 1895static const unsigned int drif0_data1_c_mux[] = { 1896 RIF0_D1_C_MARK, 1897}; 1898/* - DRIF1 --------------------------------------------------------------- */ 1899static const unsigned int drif1_ctrl_a_pins[] = { 1900 /* CLK, SYNC */ 1901 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 1902}; 1903static const unsigned int drif1_ctrl_a_mux[] = { 1904 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK, 1905}; 1906static const unsigned int drif1_data0_a_pins[] = { 1907 /* D0 */ 1908 RCAR_GP_PIN(6, 19), 1909}; 1910static const unsigned int drif1_data0_a_mux[] = { 1911 RIF1_D0_A_MARK, 1912}; 1913static const unsigned int drif1_data1_a_pins[] = { 1914 /* D1 */ 1915 RCAR_GP_PIN(6, 20), 1916}; 1917static const unsigned int drif1_data1_a_mux[] = { 1918 RIF1_D1_A_MARK, 1919}; 1920static const unsigned int drif1_ctrl_b_pins[] = { 1921 /* CLK, SYNC */ 1922 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3), 1923}; 1924static const unsigned int drif1_ctrl_b_mux[] = { 1925 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK, 1926}; 1927static const unsigned int drif1_data0_b_pins[] = { 1928 /* D0 */ 1929 RCAR_GP_PIN(5, 7), 1930}; 1931static const unsigned int drif1_data0_b_mux[] = { 1932 RIF1_D0_B_MARK, 1933}; 1934static const unsigned int drif1_data1_b_pins[] = { 1935 /* D1 */ 1936 RCAR_GP_PIN(5, 8), 1937}; 1938static const unsigned int drif1_data1_b_mux[] = { 1939 RIF1_D1_B_MARK, 1940}; 1941static const unsigned int drif1_ctrl_c_pins[] = { 1942 /* CLK, SYNC */ 1943 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), 1944}; 1945static const unsigned int drif1_ctrl_c_mux[] = { 1946 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK, 1947}; 1948static const unsigned int drif1_data0_c_pins[] = { 1949 /* D0 */ 1950 RCAR_GP_PIN(5, 6), 1951}; 1952static const unsigned int drif1_data0_c_mux[] = { 1953 RIF1_D0_C_MARK, 1954}; 1955static const unsigned int drif1_data1_c_pins[] = { 1956 /* D1 */ 1957 RCAR_GP_PIN(5, 10), 1958}; 1959static const unsigned int drif1_data1_c_mux[] = { 1960 RIF1_D1_C_MARK, 1961}; 1962/* - DRIF2 --------------------------------------------------------------- */ 1963static const unsigned int drif2_ctrl_a_pins[] = { 1964 /* CLK, SYNC */ 1965 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 1966}; 1967static const unsigned int drif2_ctrl_a_mux[] = { 1968 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK, 1969}; 1970static const unsigned int drif2_data0_a_pins[] = { 1971 /* D0 */ 1972 RCAR_GP_PIN(6, 7), 1973}; 1974static const unsigned int drif2_data0_a_mux[] = { 1975 RIF2_D0_A_MARK, 1976}; 1977static const unsigned int drif2_data1_a_pins[] = { 1978 /* D1 */ 1979 RCAR_GP_PIN(6, 10), 1980}; 1981static const unsigned int drif2_data1_a_mux[] = { 1982 RIF2_D1_A_MARK, 1983}; 1984static const unsigned int drif2_ctrl_b_pins[] = { 1985 /* CLK, SYNC */ 1986 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 1987}; 1988static const unsigned int drif2_ctrl_b_mux[] = { 1989 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK, 1990}; 1991static const unsigned int drif2_data0_b_pins[] = { 1992 /* D0 */ 1993 RCAR_GP_PIN(6, 30), 1994}; 1995static const unsigned int drif2_data0_b_mux[] = { 1996 RIF2_D0_B_MARK, 1997}; 1998static const unsigned int drif2_data1_b_pins[] = { 1999 /* D1 */ 2000 RCAR_GP_PIN(6, 31), 2001}; 2002static const unsigned int drif2_data1_b_mux[] = { 2003 RIF2_D1_B_MARK, 2004}; 2005/* - DRIF3 --------------------------------------------------------------- */ 2006static const unsigned int drif3_ctrl_a_pins[] = { 2007 /* CLK, SYNC */ 2008 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 2009}; 2010static const unsigned int drif3_ctrl_a_mux[] = { 2011 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK, 2012}; 2013static const unsigned int drif3_data0_a_pins[] = { 2014 /* D0 */ 2015 RCAR_GP_PIN(6, 19), 2016}; 2017static const unsigned int drif3_data0_a_mux[] = { 2018 RIF3_D0_A_MARK, 2019}; 2020static const unsigned int drif3_data1_a_pins[] = { 2021 /* D1 */ 2022 RCAR_GP_PIN(6, 20), 2023}; 2024static const unsigned int drif3_data1_a_mux[] = { 2025 RIF3_D1_A_MARK, 2026}; 2027static const unsigned int drif3_ctrl_b_pins[] = { 2028 /* CLK, SYNC */ 2029 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 2030}; 2031static const unsigned int drif3_ctrl_b_mux[] = { 2032 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK, 2033}; 2034static const unsigned int drif3_data0_b_pins[] = { 2035 /* D0 */ 2036 RCAR_GP_PIN(6, 28), 2037}; 2038static const unsigned int drif3_data0_b_mux[] = { 2039 RIF3_D0_B_MARK, 2040}; 2041static const unsigned int drif3_data1_b_pins[] = { 2042 /* D1 */ 2043 RCAR_GP_PIN(6, 29), 2044}; 2045static const unsigned int drif3_data1_b_mux[] = { 2046 RIF3_D1_B_MARK, 2047}; 2048 2049/* - DU --------------------------------------------------------------------- */ 2050static const unsigned int du_rgb666_pins[] = { 2051 /* R[7:2], G[7:2], B[7:2] */ 2052 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 2053 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 2054 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2055 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2056 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 2057 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2058}; 2059static const unsigned int du_rgb666_mux[] = { 2060 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 2061 DU_DR3_MARK, DU_DR2_MARK, 2062 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 2063 DU_DG3_MARK, DU_DG2_MARK, 2064 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 2065 DU_DB3_MARK, DU_DB2_MARK, 2066}; 2067static const unsigned int du_rgb888_pins[] = { 2068 /* R[7:0], G[7:0], B[7:0] */ 2069 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 2070 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 2071 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), 2072 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2073 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2074 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), 2075 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 2076 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2077 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), 2078}; 2079static const unsigned int du_rgb888_mux[] = { 2080 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 2081 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, 2082 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 2083 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, 2084 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 2085 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, 2086}; 2087static const unsigned int du_clk_out_0_pins[] = { 2088 /* CLKOUT */ 2089 RCAR_GP_PIN(1, 27), 2090}; 2091static const unsigned int du_clk_out_0_mux[] = { 2092 DU_DOTCLKOUT0_MARK 2093}; 2094static const unsigned int du_clk_out_1_pins[] = { 2095 /* CLKOUT */ 2096 RCAR_GP_PIN(2, 3), 2097}; 2098static const unsigned int du_clk_out_1_mux[] = { 2099 DU_DOTCLKOUT1_MARK 2100}; 2101static const unsigned int du_sync_pins[] = { 2102 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ 2103 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), 2104}; 2105static const unsigned int du_sync_mux[] = { 2106 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK 2107}; 2108static const unsigned int du_oddf_pins[] = { 2109 /* EXDISP/EXODDF/EXCDE */ 2110 RCAR_GP_PIN(2, 2), 2111}; 2112static const unsigned int du_oddf_mux[] = { 2113 DU_EXODDF_DU_ODDF_DISP_CDE_MARK, 2114}; 2115static const unsigned int du_cde_pins[] = { 2116 /* CDE */ 2117 RCAR_GP_PIN(2, 0), 2118}; 2119static const unsigned int du_cde_mux[] = { 2120 DU_CDE_MARK, 2121}; 2122static const unsigned int du_disp_pins[] = { 2123 /* DISP */ 2124 RCAR_GP_PIN(2, 1), 2125}; 2126static const unsigned int du_disp_mux[] = { 2127 DU_DISP_MARK, 2128}; 2129 2130/* - HSCIF0 ----------------------------------------------------------------- */ 2131static const unsigned int hscif0_data_pins[] = { 2132 /* RX, TX */ 2133 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), 2134}; 2135static const unsigned int hscif0_data_mux[] = { 2136 HRX0_MARK, HTX0_MARK, 2137}; 2138static const unsigned int hscif0_clk_pins[] = { 2139 /* SCK */ 2140 RCAR_GP_PIN(5, 12), 2141}; 2142static const unsigned int hscif0_clk_mux[] = { 2143 HSCK0_MARK, 2144}; 2145static const unsigned int hscif0_ctrl_pins[] = { 2146 /* RTS, CTS */ 2147 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), 2148}; 2149static const unsigned int hscif0_ctrl_mux[] = { 2150 HRTS0_N_MARK, HCTS0_N_MARK, 2151}; 2152/* - HSCIF1 ----------------------------------------------------------------- */ 2153static const unsigned int hscif1_data_a_pins[] = { 2154 /* RX, TX */ 2155 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2156}; 2157static const unsigned int hscif1_data_a_mux[] = { 2158 HRX1_A_MARK, HTX1_A_MARK, 2159}; 2160static const unsigned int hscif1_clk_a_pins[] = { 2161 /* SCK */ 2162 RCAR_GP_PIN(6, 21), 2163}; 2164static const unsigned int hscif1_clk_a_mux[] = { 2165 HSCK1_A_MARK, 2166}; 2167static const unsigned int hscif1_ctrl_a_pins[] = { 2168 /* RTS, CTS */ 2169 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 2170}; 2171static const unsigned int hscif1_ctrl_a_mux[] = { 2172 HRTS1_N_A_MARK, HCTS1_N_A_MARK, 2173}; 2174 2175static const unsigned int hscif1_data_b_pins[] = { 2176 /* RX, TX */ 2177 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 2178}; 2179static const unsigned int hscif1_data_b_mux[] = { 2180 HRX1_B_MARK, HTX1_B_MARK, 2181}; 2182static const unsigned int hscif1_clk_b_pins[] = { 2183 /* SCK */ 2184 RCAR_GP_PIN(5, 0), 2185}; 2186static const unsigned int hscif1_clk_b_mux[] = { 2187 HSCK1_B_MARK, 2188}; 2189static const unsigned int hscif1_ctrl_b_pins[] = { 2190 /* RTS, CTS */ 2191 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 2192}; 2193static const unsigned int hscif1_ctrl_b_mux[] = { 2194 HRTS1_N_B_MARK, HCTS1_N_B_MARK, 2195}; 2196/* - HSCIF2 ----------------------------------------------------------------- */ 2197static const unsigned int hscif2_data_a_pins[] = { 2198 /* RX, TX */ 2199 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 2200}; 2201static const unsigned int hscif2_data_a_mux[] = { 2202 HRX2_A_MARK, HTX2_A_MARK, 2203}; 2204static const unsigned int hscif2_clk_a_pins[] = { 2205 /* SCK */ 2206 RCAR_GP_PIN(6, 10), 2207}; 2208static const unsigned int hscif2_clk_a_mux[] = { 2209 HSCK2_A_MARK, 2210}; 2211static const unsigned int hscif2_ctrl_a_pins[] = { 2212 /* RTS, CTS */ 2213 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 2214}; 2215static const unsigned int hscif2_ctrl_a_mux[] = { 2216 HRTS2_N_A_MARK, HCTS2_N_A_MARK, 2217}; 2218 2219static const unsigned int hscif2_data_b_pins[] = { 2220 /* RX, TX */ 2221 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 2222}; 2223static const unsigned int hscif2_data_b_mux[] = { 2224 HRX2_B_MARK, HTX2_B_MARK, 2225}; 2226static const unsigned int hscif2_clk_b_pins[] = { 2227 /* SCK */ 2228 RCAR_GP_PIN(6, 21), 2229}; 2230static const unsigned int hscif2_clk_b_mux[] = { 2231 HSCK2_B_MARK, 2232}; 2233static const unsigned int hscif2_ctrl_b_pins[] = { 2234 /* RTS, CTS */ 2235 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19), 2236}; 2237static const unsigned int hscif2_ctrl_b_mux[] = { 2238 HRTS2_N_B_MARK, HCTS2_N_B_MARK, 2239}; 2240 2241static const unsigned int hscif2_data_c_pins[] = { 2242 /* RX, TX */ 2243 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26), 2244}; 2245static const unsigned int hscif2_data_c_mux[] = { 2246 HRX2_C_MARK, HTX2_C_MARK, 2247}; 2248static const unsigned int hscif2_clk_c_pins[] = { 2249 /* SCK */ 2250 RCAR_GP_PIN(6, 24), 2251}; 2252static const unsigned int hscif2_clk_c_mux[] = { 2253 HSCK2_C_MARK, 2254}; 2255static const unsigned int hscif2_ctrl_c_pins[] = { 2256 /* RTS, CTS */ 2257 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27), 2258}; 2259static const unsigned int hscif2_ctrl_c_mux[] = { 2260 HRTS2_N_C_MARK, HCTS2_N_C_MARK, 2261}; 2262/* - HSCIF3 ----------------------------------------------------------------- */ 2263static const unsigned int hscif3_data_a_pins[] = { 2264 /* RX, TX */ 2265 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 2266}; 2267static const unsigned int hscif3_data_a_mux[] = { 2268 HRX3_A_MARK, HTX3_A_MARK, 2269}; 2270static const unsigned int hscif3_clk_pins[] = { 2271 /* SCK */ 2272 RCAR_GP_PIN(1, 22), 2273}; 2274static const unsigned int hscif3_clk_mux[] = { 2275 HSCK3_MARK, 2276}; 2277static const unsigned int hscif3_ctrl_pins[] = { 2278 /* RTS, CTS */ 2279 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2280}; 2281static const unsigned int hscif3_ctrl_mux[] = { 2282 HRTS3_N_MARK, HCTS3_N_MARK, 2283}; 2284 2285static const unsigned int hscif3_data_b_pins[] = { 2286 /* RX, TX */ 2287 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 2288}; 2289static const unsigned int hscif3_data_b_mux[] = { 2290 HRX3_B_MARK, HTX3_B_MARK, 2291}; 2292static const unsigned int hscif3_data_c_pins[] = { 2293 /* RX, TX */ 2294 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 2295}; 2296static const unsigned int hscif3_data_c_mux[] = { 2297 HRX3_C_MARK, HTX3_C_MARK, 2298}; 2299static const unsigned int hscif3_data_d_pins[] = { 2300 /* RX, TX */ 2301 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2302}; 2303static const unsigned int hscif3_data_d_mux[] = { 2304 HRX3_D_MARK, HTX3_D_MARK, 2305}; 2306/* - HSCIF4 ----------------------------------------------------------------- */ 2307static const unsigned int hscif4_data_a_pins[] = { 2308 /* RX, TX */ 2309 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 2310}; 2311static const unsigned int hscif4_data_a_mux[] = { 2312 HRX4_A_MARK, HTX4_A_MARK, 2313}; 2314static const unsigned int hscif4_clk_pins[] = { 2315 /* SCK */ 2316 RCAR_GP_PIN(1, 11), 2317}; 2318static const unsigned int hscif4_clk_mux[] = { 2319 HSCK4_MARK, 2320}; 2321static const unsigned int hscif4_ctrl_pins[] = { 2322 /* RTS, CTS */ 2323 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), 2324}; 2325static const unsigned int hscif4_ctrl_mux[] = { 2326 HRTS4_N_MARK, HCTS4_N_MARK, 2327}; 2328 2329static const unsigned int hscif4_data_b_pins[] = { 2330 /* RX, TX */ 2331 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2332}; 2333static const unsigned int hscif4_data_b_mux[] = { 2334 HRX4_B_MARK, HTX4_B_MARK, 2335}; 2336 2337/* - I2C -------------------------------------------------------------------- */ 2338static const unsigned int i2c0_pins[] = { 2339 /* SCL, SDA */ 2340 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2341}; 2342 2343static const unsigned int i2c0_mux[] = { 2344 SCL0_MARK, SDA0_MARK, 2345}; 2346 2347static const unsigned int i2c1_a_pins[] = { 2348 /* SDA, SCL */ 2349 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 2350}; 2351static const unsigned int i2c1_a_mux[] = { 2352 SDA1_A_MARK, SCL1_A_MARK, 2353}; 2354static const unsigned int i2c1_b_pins[] = { 2355 /* SDA, SCL */ 2356 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), 2357}; 2358static const unsigned int i2c1_b_mux[] = { 2359 SDA1_B_MARK, SCL1_B_MARK, 2360}; 2361static const unsigned int i2c2_a_pins[] = { 2362 /* SDA, SCL */ 2363 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 2364}; 2365static const unsigned int i2c2_a_mux[] = { 2366 SDA2_A_MARK, SCL2_A_MARK, 2367}; 2368static const unsigned int i2c2_b_pins[] = { 2369 /* SDA, SCL */ 2370 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), 2371}; 2372static const unsigned int i2c2_b_mux[] = { 2373 SDA2_B_MARK, SCL2_B_MARK, 2374}; 2375 2376static const unsigned int i2c3_pins[] = { 2377 /* SCL, SDA */ 2378 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2379}; 2380 2381static const unsigned int i2c3_mux[] = { 2382 SCL3_MARK, SDA3_MARK, 2383}; 2384 2385static const unsigned int i2c5_pins[] = { 2386 /* SCL, SDA */ 2387 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), 2388}; 2389 2390static const unsigned int i2c5_mux[] = { 2391 SCL5_MARK, SDA5_MARK, 2392}; 2393 2394static const unsigned int i2c6_a_pins[] = { 2395 /* SDA, SCL */ 2396 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2397}; 2398static const unsigned int i2c6_a_mux[] = { 2399 SDA6_A_MARK, SCL6_A_MARK, 2400}; 2401static const unsigned int i2c6_b_pins[] = { 2402 /* SDA, SCL */ 2403 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2404}; 2405static const unsigned int i2c6_b_mux[] = { 2406 SDA6_B_MARK, SCL6_B_MARK, 2407}; 2408static const unsigned int i2c6_c_pins[] = { 2409 /* SDA, SCL */ 2410 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), 2411}; 2412static const unsigned int i2c6_c_mux[] = { 2413 SDA6_C_MARK, SCL6_C_MARK, 2414}; 2415 2416/* - INTC-EX ---------------------------------------------------------------- */ 2417static const unsigned int intc_ex_irq0_pins[] = { 2418 /* IRQ0 */ 2419 RCAR_GP_PIN(2, 0), 2420}; 2421static const unsigned int intc_ex_irq0_mux[] = { 2422 IRQ0_MARK, 2423}; 2424static const unsigned int intc_ex_irq1_pins[] = { 2425 /* IRQ1 */ 2426 RCAR_GP_PIN(2, 1), 2427}; 2428static const unsigned int intc_ex_irq1_mux[] = { 2429 IRQ1_MARK, 2430}; 2431static const unsigned int intc_ex_irq2_pins[] = { 2432 /* IRQ2 */ 2433 RCAR_GP_PIN(2, 2), 2434}; 2435static const unsigned int intc_ex_irq2_mux[] = { 2436 IRQ2_MARK, 2437}; 2438static const unsigned int intc_ex_irq3_pins[] = { 2439 /* IRQ3 */ 2440 RCAR_GP_PIN(2, 3), 2441}; 2442static const unsigned int intc_ex_irq3_mux[] = { 2443 IRQ3_MARK, 2444}; 2445static const unsigned int intc_ex_irq4_pins[] = { 2446 /* IRQ4 */ 2447 RCAR_GP_PIN(2, 4), 2448}; 2449static const unsigned int intc_ex_irq4_mux[] = { 2450 IRQ4_MARK, 2451}; 2452static const unsigned int intc_ex_irq5_pins[] = { 2453 /* IRQ5 */ 2454 RCAR_GP_PIN(2, 5), 2455}; 2456static const unsigned int intc_ex_irq5_mux[] = { 2457 IRQ5_MARK, 2458}; 2459 2460/* - MSIOF0 ----------------------------------------------------------------- */ 2461static const unsigned int msiof0_clk_pins[] = { 2462 /* SCK */ 2463 RCAR_GP_PIN(5, 17), 2464}; 2465static const unsigned int msiof0_clk_mux[] = { 2466 MSIOF0_SCK_MARK, 2467}; 2468static const unsigned int msiof0_sync_pins[] = { 2469 /* SYNC */ 2470 RCAR_GP_PIN(5, 18), 2471}; 2472static const unsigned int msiof0_sync_mux[] = { 2473 MSIOF0_SYNC_MARK, 2474}; 2475static const unsigned int msiof0_ss1_pins[] = { 2476 /* SS1 */ 2477 RCAR_GP_PIN(5, 19), 2478}; 2479static const unsigned int msiof0_ss1_mux[] = { 2480 MSIOF0_SS1_MARK, 2481}; 2482static const unsigned int msiof0_ss2_pins[] = { 2483 /* SS2 */ 2484 RCAR_GP_PIN(5, 21), 2485}; 2486static const unsigned int msiof0_ss2_mux[] = { 2487 MSIOF0_SS2_MARK, 2488}; 2489static const unsigned int msiof0_txd_pins[] = { 2490 /* TXD */ 2491 RCAR_GP_PIN(5, 20), 2492}; 2493static const unsigned int msiof0_txd_mux[] = { 2494 MSIOF0_TXD_MARK, 2495}; 2496static const unsigned int msiof0_rxd_pins[] = { 2497 /* RXD */ 2498 RCAR_GP_PIN(5, 22), 2499}; 2500static const unsigned int msiof0_rxd_mux[] = { 2501 MSIOF0_RXD_MARK, 2502}; 2503/* - MSIOF1 ----------------------------------------------------------------- */ 2504static const unsigned int msiof1_clk_a_pins[] = { 2505 /* SCK */ 2506 RCAR_GP_PIN(6, 8), 2507}; 2508static const unsigned int msiof1_clk_a_mux[] = { 2509 MSIOF1_SCK_A_MARK, 2510}; 2511static const unsigned int msiof1_sync_a_pins[] = { 2512 /* SYNC */ 2513 RCAR_GP_PIN(6, 9), 2514}; 2515static const unsigned int msiof1_sync_a_mux[] = { 2516 MSIOF1_SYNC_A_MARK, 2517}; 2518static const unsigned int msiof1_ss1_a_pins[] = { 2519 /* SS1 */ 2520 RCAR_GP_PIN(6, 5), 2521}; 2522static const unsigned int msiof1_ss1_a_mux[] = { 2523 MSIOF1_SS1_A_MARK, 2524}; 2525static const unsigned int msiof1_ss2_a_pins[] = { 2526 /* SS2 */ 2527 RCAR_GP_PIN(6, 6), 2528}; 2529static const unsigned int msiof1_ss2_a_mux[] = { 2530 MSIOF1_SS2_A_MARK, 2531}; 2532static const unsigned int msiof1_txd_a_pins[] = { 2533 /* TXD */ 2534 RCAR_GP_PIN(6, 7), 2535}; 2536static const unsigned int msiof1_txd_a_mux[] = { 2537 MSIOF1_TXD_A_MARK, 2538}; 2539static const unsigned int msiof1_rxd_a_pins[] = { 2540 /* RXD */ 2541 RCAR_GP_PIN(6, 10), 2542}; 2543static const unsigned int msiof1_rxd_a_mux[] = { 2544 MSIOF1_RXD_A_MARK, 2545}; 2546static const unsigned int msiof1_clk_b_pins[] = { 2547 /* SCK */ 2548 RCAR_GP_PIN(5, 9), 2549}; 2550static const unsigned int msiof1_clk_b_mux[] = { 2551 MSIOF1_SCK_B_MARK, 2552}; 2553static const unsigned int msiof1_sync_b_pins[] = { 2554 /* SYNC */ 2555 RCAR_GP_PIN(5, 3), 2556}; 2557static const unsigned int msiof1_sync_b_mux[] = { 2558 MSIOF1_SYNC_B_MARK, 2559}; 2560static const unsigned int msiof1_ss1_b_pins[] = { 2561 /* SS1 */ 2562 RCAR_GP_PIN(5, 4), 2563}; 2564static const unsigned int msiof1_ss1_b_mux[] = { 2565 MSIOF1_SS1_B_MARK, 2566}; 2567static const unsigned int msiof1_ss2_b_pins[] = { 2568 /* SS2 */ 2569 RCAR_GP_PIN(5, 0), 2570}; 2571static const unsigned int msiof1_ss2_b_mux[] = { 2572 MSIOF1_SS2_B_MARK, 2573}; 2574static const unsigned int msiof1_txd_b_pins[] = { 2575 /* TXD */ 2576 RCAR_GP_PIN(5, 8), 2577}; 2578static const unsigned int msiof1_txd_b_mux[] = { 2579 MSIOF1_TXD_B_MARK, 2580}; 2581static const unsigned int msiof1_rxd_b_pins[] = { 2582 /* RXD */ 2583 RCAR_GP_PIN(5, 7), 2584}; 2585static const unsigned int msiof1_rxd_b_mux[] = { 2586 MSIOF1_RXD_B_MARK, 2587}; 2588static const unsigned int msiof1_clk_c_pins[] = { 2589 /* SCK */ 2590 RCAR_GP_PIN(6, 17), 2591}; 2592static const unsigned int msiof1_clk_c_mux[] = { 2593 MSIOF1_SCK_C_MARK, 2594}; 2595static const unsigned int msiof1_sync_c_pins[] = { 2596 /* SYNC */ 2597 RCAR_GP_PIN(6, 18), 2598}; 2599static const unsigned int msiof1_sync_c_mux[] = { 2600 MSIOF1_SYNC_C_MARK, 2601}; 2602static const unsigned int msiof1_ss1_c_pins[] = { 2603 /* SS1 */ 2604 RCAR_GP_PIN(6, 21), 2605}; 2606static const unsigned int msiof1_ss1_c_mux[] = { 2607 MSIOF1_SS1_C_MARK, 2608}; 2609static const unsigned int msiof1_ss2_c_pins[] = { 2610 /* SS2 */ 2611 RCAR_GP_PIN(6, 27), 2612}; 2613static const unsigned int msiof1_ss2_c_mux[] = { 2614 MSIOF1_SS2_C_MARK, 2615}; 2616static const unsigned int msiof1_txd_c_pins[] = { 2617 /* TXD */ 2618 RCAR_GP_PIN(6, 20), 2619}; 2620static const unsigned int msiof1_txd_c_mux[] = { 2621 MSIOF1_TXD_C_MARK, 2622}; 2623static const unsigned int msiof1_rxd_c_pins[] = { 2624 /* RXD */ 2625 RCAR_GP_PIN(6, 19), 2626}; 2627static const unsigned int msiof1_rxd_c_mux[] = { 2628 MSIOF1_RXD_C_MARK, 2629}; 2630static const unsigned int msiof1_clk_d_pins[] = { 2631 /* SCK */ 2632 RCAR_GP_PIN(5, 12), 2633}; 2634static const unsigned int msiof1_clk_d_mux[] = { 2635 MSIOF1_SCK_D_MARK, 2636}; 2637static const unsigned int msiof1_sync_d_pins[] = { 2638 /* SYNC */ 2639 RCAR_GP_PIN(5, 15), 2640}; 2641static const unsigned int msiof1_sync_d_mux[] = { 2642 MSIOF1_SYNC_D_MARK, 2643}; 2644static const unsigned int msiof1_ss1_d_pins[] = { 2645 /* SS1 */ 2646 RCAR_GP_PIN(5, 16), 2647}; 2648static const unsigned int msiof1_ss1_d_mux[] = { 2649 MSIOF1_SS1_D_MARK, 2650}; 2651static const unsigned int msiof1_ss2_d_pins[] = { 2652 /* SS2 */ 2653 RCAR_GP_PIN(5, 21), 2654}; 2655static const unsigned int msiof1_ss2_d_mux[] = { 2656 MSIOF1_SS2_D_MARK, 2657}; 2658static const unsigned int msiof1_txd_d_pins[] = { 2659 /* TXD */ 2660 RCAR_GP_PIN(5, 14), 2661}; 2662static const unsigned int msiof1_txd_d_mux[] = { 2663 MSIOF1_TXD_D_MARK, 2664}; 2665static const unsigned int msiof1_rxd_d_pins[] = { 2666 /* RXD */ 2667 RCAR_GP_PIN(5, 13), 2668}; 2669static const unsigned int msiof1_rxd_d_mux[] = { 2670 MSIOF1_RXD_D_MARK, 2671}; 2672static const unsigned int msiof1_clk_e_pins[] = { 2673 /* SCK */ 2674 RCAR_GP_PIN(3, 0), 2675}; 2676static const unsigned int msiof1_clk_e_mux[] = { 2677 MSIOF1_SCK_E_MARK, 2678}; 2679static const unsigned int msiof1_sync_e_pins[] = { 2680 /* SYNC */ 2681 RCAR_GP_PIN(3, 1), 2682}; 2683static const unsigned int msiof1_sync_e_mux[] = { 2684 MSIOF1_SYNC_E_MARK, 2685}; 2686static const unsigned int msiof1_ss1_e_pins[] = { 2687 /* SS1 */ 2688 RCAR_GP_PIN(3, 4), 2689}; 2690static const unsigned int msiof1_ss1_e_mux[] = { 2691 MSIOF1_SS1_E_MARK, 2692}; 2693static const unsigned int msiof1_ss2_e_pins[] = { 2694 /* SS2 */ 2695 RCAR_GP_PIN(3, 5), 2696}; 2697static const unsigned int msiof1_ss2_e_mux[] = { 2698 MSIOF1_SS2_E_MARK, 2699}; 2700static const unsigned int msiof1_txd_e_pins[] = { 2701 /* TXD */ 2702 RCAR_GP_PIN(3, 3), 2703}; 2704static const unsigned int msiof1_txd_e_mux[] = { 2705 MSIOF1_TXD_E_MARK, 2706}; 2707static const unsigned int msiof1_rxd_e_pins[] = { 2708 /* RXD */ 2709 RCAR_GP_PIN(3, 2), 2710}; 2711static const unsigned int msiof1_rxd_e_mux[] = { 2712 MSIOF1_RXD_E_MARK, 2713}; 2714static const unsigned int msiof1_clk_f_pins[] = { 2715 /* SCK */ 2716 RCAR_GP_PIN(5, 23), 2717}; 2718static const unsigned int msiof1_clk_f_mux[] = { 2719 MSIOF1_SCK_F_MARK, 2720}; 2721static const unsigned int msiof1_sync_f_pins[] = { 2722 /* SYNC */ 2723 RCAR_GP_PIN(5, 24), 2724}; 2725static const unsigned int msiof1_sync_f_mux[] = { 2726 MSIOF1_SYNC_F_MARK, 2727}; 2728static const unsigned int msiof1_ss1_f_pins[] = { 2729 /* SS1 */ 2730 RCAR_GP_PIN(6, 1), 2731}; 2732static const unsigned int msiof1_ss1_f_mux[] = { 2733 MSIOF1_SS1_F_MARK, 2734}; 2735static const unsigned int msiof1_ss2_f_pins[] = { 2736 /* SS2 */ 2737 RCAR_GP_PIN(6, 2), 2738}; 2739static const unsigned int msiof1_ss2_f_mux[] = { 2740 MSIOF1_SS2_F_MARK, 2741}; 2742static const unsigned int msiof1_txd_f_pins[] = { 2743 /* TXD */ 2744 RCAR_GP_PIN(6, 0), 2745}; 2746static const unsigned int msiof1_txd_f_mux[] = { 2747 MSIOF1_TXD_F_MARK, 2748}; 2749static const unsigned int msiof1_rxd_f_pins[] = { 2750 /* RXD */ 2751 RCAR_GP_PIN(5, 25), 2752}; 2753static const unsigned int msiof1_rxd_f_mux[] = { 2754 MSIOF1_RXD_F_MARK, 2755}; 2756static const unsigned int msiof1_clk_g_pins[] = { 2757 /* SCK */ 2758 RCAR_GP_PIN(3, 6), 2759}; 2760static const unsigned int msiof1_clk_g_mux[] = { 2761 MSIOF1_SCK_G_MARK, 2762}; 2763static const unsigned int msiof1_sync_g_pins[] = { 2764 /* SYNC */ 2765 RCAR_GP_PIN(3, 7), 2766}; 2767static const unsigned int msiof1_sync_g_mux[] = { 2768 MSIOF1_SYNC_G_MARK, 2769}; 2770static const unsigned int msiof1_ss1_g_pins[] = { 2771 /* SS1 */ 2772 RCAR_GP_PIN(3, 10), 2773}; 2774static const unsigned int msiof1_ss1_g_mux[] = { 2775 MSIOF1_SS1_G_MARK, 2776}; 2777static const unsigned int msiof1_ss2_g_pins[] = { 2778 /* SS2 */ 2779 RCAR_GP_PIN(3, 11), 2780}; 2781static const unsigned int msiof1_ss2_g_mux[] = { 2782 MSIOF1_SS2_G_MARK, 2783}; 2784static const unsigned int msiof1_txd_g_pins[] = { 2785 /* TXD */ 2786 RCAR_GP_PIN(3, 9), 2787}; 2788static const unsigned int msiof1_txd_g_mux[] = { 2789 MSIOF1_TXD_G_MARK, 2790}; 2791static const unsigned int msiof1_rxd_g_pins[] = { 2792 /* RXD */ 2793 RCAR_GP_PIN(3, 8), 2794}; 2795static const unsigned int msiof1_rxd_g_mux[] = { 2796 MSIOF1_RXD_G_MARK, 2797}; 2798/* - MSIOF2 ----------------------------------------------------------------- */ 2799static const unsigned int msiof2_clk_a_pins[] = { 2800 /* SCK */ 2801 RCAR_GP_PIN(1, 9), 2802}; 2803static const unsigned int msiof2_clk_a_mux[] = { 2804 MSIOF2_SCK_A_MARK, 2805}; 2806static const unsigned int msiof2_sync_a_pins[] = { 2807 /* SYNC */ 2808 RCAR_GP_PIN(1, 8), 2809}; 2810static const unsigned int msiof2_sync_a_mux[] = { 2811 MSIOF2_SYNC_A_MARK, 2812}; 2813static const unsigned int msiof2_ss1_a_pins[] = { 2814 /* SS1 */ 2815 RCAR_GP_PIN(1, 6), 2816}; 2817static const unsigned int msiof2_ss1_a_mux[] = { 2818 MSIOF2_SS1_A_MARK, 2819}; 2820static const unsigned int msiof2_ss2_a_pins[] = { 2821 /* SS2 */ 2822 RCAR_GP_PIN(1, 7), 2823}; 2824static const unsigned int msiof2_ss2_a_mux[] = { 2825 MSIOF2_SS2_A_MARK, 2826}; 2827static const unsigned int msiof2_txd_a_pins[] = { 2828 /* TXD */ 2829 RCAR_GP_PIN(1, 11), 2830}; 2831static const unsigned int msiof2_txd_a_mux[] = { 2832 MSIOF2_TXD_A_MARK, 2833}; 2834static const unsigned int msiof2_rxd_a_pins[] = { 2835 /* RXD */ 2836 RCAR_GP_PIN(1, 10), 2837}; 2838static const unsigned int msiof2_rxd_a_mux[] = { 2839 MSIOF2_RXD_A_MARK, 2840}; 2841static const unsigned int msiof2_clk_b_pins[] = { 2842 /* SCK */ 2843 RCAR_GP_PIN(0, 4), 2844}; 2845static const unsigned int msiof2_clk_b_mux[] = { 2846 MSIOF2_SCK_B_MARK, 2847}; 2848static const unsigned int msiof2_sync_b_pins[] = { 2849 /* SYNC */ 2850 RCAR_GP_PIN(0, 5), 2851}; 2852static const unsigned int msiof2_sync_b_mux[] = { 2853 MSIOF2_SYNC_B_MARK, 2854}; 2855static const unsigned int msiof2_ss1_b_pins[] = { 2856 /* SS1 */ 2857 RCAR_GP_PIN(0, 0), 2858}; 2859static const unsigned int msiof2_ss1_b_mux[] = { 2860 MSIOF2_SS1_B_MARK, 2861}; 2862static const unsigned int msiof2_ss2_b_pins[] = { 2863 /* SS2 */ 2864 RCAR_GP_PIN(0, 1), 2865}; 2866static const unsigned int msiof2_ss2_b_mux[] = { 2867 MSIOF2_SS2_B_MARK, 2868}; 2869static const unsigned int msiof2_txd_b_pins[] = { 2870 /* TXD */ 2871 RCAR_GP_PIN(0, 7), 2872}; 2873static const unsigned int msiof2_txd_b_mux[] = { 2874 MSIOF2_TXD_B_MARK, 2875}; 2876static const unsigned int msiof2_rxd_b_pins[] = { 2877 /* RXD */ 2878 RCAR_GP_PIN(0, 6), 2879}; 2880static const unsigned int msiof2_rxd_b_mux[] = { 2881 MSIOF2_RXD_B_MARK, 2882}; 2883static const unsigned int msiof2_clk_c_pins[] = { 2884 /* SCK */ 2885 RCAR_GP_PIN(2, 12), 2886}; 2887static const unsigned int msiof2_clk_c_mux[] = { 2888 MSIOF2_SCK_C_MARK, 2889}; 2890static const unsigned int msiof2_sync_c_pins[] = { 2891 /* SYNC */ 2892 RCAR_GP_PIN(2, 11), 2893}; 2894static const unsigned int msiof2_sync_c_mux[] = { 2895 MSIOF2_SYNC_C_MARK, 2896}; 2897static const unsigned int msiof2_ss1_c_pins[] = { 2898 /* SS1 */ 2899 RCAR_GP_PIN(2, 10), 2900}; 2901static const unsigned int msiof2_ss1_c_mux[] = { 2902 MSIOF2_SS1_C_MARK, 2903}; 2904static const unsigned int msiof2_ss2_c_pins[] = { 2905 /* SS2 */ 2906 RCAR_GP_PIN(2, 9), 2907}; 2908static const unsigned int msiof2_ss2_c_mux[] = { 2909 MSIOF2_SS2_C_MARK, 2910}; 2911static const unsigned int msiof2_txd_c_pins[] = { 2912 /* TXD */ 2913 RCAR_GP_PIN(2, 14), 2914}; 2915static const unsigned int msiof2_txd_c_mux[] = { 2916 MSIOF2_TXD_C_MARK, 2917}; 2918static const unsigned int msiof2_rxd_c_pins[] = { 2919 /* RXD */ 2920 RCAR_GP_PIN(2, 13), 2921}; 2922static const unsigned int msiof2_rxd_c_mux[] = { 2923 MSIOF2_RXD_C_MARK, 2924}; 2925static const unsigned int msiof2_clk_d_pins[] = { 2926 /* SCK */ 2927 RCAR_GP_PIN(0, 8), 2928}; 2929static const unsigned int msiof2_clk_d_mux[] = { 2930 MSIOF2_SCK_D_MARK, 2931}; 2932static const unsigned int msiof2_sync_d_pins[] = { 2933 /* SYNC */ 2934 RCAR_GP_PIN(0, 9), 2935}; 2936static const unsigned int msiof2_sync_d_mux[] = { 2937 MSIOF2_SYNC_D_MARK, 2938}; 2939static const unsigned int msiof2_ss1_d_pins[] = { 2940 /* SS1 */ 2941 RCAR_GP_PIN(0, 12), 2942}; 2943static const unsigned int msiof2_ss1_d_mux[] = { 2944 MSIOF2_SS1_D_MARK, 2945}; 2946static const unsigned int msiof2_ss2_d_pins[] = { 2947 /* SS2 */ 2948 RCAR_GP_PIN(0, 13), 2949}; 2950static const unsigned int msiof2_ss2_d_mux[] = { 2951 MSIOF2_SS2_D_MARK, 2952}; 2953static const unsigned int msiof2_txd_d_pins[] = { 2954 /* TXD */ 2955 RCAR_GP_PIN(0, 11), 2956}; 2957static const unsigned int msiof2_txd_d_mux[] = { 2958 MSIOF2_TXD_D_MARK, 2959}; 2960static const unsigned int msiof2_rxd_d_pins[] = { 2961 /* RXD */ 2962 RCAR_GP_PIN(0, 10), 2963}; 2964static const unsigned int msiof2_rxd_d_mux[] = { 2965 MSIOF2_RXD_D_MARK, 2966}; 2967/* - MSIOF3 ----------------------------------------------------------------- */ 2968static const unsigned int msiof3_clk_a_pins[] = { 2969 /* SCK */ 2970 RCAR_GP_PIN(0, 0), 2971}; 2972static const unsigned int msiof3_clk_a_mux[] = { 2973 MSIOF3_SCK_A_MARK, 2974}; 2975static const unsigned int msiof3_sync_a_pins[] = { 2976 /* SYNC */ 2977 RCAR_GP_PIN(0, 1), 2978}; 2979static const unsigned int msiof3_sync_a_mux[] = { 2980 MSIOF3_SYNC_A_MARK, 2981}; 2982static const unsigned int msiof3_ss1_a_pins[] = { 2983 /* SS1 */ 2984 RCAR_GP_PIN(0, 14), 2985}; 2986static const unsigned int msiof3_ss1_a_mux[] = { 2987 MSIOF3_SS1_A_MARK, 2988}; 2989static const unsigned int msiof3_ss2_a_pins[] = { 2990 /* SS2 */ 2991 RCAR_GP_PIN(0, 15), 2992}; 2993static const unsigned int msiof3_ss2_a_mux[] = { 2994 MSIOF3_SS2_A_MARK, 2995}; 2996static const unsigned int msiof3_txd_a_pins[] = { 2997 /* TXD */ 2998 RCAR_GP_PIN(0, 3), 2999}; 3000static const unsigned int msiof3_txd_a_mux[] = { 3001 MSIOF3_TXD_A_MARK, 3002}; 3003static const unsigned int msiof3_rxd_a_pins[] = { 3004 /* RXD */ 3005 RCAR_GP_PIN(0, 2), 3006}; 3007static const unsigned int msiof3_rxd_a_mux[] = { 3008 MSIOF3_RXD_A_MARK, 3009}; 3010static const unsigned int msiof3_clk_b_pins[] = { 3011 /* SCK */ 3012 RCAR_GP_PIN(1, 2), 3013}; 3014static const unsigned int msiof3_clk_b_mux[] = { 3015 MSIOF3_SCK_B_MARK, 3016}; 3017static const unsigned int msiof3_sync_b_pins[] = { 3018 /* SYNC */ 3019 RCAR_GP_PIN(1, 0), 3020}; 3021static const unsigned int msiof3_sync_b_mux[] = { 3022 MSIOF3_SYNC_B_MARK, 3023}; 3024static const unsigned int msiof3_ss1_b_pins[] = { 3025 /* SS1 */ 3026 RCAR_GP_PIN(1, 4), 3027}; 3028static const unsigned int msiof3_ss1_b_mux[] = { 3029 MSIOF3_SS1_B_MARK, 3030}; 3031static const unsigned int msiof3_ss2_b_pins[] = { 3032 /* SS2 */ 3033 RCAR_GP_PIN(1, 5), 3034}; 3035static const unsigned int msiof3_ss2_b_mux[] = { 3036 MSIOF3_SS2_B_MARK, 3037}; 3038static const unsigned int msiof3_txd_b_pins[] = { 3039 /* TXD */ 3040 RCAR_GP_PIN(1, 1), 3041}; 3042static const unsigned int msiof3_txd_b_mux[] = { 3043 MSIOF3_TXD_B_MARK, 3044}; 3045static const unsigned int msiof3_rxd_b_pins[] = { 3046 /* RXD */ 3047 RCAR_GP_PIN(1, 3), 3048}; 3049static const unsigned int msiof3_rxd_b_mux[] = { 3050 MSIOF3_RXD_B_MARK, 3051}; 3052static const unsigned int msiof3_clk_c_pins[] = { 3053 /* SCK */ 3054 RCAR_GP_PIN(1, 12), 3055}; 3056static const unsigned int msiof3_clk_c_mux[] = { 3057 MSIOF3_SCK_C_MARK, 3058}; 3059static const unsigned int msiof3_sync_c_pins[] = { 3060 /* SYNC */ 3061 RCAR_GP_PIN(1, 13), 3062}; 3063static const unsigned int msiof3_sync_c_mux[] = { 3064 MSIOF3_SYNC_C_MARK, 3065}; 3066static const unsigned int msiof3_txd_c_pins[] = { 3067 /* TXD */ 3068 RCAR_GP_PIN(1, 15), 3069}; 3070static const unsigned int msiof3_txd_c_mux[] = { 3071 MSIOF3_TXD_C_MARK, 3072}; 3073static const unsigned int msiof3_rxd_c_pins[] = { 3074 /* RXD */ 3075 RCAR_GP_PIN(1, 14), 3076}; 3077static const unsigned int msiof3_rxd_c_mux[] = { 3078 MSIOF3_RXD_C_MARK, 3079}; 3080static const unsigned int msiof3_clk_d_pins[] = { 3081 /* SCK */ 3082 RCAR_GP_PIN(1, 22), 3083}; 3084static const unsigned int msiof3_clk_d_mux[] = { 3085 MSIOF3_SCK_D_MARK, 3086}; 3087static const unsigned int msiof3_sync_d_pins[] = { 3088 /* SYNC */ 3089 RCAR_GP_PIN(1, 23), 3090}; 3091static const unsigned int msiof3_sync_d_mux[] = { 3092 MSIOF3_SYNC_D_MARK, 3093}; 3094static const unsigned int msiof3_ss1_d_pins[] = { 3095 /* SS1 */ 3096 RCAR_GP_PIN(1, 26), 3097}; 3098static const unsigned int msiof3_ss1_d_mux[] = { 3099 MSIOF3_SS1_D_MARK, 3100}; 3101static const unsigned int msiof3_txd_d_pins[] = { 3102 /* TXD */ 3103 RCAR_GP_PIN(1, 25), 3104}; 3105static const unsigned int msiof3_txd_d_mux[] = { 3106 MSIOF3_TXD_D_MARK, 3107}; 3108static const unsigned int msiof3_rxd_d_pins[] = { 3109 /* RXD */ 3110 RCAR_GP_PIN(1, 24), 3111}; 3112static const unsigned int msiof3_rxd_d_mux[] = { 3113 MSIOF3_RXD_D_MARK, 3114}; 3115 3116static const unsigned int msiof3_clk_e_pins[] = { 3117 /* SCK */ 3118 RCAR_GP_PIN(2, 3), 3119}; 3120static const unsigned int msiof3_clk_e_mux[] = { 3121 MSIOF3_SCK_E_MARK, 3122}; 3123static const unsigned int msiof3_sync_e_pins[] = { 3124 /* SYNC */ 3125 RCAR_GP_PIN(2, 2), 3126}; 3127static const unsigned int msiof3_sync_e_mux[] = { 3128 MSIOF3_SYNC_E_MARK, 3129}; 3130static const unsigned int msiof3_ss1_e_pins[] = { 3131 /* SS1 */ 3132 RCAR_GP_PIN(2, 1), 3133}; 3134static const unsigned int msiof3_ss1_e_mux[] = { 3135 MSIOF3_SS1_E_MARK, 3136}; 3137static const unsigned int msiof3_ss2_e_pins[] = { 3138 /* SS2 */ 3139 RCAR_GP_PIN(2, 0), 3140}; 3141static const unsigned int msiof3_ss2_e_mux[] = { 3142 MSIOF3_SS2_E_MARK, 3143}; 3144static const unsigned int msiof3_txd_e_pins[] = { 3145 /* TXD */ 3146 RCAR_GP_PIN(2, 5), 3147}; 3148static const unsigned int msiof3_txd_e_mux[] = { 3149 MSIOF3_TXD_E_MARK, 3150}; 3151static const unsigned int msiof3_rxd_e_pins[] = { 3152 /* RXD */ 3153 RCAR_GP_PIN(2, 4), 3154}; 3155static const unsigned int msiof3_rxd_e_mux[] = { 3156 MSIOF3_RXD_E_MARK, 3157}; 3158 3159/* - PWM0 --------------------------------------------------------------------*/ 3160static const unsigned int pwm0_pins[] = { 3161 /* PWM */ 3162 RCAR_GP_PIN(2, 6), 3163}; 3164static const unsigned int pwm0_mux[] = { 3165 PWM0_MARK, 3166}; 3167/* - PWM1 --------------------------------------------------------------------*/ 3168static const unsigned int pwm1_a_pins[] = { 3169 /* PWM */ 3170 RCAR_GP_PIN(2, 7), 3171}; 3172static const unsigned int pwm1_a_mux[] = { 3173 PWM1_A_MARK, 3174}; 3175static const unsigned int pwm1_b_pins[] = { 3176 /* PWM */ 3177 RCAR_GP_PIN(1, 8), 3178}; 3179static const unsigned int pwm1_b_mux[] = { 3180 PWM1_B_MARK, 3181}; 3182/* - PWM2 --------------------------------------------------------------------*/ 3183static const unsigned int pwm2_a_pins[] = { 3184 /* PWM */ 3185 RCAR_GP_PIN(2, 8), 3186}; 3187static const unsigned int pwm2_a_mux[] = { 3188 PWM2_A_MARK, 3189}; 3190static const unsigned int pwm2_b_pins[] = { 3191 /* PWM */ 3192 RCAR_GP_PIN(1, 11), 3193}; 3194static const unsigned int pwm2_b_mux[] = { 3195 PWM2_B_MARK, 3196}; 3197/* - PWM3 --------------------------------------------------------------------*/ 3198static const unsigned int pwm3_a_pins[] = { 3199 /* PWM */ 3200 RCAR_GP_PIN(1, 0), 3201}; 3202static const unsigned int pwm3_a_mux[] = { 3203 PWM3_A_MARK, 3204}; 3205static const unsigned int pwm3_b_pins[] = { 3206 /* PWM */ 3207 RCAR_GP_PIN(2, 2), 3208}; 3209static const unsigned int pwm3_b_mux[] = { 3210 PWM3_B_MARK, 3211}; 3212/* - PWM4 --------------------------------------------------------------------*/ 3213static const unsigned int pwm4_a_pins[] = { 3214 /* PWM */ 3215 RCAR_GP_PIN(1, 1), 3216}; 3217static const unsigned int pwm4_a_mux[] = { 3218 PWM4_A_MARK, 3219}; 3220static const unsigned int pwm4_b_pins[] = { 3221 /* PWM */ 3222 RCAR_GP_PIN(2, 3), 3223}; 3224static const unsigned int pwm4_b_mux[] = { 3225 PWM4_B_MARK, 3226}; 3227/* - PWM5 --------------------------------------------------------------------*/ 3228static const unsigned int pwm5_a_pins[] = { 3229 /* PWM */ 3230 RCAR_GP_PIN(1, 2), 3231}; 3232static const unsigned int pwm5_a_mux[] = { 3233 PWM5_A_MARK, 3234}; 3235static const unsigned int pwm5_b_pins[] = { 3236 /* PWM */ 3237 RCAR_GP_PIN(2, 4), 3238}; 3239static const unsigned int pwm5_b_mux[] = { 3240 PWM5_B_MARK, 3241}; 3242/* - PWM6 --------------------------------------------------------------------*/ 3243static const unsigned int pwm6_a_pins[] = { 3244 /* PWM */ 3245 RCAR_GP_PIN(1, 3), 3246}; 3247static const unsigned int pwm6_a_mux[] = { 3248 PWM6_A_MARK, 3249}; 3250static const unsigned int pwm6_b_pins[] = { 3251 /* PWM */ 3252 RCAR_GP_PIN(2, 5), 3253}; 3254static const unsigned int pwm6_b_mux[] = { 3255 PWM6_B_MARK, 3256}; 3257 3258/* - SCIF0 ------------------------------------------------------------------ */ 3259static const unsigned int scif0_data_pins[] = { 3260 /* RX, TX */ 3261 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 3262}; 3263static const unsigned int scif0_data_mux[] = { 3264 RX0_MARK, TX0_MARK, 3265}; 3266static const unsigned int scif0_clk_pins[] = { 3267 /* SCK */ 3268 RCAR_GP_PIN(5, 0), 3269}; 3270static const unsigned int scif0_clk_mux[] = { 3271 SCK0_MARK, 3272}; 3273static const unsigned int scif0_ctrl_pins[] = { 3274 /* RTS, CTS */ 3275 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 3276}; 3277static const unsigned int scif0_ctrl_mux[] = { 3278 RTS0_N_MARK, CTS0_N_MARK, 3279}; 3280/* - SCIF1 ------------------------------------------------------------------ */ 3281static const unsigned int scif1_data_a_pins[] = { 3282 /* RX, TX */ 3283 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 3284}; 3285static const unsigned int scif1_data_a_mux[] = { 3286 RX1_A_MARK, TX1_A_MARK, 3287}; 3288static const unsigned int scif1_clk_pins[] = { 3289 /* SCK */ 3290 RCAR_GP_PIN(6, 21), 3291}; 3292static const unsigned int scif1_clk_mux[] = { 3293 SCK1_MARK, 3294}; 3295static const unsigned int scif1_ctrl_pins[] = { 3296 /* RTS, CTS */ 3297 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 3298}; 3299static const unsigned int scif1_ctrl_mux[] = { 3300 RTS1_N_MARK, CTS1_N_MARK, 3301}; 3302 3303static const unsigned int scif1_data_b_pins[] = { 3304 /* RX, TX */ 3305 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), 3306}; 3307static const unsigned int scif1_data_b_mux[] = { 3308 RX1_B_MARK, TX1_B_MARK, 3309}; 3310/* - SCIF2 ------------------------------------------------------------------ */ 3311static const unsigned int scif2_data_a_pins[] = { 3312 /* RX, TX */ 3313 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 3314}; 3315static const unsigned int scif2_data_a_mux[] = { 3316 RX2_A_MARK, TX2_A_MARK, 3317}; 3318static const unsigned int scif2_clk_pins[] = { 3319 /* SCK */ 3320 RCAR_GP_PIN(5, 9), 3321}; 3322static const unsigned int scif2_clk_mux[] = { 3323 SCK2_MARK, 3324}; 3325static const unsigned int scif2_data_b_pins[] = { 3326 /* RX, TX */ 3327 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 3328}; 3329static const unsigned int scif2_data_b_mux[] = { 3330 RX2_B_MARK, TX2_B_MARK, 3331}; 3332/* - SCIF3 ------------------------------------------------------------------ */ 3333static const unsigned int scif3_data_a_pins[] = { 3334 /* RX, TX */ 3335 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 3336}; 3337static const unsigned int scif3_data_a_mux[] = { 3338 RX3_A_MARK, TX3_A_MARK, 3339}; 3340static const unsigned int scif3_clk_pins[] = { 3341 /* SCK */ 3342 RCAR_GP_PIN(1, 22), 3343}; 3344static const unsigned int scif3_clk_mux[] = { 3345 SCK3_MARK, 3346}; 3347static const unsigned int scif3_ctrl_pins[] = { 3348 /* RTS, CTS */ 3349 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 3350}; 3351static const unsigned int scif3_ctrl_mux[] = { 3352 RTS3_N_MARK, CTS3_N_MARK, 3353}; 3354static const unsigned int scif3_data_b_pins[] = { 3355 /* RX, TX */ 3356 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 3357}; 3358static const unsigned int scif3_data_b_mux[] = { 3359 RX3_B_MARK, TX3_B_MARK, 3360}; 3361/* - SCIF4 ------------------------------------------------------------------ */ 3362static const unsigned int scif4_data_a_pins[] = { 3363 /* RX, TX */ 3364 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 3365}; 3366static const unsigned int scif4_data_a_mux[] = { 3367 RX4_A_MARK, TX4_A_MARK, 3368}; 3369static const unsigned int scif4_clk_a_pins[] = { 3370 /* SCK */ 3371 RCAR_GP_PIN(2, 10), 3372}; 3373static const unsigned int scif4_clk_a_mux[] = { 3374 SCK4_A_MARK, 3375}; 3376static const unsigned int scif4_ctrl_a_pins[] = { 3377 /* RTS, CTS */ 3378 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 3379}; 3380static const unsigned int scif4_ctrl_a_mux[] = { 3381 RTS4_N_A_MARK, CTS4_N_A_MARK, 3382}; 3383static const unsigned int scif4_data_b_pins[] = { 3384 /* RX, TX */ 3385 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3386}; 3387static const unsigned int scif4_data_b_mux[] = { 3388 RX4_B_MARK, TX4_B_MARK, 3389}; 3390static const unsigned int scif4_clk_b_pins[] = { 3391 /* SCK */ 3392 RCAR_GP_PIN(1, 5), 3393}; 3394static const unsigned int scif4_clk_b_mux[] = { 3395 SCK4_B_MARK, 3396}; 3397static const unsigned int scif4_ctrl_b_pins[] = { 3398 /* RTS, CTS */ 3399 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), 3400}; 3401static const unsigned int scif4_ctrl_b_mux[] = { 3402 RTS4_N_B_MARK, CTS4_N_B_MARK, 3403}; 3404static const unsigned int scif4_data_c_pins[] = { 3405 /* RX, TX */ 3406 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3407}; 3408static const unsigned int scif4_data_c_mux[] = { 3409 RX4_C_MARK, TX4_C_MARK, 3410}; 3411static const unsigned int scif4_clk_c_pins[] = { 3412 /* SCK */ 3413 RCAR_GP_PIN(0, 8), 3414}; 3415static const unsigned int scif4_clk_c_mux[] = { 3416 SCK4_C_MARK, 3417}; 3418static const unsigned int scif4_ctrl_c_pins[] = { 3419 /* RTS, CTS */ 3420 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 3421}; 3422static const unsigned int scif4_ctrl_c_mux[] = { 3423 RTS4_N_C_MARK, CTS4_N_C_MARK, 3424}; 3425/* - SCIF5 ------------------------------------------------------------------ */ 3426static const unsigned int scif5_data_a_pins[] = { 3427 /* RX, TX */ 3428 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), 3429}; 3430static const unsigned int scif5_data_a_mux[] = { 3431 RX5_A_MARK, TX5_A_MARK, 3432}; 3433static const unsigned int scif5_clk_a_pins[] = { 3434 /* SCK */ 3435 RCAR_GP_PIN(6, 21), 3436}; 3437static const unsigned int scif5_clk_a_mux[] = { 3438 SCK5_A_MARK, 3439}; 3440 3441static const unsigned int scif5_data_b_pins[] = { 3442 /* RX, TX */ 3443 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18), 3444}; 3445static const unsigned int scif5_data_b_mux[] = { 3446 RX5_B_MARK, TX5_B_MARK, 3447}; 3448static const unsigned int scif5_clk_b_pins[] = { 3449 /* SCK */ 3450 RCAR_GP_PIN(5, 0), 3451}; 3452static const unsigned int scif5_clk_b_mux[] = { 3453 SCK5_B_MARK, 3454}; 3455 3456/* - SCIF Clock ------------------------------------------------------------- */ 3457static const unsigned int scif_clk_a_pins[] = { 3458 /* SCIF_CLK */ 3459 RCAR_GP_PIN(6, 23), 3460}; 3461static const unsigned int scif_clk_a_mux[] = { 3462 SCIF_CLK_A_MARK, 3463}; 3464static const unsigned int scif_clk_b_pins[] = { 3465 /* SCIF_CLK */ 3466 RCAR_GP_PIN(5, 9), 3467}; 3468static const unsigned int scif_clk_b_mux[] = { 3469 SCIF_CLK_B_MARK, 3470}; 3471 3472/* - SDHI0 ------------------------------------------------------------------ */ 3473static const unsigned int sdhi0_data1_pins[] = { 3474 /* D0 */ 3475 RCAR_GP_PIN(3, 2), 3476}; 3477static const unsigned int sdhi0_data1_mux[] = { 3478 SD0_DAT0_MARK, 3479}; 3480static const unsigned int sdhi0_data4_pins[] = { 3481 /* D[0:3] */ 3482 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3483 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 3484}; 3485static const unsigned int sdhi0_data4_mux[] = { 3486 SD0_DAT0_MARK, SD0_DAT1_MARK, 3487 SD0_DAT2_MARK, SD0_DAT3_MARK, 3488}; 3489static const unsigned int sdhi0_ctrl_pins[] = { 3490 /* CLK, CMD */ 3491 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 3492}; 3493static const unsigned int sdhi0_ctrl_mux[] = { 3494 SD0_CLK_MARK, SD0_CMD_MARK, 3495}; 3496static const unsigned int sdhi0_cd_pins[] = { 3497 /* CD */ 3498 RCAR_GP_PIN(3, 12), 3499}; 3500static const unsigned int sdhi0_cd_mux[] = { 3501 SD0_CD_MARK, 3502}; 3503static const unsigned int sdhi0_wp_pins[] = { 3504 /* WP */ 3505 RCAR_GP_PIN(3, 13), 3506}; 3507static const unsigned int sdhi0_wp_mux[] = { 3508 SD0_WP_MARK, 3509}; 3510/* - SDHI1 ------------------------------------------------------------------ */ 3511static const unsigned int sdhi1_data1_pins[] = { 3512 /* D0 */ 3513 RCAR_GP_PIN(3, 8), 3514}; 3515static const unsigned int sdhi1_data1_mux[] = { 3516 SD1_DAT0_MARK, 3517}; 3518static const unsigned int sdhi1_data4_pins[] = { 3519 /* D[0:3] */ 3520 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3521 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3522}; 3523static const unsigned int sdhi1_data4_mux[] = { 3524 SD1_DAT0_MARK, SD1_DAT1_MARK, 3525 SD1_DAT2_MARK, SD1_DAT3_MARK, 3526}; 3527static const unsigned int sdhi1_ctrl_pins[] = { 3528 /* CLK, CMD */ 3529 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 3530}; 3531static const unsigned int sdhi1_ctrl_mux[] = { 3532 SD1_CLK_MARK, SD1_CMD_MARK, 3533}; 3534static const unsigned int sdhi1_cd_pins[] = { 3535 /* CD */ 3536 RCAR_GP_PIN(3, 14), 3537}; 3538static const unsigned int sdhi1_cd_mux[] = { 3539 SD1_CD_MARK, 3540}; 3541static const unsigned int sdhi1_wp_pins[] = { 3542 /* WP */ 3543 RCAR_GP_PIN(3, 15), 3544}; 3545static const unsigned int sdhi1_wp_mux[] = { 3546 SD1_WP_MARK, 3547}; 3548/* - SDHI2 ------------------------------------------------------------------ */ 3549static const unsigned int sdhi2_data1_pins[] = { 3550 /* D0 */ 3551 RCAR_GP_PIN(4, 2), 3552}; 3553static const unsigned int sdhi2_data1_mux[] = { 3554 SD2_DAT0_MARK, 3555}; 3556static const unsigned int sdhi2_data4_pins[] = { 3557 /* D[0:3] */ 3558 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3559 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3560}; 3561static const unsigned int sdhi2_data4_mux[] = { 3562 SD2_DAT0_MARK, SD2_DAT1_MARK, 3563 SD2_DAT2_MARK, SD2_DAT3_MARK, 3564}; 3565static const unsigned int sdhi2_data8_pins[] = { 3566 /* D[0:7] */ 3567 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3568 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3569 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3570 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3571}; 3572static const unsigned int sdhi2_data8_mux[] = { 3573 SD2_DAT0_MARK, SD2_DAT1_MARK, 3574 SD2_DAT2_MARK, SD2_DAT3_MARK, 3575 SD2_DAT4_MARK, SD2_DAT5_MARK, 3576 SD2_DAT6_MARK, SD2_DAT7_MARK, 3577}; 3578static const unsigned int sdhi2_ctrl_pins[] = { 3579 /* CLK, CMD */ 3580 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 3581}; 3582static const unsigned int sdhi2_ctrl_mux[] = { 3583 SD2_CLK_MARK, SD2_CMD_MARK, 3584}; 3585static const unsigned int sdhi2_cd_a_pins[] = { 3586 /* CD */ 3587 RCAR_GP_PIN(4, 13), 3588}; 3589static const unsigned int sdhi2_cd_a_mux[] = { 3590 SD2_CD_A_MARK, 3591}; 3592static const unsigned int sdhi2_cd_b_pins[] = { 3593 /* CD */ 3594 RCAR_GP_PIN(5, 10), 3595}; 3596static const unsigned int sdhi2_cd_b_mux[] = { 3597 SD2_CD_B_MARK, 3598}; 3599static const unsigned int sdhi2_wp_a_pins[] = { 3600 /* WP */ 3601 RCAR_GP_PIN(4, 14), 3602}; 3603static const unsigned int sdhi2_wp_a_mux[] = { 3604 SD2_WP_A_MARK, 3605}; 3606static const unsigned int sdhi2_wp_b_pins[] = { 3607 /* WP */ 3608 RCAR_GP_PIN(5, 11), 3609}; 3610static const unsigned int sdhi2_wp_b_mux[] = { 3611 SD2_WP_B_MARK, 3612}; 3613static const unsigned int sdhi2_ds_pins[] = { 3614 /* DS */ 3615 RCAR_GP_PIN(4, 6), 3616}; 3617static const unsigned int sdhi2_ds_mux[] = { 3618 SD2_DS_MARK, 3619}; 3620/* - SDHI3 ------------------------------------------------------------------ */ 3621static const unsigned int sdhi3_data1_pins[] = { 3622 /* D0 */ 3623 RCAR_GP_PIN(4, 9), 3624}; 3625static const unsigned int sdhi3_data1_mux[] = { 3626 SD3_DAT0_MARK, 3627}; 3628static const unsigned int sdhi3_data4_pins[] = { 3629 /* D[0:3] */ 3630 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3631 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3632}; 3633static const unsigned int sdhi3_data4_mux[] = { 3634 SD3_DAT0_MARK, SD3_DAT1_MARK, 3635 SD3_DAT2_MARK, SD3_DAT3_MARK, 3636}; 3637static const unsigned int sdhi3_data8_pins[] = { 3638 /* D[0:7] */ 3639 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3640 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3641 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), 3642 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 3643}; 3644static const unsigned int sdhi3_data8_mux[] = { 3645 SD3_DAT0_MARK, SD3_DAT1_MARK, 3646 SD3_DAT2_MARK, SD3_DAT3_MARK, 3647 SD3_DAT4_MARK, SD3_DAT5_MARK, 3648 SD3_DAT6_MARK, SD3_DAT7_MARK, 3649}; 3650static const unsigned int sdhi3_ctrl_pins[] = { 3651 /* CLK, CMD */ 3652 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), 3653}; 3654static const unsigned int sdhi3_ctrl_mux[] = { 3655 SD3_CLK_MARK, SD3_CMD_MARK, 3656}; 3657static const unsigned int sdhi3_cd_pins[] = { 3658 /* CD */ 3659 RCAR_GP_PIN(4, 15), 3660}; 3661static const unsigned int sdhi3_cd_mux[] = { 3662 SD3_CD_MARK, 3663}; 3664static const unsigned int sdhi3_wp_pins[] = { 3665 /* WP */ 3666 RCAR_GP_PIN(4, 16), 3667}; 3668static const unsigned int sdhi3_wp_mux[] = { 3669 SD3_WP_MARK, 3670}; 3671static const unsigned int sdhi3_ds_pins[] = { 3672 /* DS */ 3673 RCAR_GP_PIN(4, 17), 3674}; 3675static const unsigned int sdhi3_ds_mux[] = { 3676 SD3_DS_MARK, 3677}; 3678 3679/* - SSI -------------------------------------------------------------------- */ 3680static const unsigned int ssi0_data_pins[] = { 3681 /* SDATA */ 3682 RCAR_GP_PIN(6, 2), 3683}; 3684static const unsigned int ssi0_data_mux[] = { 3685 SSI_SDATA0_MARK, 3686}; 3687static const unsigned int ssi01239_ctrl_pins[] = { 3688 /* SCK, WS */ 3689 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), 3690}; 3691static const unsigned int ssi01239_ctrl_mux[] = { 3692 SSI_SCK01239_MARK, SSI_WS01239_MARK, 3693}; 3694static const unsigned int ssi1_data_a_pins[] = { 3695 /* SDATA */ 3696 RCAR_GP_PIN(6, 3), 3697}; 3698static const unsigned int ssi1_data_a_mux[] = { 3699 SSI_SDATA1_A_MARK, 3700}; 3701static const unsigned int ssi1_data_b_pins[] = { 3702 /* SDATA */ 3703 RCAR_GP_PIN(5, 12), 3704}; 3705static const unsigned int ssi1_data_b_mux[] = { 3706 SSI_SDATA1_B_MARK, 3707}; 3708static const unsigned int ssi1_ctrl_a_pins[] = { 3709 /* SCK, WS */ 3710 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 3711}; 3712static const unsigned int ssi1_ctrl_a_mux[] = { 3713 SSI_SCK1_A_MARK, SSI_WS1_A_MARK, 3714}; 3715static const unsigned int ssi1_ctrl_b_pins[] = { 3716 /* SCK, WS */ 3717 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21), 3718}; 3719static const unsigned int ssi1_ctrl_b_mux[] = { 3720 SSI_SCK1_B_MARK, SSI_WS1_B_MARK, 3721}; 3722static const unsigned int ssi2_data_a_pins[] = { 3723 /* SDATA */ 3724 RCAR_GP_PIN(6, 4), 3725}; 3726static const unsigned int ssi2_data_a_mux[] = { 3727 SSI_SDATA2_A_MARK, 3728}; 3729static const unsigned int ssi2_data_b_pins[] = { 3730 /* SDATA */ 3731 RCAR_GP_PIN(5, 13), 3732}; 3733static const unsigned int ssi2_data_b_mux[] = { 3734 SSI_SDATA2_B_MARK, 3735}; 3736static const unsigned int ssi2_ctrl_a_pins[] = { 3737 /* SCK, WS */ 3738 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), 3739}; 3740static const unsigned int ssi2_ctrl_a_mux[] = { 3741 SSI_SCK2_A_MARK, SSI_WS2_A_MARK, 3742}; 3743static const unsigned int ssi2_ctrl_b_pins[] = { 3744 /* SCK, WS */ 3745 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 3746}; 3747static const unsigned int ssi2_ctrl_b_mux[] = { 3748 SSI_SCK2_B_MARK, SSI_WS2_B_MARK, 3749}; 3750static const unsigned int ssi3_data_pins[] = { 3751 /* SDATA */ 3752 RCAR_GP_PIN(6, 7), 3753}; 3754static const unsigned int ssi3_data_mux[] = { 3755 SSI_SDATA3_MARK, 3756}; 3757static const unsigned int ssi349_ctrl_pins[] = { 3758 /* SCK, WS */ 3759 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), 3760}; 3761static const unsigned int ssi349_ctrl_mux[] = { 3762 SSI_SCK349_MARK, SSI_WS349_MARK, 3763}; 3764static const unsigned int ssi4_data_pins[] = { 3765 /* SDATA */ 3766 RCAR_GP_PIN(6, 10), 3767}; 3768static const unsigned int ssi4_data_mux[] = { 3769 SSI_SDATA4_MARK, 3770}; 3771static const unsigned int ssi4_ctrl_pins[] = { 3772 /* SCK, WS */ 3773 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 3774}; 3775static const unsigned int ssi4_ctrl_mux[] = { 3776 SSI_SCK4_MARK, SSI_WS4_MARK, 3777}; 3778static const unsigned int ssi5_data_pins[] = { 3779 /* SDATA */ 3780 RCAR_GP_PIN(6, 13), 3781}; 3782static const unsigned int ssi5_data_mux[] = { 3783 SSI_SDATA5_MARK, 3784}; 3785static const unsigned int ssi5_ctrl_pins[] = { 3786 /* SCK, WS */ 3787 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), 3788}; 3789static const unsigned int ssi5_ctrl_mux[] = { 3790 SSI_SCK5_MARK, SSI_WS5_MARK, 3791}; 3792static const unsigned int ssi6_data_pins[] = { 3793 /* SDATA */ 3794 RCAR_GP_PIN(6, 16), 3795}; 3796static const unsigned int ssi6_data_mux[] = { 3797 SSI_SDATA6_MARK, 3798}; 3799static const unsigned int ssi6_ctrl_pins[] = { 3800 /* SCK, WS */ 3801 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), 3802}; 3803static const unsigned int ssi6_ctrl_mux[] = { 3804 SSI_SCK6_MARK, SSI_WS6_MARK, 3805}; 3806static const unsigned int ssi7_data_pins[] = { 3807 /* SDATA */ 3808 RCAR_GP_PIN(6, 19), 3809}; 3810static const unsigned int ssi7_data_mux[] = { 3811 SSI_SDATA7_MARK, 3812}; 3813static const unsigned int ssi78_ctrl_pins[] = { 3814 /* SCK, WS */ 3815 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 3816}; 3817static const unsigned int ssi78_ctrl_mux[] = { 3818 SSI_SCK78_MARK, SSI_WS78_MARK, 3819}; 3820static const unsigned int ssi8_data_pins[] = { 3821 /* SDATA */ 3822 RCAR_GP_PIN(6, 20), 3823}; 3824static const unsigned int ssi8_data_mux[] = { 3825 SSI_SDATA8_MARK, 3826}; 3827static const unsigned int ssi9_data_a_pins[] = { 3828 /* SDATA */ 3829 RCAR_GP_PIN(6, 21), 3830}; 3831static const unsigned int ssi9_data_a_mux[] = { 3832 SSI_SDATA9_A_MARK, 3833}; 3834static const unsigned int ssi9_data_b_pins[] = { 3835 /* SDATA */ 3836 RCAR_GP_PIN(5, 14), 3837}; 3838static const unsigned int ssi9_data_b_mux[] = { 3839 SSI_SDATA9_B_MARK, 3840}; 3841static const unsigned int ssi9_ctrl_a_pins[] = { 3842 /* SCK, WS */ 3843 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 3844}; 3845static const unsigned int ssi9_ctrl_a_mux[] = { 3846 SSI_SCK9_A_MARK, SSI_WS9_A_MARK, 3847}; 3848static const unsigned int ssi9_ctrl_b_pins[] = { 3849 /* SCK, WS */ 3850 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), 3851}; 3852static const unsigned int ssi9_ctrl_b_mux[] = { 3853 SSI_SCK9_B_MARK, SSI_WS9_B_MARK, 3854}; 3855 3856/* - TMU -------------------------------------------------------------------- */ 3857static const unsigned int tmu_tclk1_a_pins[] = { 3858 /* TCLK */ 3859 RCAR_GP_PIN(6, 23), 3860}; 3861static const unsigned int tmu_tclk1_a_mux[] = { 3862 TCLK1_A_MARK, 3863}; 3864static const unsigned int tmu_tclk1_b_pins[] = { 3865 /* TCLK */ 3866 RCAR_GP_PIN(5, 19), 3867}; 3868static const unsigned int tmu_tclk1_b_mux[] = { 3869 TCLK1_B_MARK, 3870}; 3871static const unsigned int tmu_tclk2_a_pins[] = { 3872 /* TCLK */ 3873 RCAR_GP_PIN(6, 19), 3874}; 3875static const unsigned int tmu_tclk2_a_mux[] = { 3876 TCLK2_A_MARK, 3877}; 3878static const unsigned int tmu_tclk2_b_pins[] = { 3879 /* TCLK */ 3880 RCAR_GP_PIN(6, 28), 3881}; 3882static const unsigned int tmu_tclk2_b_mux[] = { 3883 TCLK2_B_MARK, 3884}; 3885 3886/* - TPU ------------------------------------------------------------------- */ 3887static const unsigned int tpu_to0_pins[] = { 3888 /* TPU0TO0 */ 3889 RCAR_GP_PIN(6, 28), 3890}; 3891static const unsigned int tpu_to0_mux[] = { 3892 TPU0TO0_MARK, 3893}; 3894static const unsigned int tpu_to1_pins[] = { 3895 /* TPU0TO1 */ 3896 RCAR_GP_PIN(6, 29), 3897}; 3898static const unsigned int tpu_to1_mux[] = { 3899 TPU0TO1_MARK, 3900}; 3901static const unsigned int tpu_to2_pins[] = { 3902 /* TPU0TO2 */ 3903 RCAR_GP_PIN(6, 30), 3904}; 3905static const unsigned int tpu_to2_mux[] = { 3906 TPU0TO2_MARK, 3907}; 3908static const unsigned int tpu_to3_pins[] = { 3909 /* TPU0TO3 */ 3910 RCAR_GP_PIN(6, 31), 3911}; 3912static const unsigned int tpu_to3_mux[] = { 3913 TPU0TO3_MARK, 3914}; 3915 3916/* - USB0 ------------------------------------------------------------------- */ 3917static const unsigned int usb0_pins[] = { 3918 /* PWEN, OVC */ 3919 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 3920}; 3921static const unsigned int usb0_mux[] = { 3922 USB0_PWEN_MARK, USB0_OVC_MARK, 3923}; 3924/* - USB1 ------------------------------------------------------------------- */ 3925static const unsigned int usb1_pins[] = { 3926 /* PWEN, OVC */ 3927 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 3928}; 3929static const unsigned int usb1_mux[] = { 3930 USB1_PWEN_MARK, USB1_OVC_MARK, 3931}; 3932 3933/* - USB30 ------------------------------------------------------------------ */ 3934static const unsigned int usb30_pins[] = { 3935 /* PWEN, OVC */ 3936 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 3937}; 3938static const unsigned int usb30_mux[] = { 3939 USB30_PWEN_MARK, USB30_OVC_MARK, 3940}; 3941 3942/* - VIN4 ------------------------------------------------------------------- */ 3943static const unsigned int vin4_data18_a_pins[] = { 3944 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3945 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3946 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 3947 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 3948 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3949 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3950 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3951 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3952 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 3953}; 3954static const unsigned int vin4_data18_a_mux[] = { 3955 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 3956 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 3957 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 3958 VI4_DATA10_MARK, VI4_DATA11_MARK, 3959 VI4_DATA12_MARK, VI4_DATA13_MARK, 3960 VI4_DATA14_MARK, VI4_DATA15_MARK, 3961 VI4_DATA18_MARK, VI4_DATA19_MARK, 3962 VI4_DATA20_MARK, VI4_DATA21_MARK, 3963 VI4_DATA22_MARK, VI4_DATA23_MARK, 3964}; 3965static const unsigned int vin4_data18_b_pins[] = { 3966 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 3967 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 3968 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 3969 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 3970 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3971 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3972 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3973 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3974 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 3975}; 3976static const unsigned int vin4_data18_b_mux[] = { 3977 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 3978 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 3979 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 3980 VI4_DATA10_MARK, VI4_DATA11_MARK, 3981 VI4_DATA12_MARK, VI4_DATA13_MARK, 3982 VI4_DATA14_MARK, VI4_DATA15_MARK, 3983 VI4_DATA18_MARK, VI4_DATA19_MARK, 3984 VI4_DATA20_MARK, VI4_DATA21_MARK, 3985 VI4_DATA22_MARK, VI4_DATA23_MARK, 3986}; 3987static const union vin_data vin4_data_a_pins = { 3988 .data24 = { 3989 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 3990 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3991 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3992 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 3993 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 3994 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 3995 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3996 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3997 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 3998 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3999 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4000 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4001 }, 4002}; 4003static const union vin_data vin4_data_a_mux = { 4004 .data24 = { 4005 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, 4006 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 4007 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 4008 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 4009 VI4_DATA8_MARK, VI4_DATA9_MARK, 4010 VI4_DATA10_MARK, VI4_DATA11_MARK, 4011 VI4_DATA12_MARK, VI4_DATA13_MARK, 4012 VI4_DATA14_MARK, VI4_DATA15_MARK, 4013 VI4_DATA16_MARK, VI4_DATA17_MARK, 4014 VI4_DATA18_MARK, VI4_DATA19_MARK, 4015 VI4_DATA20_MARK, VI4_DATA21_MARK, 4016 VI4_DATA22_MARK, VI4_DATA23_MARK, 4017 }, 4018}; 4019static const union vin_data vin4_data_b_pins = { 4020 .data24 = { 4021 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 4022 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 4023 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 4024 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 4025 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 4026 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4027 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4028 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4029 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4030 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4031 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4032 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4033 }, 4034}; 4035static const union vin_data vin4_data_b_mux = { 4036 .data24 = { 4037 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, 4038 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 4039 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 4040 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 4041 VI4_DATA8_MARK, VI4_DATA9_MARK, 4042 VI4_DATA10_MARK, VI4_DATA11_MARK, 4043 VI4_DATA12_MARK, VI4_DATA13_MARK, 4044 VI4_DATA14_MARK, VI4_DATA15_MARK, 4045 VI4_DATA16_MARK, VI4_DATA17_MARK, 4046 VI4_DATA18_MARK, VI4_DATA19_MARK, 4047 VI4_DATA20_MARK, VI4_DATA21_MARK, 4048 VI4_DATA22_MARK, VI4_DATA23_MARK, 4049 }, 4050}; 4051static const unsigned int vin4_sync_pins[] = { 4052 /* HSYNC#, VSYNC# */ 4053 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17), 4054}; 4055static const unsigned int vin4_sync_mux[] = { 4056 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, 4057}; 4058static const unsigned int vin4_field_pins[] = { 4059 /* FIELD */ 4060 RCAR_GP_PIN(1, 16), 4061}; 4062static const unsigned int vin4_field_mux[] = { 4063 VI4_FIELD_MARK, 4064}; 4065static const unsigned int vin4_clkenb_pins[] = { 4066 /* CLKENB */ 4067 RCAR_GP_PIN(1, 19), 4068}; 4069static const unsigned int vin4_clkenb_mux[] = { 4070 VI4_CLKENB_MARK, 4071}; 4072static const unsigned int vin4_clk_pins[] = { 4073 /* CLK */ 4074 RCAR_GP_PIN(1, 27), 4075}; 4076static const unsigned int vin4_clk_mux[] = { 4077 VI4_CLK_MARK, 4078}; 4079 4080/* - VIN5 ------------------------------------------------------------------- */ 4081static const union vin_data16 vin5_data_pins = { 4082 .data16 = { 4083 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4084 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4085 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4086 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4087 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 4088 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 4089 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4090 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4091 }, 4092}; 4093static const union vin_data16 vin5_data_mux = { 4094 .data16 = { 4095 VI5_DATA0_MARK, VI5_DATA1_MARK, 4096 VI5_DATA2_MARK, VI5_DATA3_MARK, 4097 VI5_DATA4_MARK, VI5_DATA5_MARK, 4098 VI5_DATA6_MARK, VI5_DATA7_MARK, 4099 VI5_DATA8_MARK, VI5_DATA9_MARK, 4100 VI5_DATA10_MARK, VI5_DATA11_MARK, 4101 VI5_DATA12_MARK, VI5_DATA13_MARK, 4102 VI5_DATA14_MARK, VI5_DATA15_MARK, 4103 }, 4104}; 4105static const unsigned int vin5_sync_pins[] = { 4106 /* HSYNC#, VSYNC# */ 4107 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), 4108}; 4109static const unsigned int vin5_sync_mux[] = { 4110 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK, 4111}; 4112static const unsigned int vin5_field_pins[] = { 4113 RCAR_GP_PIN(1, 11), 4114}; 4115static const unsigned int vin5_field_mux[] = { 4116 /* FIELD */ 4117 VI5_FIELD_MARK, 4118}; 4119static const unsigned int vin5_clkenb_pins[] = { 4120 RCAR_GP_PIN(1, 20), 4121}; 4122static const unsigned int vin5_clkenb_mux[] = { 4123 /* CLKENB */ 4124 VI5_CLKENB_MARK, 4125}; 4126static const unsigned int vin5_clk_pins[] = { 4127 RCAR_GP_PIN(1, 21), 4128}; 4129static const unsigned int vin5_clk_mux[] = { 4130 /* CLK */ 4131 VI5_CLK_MARK, 4132}; 4133 4134static const struct { 4135 struct sh_pfc_pin_group common[316]; 4136 struct sh_pfc_pin_group automotive[30]; 4137} pinmux_groups = { 4138 .common = { 4139 SH_PFC_PIN_GROUP(audio_clk_a_a), 4140 SH_PFC_PIN_GROUP(audio_clk_a_b), 4141 SH_PFC_PIN_GROUP(audio_clk_a_c), 4142 SH_PFC_PIN_GROUP(audio_clk_b_a), 4143 SH_PFC_PIN_GROUP(audio_clk_b_b), 4144 SH_PFC_PIN_GROUP(audio_clk_c_a), 4145 SH_PFC_PIN_GROUP(audio_clk_c_b), 4146 SH_PFC_PIN_GROUP(audio_clkout_a), 4147 SH_PFC_PIN_GROUP(audio_clkout_b), 4148 SH_PFC_PIN_GROUP(audio_clkout_c), 4149 SH_PFC_PIN_GROUP(audio_clkout_d), 4150 SH_PFC_PIN_GROUP(audio_clkout1_a), 4151 SH_PFC_PIN_GROUP(audio_clkout1_b), 4152 SH_PFC_PIN_GROUP(audio_clkout2_a), 4153 SH_PFC_PIN_GROUP(audio_clkout2_b), 4154 SH_PFC_PIN_GROUP(audio_clkout3_a), 4155 SH_PFC_PIN_GROUP(audio_clkout3_b), 4156 SH_PFC_PIN_GROUP(avb_link), 4157 SH_PFC_PIN_GROUP(avb_magic), 4158 SH_PFC_PIN_GROUP(avb_phy_int), 4159 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ 4160 SH_PFC_PIN_GROUP(avb_mdio), 4161 SH_PFC_PIN_GROUP(avb_mii), 4162 SH_PFC_PIN_GROUP(avb_avtp_pps), 4163 SH_PFC_PIN_GROUP(avb_avtp_match_a), 4164 SH_PFC_PIN_GROUP(avb_avtp_capture_a), 4165 SH_PFC_PIN_GROUP(avb_avtp_match_b), 4166 SH_PFC_PIN_GROUP(avb_avtp_capture_b), 4167 SH_PFC_PIN_GROUP(can0_data_a), 4168 SH_PFC_PIN_GROUP(can0_data_b), 4169 SH_PFC_PIN_GROUP(can1_data), 4170 SH_PFC_PIN_GROUP(can_clk), 4171 SH_PFC_PIN_GROUP(canfd0_data_a), 4172 SH_PFC_PIN_GROUP(canfd0_data_b), 4173 SH_PFC_PIN_GROUP(canfd1_data), 4174 SH_PFC_PIN_GROUP(du_rgb666), 4175 SH_PFC_PIN_GROUP(du_rgb888), 4176 SH_PFC_PIN_GROUP(du_clk_out_0), 4177 SH_PFC_PIN_GROUP(du_clk_out_1), 4178 SH_PFC_PIN_GROUP(du_sync), 4179 SH_PFC_PIN_GROUP(du_oddf), 4180 SH_PFC_PIN_GROUP(du_cde), 4181 SH_PFC_PIN_GROUP(du_disp), 4182 SH_PFC_PIN_GROUP(hscif0_data), 4183 SH_PFC_PIN_GROUP(hscif0_clk), 4184 SH_PFC_PIN_GROUP(hscif0_ctrl), 4185 SH_PFC_PIN_GROUP(hscif1_data_a), 4186 SH_PFC_PIN_GROUP(hscif1_clk_a), 4187 SH_PFC_PIN_GROUP(hscif1_ctrl_a), 4188 SH_PFC_PIN_GROUP(hscif1_data_b), 4189 SH_PFC_PIN_GROUP(hscif1_clk_b), 4190 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 4191 SH_PFC_PIN_GROUP(hscif2_data_a), 4192 SH_PFC_PIN_GROUP(hscif2_clk_a), 4193 SH_PFC_PIN_GROUP(hscif2_ctrl_a), 4194 SH_PFC_PIN_GROUP(hscif2_data_b), 4195 SH_PFC_PIN_GROUP(hscif2_clk_b), 4196 SH_PFC_PIN_GROUP(hscif2_ctrl_b), 4197 SH_PFC_PIN_GROUP(hscif2_data_c), 4198 SH_PFC_PIN_GROUP(hscif2_clk_c), 4199 SH_PFC_PIN_GROUP(hscif2_ctrl_c), 4200 SH_PFC_PIN_GROUP(hscif3_data_a), 4201 SH_PFC_PIN_GROUP(hscif3_clk), 4202 SH_PFC_PIN_GROUP(hscif3_ctrl), 4203 SH_PFC_PIN_GROUP(hscif3_data_b), 4204 SH_PFC_PIN_GROUP(hscif3_data_c), 4205 SH_PFC_PIN_GROUP(hscif3_data_d), 4206 SH_PFC_PIN_GROUP(hscif4_data_a), 4207 SH_PFC_PIN_GROUP(hscif4_clk), 4208 SH_PFC_PIN_GROUP(hscif4_ctrl), 4209 SH_PFC_PIN_GROUP(hscif4_data_b), 4210 SH_PFC_PIN_GROUP(i2c0), 4211 SH_PFC_PIN_GROUP(i2c1_a), 4212 SH_PFC_PIN_GROUP(i2c1_b), 4213 SH_PFC_PIN_GROUP(i2c2_a), 4214 SH_PFC_PIN_GROUP(i2c2_b), 4215 SH_PFC_PIN_GROUP(i2c3), 4216 SH_PFC_PIN_GROUP(i2c5), 4217 SH_PFC_PIN_GROUP(i2c6_a), 4218 SH_PFC_PIN_GROUP(i2c6_b), 4219 SH_PFC_PIN_GROUP(i2c6_c), 4220 SH_PFC_PIN_GROUP(intc_ex_irq0), 4221 SH_PFC_PIN_GROUP(intc_ex_irq1), 4222 SH_PFC_PIN_GROUP(intc_ex_irq2), 4223 SH_PFC_PIN_GROUP(intc_ex_irq3), 4224 SH_PFC_PIN_GROUP(intc_ex_irq4), 4225 SH_PFC_PIN_GROUP(intc_ex_irq5), 4226 SH_PFC_PIN_GROUP(msiof0_clk), 4227 SH_PFC_PIN_GROUP(msiof0_sync), 4228 SH_PFC_PIN_GROUP(msiof0_ss1), 4229 SH_PFC_PIN_GROUP(msiof0_ss2), 4230 SH_PFC_PIN_GROUP(msiof0_txd), 4231 SH_PFC_PIN_GROUP(msiof0_rxd), 4232 SH_PFC_PIN_GROUP(msiof1_clk_a), 4233 SH_PFC_PIN_GROUP(msiof1_sync_a), 4234 SH_PFC_PIN_GROUP(msiof1_ss1_a), 4235 SH_PFC_PIN_GROUP(msiof1_ss2_a), 4236 SH_PFC_PIN_GROUP(msiof1_txd_a), 4237 SH_PFC_PIN_GROUP(msiof1_rxd_a), 4238 SH_PFC_PIN_GROUP(msiof1_clk_b), 4239 SH_PFC_PIN_GROUP(msiof1_sync_b), 4240 SH_PFC_PIN_GROUP(msiof1_ss1_b), 4241 SH_PFC_PIN_GROUP(msiof1_ss2_b), 4242 SH_PFC_PIN_GROUP(msiof1_txd_b), 4243 SH_PFC_PIN_GROUP(msiof1_rxd_b), 4244 SH_PFC_PIN_GROUP(msiof1_clk_c), 4245 SH_PFC_PIN_GROUP(msiof1_sync_c), 4246 SH_PFC_PIN_GROUP(msiof1_ss1_c), 4247 SH_PFC_PIN_GROUP(msiof1_ss2_c), 4248 SH_PFC_PIN_GROUP(msiof1_txd_c), 4249 SH_PFC_PIN_GROUP(msiof1_rxd_c), 4250 SH_PFC_PIN_GROUP(msiof1_clk_d), 4251 SH_PFC_PIN_GROUP(msiof1_sync_d), 4252 SH_PFC_PIN_GROUP(msiof1_ss1_d), 4253 SH_PFC_PIN_GROUP(msiof1_ss2_d), 4254 SH_PFC_PIN_GROUP(msiof1_txd_d), 4255 SH_PFC_PIN_GROUP(msiof1_rxd_d), 4256 SH_PFC_PIN_GROUP(msiof1_clk_e), 4257 SH_PFC_PIN_GROUP(msiof1_sync_e), 4258 SH_PFC_PIN_GROUP(msiof1_ss1_e), 4259 SH_PFC_PIN_GROUP(msiof1_ss2_e), 4260 SH_PFC_PIN_GROUP(msiof1_txd_e), 4261 SH_PFC_PIN_GROUP(msiof1_rxd_e), 4262 SH_PFC_PIN_GROUP(msiof1_clk_f), 4263 SH_PFC_PIN_GROUP(msiof1_sync_f), 4264 SH_PFC_PIN_GROUP(msiof1_ss1_f), 4265 SH_PFC_PIN_GROUP(msiof1_ss2_f), 4266 SH_PFC_PIN_GROUP(msiof1_txd_f), 4267 SH_PFC_PIN_GROUP(msiof1_rxd_f), 4268 SH_PFC_PIN_GROUP(msiof1_clk_g), 4269 SH_PFC_PIN_GROUP(msiof1_sync_g), 4270 SH_PFC_PIN_GROUP(msiof1_ss1_g), 4271 SH_PFC_PIN_GROUP(msiof1_ss2_g), 4272 SH_PFC_PIN_GROUP(msiof1_txd_g), 4273 SH_PFC_PIN_GROUP(msiof1_rxd_g), 4274 SH_PFC_PIN_GROUP(msiof2_clk_a), 4275 SH_PFC_PIN_GROUP(msiof2_sync_a), 4276 SH_PFC_PIN_GROUP(msiof2_ss1_a), 4277 SH_PFC_PIN_GROUP(msiof2_ss2_a), 4278 SH_PFC_PIN_GROUP(msiof2_txd_a), 4279 SH_PFC_PIN_GROUP(msiof2_rxd_a), 4280 SH_PFC_PIN_GROUP(msiof2_clk_b), 4281 SH_PFC_PIN_GROUP(msiof2_sync_b), 4282 SH_PFC_PIN_GROUP(msiof2_ss1_b), 4283 SH_PFC_PIN_GROUP(msiof2_ss2_b), 4284 SH_PFC_PIN_GROUP(msiof2_txd_b), 4285 SH_PFC_PIN_GROUP(msiof2_rxd_b), 4286 SH_PFC_PIN_GROUP(msiof2_clk_c), 4287 SH_PFC_PIN_GROUP(msiof2_sync_c), 4288 SH_PFC_PIN_GROUP(msiof2_ss1_c), 4289 SH_PFC_PIN_GROUP(msiof2_ss2_c), 4290 SH_PFC_PIN_GROUP(msiof2_txd_c), 4291 SH_PFC_PIN_GROUP(msiof2_rxd_c), 4292 SH_PFC_PIN_GROUP(msiof2_clk_d), 4293 SH_PFC_PIN_GROUP(msiof2_sync_d), 4294 SH_PFC_PIN_GROUP(msiof2_ss1_d), 4295 SH_PFC_PIN_GROUP(msiof2_ss2_d), 4296 SH_PFC_PIN_GROUP(msiof2_txd_d), 4297 SH_PFC_PIN_GROUP(msiof2_rxd_d), 4298 SH_PFC_PIN_GROUP(msiof3_clk_a), 4299 SH_PFC_PIN_GROUP(msiof3_sync_a), 4300 SH_PFC_PIN_GROUP(msiof3_ss1_a), 4301 SH_PFC_PIN_GROUP(msiof3_ss2_a), 4302 SH_PFC_PIN_GROUP(msiof3_txd_a), 4303 SH_PFC_PIN_GROUP(msiof3_rxd_a), 4304 SH_PFC_PIN_GROUP(msiof3_clk_b), 4305 SH_PFC_PIN_GROUP(msiof3_sync_b), 4306 SH_PFC_PIN_GROUP(msiof3_ss1_b), 4307 SH_PFC_PIN_GROUP(msiof3_ss2_b), 4308 SH_PFC_PIN_GROUP(msiof3_txd_b), 4309 SH_PFC_PIN_GROUP(msiof3_rxd_b), 4310 SH_PFC_PIN_GROUP(msiof3_clk_c), 4311 SH_PFC_PIN_GROUP(msiof3_sync_c), 4312 SH_PFC_PIN_GROUP(msiof3_txd_c), 4313 SH_PFC_PIN_GROUP(msiof3_rxd_c), 4314 SH_PFC_PIN_GROUP(msiof3_clk_d), 4315 SH_PFC_PIN_GROUP(msiof3_sync_d), 4316 SH_PFC_PIN_GROUP(msiof3_ss1_d), 4317 SH_PFC_PIN_GROUP(msiof3_txd_d), 4318 SH_PFC_PIN_GROUP(msiof3_rxd_d), 4319 SH_PFC_PIN_GROUP(msiof3_clk_e), 4320 SH_PFC_PIN_GROUP(msiof3_sync_e), 4321 SH_PFC_PIN_GROUP(msiof3_ss1_e), 4322 SH_PFC_PIN_GROUP(msiof3_ss2_e), 4323 SH_PFC_PIN_GROUP(msiof3_txd_e), 4324 SH_PFC_PIN_GROUP(msiof3_rxd_e), 4325 SH_PFC_PIN_GROUP(pwm0), 4326 SH_PFC_PIN_GROUP(pwm1_a), 4327 SH_PFC_PIN_GROUP(pwm1_b), 4328 SH_PFC_PIN_GROUP(pwm2_a), 4329 SH_PFC_PIN_GROUP(pwm2_b), 4330 SH_PFC_PIN_GROUP(pwm3_a), 4331 SH_PFC_PIN_GROUP(pwm3_b), 4332 SH_PFC_PIN_GROUP(pwm4_a), 4333 SH_PFC_PIN_GROUP(pwm4_b), 4334 SH_PFC_PIN_GROUP(pwm5_a), 4335 SH_PFC_PIN_GROUP(pwm5_b), 4336 SH_PFC_PIN_GROUP(pwm6_a), 4337 SH_PFC_PIN_GROUP(pwm6_b), 4338 SH_PFC_PIN_GROUP(scif0_data), 4339 SH_PFC_PIN_GROUP(scif0_clk), 4340 SH_PFC_PIN_GROUP(scif0_ctrl), 4341 SH_PFC_PIN_GROUP(scif1_data_a), 4342 SH_PFC_PIN_GROUP(scif1_clk), 4343 SH_PFC_PIN_GROUP(scif1_ctrl), 4344 SH_PFC_PIN_GROUP(scif1_data_b), 4345 SH_PFC_PIN_GROUP(scif2_data_a), 4346 SH_PFC_PIN_GROUP(scif2_clk), 4347 SH_PFC_PIN_GROUP(scif2_data_b), 4348 SH_PFC_PIN_GROUP(scif3_data_a), 4349 SH_PFC_PIN_GROUP(scif3_clk), 4350 SH_PFC_PIN_GROUP(scif3_ctrl), 4351 SH_PFC_PIN_GROUP(scif3_data_b), 4352 SH_PFC_PIN_GROUP(scif4_data_a), 4353 SH_PFC_PIN_GROUP(scif4_clk_a), 4354 SH_PFC_PIN_GROUP(scif4_ctrl_a), 4355 SH_PFC_PIN_GROUP(scif4_data_b), 4356 SH_PFC_PIN_GROUP(scif4_clk_b), 4357 SH_PFC_PIN_GROUP(scif4_ctrl_b), 4358 SH_PFC_PIN_GROUP(scif4_data_c), 4359 SH_PFC_PIN_GROUP(scif4_clk_c), 4360 SH_PFC_PIN_GROUP(scif4_ctrl_c), 4361 SH_PFC_PIN_GROUP(scif5_data_a), 4362 SH_PFC_PIN_GROUP(scif5_clk_a), 4363 SH_PFC_PIN_GROUP(scif5_data_b), 4364 SH_PFC_PIN_GROUP(scif5_clk_b), 4365 SH_PFC_PIN_GROUP(scif_clk_a), 4366 SH_PFC_PIN_GROUP(scif_clk_b), 4367 SH_PFC_PIN_GROUP(sdhi0_data1), 4368 SH_PFC_PIN_GROUP(sdhi0_data4), 4369 SH_PFC_PIN_GROUP(sdhi0_ctrl), 4370 SH_PFC_PIN_GROUP(sdhi0_cd), 4371 SH_PFC_PIN_GROUP(sdhi0_wp), 4372 SH_PFC_PIN_GROUP(sdhi1_data1), 4373 SH_PFC_PIN_GROUP(sdhi1_data4), 4374 SH_PFC_PIN_GROUP(sdhi1_ctrl), 4375 SH_PFC_PIN_GROUP(sdhi1_cd), 4376 SH_PFC_PIN_GROUP(sdhi1_wp), 4377 SH_PFC_PIN_GROUP(sdhi2_data1), 4378 SH_PFC_PIN_GROUP(sdhi2_data4), 4379 SH_PFC_PIN_GROUP(sdhi2_data8), 4380 SH_PFC_PIN_GROUP(sdhi2_ctrl), 4381 SH_PFC_PIN_GROUP(sdhi2_cd_a), 4382 SH_PFC_PIN_GROUP(sdhi2_wp_a), 4383 SH_PFC_PIN_GROUP(sdhi2_cd_b), 4384 SH_PFC_PIN_GROUP(sdhi2_wp_b), 4385 SH_PFC_PIN_GROUP(sdhi2_ds), 4386 SH_PFC_PIN_GROUP(sdhi3_data1), 4387 SH_PFC_PIN_GROUP(sdhi3_data4), 4388 SH_PFC_PIN_GROUP(sdhi3_data8), 4389 SH_PFC_PIN_GROUP(sdhi3_ctrl), 4390 SH_PFC_PIN_GROUP(sdhi3_cd), 4391 SH_PFC_PIN_GROUP(sdhi3_wp), 4392 SH_PFC_PIN_GROUP(sdhi3_ds), 4393 SH_PFC_PIN_GROUP(ssi0_data), 4394 SH_PFC_PIN_GROUP(ssi01239_ctrl), 4395 SH_PFC_PIN_GROUP(ssi1_data_a), 4396 SH_PFC_PIN_GROUP(ssi1_data_b), 4397 SH_PFC_PIN_GROUP(ssi1_ctrl_a), 4398 SH_PFC_PIN_GROUP(ssi1_ctrl_b), 4399 SH_PFC_PIN_GROUP(ssi2_data_a), 4400 SH_PFC_PIN_GROUP(ssi2_data_b), 4401 SH_PFC_PIN_GROUP(ssi2_ctrl_a), 4402 SH_PFC_PIN_GROUP(ssi2_ctrl_b), 4403 SH_PFC_PIN_GROUP(ssi3_data), 4404 SH_PFC_PIN_GROUP(ssi349_ctrl), 4405 SH_PFC_PIN_GROUP(ssi4_data), 4406 SH_PFC_PIN_GROUP(ssi4_ctrl), 4407 SH_PFC_PIN_GROUP(ssi5_data), 4408 SH_PFC_PIN_GROUP(ssi5_ctrl), 4409 SH_PFC_PIN_GROUP(ssi6_data), 4410 SH_PFC_PIN_GROUP(ssi6_ctrl), 4411 SH_PFC_PIN_GROUP(ssi7_data), 4412 SH_PFC_PIN_GROUP(ssi78_ctrl), 4413 SH_PFC_PIN_GROUP(ssi8_data), 4414 SH_PFC_PIN_GROUP(ssi9_data_a), 4415 SH_PFC_PIN_GROUP(ssi9_data_b), 4416 SH_PFC_PIN_GROUP(ssi9_ctrl_a), 4417 SH_PFC_PIN_GROUP(ssi9_ctrl_b), 4418 SH_PFC_PIN_GROUP(tmu_tclk1_a), 4419 SH_PFC_PIN_GROUP(tmu_tclk1_b), 4420 SH_PFC_PIN_GROUP(tmu_tclk2_a), 4421 SH_PFC_PIN_GROUP(tmu_tclk2_b), 4422 SH_PFC_PIN_GROUP(tpu_to0), 4423 SH_PFC_PIN_GROUP(tpu_to1), 4424 SH_PFC_PIN_GROUP(tpu_to2), 4425 SH_PFC_PIN_GROUP(tpu_to3), 4426 SH_PFC_PIN_GROUP(usb0), 4427 SH_PFC_PIN_GROUP(usb1), 4428 SH_PFC_PIN_GROUP(usb30), 4429 VIN_DATA_PIN_GROUP(vin4_data, 8, _a), 4430 VIN_DATA_PIN_GROUP(vin4_data, 10, _a), 4431 VIN_DATA_PIN_GROUP(vin4_data, 12, _a), 4432 VIN_DATA_PIN_GROUP(vin4_data, 16, _a), 4433 SH_PFC_PIN_GROUP(vin4_data18_a), 4434 VIN_DATA_PIN_GROUP(vin4_data, 20, _a), 4435 VIN_DATA_PIN_GROUP(vin4_data, 24, _a), 4436 VIN_DATA_PIN_GROUP(vin4_data, 8, _b), 4437 VIN_DATA_PIN_GROUP(vin4_data, 10, _b), 4438 VIN_DATA_PIN_GROUP(vin4_data, 12, _b), 4439 VIN_DATA_PIN_GROUP(vin4_data, 16, _b), 4440 SH_PFC_PIN_GROUP(vin4_data18_b), 4441 VIN_DATA_PIN_GROUP(vin4_data, 20, _b), 4442 VIN_DATA_PIN_GROUP(vin4_data, 24, _b), 4443 SH_PFC_PIN_GROUP(vin4_sync), 4444 SH_PFC_PIN_GROUP(vin4_field), 4445 SH_PFC_PIN_GROUP(vin4_clkenb), 4446 SH_PFC_PIN_GROUP(vin4_clk), 4447 VIN_DATA_PIN_GROUP(vin5_data, 8), 4448 VIN_DATA_PIN_GROUP(vin5_data, 10), 4449 VIN_DATA_PIN_GROUP(vin5_data, 12), 4450 VIN_DATA_PIN_GROUP(vin5_data, 16), 4451 SH_PFC_PIN_GROUP(vin5_sync), 4452 SH_PFC_PIN_GROUP(vin5_field), 4453 SH_PFC_PIN_GROUP(vin5_clkenb), 4454 SH_PFC_PIN_GROUP(vin5_clk), 4455 }, 4456 .automotive = { 4457 SH_PFC_PIN_GROUP(drif0_ctrl_a), 4458 SH_PFC_PIN_GROUP(drif0_data0_a), 4459 SH_PFC_PIN_GROUP(drif0_data1_a), 4460 SH_PFC_PIN_GROUP(drif0_ctrl_b), 4461 SH_PFC_PIN_GROUP(drif0_data0_b), 4462 SH_PFC_PIN_GROUP(drif0_data1_b), 4463 SH_PFC_PIN_GROUP(drif0_ctrl_c), 4464 SH_PFC_PIN_GROUP(drif0_data0_c), 4465 SH_PFC_PIN_GROUP(drif0_data1_c), 4466 SH_PFC_PIN_GROUP(drif1_ctrl_a), 4467 SH_PFC_PIN_GROUP(drif1_data0_a), 4468 SH_PFC_PIN_GROUP(drif1_data1_a), 4469 SH_PFC_PIN_GROUP(drif1_ctrl_b), 4470 SH_PFC_PIN_GROUP(drif1_data0_b), 4471 SH_PFC_PIN_GROUP(drif1_data1_b), 4472 SH_PFC_PIN_GROUP(drif1_ctrl_c), 4473 SH_PFC_PIN_GROUP(drif1_data0_c), 4474 SH_PFC_PIN_GROUP(drif1_data1_c), 4475 SH_PFC_PIN_GROUP(drif2_ctrl_a), 4476 SH_PFC_PIN_GROUP(drif2_data0_a), 4477 SH_PFC_PIN_GROUP(drif2_data1_a), 4478 SH_PFC_PIN_GROUP(drif2_ctrl_b), 4479 SH_PFC_PIN_GROUP(drif2_data0_b), 4480 SH_PFC_PIN_GROUP(drif2_data1_b), 4481 SH_PFC_PIN_GROUP(drif3_ctrl_a), 4482 SH_PFC_PIN_GROUP(drif3_data0_a), 4483 SH_PFC_PIN_GROUP(drif3_data1_a), 4484 SH_PFC_PIN_GROUP(drif3_ctrl_b), 4485 SH_PFC_PIN_GROUP(drif3_data0_b), 4486 SH_PFC_PIN_GROUP(drif3_data1_b), 4487 } 4488}; 4489 4490static const char * const audio_clk_groups[] = { 4491 "audio_clk_a_a", 4492 "audio_clk_a_b", 4493 "audio_clk_a_c", 4494 "audio_clk_b_a", 4495 "audio_clk_b_b", 4496 "audio_clk_c_a", 4497 "audio_clk_c_b", 4498 "audio_clkout_a", 4499 "audio_clkout_b", 4500 "audio_clkout_c", 4501 "audio_clkout_d", 4502 "audio_clkout1_a", 4503 "audio_clkout1_b", 4504 "audio_clkout2_a", 4505 "audio_clkout2_b", 4506 "audio_clkout3_a", 4507 "audio_clkout3_b", 4508}; 4509 4510static const char * const avb_groups[] = { 4511 "avb_link", 4512 "avb_magic", 4513 "avb_phy_int", 4514 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */ 4515 "avb_mdio", 4516 "avb_mii", 4517 "avb_avtp_pps", 4518 "avb_avtp_match_a", 4519 "avb_avtp_capture_a", 4520 "avb_avtp_match_b", 4521 "avb_avtp_capture_b", 4522}; 4523 4524static const char * const can0_groups[] = { 4525 "can0_data_a", 4526 "can0_data_b", 4527}; 4528 4529static const char * const can1_groups[] = { 4530 "can1_data", 4531}; 4532 4533static const char * const can_clk_groups[] = { 4534 "can_clk", 4535}; 4536 4537static const char * const canfd0_groups[] = { 4538 "canfd0_data_a", 4539 "canfd0_data_b", 4540}; 4541 4542static const char * const canfd1_groups[] = { 4543 "canfd1_data", 4544}; 4545 4546static const char * const drif0_groups[] = { 4547 "drif0_ctrl_a", 4548 "drif0_data0_a", 4549 "drif0_data1_a", 4550 "drif0_ctrl_b", 4551 "drif0_data0_b", 4552 "drif0_data1_b", 4553 "drif0_ctrl_c", 4554 "drif0_data0_c", 4555 "drif0_data1_c", 4556}; 4557 4558static const char * const drif1_groups[] = { 4559 "drif1_ctrl_a", 4560 "drif1_data0_a", 4561 "drif1_data1_a", 4562 "drif1_ctrl_b", 4563 "drif1_data0_b", 4564 "drif1_data1_b", 4565 "drif1_ctrl_c", 4566 "drif1_data0_c", 4567 "drif1_data1_c", 4568}; 4569 4570static const char * const drif2_groups[] = { 4571 "drif2_ctrl_a", 4572 "drif2_data0_a", 4573 "drif2_data1_a", 4574 "drif2_ctrl_b", 4575 "drif2_data0_b", 4576 "drif2_data1_b", 4577}; 4578 4579static const char * const drif3_groups[] = { 4580 "drif3_ctrl_a", 4581 "drif3_data0_a", 4582 "drif3_data1_a", 4583 "drif3_ctrl_b", 4584 "drif3_data0_b", 4585 "drif3_data1_b", 4586}; 4587 4588static const char * const du_groups[] = { 4589 "du_rgb666", 4590 "du_rgb888", 4591 "du_clk_out_0", 4592 "du_clk_out_1", 4593 "du_sync", 4594 "du_oddf", 4595 "du_cde", 4596 "du_disp", 4597}; 4598 4599static const char * const hscif0_groups[] = { 4600 "hscif0_data", 4601 "hscif0_clk", 4602 "hscif0_ctrl", 4603}; 4604 4605static const char * const hscif1_groups[] = { 4606 "hscif1_data_a", 4607 "hscif1_clk_a", 4608 "hscif1_ctrl_a", 4609 "hscif1_data_b", 4610 "hscif1_clk_b", 4611 "hscif1_ctrl_b", 4612}; 4613 4614static const char * const hscif2_groups[] = { 4615 "hscif2_data_a", 4616 "hscif2_clk_a", 4617 "hscif2_ctrl_a", 4618 "hscif2_data_b", 4619 "hscif2_clk_b", 4620 "hscif2_ctrl_b", 4621 "hscif2_data_c", 4622 "hscif2_clk_c", 4623 "hscif2_ctrl_c", 4624}; 4625 4626static const char * const hscif3_groups[] = { 4627 "hscif3_data_a", 4628 "hscif3_clk", 4629 "hscif3_ctrl", 4630 "hscif3_data_b", 4631 "hscif3_data_c", 4632 "hscif3_data_d", 4633}; 4634 4635static const char * const hscif4_groups[] = { 4636 "hscif4_data_a", 4637 "hscif4_clk", 4638 "hscif4_ctrl", 4639 "hscif4_data_b", 4640}; 4641 4642static const char * const i2c0_groups[] = { 4643 "i2c0", 4644}; 4645 4646static const char * const i2c1_groups[] = { 4647 "i2c1_a", 4648 "i2c1_b", 4649}; 4650 4651static const char * const i2c2_groups[] = { 4652 "i2c2_a", 4653 "i2c2_b", 4654}; 4655 4656static const char * const i2c3_groups[] = { 4657 "i2c3", 4658}; 4659 4660static const char * const i2c5_groups[] = { 4661 "i2c5", 4662}; 4663 4664static const char * const i2c6_groups[] = { 4665 "i2c6_a", 4666 "i2c6_b", 4667 "i2c6_c", 4668}; 4669 4670static const char * const intc_ex_groups[] = { 4671 "intc_ex_irq0", 4672 "intc_ex_irq1", 4673 "intc_ex_irq2", 4674 "intc_ex_irq3", 4675 "intc_ex_irq4", 4676 "intc_ex_irq5", 4677}; 4678 4679static const char * const msiof0_groups[] = { 4680 "msiof0_clk", 4681 "msiof0_sync", 4682 "msiof0_ss1", 4683 "msiof0_ss2", 4684 "msiof0_txd", 4685 "msiof0_rxd", 4686}; 4687 4688static const char * const msiof1_groups[] = { 4689 "msiof1_clk_a", 4690 "msiof1_sync_a", 4691 "msiof1_ss1_a", 4692 "msiof1_ss2_a", 4693 "msiof1_txd_a", 4694 "msiof1_rxd_a", 4695 "msiof1_clk_b", 4696 "msiof1_sync_b", 4697 "msiof1_ss1_b", 4698 "msiof1_ss2_b", 4699 "msiof1_txd_b", 4700 "msiof1_rxd_b", 4701 "msiof1_clk_c", 4702 "msiof1_sync_c", 4703 "msiof1_ss1_c", 4704 "msiof1_ss2_c", 4705 "msiof1_txd_c", 4706 "msiof1_rxd_c", 4707 "msiof1_clk_d", 4708 "msiof1_sync_d", 4709 "msiof1_ss1_d", 4710 "msiof1_ss2_d", 4711 "msiof1_txd_d", 4712 "msiof1_rxd_d", 4713 "msiof1_clk_e", 4714 "msiof1_sync_e", 4715 "msiof1_ss1_e", 4716 "msiof1_ss2_e", 4717 "msiof1_txd_e", 4718 "msiof1_rxd_e", 4719 "msiof1_clk_f", 4720 "msiof1_sync_f", 4721 "msiof1_ss1_f", 4722 "msiof1_ss2_f", 4723 "msiof1_txd_f", 4724 "msiof1_rxd_f", 4725 "msiof1_clk_g", 4726 "msiof1_sync_g", 4727 "msiof1_ss1_g", 4728 "msiof1_ss2_g", 4729 "msiof1_txd_g", 4730 "msiof1_rxd_g", 4731}; 4732 4733static const char * const msiof2_groups[] = { 4734 "msiof2_clk_a", 4735 "msiof2_sync_a", 4736 "msiof2_ss1_a", 4737 "msiof2_ss2_a", 4738 "msiof2_txd_a", 4739 "msiof2_rxd_a", 4740 "msiof2_clk_b", 4741 "msiof2_sync_b", 4742 "msiof2_ss1_b", 4743 "msiof2_ss2_b", 4744 "msiof2_txd_b", 4745 "msiof2_rxd_b", 4746 "msiof2_clk_c", 4747 "msiof2_sync_c", 4748 "msiof2_ss1_c", 4749 "msiof2_ss2_c", 4750 "msiof2_txd_c", 4751 "msiof2_rxd_c", 4752 "msiof2_clk_d", 4753 "msiof2_sync_d", 4754 "msiof2_ss1_d", 4755 "msiof2_ss2_d", 4756 "msiof2_txd_d", 4757 "msiof2_rxd_d", 4758}; 4759 4760static const char * const msiof3_groups[] = { 4761 "msiof3_clk_a", 4762 "msiof3_sync_a", 4763 "msiof3_ss1_a", 4764 "msiof3_ss2_a", 4765 "msiof3_txd_a", 4766 "msiof3_rxd_a", 4767 "msiof3_clk_b", 4768 "msiof3_sync_b", 4769 "msiof3_ss1_b", 4770 "msiof3_ss2_b", 4771 "msiof3_txd_b", 4772 "msiof3_rxd_b", 4773 "msiof3_clk_c", 4774 "msiof3_sync_c", 4775 "msiof3_txd_c", 4776 "msiof3_rxd_c", 4777 "msiof3_clk_d", 4778 "msiof3_sync_d", 4779 "msiof3_ss1_d", 4780 "msiof3_txd_d", 4781 "msiof3_rxd_d", 4782 "msiof3_clk_e", 4783 "msiof3_sync_e", 4784 "msiof3_ss1_e", 4785 "msiof3_ss2_e", 4786 "msiof3_txd_e", 4787 "msiof3_rxd_e", 4788}; 4789 4790static const char * const pwm0_groups[] = { 4791 "pwm0", 4792}; 4793 4794static const char * const pwm1_groups[] = { 4795 "pwm1_a", 4796 "pwm1_b", 4797}; 4798 4799static const char * const pwm2_groups[] = { 4800 "pwm2_a", 4801 "pwm2_b", 4802}; 4803 4804static const char * const pwm3_groups[] = { 4805 "pwm3_a", 4806 "pwm3_b", 4807}; 4808 4809static const char * const pwm4_groups[] = { 4810 "pwm4_a", 4811 "pwm4_b", 4812}; 4813 4814static const char * const pwm5_groups[] = { 4815 "pwm5_a", 4816 "pwm5_b", 4817}; 4818 4819static const char * const pwm6_groups[] = { 4820 "pwm6_a", 4821 "pwm6_b", 4822}; 4823 4824static const char * const scif0_groups[] = { 4825 "scif0_data", 4826 "scif0_clk", 4827 "scif0_ctrl", 4828}; 4829 4830static const char * const scif1_groups[] = { 4831 "scif1_data_a", 4832 "scif1_clk", 4833 "scif1_ctrl", 4834 "scif1_data_b", 4835}; 4836 4837static const char * const scif2_groups[] = { 4838 "scif2_data_a", 4839 "scif2_clk", 4840 "scif2_data_b", 4841}; 4842 4843static const char * const scif3_groups[] = { 4844 "scif3_data_a", 4845 "scif3_clk", 4846 "scif3_ctrl", 4847 "scif3_data_b", 4848}; 4849 4850static const char * const scif4_groups[] = { 4851 "scif4_data_a", 4852 "scif4_clk_a", 4853 "scif4_ctrl_a", 4854 "scif4_data_b", 4855 "scif4_clk_b", 4856 "scif4_ctrl_b", 4857 "scif4_data_c", 4858 "scif4_clk_c", 4859 "scif4_ctrl_c", 4860}; 4861 4862static const char * const scif5_groups[] = { 4863 "scif5_data_a", 4864 "scif5_clk_a", 4865 "scif5_data_b", 4866 "scif5_clk_b", 4867}; 4868 4869static const char * const scif_clk_groups[] = { 4870 "scif_clk_a", 4871 "scif_clk_b", 4872}; 4873 4874static const char * const sdhi0_groups[] = { 4875 "sdhi0_data1", 4876 "sdhi0_data4", 4877 "sdhi0_ctrl", 4878 "sdhi0_cd", 4879 "sdhi0_wp", 4880}; 4881 4882static const char * const sdhi1_groups[] = { 4883 "sdhi1_data1", 4884 "sdhi1_data4", 4885 "sdhi1_ctrl", 4886 "sdhi1_cd", 4887 "sdhi1_wp", 4888}; 4889 4890static const char * const sdhi2_groups[] = { 4891 "sdhi2_data1", 4892 "sdhi2_data4", 4893 "sdhi2_data8", 4894 "sdhi2_ctrl", 4895 "sdhi2_cd_a", 4896 "sdhi2_wp_a", 4897 "sdhi2_cd_b", 4898 "sdhi2_wp_b", 4899 "sdhi2_ds", 4900}; 4901 4902static const char * const sdhi3_groups[] = { 4903 "sdhi3_data1", 4904 "sdhi3_data4", 4905 "sdhi3_data8", 4906 "sdhi3_ctrl", 4907 "sdhi3_cd", 4908 "sdhi3_wp", 4909 "sdhi3_ds", 4910}; 4911 4912static const char * const ssi_groups[] = { 4913 "ssi0_data", 4914 "ssi01239_ctrl", 4915 "ssi1_data_a", 4916 "ssi1_data_b", 4917 "ssi1_ctrl_a", 4918 "ssi1_ctrl_b", 4919 "ssi2_data_a", 4920 "ssi2_data_b", 4921 "ssi2_ctrl_a", 4922 "ssi2_ctrl_b", 4923 "ssi3_data", 4924 "ssi349_ctrl", 4925 "ssi4_data", 4926 "ssi4_ctrl", 4927 "ssi5_data", 4928 "ssi5_ctrl", 4929 "ssi6_data", 4930 "ssi6_ctrl", 4931 "ssi7_data", 4932 "ssi78_ctrl", 4933 "ssi8_data", 4934 "ssi9_data_a", 4935 "ssi9_data_b", 4936 "ssi9_ctrl_a", 4937 "ssi9_ctrl_b", 4938}; 4939 4940static const char * const tmu_groups[] = { 4941 "tmu_tclk1_a", 4942 "tmu_tclk1_b", 4943 "tmu_tclk2_a", 4944 "tmu_tclk2_b", 4945}; 4946 4947static const char * const tpu_groups[] = { 4948 "tpu_to0", 4949 "tpu_to1", 4950 "tpu_to2", 4951 "tpu_to3", 4952}; 4953 4954static const char * const usb0_groups[] = { 4955 "usb0", 4956}; 4957 4958static const char * const usb1_groups[] = { 4959 "usb1", 4960}; 4961 4962static const char * const usb30_groups[] = { 4963 "usb30", 4964}; 4965 4966static const char * const vin4_groups[] = { 4967 "vin4_data8_a", 4968 "vin4_data10_a", 4969 "vin4_data12_a", 4970 "vin4_data16_a", 4971 "vin4_data18_a", 4972 "vin4_data20_a", 4973 "vin4_data24_a", 4974 "vin4_data8_b", 4975 "vin4_data10_b", 4976 "vin4_data12_b", 4977 "vin4_data16_b", 4978 "vin4_data18_b", 4979 "vin4_data20_b", 4980 "vin4_data24_b", 4981 "vin4_sync", 4982 "vin4_field", 4983 "vin4_clkenb", 4984 "vin4_clk", 4985}; 4986 4987static const char * const vin5_groups[] = { 4988 "vin5_data8", 4989 "vin5_data10", 4990 "vin5_data12", 4991 "vin5_data16", 4992 "vin5_sync", 4993 "vin5_field", 4994 "vin5_clkenb", 4995 "vin5_clk", 4996}; 4997 4998static const struct { 4999 struct sh_pfc_function common[50]; 5000 struct sh_pfc_function automotive[4]; 5001} pinmux_functions = { 5002 .common = { 5003 SH_PFC_FUNCTION(audio_clk), 5004 SH_PFC_FUNCTION(avb), 5005 SH_PFC_FUNCTION(can0), 5006 SH_PFC_FUNCTION(can1), 5007 SH_PFC_FUNCTION(can_clk), 5008 SH_PFC_FUNCTION(canfd0), 5009 SH_PFC_FUNCTION(canfd1), 5010 SH_PFC_FUNCTION(du), 5011 SH_PFC_FUNCTION(hscif0), 5012 SH_PFC_FUNCTION(hscif1), 5013 SH_PFC_FUNCTION(hscif2), 5014 SH_PFC_FUNCTION(hscif3), 5015 SH_PFC_FUNCTION(hscif4), 5016 SH_PFC_FUNCTION(i2c0), 5017 SH_PFC_FUNCTION(i2c1), 5018 SH_PFC_FUNCTION(i2c2), 5019 SH_PFC_FUNCTION(i2c3), 5020 SH_PFC_FUNCTION(i2c5), 5021 SH_PFC_FUNCTION(i2c6), 5022 SH_PFC_FUNCTION(intc_ex), 5023 SH_PFC_FUNCTION(msiof0), 5024 SH_PFC_FUNCTION(msiof1), 5025 SH_PFC_FUNCTION(msiof2), 5026 SH_PFC_FUNCTION(msiof3), 5027 SH_PFC_FUNCTION(pwm0), 5028 SH_PFC_FUNCTION(pwm1), 5029 SH_PFC_FUNCTION(pwm2), 5030 SH_PFC_FUNCTION(pwm3), 5031 SH_PFC_FUNCTION(pwm4), 5032 SH_PFC_FUNCTION(pwm5), 5033 SH_PFC_FUNCTION(pwm6), 5034 SH_PFC_FUNCTION(scif0), 5035 SH_PFC_FUNCTION(scif1), 5036 SH_PFC_FUNCTION(scif2), 5037 SH_PFC_FUNCTION(scif3), 5038 SH_PFC_FUNCTION(scif4), 5039 SH_PFC_FUNCTION(scif5), 5040 SH_PFC_FUNCTION(scif_clk), 5041 SH_PFC_FUNCTION(sdhi0), 5042 SH_PFC_FUNCTION(sdhi1), 5043 SH_PFC_FUNCTION(sdhi2), 5044 SH_PFC_FUNCTION(sdhi3), 5045 SH_PFC_FUNCTION(ssi), 5046 SH_PFC_FUNCTION(tmu), 5047 SH_PFC_FUNCTION(tpu), 5048 SH_PFC_FUNCTION(usb0), 5049 SH_PFC_FUNCTION(usb1), 5050 SH_PFC_FUNCTION(usb30), 5051 SH_PFC_FUNCTION(vin4), 5052 SH_PFC_FUNCTION(vin5), 5053 }, 5054 .automotive = { 5055 SH_PFC_FUNCTION(drif0), 5056 SH_PFC_FUNCTION(drif1), 5057 SH_PFC_FUNCTION(drif2), 5058 SH_PFC_FUNCTION(drif3), 5059 } 5060}; 5061 5062static const struct pinmux_cfg_reg pinmux_config_regs[] = { 5063#define F_(x, y) FN_##y 5064#define FM(x) FN_##x 5065 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 5066 0, 0, 5067 0, 0, 5068 0, 0, 5069 0, 0, 5070 0, 0, 5071 0, 0, 5072 0, 0, 5073 0, 0, 5074 0, 0, 5075 0, 0, 5076 0, 0, 5077 0, 0, 5078 0, 0, 5079 0, 0, 5080 0, 0, 5081 0, 0, 5082 GP_0_15_FN, GPSR0_15, 5083 GP_0_14_FN, GPSR0_14, 5084 GP_0_13_FN, GPSR0_13, 5085 GP_0_12_FN, GPSR0_12, 5086 GP_0_11_FN, GPSR0_11, 5087 GP_0_10_FN, GPSR0_10, 5088 GP_0_9_FN, GPSR0_9, 5089 GP_0_8_FN, GPSR0_8, 5090 GP_0_7_FN, GPSR0_7, 5091 GP_0_6_FN, GPSR0_6, 5092 GP_0_5_FN, GPSR0_5, 5093 GP_0_4_FN, GPSR0_4, 5094 GP_0_3_FN, GPSR0_3, 5095 GP_0_2_FN, GPSR0_2, 5096 GP_0_1_FN, GPSR0_1, 5097 GP_0_0_FN, GPSR0_0, )) 5098 }, 5099 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 5100 0, 0, 5101 0, 0, 5102 0, 0, 5103 GP_1_28_FN, GPSR1_28, 5104 GP_1_27_FN, GPSR1_27, 5105 GP_1_26_FN, GPSR1_26, 5106 GP_1_25_FN, GPSR1_25, 5107 GP_1_24_FN, GPSR1_24, 5108 GP_1_23_FN, GPSR1_23, 5109 GP_1_22_FN, GPSR1_22, 5110 GP_1_21_FN, GPSR1_21, 5111 GP_1_20_FN, GPSR1_20, 5112 GP_1_19_FN, GPSR1_19, 5113 GP_1_18_FN, GPSR1_18, 5114 GP_1_17_FN, GPSR1_17, 5115 GP_1_16_FN, GPSR1_16, 5116 GP_1_15_FN, GPSR1_15, 5117 GP_1_14_FN, GPSR1_14, 5118 GP_1_13_FN, GPSR1_13, 5119 GP_1_12_FN, GPSR1_12, 5120 GP_1_11_FN, GPSR1_11, 5121 GP_1_10_FN, GPSR1_10, 5122 GP_1_9_FN, GPSR1_9, 5123 GP_1_8_FN, GPSR1_8, 5124 GP_1_7_FN, GPSR1_7, 5125 GP_1_6_FN, GPSR1_6, 5126 GP_1_5_FN, GPSR1_5, 5127 GP_1_4_FN, GPSR1_4, 5128 GP_1_3_FN, GPSR1_3, 5129 GP_1_2_FN, GPSR1_2, 5130 GP_1_1_FN, GPSR1_1, 5131 GP_1_0_FN, GPSR1_0, )) 5132 }, 5133 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 5134 0, 0, 5135 0, 0, 5136 0, 0, 5137 0, 0, 5138 0, 0, 5139 0, 0, 5140 0, 0, 5141 0, 0, 5142 0, 0, 5143 0, 0, 5144 0, 0, 5145 0, 0, 5146 0, 0, 5147 0, 0, 5148 0, 0, 5149 0, 0, 5150 0, 0, 5151 GP_2_14_FN, GPSR2_14, 5152 GP_2_13_FN, GPSR2_13, 5153 GP_2_12_FN, GPSR2_12, 5154 GP_2_11_FN, GPSR2_11, 5155 GP_2_10_FN, GPSR2_10, 5156 GP_2_9_FN, GPSR2_9, 5157 GP_2_8_FN, GPSR2_8, 5158 GP_2_7_FN, GPSR2_7, 5159 GP_2_6_FN, GPSR2_6, 5160 GP_2_5_FN, GPSR2_5, 5161 GP_2_4_FN, GPSR2_4, 5162 GP_2_3_FN, GPSR2_3, 5163 GP_2_2_FN, GPSR2_2, 5164 GP_2_1_FN, GPSR2_1, 5165 GP_2_0_FN, GPSR2_0, )) 5166 }, 5167 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 5168 0, 0, 5169 0, 0, 5170 0, 0, 5171 0, 0, 5172 0, 0, 5173 0, 0, 5174 0, 0, 5175 0, 0, 5176 0, 0, 5177 0, 0, 5178 0, 0, 5179 0, 0, 5180 0, 0, 5181 0, 0, 5182 0, 0, 5183 0, 0, 5184 GP_3_15_FN, GPSR3_15, 5185 GP_3_14_FN, GPSR3_14, 5186 GP_3_13_FN, GPSR3_13, 5187 GP_3_12_FN, GPSR3_12, 5188 GP_3_11_FN, GPSR3_11, 5189 GP_3_10_FN, GPSR3_10, 5190 GP_3_9_FN, GPSR3_9, 5191 GP_3_8_FN, GPSR3_8, 5192 GP_3_7_FN, GPSR3_7, 5193 GP_3_6_FN, GPSR3_6, 5194 GP_3_5_FN, GPSR3_5, 5195 GP_3_4_FN, GPSR3_4, 5196 GP_3_3_FN, GPSR3_3, 5197 GP_3_2_FN, GPSR3_2, 5198 GP_3_1_FN, GPSR3_1, 5199 GP_3_0_FN, GPSR3_0, )) 5200 }, 5201 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 5202 0, 0, 5203 0, 0, 5204 0, 0, 5205 0, 0, 5206 0, 0, 5207 0, 0, 5208 0, 0, 5209 0, 0, 5210 0, 0, 5211 0, 0, 5212 0, 0, 5213 0, 0, 5214 0, 0, 5215 0, 0, 5216 GP_4_17_FN, GPSR4_17, 5217 GP_4_16_FN, GPSR4_16, 5218 GP_4_15_FN, GPSR4_15, 5219 GP_4_14_FN, GPSR4_14, 5220 GP_4_13_FN, GPSR4_13, 5221 GP_4_12_FN, GPSR4_12, 5222 GP_4_11_FN, GPSR4_11, 5223 GP_4_10_FN, GPSR4_10, 5224 GP_4_9_FN, GPSR4_9, 5225 GP_4_8_FN, GPSR4_8, 5226 GP_4_7_FN, GPSR4_7, 5227 GP_4_6_FN, GPSR4_6, 5228 GP_4_5_FN, GPSR4_5, 5229 GP_4_4_FN, GPSR4_4, 5230 GP_4_3_FN, GPSR4_3, 5231 GP_4_2_FN, GPSR4_2, 5232 GP_4_1_FN, GPSR4_1, 5233 GP_4_0_FN, GPSR4_0, )) 5234 }, 5235 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 5236 0, 0, 5237 0, 0, 5238 0, 0, 5239 0, 0, 5240 0, 0, 5241 0, 0, 5242 GP_5_25_FN, GPSR5_25, 5243 GP_5_24_FN, GPSR5_24, 5244 GP_5_23_FN, GPSR5_23, 5245 GP_5_22_FN, GPSR5_22, 5246 GP_5_21_FN, GPSR5_21, 5247 GP_5_20_FN, GPSR5_20, 5248 GP_5_19_FN, GPSR5_19, 5249 GP_5_18_FN, GPSR5_18, 5250 GP_5_17_FN, GPSR5_17, 5251 GP_5_16_FN, GPSR5_16, 5252 GP_5_15_FN, GPSR5_15, 5253 GP_5_14_FN, GPSR5_14, 5254 GP_5_13_FN, GPSR5_13, 5255 GP_5_12_FN, GPSR5_12, 5256 GP_5_11_FN, GPSR5_11, 5257 GP_5_10_FN, GPSR5_10, 5258 GP_5_9_FN, GPSR5_9, 5259 GP_5_8_FN, GPSR5_8, 5260 GP_5_7_FN, GPSR5_7, 5261 GP_5_6_FN, GPSR5_6, 5262 GP_5_5_FN, GPSR5_5, 5263 GP_5_4_FN, GPSR5_4, 5264 GP_5_3_FN, GPSR5_3, 5265 GP_5_2_FN, GPSR5_2, 5266 GP_5_1_FN, GPSR5_1, 5267 GP_5_0_FN, GPSR5_0, )) 5268 }, 5269 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( 5270 GP_6_31_FN, GPSR6_31, 5271 GP_6_30_FN, GPSR6_30, 5272 GP_6_29_FN, GPSR6_29, 5273 GP_6_28_FN, GPSR6_28, 5274 GP_6_27_FN, GPSR6_27, 5275 GP_6_26_FN, GPSR6_26, 5276 GP_6_25_FN, GPSR6_25, 5277 GP_6_24_FN, GPSR6_24, 5278 GP_6_23_FN, GPSR6_23, 5279 GP_6_22_FN, GPSR6_22, 5280 GP_6_21_FN, GPSR6_21, 5281 GP_6_20_FN, GPSR6_20, 5282 GP_6_19_FN, GPSR6_19, 5283 GP_6_18_FN, GPSR6_18, 5284 GP_6_17_FN, GPSR6_17, 5285 GP_6_16_FN, GPSR6_16, 5286 GP_6_15_FN, GPSR6_15, 5287 GP_6_14_FN, GPSR6_14, 5288 GP_6_13_FN, GPSR6_13, 5289 GP_6_12_FN, GPSR6_12, 5290 GP_6_11_FN, GPSR6_11, 5291 GP_6_10_FN, GPSR6_10, 5292 GP_6_9_FN, GPSR6_9, 5293 GP_6_8_FN, GPSR6_8, 5294 GP_6_7_FN, GPSR6_7, 5295 GP_6_6_FN, GPSR6_6, 5296 GP_6_5_FN, GPSR6_5, 5297 GP_6_4_FN, GPSR6_4, 5298 GP_6_3_FN, GPSR6_3, 5299 GP_6_2_FN, GPSR6_2, 5300 GP_6_1_FN, GPSR6_1, 5301 GP_6_0_FN, GPSR6_0, )) 5302 }, 5303 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP( 5304 0, 0, 5305 0, 0, 5306 0, 0, 5307 0, 0, 5308 0, 0, 5309 0, 0, 5310 0, 0, 5311 0, 0, 5312 0, 0, 5313 0, 0, 5314 0, 0, 5315 0, 0, 5316 0, 0, 5317 0, 0, 5318 0, 0, 5319 0, 0, 5320 0, 0, 5321 0, 0, 5322 0, 0, 5323 0, 0, 5324 0, 0, 5325 0, 0, 5326 0, 0, 5327 0, 0, 5328 0, 0, 5329 0, 0, 5330 0, 0, 5331 0, 0, 5332 GP_7_3_FN, GPSR7_3, 5333 GP_7_2_FN, GPSR7_2, 5334 GP_7_1_FN, GPSR7_1, 5335 GP_7_0_FN, GPSR7_0, )) 5336 }, 5337#undef F_ 5338#undef FM 5339 5340#define F_(x, y) x, 5341#define FM(x) FN_##x, 5342 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( 5343 IP0_31_28 5344 IP0_27_24 5345 IP0_23_20 5346 IP0_19_16 5347 IP0_15_12 5348 IP0_11_8 5349 IP0_7_4 5350 IP0_3_0 )) 5351 }, 5352 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( 5353 IP1_31_28 5354 IP1_27_24 5355 IP1_23_20 5356 IP1_19_16 5357 IP1_15_12 5358 IP1_11_8 5359 IP1_7_4 5360 IP1_3_0 )) 5361 }, 5362 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( 5363 IP2_31_28 5364 IP2_27_24 5365 IP2_23_20 5366 IP2_19_16 5367 IP2_15_12 5368 IP2_11_8 5369 IP2_7_4 5370 IP2_3_0 )) 5371 }, 5372 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( 5373 IP3_31_28 5374 IP3_27_24 5375 IP3_23_20 5376 IP3_19_16 5377 IP3_15_12 5378 IP3_11_8 5379 IP3_7_4 5380 IP3_3_0 )) 5381 }, 5382 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( 5383 IP4_31_28 5384 IP4_27_24 5385 IP4_23_20 5386 IP4_19_16 5387 IP4_15_12 5388 IP4_11_8 5389 IP4_7_4 5390 IP4_3_0 )) 5391 }, 5392 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( 5393 IP5_31_28 5394 IP5_27_24 5395 IP5_23_20 5396 IP5_19_16 5397 IP5_15_12 5398 IP5_11_8 5399 IP5_7_4 5400 IP5_3_0 )) 5401 }, 5402 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( 5403 IP6_31_28 5404 IP6_27_24 5405 IP6_23_20 5406 IP6_19_16 5407 IP6_15_12 5408 IP6_11_8 5409 IP6_7_4 5410 IP6_3_0 )) 5411 }, 5412 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( 5413 IP7_31_28 5414 IP7_27_24 5415 IP7_23_20 5416 IP7_19_16 5417 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5418 IP7_11_8 5419 IP7_7_4 5420 IP7_3_0 )) 5421 }, 5422 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( 5423 IP8_31_28 5424 IP8_27_24 5425 IP8_23_20 5426 IP8_19_16 5427 IP8_15_12 5428 IP8_11_8 5429 IP8_7_4 5430 IP8_3_0 )) 5431 }, 5432 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( 5433 IP9_31_28 5434 IP9_27_24 5435 IP9_23_20 5436 IP9_19_16 5437 IP9_15_12 5438 IP9_11_8 5439 IP9_7_4 5440 IP9_3_0 )) 5441 }, 5442 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( 5443 IP10_31_28 5444 IP10_27_24 5445 IP10_23_20 5446 IP10_19_16 5447 IP10_15_12 5448 IP10_11_8 5449 IP10_7_4 5450 IP10_3_0 )) 5451 }, 5452 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( 5453 IP11_31_28 5454 IP11_27_24 5455 IP11_23_20 5456 IP11_19_16 5457 IP11_15_12 5458 IP11_11_8 5459 IP11_7_4 5460 IP11_3_0 )) 5461 }, 5462 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( 5463 IP12_31_28 5464 IP12_27_24 5465 IP12_23_20 5466 IP12_19_16 5467 IP12_15_12 5468 IP12_11_8 5469 IP12_7_4 5470 IP12_3_0 )) 5471 }, 5472 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( 5473 IP13_31_28 5474 IP13_27_24 5475 IP13_23_20 5476 IP13_19_16 5477 IP13_15_12 5478 IP13_11_8 5479 IP13_7_4 5480 IP13_3_0 )) 5481 }, 5482 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( 5483 IP14_31_28 5484 IP14_27_24 5485 IP14_23_20 5486 IP14_19_16 5487 IP14_15_12 5488 IP14_11_8 5489 IP14_7_4 5490 IP14_3_0 )) 5491 }, 5492 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( 5493 IP15_31_28 5494 IP15_27_24 5495 IP15_23_20 5496 IP15_19_16 5497 IP15_15_12 5498 IP15_11_8 5499 IP15_7_4 5500 IP15_3_0 )) 5501 }, 5502 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP( 5503 IP16_31_28 5504 IP16_27_24 5505 IP16_23_20 5506 IP16_19_16 5507 IP16_15_12 5508 IP16_11_8 5509 IP16_7_4 5510 IP16_3_0 )) 5511 }, 5512 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP( 5513 IP17_31_28 5514 IP17_27_24 5515 IP17_23_20 5516 IP17_19_16 5517 IP17_15_12 5518 IP17_11_8 5519 IP17_7_4 5520 IP17_3_0 )) 5521 }, 5522 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP( 5523 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5524 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5525 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5526 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5527 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5528 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5529 IP18_7_4 5530 IP18_3_0 )) 5531 }, 5532#undef F_ 5533#undef FM 5534 5535#define F_(x, y) x, 5536#define FM(x) FN_##x, 5537 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 5538 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2, 5539 1, 1, 1, 2, 2, 1, 2, 3), 5540 GROUP( 5541 MOD_SEL0_31_30_29 5542 MOD_SEL0_28_27 5543 MOD_SEL0_26_25_24 5544 MOD_SEL0_23 5545 MOD_SEL0_22 5546 MOD_SEL0_21 5547 MOD_SEL0_20 5548 MOD_SEL0_19 5549 MOD_SEL0_18_17 5550 MOD_SEL0_16 5551 0, 0, /* RESERVED 15 */ 5552 MOD_SEL0_14_13 5553 MOD_SEL0_12 5554 MOD_SEL0_11 5555 MOD_SEL0_10 5556 MOD_SEL0_9_8 5557 MOD_SEL0_7_6 5558 MOD_SEL0_5 5559 MOD_SEL0_4_3 5560 /* RESERVED 2, 1, 0 */ 5561 0, 0, 0, 0, 0, 0, 0, 0 )) 5562 }, 5563 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, 5564 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1, 5565 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1), 5566 GROUP( 5567 MOD_SEL1_31_30 5568 MOD_SEL1_29_28_27 5569 MOD_SEL1_26 5570 MOD_SEL1_25_24 5571 MOD_SEL1_23_22_21 5572 MOD_SEL1_20 5573 MOD_SEL1_19 5574 MOD_SEL1_18_17 5575 MOD_SEL1_16 5576 MOD_SEL1_15_14 5577 MOD_SEL1_13 5578 MOD_SEL1_12 5579 MOD_SEL1_11 5580 MOD_SEL1_10 5581 MOD_SEL1_9 5582 0, 0, 0, 0, /* RESERVED 8, 7 */ 5583 MOD_SEL1_6 5584 MOD_SEL1_5 5585 MOD_SEL1_4 5586 MOD_SEL1_3 5587 MOD_SEL1_2 5588 MOD_SEL1_1 5589 MOD_SEL1_0 )) 5590 }, 5591 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, 5592 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 5593 1, 4, 4, 4, 3, 1), 5594 GROUP( 5595 MOD_SEL2_31 5596 MOD_SEL2_30 5597 MOD_SEL2_29 5598 MOD_SEL2_28_27 5599 MOD_SEL2_26 5600 MOD_SEL2_25_24_23 5601 MOD_SEL2_22 5602 MOD_SEL2_21 5603 MOD_SEL2_20 5604 MOD_SEL2_19 5605 MOD_SEL2_18 5606 MOD_SEL2_17 5607 /* RESERVED 16 */ 5608 0, 0, 5609 /* RESERVED 15, 14, 13, 12 */ 5610 0, 0, 0, 0, 0, 0, 0, 0, 5611 0, 0, 0, 0, 0, 0, 0, 0, 5612 /* RESERVED 11, 10, 9, 8 */ 5613 0, 0, 0, 0, 0, 0, 0, 0, 5614 0, 0, 0, 0, 0, 0, 0, 0, 5615 /* RESERVED 7, 6, 5, 4 */ 5616 0, 0, 0, 0, 0, 0, 0, 0, 5617 0, 0, 0, 0, 0, 0, 0, 0, 5618 /* RESERVED 3, 2, 1 */ 5619 0, 0, 0, 0, 0, 0, 0, 0, 5620 MOD_SEL2_0 )) 5621 }, 5622 { }, 5623}; 5624 5625static const struct pinmux_drive_reg pinmux_drive_regs[] = { 5626 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { 5627 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */ 5628 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */ 5629 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */ 5630 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */ 5631 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */ 5632 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */ 5633 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */ 5634 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ 5635 } }, 5636 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { 5637 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */ 5638 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */ 5639 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */ 5640 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */ 5641 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */ 5642 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */ 5643 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */ 5644 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ 5645 } }, 5646 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { 5647 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */ 5648 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */ 5649 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */ 5650 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */ 5651 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */ 5652 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */ 5653 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */ 5654 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ 5655 } }, 5656 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { 5657 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */ 5658 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */ 5659 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */ 5660 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */ 5661 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */ 5662 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ 5663 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ 5664 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ 5665 } }, 5666 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { 5667 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ 5668 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */ 5669 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */ 5670 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */ 5671 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */ 5672 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */ 5673 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */ 5674 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */ 5675 } }, 5676 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) { 5677 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */ 5678 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */ 5679 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */ 5680 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */ 5681 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */ 5682 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */ 5683 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */ 5684 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */ 5685 } }, 5686 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) { 5687 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */ 5688 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */ 5689 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */ 5690 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */ 5691 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */ 5692 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */ 5693 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */ 5694 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */ 5695 } }, 5696 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) { 5697 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */ 5698 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */ 5699 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */ 5700 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */ 5701 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */ 5702 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */ 5703 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */ 5704 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ 5705 } }, 5706 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { 5707 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */ 5708 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ 5709 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ 5710 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ 5711 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */ 5712 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */ 5713 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */ 5714 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */ 5715 } }, 5716 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { 5717 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ 5718 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ 5719 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ 5720 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ 5721 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ 5722 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */ 5723 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */ 5724 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */ 5725 } }, 5726 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) { 5727 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */ 5728 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */ 5729 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */ 5730 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */ 5731 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */ 5732 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */ 5733 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */ 5734 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ 5735 } }, 5736 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { 5737 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ 5738 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ 5739 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ 5740 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ 5741 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ 5742 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ 5743 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */ 5744 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ 5745 } }, 5746 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { 5747 { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */ 5748 { PIN_FSCLKST, 20, 2 }, /* FSCLKST */ 5749 { PIN_TMS, 4, 2 }, /* TMS */ 5750 } }, 5751 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { 5752 { PIN_TDO, 28, 2 }, /* TDO */ 5753 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */ 5754 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ 5755 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ 5756 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ 5757 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ 5758 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ 5759 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ 5760 } }, 5761 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { 5762 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ 5763 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */ 5764 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */ 5765 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */ 5766 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */ 5767 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */ 5768 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */ 5769 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */ 5770 } }, 5771 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) { 5772 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */ 5773 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */ 5774 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */ 5775 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */ 5776 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */ 5777 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */ 5778 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */ 5779 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */ 5780 } }, 5781 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) { 5782 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */ 5783 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */ 5784 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */ 5785 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */ 5786 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */ 5787 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */ 5788 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */ 5789 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */ 5790 } }, 5791 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) { 5792 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */ 5793 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */ 5794 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */ 5795 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */ 5796 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */ 5797 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */ 5798 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */ 5799 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ 5800 } }, 5801 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { 5802 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */ 5803 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ 5804 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ 5805 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ 5806 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */ 5807 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ 5808 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ 5809 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ 5810 } }, 5811 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) { 5812 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */ 5813 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */ 5814 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */ 5815 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */ 5816 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */ 5817 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */ 5818 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */ 5819 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */ 5820 } }, 5821 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) { 5822 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */ 5823 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */ 5824 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */ 5825 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ 5826 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ 5827 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ 5828 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */ 5829 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ 5830 } }, 5831 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { 5832 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */ 5833 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */ 5834 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */ 5835 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */ 5836 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */ 5837 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */ 5838 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */ 5839 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */ 5840 } }, 5841 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) { 5842 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */ 5843 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */ 5844 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */ 5845 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */ 5846 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */ 5847 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */ 5848 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */ 5849 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */ 5850 } }, 5851 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) { 5852 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */ 5853 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */ 5854 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */ 5855 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */ 5856 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */ 5857 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */ 5858 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */ 5859 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */ 5860 } }, 5861 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) { 5862 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */ 5863 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */ 5864 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ 5865 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ 5866 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ 5867 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */ 5868 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */ 5869 } }, 5870 { }, 5871}; 5872 5873enum ioctrl_regs { 5874 POCCTRL, 5875 TDSELCTRL, 5876}; 5877 5878static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 5879 [POCCTRL] = { 0xe6060380, }, 5880 [TDSELCTRL] = { 0xe60603c0, }, 5881 { /* sentinel */ }, 5882}; 5883 5884static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) 5885{ 5886 int bit = -EINVAL; 5887 5888 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg; 5889 5890 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) 5891 bit = pin & 0x1f; 5892 5893 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17)) 5894 bit = (pin & 0x1f) + 12; 5895 5896 return bit; 5897} 5898 5899static const struct pinmux_bias_reg pinmux_bias_regs[] = { 5900 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { 5901 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */ 5902 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */ 5903 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */ 5904 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */ 5905 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */ 5906 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */ 5907 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */ 5908 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */ 5909 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */ 5910 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */ 5911 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */ 5912 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */ 5913 [12] = PIN_RPC_INT_N, /* RPC_INT# */ 5914 [13] = PIN_RPC_WP_N, /* RPC_WP# */ 5915 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */ 5916 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */ 5917 [16] = PIN_AVB_RXC, /* AVB_RXC */ 5918 [17] = PIN_AVB_RD0, /* AVB_RD0 */ 5919 [18] = PIN_AVB_RD1, /* AVB_RD1 */ 5920 [19] = PIN_AVB_RD2, /* AVB_RD2 */ 5921 [20] = PIN_AVB_RD3, /* AVB_RD3 */ 5922 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ 5923 [22] = PIN_AVB_TXC, /* AVB_TXC */ 5924 [23] = PIN_AVB_TD0, /* AVB_TD0 */ 5925 [24] = PIN_AVB_TD1, /* AVB_TD1 */ 5926 [25] = PIN_AVB_TD2, /* AVB_TD2 */ 5927 [26] = PIN_AVB_TD3, /* AVB_TD3 */ 5928 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */ 5929 [28] = PIN_AVB_MDIO, /* AVB_MDIO */ 5930 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ 5931 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ 5932 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ 5933 } }, 5934 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { 5935 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */ 5936 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */ 5937 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */ 5938 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */ 5939 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */ 5940 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */ 5941 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */ 5942 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */ 5943 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */ 5944 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */ 5945 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */ 5946 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */ 5947 [12] = RCAR_GP_PIN(1, 0), /* A0 */ 5948 [13] = RCAR_GP_PIN(1, 1), /* A1 */ 5949 [14] = RCAR_GP_PIN(1, 2), /* A2 */ 5950 [15] = RCAR_GP_PIN(1, 3), /* A3 */ 5951 [16] = RCAR_GP_PIN(1, 4), /* A4 */ 5952 [17] = RCAR_GP_PIN(1, 5), /* A5 */ 5953 [18] = RCAR_GP_PIN(1, 6), /* A6 */ 5954 [19] = RCAR_GP_PIN(1, 7), /* A7 */ 5955 [20] = RCAR_GP_PIN(1, 8), /* A8 */ 5956 [21] = RCAR_GP_PIN(1, 9), /* A9 */ 5957 [22] = RCAR_GP_PIN(1, 10), /* A10 */ 5958 [23] = RCAR_GP_PIN(1, 11), /* A11 */ 5959 [24] = RCAR_GP_PIN(1, 12), /* A12 */ 5960 [25] = RCAR_GP_PIN(1, 13), /* A13 */ 5961 [26] = RCAR_GP_PIN(1, 14), /* A14 */ 5962 [27] = RCAR_GP_PIN(1, 15), /* A15 */ 5963 [28] = RCAR_GP_PIN(1, 16), /* A16 */ 5964 [29] = RCAR_GP_PIN(1, 17), /* A17 */ 5965 [30] = RCAR_GP_PIN(1, 18), /* A18 */ 5966 [31] = RCAR_GP_PIN(1, 19), /* A19 */ 5967 } }, 5968 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { 5969 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */ 5970 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */ 5971 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */ 5972 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */ 5973 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */ 5974 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */ 5975 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ 5976 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ 5977 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ 5978 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */ 5979 [10] = RCAR_GP_PIN(0, 0), /* D0 */ 5980 [11] = RCAR_GP_PIN(0, 1), /* D1 */ 5981 [12] = RCAR_GP_PIN(0, 2), /* D2 */ 5982 [13] = RCAR_GP_PIN(0, 3), /* D3 */ 5983 [14] = RCAR_GP_PIN(0, 4), /* D4 */ 5984 [15] = RCAR_GP_PIN(0, 5), /* D5 */ 5985 [16] = RCAR_GP_PIN(0, 6), /* D6 */ 5986 [17] = RCAR_GP_PIN(0, 7), /* D7 */ 5987 [18] = RCAR_GP_PIN(0, 8), /* D8 */ 5988 [19] = RCAR_GP_PIN(0, 9), /* D9 */ 5989 [20] = RCAR_GP_PIN(0, 10), /* D10 */ 5990 [21] = RCAR_GP_PIN(0, 11), /* D11 */ 5991 [22] = RCAR_GP_PIN(0, 12), /* D12 */ 5992 [23] = RCAR_GP_PIN(0, 13), /* D13 */ 5993 [24] = RCAR_GP_PIN(0, 14), /* D14 */ 5994 [25] = RCAR_GP_PIN(0, 15), /* D15 */ 5995 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ 5996 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ 5997 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ 5998 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ 5999 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ 6000 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ 6001 } }, 6002 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { 6003 [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */ 6004 [ 1] = SH_PFC_PIN_NONE, 6005 [ 2] = PIN_FSCLKST, /* FSCLKST */ 6006 [ 3] = PIN_EXTALR, /* EXTALR*/ 6007 [ 4] = PIN_TRST_N, /* TRST# */ 6008 [ 5] = PIN_TCK, /* TCK */ 6009 [ 6] = PIN_TMS, /* TMS */ 6010 [ 7] = PIN_TDI, /* TDI */ 6011 [ 8] = SH_PFC_PIN_NONE, 6012 [ 9] = PIN_ASEBRK, /* ASEBRK */ 6013 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ 6014 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ 6015 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ 6016 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ 6017 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ 6018 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ 6019 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ 6020 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ 6021 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ 6022 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ 6023 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ 6024 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ 6025 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */ 6026 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */ 6027 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */ 6028 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */ 6029 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */ 6030 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */ 6031 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */ 6032 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */ 6033 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */ 6034 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */ 6035 } }, 6036 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { 6037 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */ 6038 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */ 6039 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */ 6040 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */ 6041 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */ 6042 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */ 6043 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */ 6044 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */ 6045 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */ 6046 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ 6047 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */ 6048 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */ 6049 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */ 6050 [13] = RCAR_GP_PIN(5, 1), /* RX0 */ 6051 [14] = RCAR_GP_PIN(5, 2), /* TX0 */ 6052 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ 6053 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */ 6054 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ 6055 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ 6056 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ 6057 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */ 6058 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ 6059 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ 6060 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ 6061 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */ 6062 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */ 6063 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */ 6064 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */ 6065 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */ 6066 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */ 6067 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */ 6068 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */ 6069 } }, 6070 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { 6071 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */ 6072 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */ 6073 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */ 6074 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ 6075 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ 6076 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ 6077 [ 6] = PIN_MLB_REF, /* MLB_REF */ 6078 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ 6079 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ 6080 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ 6081 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */ 6082 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */ 6083 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ 6084 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ 6085 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ 6086 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */ 6087 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */ 6088 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ 6089 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ 6090 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ 6091 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ 6092 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ 6093 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ 6094 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ 6095 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */ 6096 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */ 6097 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */ 6098 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */ 6099 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */ 6100 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */ 6101 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */ 6102 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */ 6103 } }, 6104 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) { 6105 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */ 6106 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */ 6107 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */ 6108 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */ 6109 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ 6110 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */ 6111 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */ 6112 [ 7] = PIN_PRESET_N, /* PRESET# */ 6113 [ 8] = SH_PFC_PIN_NONE, 6114 [ 9] = SH_PFC_PIN_NONE, 6115 [10] = SH_PFC_PIN_NONE, 6116 [11] = SH_PFC_PIN_NONE, 6117 [12] = SH_PFC_PIN_NONE, 6118 [13] = SH_PFC_PIN_NONE, 6119 [14] = SH_PFC_PIN_NONE, 6120 [15] = SH_PFC_PIN_NONE, 6121 [16] = SH_PFC_PIN_NONE, 6122 [17] = SH_PFC_PIN_NONE, 6123 [18] = SH_PFC_PIN_NONE, 6124 [19] = SH_PFC_PIN_NONE, 6125 [20] = SH_PFC_PIN_NONE, 6126 [21] = SH_PFC_PIN_NONE, 6127 [22] = SH_PFC_PIN_NONE, 6128 [23] = SH_PFC_PIN_NONE, 6129 [24] = SH_PFC_PIN_NONE, 6130 [25] = SH_PFC_PIN_NONE, 6131 [26] = SH_PFC_PIN_NONE, 6132 [27] = SH_PFC_PIN_NONE, 6133 [28] = SH_PFC_PIN_NONE, 6134 [29] = SH_PFC_PIN_NONE, 6135 [30] = SH_PFC_PIN_NONE, 6136 [31] = SH_PFC_PIN_NONE, 6137 } }, 6138 { /* sentinel */ }, 6139}; 6140 6141static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc, 6142 unsigned int pin) 6143{ 6144 const struct pinmux_bias_reg *reg; 6145 unsigned int bit; 6146 6147 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); 6148 if (!reg) 6149 return PIN_CONFIG_BIAS_DISABLE; 6150 6151 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) 6152 return PIN_CONFIG_BIAS_DISABLE; 6153 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) 6154 return PIN_CONFIG_BIAS_PULL_UP; 6155 else 6156 return PIN_CONFIG_BIAS_PULL_DOWN; 6157} 6158 6159static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 6160 unsigned int bias) 6161{ 6162 const struct pinmux_bias_reg *reg; 6163 u32 enable, updown; 6164 unsigned int bit; 6165 6166 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); 6167 if (!reg) 6168 return; 6169 6170 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); 6171 if (bias != PIN_CONFIG_BIAS_DISABLE) 6172 enable |= BIT(bit); 6173 6174 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); 6175 if (bias == PIN_CONFIG_BIAS_PULL_UP) 6176 updown |= BIT(bit); 6177 6178 sh_pfc_write(pfc, reg->pud, updown); 6179 sh_pfc_write(pfc, reg->puen, enable); 6180} 6181 6182static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = { 6183 .pin_to_pocctrl = r8a7796_pin_to_pocctrl, 6184 .get_bias = r8a7796_pinmux_get_bias, 6185 .set_bias = r8a7796_pinmux_set_bias, 6186}; 6187 6188#ifdef CONFIG_PINCTRL_PFC_R8A774A1 6189const struct sh_pfc_soc_info r8a774a1_pinmux_info = { 6190 .name = "r8a774a1_pfc", 6191 .ops = &r8a7796_pinmux_ops, 6192 .unlock_reg = 0xe6060000, /* PMMR */ 6193 6194 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6195 6196 .pins = pinmux_pins, 6197 .nr_pins = ARRAY_SIZE(pinmux_pins), 6198 .groups = pinmux_groups.common, 6199 .nr_groups = ARRAY_SIZE(pinmux_groups.common), 6200 .functions = pinmux_functions.common, 6201 .nr_functions = ARRAY_SIZE(pinmux_functions.common), 6202 6203 .cfg_regs = pinmux_config_regs, 6204 .drive_regs = pinmux_drive_regs, 6205 .bias_regs = pinmux_bias_regs, 6206 .ioctrl_regs = pinmux_ioctrl_regs, 6207 6208 .pinmux_data = pinmux_data, 6209 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6210}; 6211#endif 6212 6213#ifdef CONFIG_PINCTRL_PFC_R8A77960 6214const struct sh_pfc_soc_info r8a77960_pinmux_info = { 6215 .name = "r8a77960_pfc", 6216 .ops = &r8a7796_pinmux_ops, 6217 .unlock_reg = 0xe6060000, /* PMMR */ 6218 6219 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6220 6221 .pins = pinmux_pins, 6222 .nr_pins = ARRAY_SIZE(pinmux_pins), 6223 .groups = pinmux_groups.common, 6224 .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 6225 ARRAY_SIZE(pinmux_groups.automotive), 6226 .functions = pinmux_functions.common, 6227 .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 6228 ARRAY_SIZE(pinmux_functions.automotive), 6229 6230 .cfg_regs = pinmux_config_regs, 6231 .drive_regs = pinmux_drive_regs, 6232 .bias_regs = pinmux_bias_regs, 6233 .ioctrl_regs = pinmux_ioctrl_regs, 6234 6235 .pinmux_data = pinmux_data, 6236 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6237}; 6238#endif 6239 6240#ifdef CONFIG_PINCTRL_PFC_R8A77961 6241const struct sh_pfc_soc_info r8a77961_pinmux_info = { 6242 .name = "r8a77961_pfc", 6243 .ops = &r8a7796_pinmux_ops, 6244 .unlock_reg = 0xe6060000, /* PMMR */ 6245 6246 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6247 6248 .pins = pinmux_pins, 6249 .nr_pins = ARRAY_SIZE(pinmux_pins), 6250 .groups = pinmux_groups.common, 6251 .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 6252 ARRAY_SIZE(pinmux_groups.automotive), 6253 .functions = pinmux_functions.common, 6254 .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 6255 ARRAY_SIZE(pinmux_functions.automotive), 6256 6257 .cfg_regs = pinmux_config_regs, 6258 .drive_regs = pinmux_drive_regs, 6259 .bias_regs = pinmux_bias_regs, 6260 .ioctrl_regs = pinmux_ioctrl_regs, 6261 6262 .pinmux_data = pinmux_data, 6263 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6264}; 6265#endif 6266