1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Pinctrl driver for Rockchip SoCs 4 * 5 * Copyright (c) 2013 MundoReader S.L. 6 * Author: Heiko Stuebner <heiko@sntech.de> 7 * 8 * With some ideas taken from pinctrl-samsung: 9 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 10 * http://www.samsung.com 11 * Copyright (c) 2012 Linaro Ltd 12 * https://www.linaro.org 13 * 14 * and pinctrl-at91: 15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 16 */ 17 18#include <linux/init.h> 19#include <linux/platform_device.h> 20#include <linux/io.h> 21#include <linux/bitops.h> 22#include <linux/gpio/driver.h> 23#include <linux/of_address.h> 24#include <linux/of_irq.h> 25#include <linux/pinctrl/machine.h> 26#include <linux/pinctrl/pinconf.h> 27#include <linux/pinctrl/pinctrl.h> 28#include <linux/pinctrl/pinmux.h> 29#include <linux/pinctrl/pinconf-generic.h> 30#include <linux/irqchip/chained_irq.h> 31#include <linux/clk.h> 32#include <linux/regmap.h> 33#include <linux/mfd/syscon.h> 34#include <dt-bindings/pinctrl/rockchip.h> 35 36#include "core.h" 37#include "pinconf.h" 38 39/* GPIO control registers */ 40#define GPIO_SWPORT_DR 0x00 41#define GPIO_SWPORT_DDR 0x04 42#define GPIO_INTEN 0x30 43#define GPIO_INTMASK 0x34 44#define GPIO_INTTYPE_LEVEL 0x38 45#define GPIO_INT_POLARITY 0x3c 46#define GPIO_INT_STATUS 0x40 47#define GPIO_INT_RAWSTATUS 0x44 48#define GPIO_DEBOUNCE 0x48 49#define GPIO_PORTS_EOI 0x4c 50#define GPIO_EXT_PORT 0x50 51#define GPIO_LS_SYNC 0x60 52 53enum rockchip_pinctrl_type { 54 PX30, 55 RV1108, 56 RK2928, 57 RK3066B, 58 RK3128, 59 RK3188, 60 RK3288, 61 RK3308, 62 RK3368, 63 RK3399, 64 RK3568, 65}; 66 67 68/** 69 * Generate a bitmask for setting a value (v) with a write mask bit in hiword 70 * register 31:16 area. 71 */ 72#define WRITE_MASK_VAL(h, l, v) \ 73 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l)))) 74 75/* 76 * Encode variants of iomux registers into a type variable 77 */ 78#define IOMUX_GPIO_ONLY BIT(0) 79#define IOMUX_WIDTH_4BIT BIT(1) 80#define IOMUX_SOURCE_PMU BIT(2) 81#define IOMUX_UNROUTED BIT(3) 82#define IOMUX_WIDTH_3BIT BIT(4) 83#define IOMUX_WIDTH_2BIT BIT(5) 84 85/** 86 * struct rockchip_iomux 87 * @type: iomux variant using IOMUX_* constants 88 * @offset: if initialized to -1 it will be autocalculated, by specifying 89 * an initial offset value the relevant source offset can be reset 90 * to a new value for autocalculating the following iomux registers. 91 */ 92struct rockchip_iomux { 93 int type; 94 int offset; 95}; 96 97/* 98 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 99 */ 100enum rockchip_pin_drv_type { 101 DRV_TYPE_IO_DEFAULT = 0, 102 DRV_TYPE_IO_1V8_OR_3V0, 103 DRV_TYPE_IO_1V8_ONLY, 104 DRV_TYPE_IO_1V8_3V0_AUTO, 105 DRV_TYPE_IO_3V3_ONLY, 106 DRV_TYPE_MAX 107}; 108 109/* 110 * enum type index corresponding to rockchip_pull_list arrays index. 111 */ 112enum rockchip_pin_pull_type { 113 PULL_TYPE_IO_DEFAULT = 0, 114 PULL_TYPE_IO_1V8_ONLY, 115 PULL_TYPE_MAX 116}; 117 118/** 119 * struct rockchip_drv 120 * @drv_type: drive strength variant using rockchip_perpin_drv_type 121 * @offset: if initialized to -1 it will be autocalculated, by specifying 122 * an initial offset value the relevant source offset can be reset 123 * to a new value for autocalculating the following drive strength 124 * registers. if used chips own cal_drv func instead to calculate 125 * registers offset, the variant could be ignored. 126 */ 127struct rockchip_drv { 128 enum rockchip_pin_drv_type drv_type; 129 int offset; 130}; 131 132/** 133 * struct rockchip_pin_bank 134 * @reg_base: register base of the gpio bank 135 * @regmap_pull: optional separate register for additional pull settings 136 * @clk: clock of the gpio bank 137 * @irq: interrupt of the gpio bank 138 * @saved_masks: Saved content of GPIO_INTEN at suspend time. 139 * @pin_base: first pin number 140 * @nr_pins: number of pins in this bank 141 * @name: name of the bank 142 * @bank_num: number of the bank, to account for holes 143 * @iomux: array describing the 4 iomux sources of the bank 144 * @drv: array describing the 4 drive strength sources of the bank 145 * @pull_type: array describing the 4 pull type sources of the bank 146 * @valid: is all necessary information present 147 * @of_node: dt node of this bank 148 * @drvdata: common pinctrl basedata 149 * @domain: irqdomain of the gpio bank 150 * @gpio_chip: gpiolib chip 151 * @grange: gpio range 152 * @slock: spinlock for the gpio bank 153 * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode 154 * @recalced_mask: bit mask to indicate a need to recalulate the mask 155 * @route_mask: bits describing the routing pins of per bank 156 */ 157struct rockchip_pin_bank { 158 void __iomem *reg_base; 159 struct regmap *regmap_pull; 160 struct clk *clk; 161 int irq; 162 u32 saved_masks; 163 u32 pin_base; 164 u8 nr_pins; 165 char *name; 166 u8 bank_num; 167 struct rockchip_iomux iomux[4]; 168 struct rockchip_drv drv[4]; 169 enum rockchip_pin_pull_type pull_type[4]; 170 bool valid; 171 struct device_node *of_node; 172 struct rockchip_pinctrl *drvdata; 173 struct irq_domain *domain; 174 struct gpio_chip gpio_chip; 175 struct pinctrl_gpio_range grange; 176 raw_spinlock_t slock; 177 u32 toggle_edge_mode; 178 u32 recalced_mask; 179 u32 route_mask; 180}; 181 182#define PIN_BANK(id, pins, label) \ 183 { \ 184 .bank_num = id, \ 185 .nr_pins = pins, \ 186 .name = label, \ 187 .iomux = { \ 188 { .offset = -1 }, \ 189 { .offset = -1 }, \ 190 { .offset = -1 }, \ 191 { .offset = -1 }, \ 192 }, \ 193 } 194 195#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 196 { \ 197 .bank_num = id, \ 198 .nr_pins = pins, \ 199 .name = label, \ 200 .iomux = { \ 201 { .type = iom0, .offset = -1 }, \ 202 { .type = iom1, .offset = -1 }, \ 203 { .type = iom2, .offset = -1 }, \ 204 { .type = iom3, .offset = -1 }, \ 205 }, \ 206 } 207 208#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 209 { \ 210 .bank_num = id, \ 211 .nr_pins = pins, \ 212 .name = label, \ 213 .iomux = { \ 214 { .offset = -1 }, \ 215 { .offset = -1 }, \ 216 { .offset = -1 }, \ 217 { .offset = -1 }, \ 218 }, \ 219 .drv = { \ 220 { .drv_type = type0, .offset = -1 }, \ 221 { .drv_type = type1, .offset = -1 }, \ 222 { .drv_type = type2, .offset = -1 }, \ 223 { .drv_type = type3, .offset = -1 }, \ 224 }, \ 225 } 226 227#define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 228 drv2, drv3, pull0, pull1, \ 229 pull2, pull3) \ 230 { \ 231 .bank_num = id, \ 232 .nr_pins = pins, \ 233 .name = label, \ 234 .iomux = { \ 235 { .offset = -1 }, \ 236 { .offset = -1 }, \ 237 { .offset = -1 }, \ 238 { .offset = -1 }, \ 239 }, \ 240 .drv = { \ 241 { .drv_type = drv0, .offset = -1 }, \ 242 { .drv_type = drv1, .offset = -1 }, \ 243 { .drv_type = drv2, .offset = -1 }, \ 244 { .drv_type = drv3, .offset = -1 }, \ 245 }, \ 246 .pull_type[0] = pull0, \ 247 .pull_type[1] = pull1, \ 248 .pull_type[2] = pull2, \ 249 .pull_type[3] = pull3, \ 250 } 251 252#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 253 iom2, iom3, drv0, drv1, drv2, \ 254 drv3, offset0, offset1, \ 255 offset2, offset3) \ 256 { \ 257 .bank_num = id, \ 258 .nr_pins = pins, \ 259 .name = label, \ 260 .iomux = { \ 261 { .type = iom0, .offset = -1 }, \ 262 { .type = iom1, .offset = -1 }, \ 263 { .type = iom2, .offset = -1 }, \ 264 { .type = iom3, .offset = -1 }, \ 265 }, \ 266 .drv = { \ 267 { .drv_type = drv0, .offset = offset0 }, \ 268 { .drv_type = drv1, .offset = offset1 }, \ 269 { .drv_type = drv2, .offset = offset2 }, \ 270 { .drv_type = drv3, .offset = offset3 }, \ 271 }, \ 272 } 273 274#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 275 label, iom0, iom1, iom2, \ 276 iom3, drv0, drv1, drv2, \ 277 drv3, offset0, offset1, \ 278 offset2, offset3, pull0, \ 279 pull1, pull2, pull3) \ 280 { \ 281 .bank_num = id, \ 282 .nr_pins = pins, \ 283 .name = label, \ 284 .iomux = { \ 285 { .type = iom0, .offset = -1 }, \ 286 { .type = iom1, .offset = -1 }, \ 287 { .type = iom2, .offset = -1 }, \ 288 { .type = iom3, .offset = -1 }, \ 289 }, \ 290 .drv = { \ 291 { .drv_type = drv0, .offset = offset0 }, \ 292 { .drv_type = drv1, .offset = offset1 }, \ 293 { .drv_type = drv2, .offset = offset2 }, \ 294 { .drv_type = drv3, .offset = offset3 }, \ 295 }, \ 296 .pull_type[0] = pull0, \ 297 .pull_type[1] = pull1, \ 298 .pull_type[2] = pull2, \ 299 .pull_type[3] = pull3, \ 300 } 301 302#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ 303 { \ 304 .bank_num = ID, \ 305 .pin = PIN, \ 306 .func = FUNC, \ 307 .route_offset = REG, \ 308 .route_val = VAL, \ 309 .route_location = FLAG, \ 310 } 311 312#define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \ 313 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME) 314 315#define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \ 316 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF) 317 318#define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \ 319 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU) 320 321/** 322 * struct rockchip_mux_recalced_data: represent a pin iomux data. 323 * @num: bank number. 324 * @pin: pin number. 325 * @bit: index at register. 326 * @reg: register offset. 327 * @mask: mask bit 328 */ 329struct rockchip_mux_recalced_data { 330 u8 num; 331 u8 pin; 332 u32 reg; 333 u8 bit; 334 u8 mask; 335}; 336 337enum rockchip_mux_route_location { 338 ROCKCHIP_ROUTE_SAME = 0, 339 ROCKCHIP_ROUTE_PMU, 340 ROCKCHIP_ROUTE_GRF, 341}; 342 343/** 344 * struct rockchip_mux_recalced_data: represent a pin iomux data. 345 * @bank_num: bank number. 346 * @pin: index at register or used to calc index. 347 * @func: the min pin. 348 * @route_location: the mux route location (same, pmu, grf). 349 * @route_offset: the max pin. 350 * @route_val: the register offset. 351 */ 352struct rockchip_mux_route_data { 353 u8 bank_num; 354 u8 pin; 355 u8 func; 356 enum rockchip_mux_route_location route_location; 357 u32 route_offset; 358 u32 route_val; 359}; 360 361struct rockchip_pin_ctrl { 362 struct rockchip_pin_bank *pin_banks; 363 u32 nr_banks; 364 u32 nr_pins; 365 char *label; 366 enum rockchip_pinctrl_type type; 367 int grf_mux_offset; 368 int pmu_mux_offset; 369 int grf_drv_offset; 370 int pmu_drv_offset; 371 struct rockchip_mux_recalced_data *iomux_recalced; 372 u32 niomux_recalced; 373 struct rockchip_mux_route_data *iomux_routes; 374 u32 niomux_routes; 375 376 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 377 int pin_num, struct regmap **regmap, 378 int *reg, u8 *bit); 379 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 380 int pin_num, struct regmap **regmap, 381 int *reg, u8 *bit); 382 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 383 int pin_num, struct regmap **regmap, 384 int *reg, u8 *bit); 385}; 386 387struct rockchip_pin_config { 388 unsigned int func; 389 unsigned long *configs; 390 unsigned int nconfigs; 391}; 392 393/** 394 * struct rockchip_pin_group: represent group of pins of a pinmux function. 395 * @name: name of the pin group, used to lookup the group. 396 * @pins: the pins included in this group. 397 * @npins: number of pins included in this group. 398 * @data: local pin configuration 399 */ 400struct rockchip_pin_group { 401 const char *name; 402 unsigned int npins; 403 unsigned int *pins; 404 struct rockchip_pin_config *data; 405}; 406 407/** 408 * struct rockchip_pmx_func: represent a pin function. 409 * @name: name of the pin function, used to lookup the function. 410 * @groups: one or more names of pin groups that provide this function. 411 * @ngroups: number of groups included in @groups. 412 */ 413struct rockchip_pmx_func { 414 const char *name; 415 const char **groups; 416 u8 ngroups; 417}; 418 419struct rockchip_pinctrl { 420 struct regmap *regmap_base; 421 int reg_size; 422 struct regmap *regmap_pull; 423 struct regmap *regmap_pmu; 424 struct device *dev; 425 struct rockchip_pin_ctrl *ctrl; 426 struct pinctrl_desc pctl; 427 struct pinctrl_dev *pctl_dev; 428 struct rockchip_pin_group *groups; 429 unsigned int ngroups; 430 struct rockchip_pmx_func *functions; 431 unsigned int nfunctions; 432}; 433 434static struct regmap_config rockchip_regmap_config = { 435 .reg_bits = 32, 436 .val_bits = 32, 437 .reg_stride = 4, 438}; 439 440static inline const struct rockchip_pin_group *pinctrl_name_to_group( 441 const struct rockchip_pinctrl *info, 442 const char *name) 443{ 444 int i; 445 446 for (i = 0; i < info->ngroups; i++) { 447 if (!strcmp(info->groups[i].name, name)) 448 return &info->groups[i]; 449 } 450 451 return NULL; 452} 453 454/* 455 * given a pin number that is local to a pin controller, find out the pin bank 456 * and the register base of the pin bank. 457 */ 458static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, 459 unsigned pin) 460{ 461 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 462 463 while (pin >= (b->pin_base + b->nr_pins)) 464 b++; 465 466 return b; 467} 468 469static struct rockchip_pin_bank *bank_num_to_bank( 470 struct rockchip_pinctrl *info, 471 unsigned num) 472{ 473 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 474 int i; 475 476 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { 477 if (b->bank_num == num) 478 return b; 479 } 480 481 return ERR_PTR(-EINVAL); 482} 483 484/* 485 * Pinctrl_ops handling 486 */ 487 488static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) 489{ 490 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 491 492 return info->ngroups; 493} 494 495static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, 496 unsigned selector) 497{ 498 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 499 500 return info->groups[selector].name; 501} 502 503static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, 504 unsigned selector, const unsigned **pins, 505 unsigned *npins) 506{ 507 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 508 509 if (selector >= info->ngroups) 510 return -EINVAL; 511 512 *pins = info->groups[selector].pins; 513 *npins = info->groups[selector].npins; 514 515 return 0; 516} 517 518static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, 519 struct device_node *np, 520 struct pinctrl_map **map, unsigned *num_maps) 521{ 522 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 523 const struct rockchip_pin_group *grp; 524 struct pinctrl_map *new_map; 525 struct device_node *parent; 526 int map_num = 1; 527 int i; 528 529 /* 530 * first find the group of this node and check if we need to create 531 * config maps for pins 532 */ 533 grp = pinctrl_name_to_group(info, np->name); 534 if (!grp) { 535 dev_err(info->dev, "unable to find group for node %pOFn\n", 536 np); 537 return -EINVAL; 538 } 539 540 map_num += grp->npins; 541 542 new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL); 543 if (!new_map) 544 return -ENOMEM; 545 546 *map = new_map; 547 *num_maps = map_num; 548 549 /* create mux map */ 550 parent = of_get_parent(np); 551 if (!parent) { 552 kfree(new_map); 553 return -EINVAL; 554 } 555 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 556 new_map[0].data.mux.function = parent->name; 557 new_map[0].data.mux.group = np->name; 558 of_node_put(parent); 559 560 /* create config map */ 561 new_map++; 562 for (i = 0; i < grp->npins; i++) { 563 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 564 new_map[i].data.configs.group_or_pin = 565 pin_get_name(pctldev, grp->pins[i]); 566 new_map[i].data.configs.configs = grp->data[i].configs; 567 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; 568 } 569 570 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 571 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 572 573 return 0; 574} 575 576static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, 577 struct pinctrl_map *map, unsigned num_maps) 578{ 579 kfree(map); 580} 581 582static const struct pinctrl_ops rockchip_pctrl_ops = { 583 .get_groups_count = rockchip_get_groups_count, 584 .get_group_name = rockchip_get_group_name, 585 .get_group_pins = rockchip_get_group_pins, 586 .dt_node_to_map = rockchip_dt_node_to_map, 587 .dt_free_map = rockchip_dt_free_map, 588}; 589 590/* 591 * Hardware access 592 */ 593 594static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 595 { 596 .num = 1, 597 .pin = 0, 598 .reg = 0x418, 599 .bit = 0, 600 .mask = 0x3 601 }, { 602 .num = 1, 603 .pin = 1, 604 .reg = 0x418, 605 .bit = 2, 606 .mask = 0x3 607 }, { 608 .num = 1, 609 .pin = 2, 610 .reg = 0x418, 611 .bit = 4, 612 .mask = 0x3 613 }, { 614 .num = 1, 615 .pin = 3, 616 .reg = 0x418, 617 .bit = 6, 618 .mask = 0x3 619 }, { 620 .num = 1, 621 .pin = 4, 622 .reg = 0x418, 623 .bit = 8, 624 .mask = 0x3 625 }, { 626 .num = 1, 627 .pin = 5, 628 .reg = 0x418, 629 .bit = 10, 630 .mask = 0x3 631 }, { 632 .num = 1, 633 .pin = 6, 634 .reg = 0x418, 635 .bit = 12, 636 .mask = 0x3 637 }, { 638 .num = 1, 639 .pin = 7, 640 .reg = 0x418, 641 .bit = 14, 642 .mask = 0x3 643 }, { 644 .num = 1, 645 .pin = 8, 646 .reg = 0x41c, 647 .bit = 0, 648 .mask = 0x3 649 }, { 650 .num = 1, 651 .pin = 9, 652 .reg = 0x41c, 653 .bit = 2, 654 .mask = 0x3 655 }, 656}; 657 658static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 659 { 660 .num = 2, 661 .pin = 20, 662 .reg = 0xe8, 663 .bit = 0, 664 .mask = 0x7 665 }, { 666 .num = 2, 667 .pin = 21, 668 .reg = 0xe8, 669 .bit = 4, 670 .mask = 0x7 671 }, { 672 .num = 2, 673 .pin = 22, 674 .reg = 0xe8, 675 .bit = 8, 676 .mask = 0x7 677 }, { 678 .num = 2, 679 .pin = 23, 680 .reg = 0xe8, 681 .bit = 12, 682 .mask = 0x7 683 }, { 684 .num = 2, 685 .pin = 24, 686 .reg = 0xd4, 687 .bit = 12, 688 .mask = 0x7 689 }, 690}; 691 692static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 693 { 694 /* gpio1b6_sel */ 695 .num = 1, 696 .pin = 14, 697 .reg = 0x28, 698 .bit = 12, 699 .mask = 0xf 700 }, { 701 /* gpio1b7_sel */ 702 .num = 1, 703 .pin = 15, 704 .reg = 0x2c, 705 .bit = 0, 706 .mask = 0x3 707 }, { 708 /* gpio1c2_sel */ 709 .num = 1, 710 .pin = 18, 711 .reg = 0x30, 712 .bit = 4, 713 .mask = 0xf 714 }, { 715 /* gpio1c3_sel */ 716 .num = 1, 717 .pin = 19, 718 .reg = 0x30, 719 .bit = 8, 720 .mask = 0xf 721 }, { 722 /* gpio1c4_sel */ 723 .num = 1, 724 .pin = 20, 725 .reg = 0x30, 726 .bit = 12, 727 .mask = 0xf 728 }, { 729 /* gpio1c5_sel */ 730 .num = 1, 731 .pin = 21, 732 .reg = 0x34, 733 .bit = 0, 734 .mask = 0xf 735 }, { 736 /* gpio1c6_sel */ 737 .num = 1, 738 .pin = 22, 739 .reg = 0x34, 740 .bit = 4, 741 .mask = 0xf 742 }, { 743 /* gpio1c7_sel */ 744 .num = 1, 745 .pin = 23, 746 .reg = 0x34, 747 .bit = 8, 748 .mask = 0xf 749 }, { 750 /* gpio3b4_sel */ 751 .num = 3, 752 .pin = 12, 753 .reg = 0x68, 754 .bit = 8, 755 .mask = 0xf 756 }, { 757 /* gpio3b5_sel */ 758 .num = 3, 759 .pin = 13, 760 .reg = 0x68, 761 .bit = 12, 762 .mask = 0xf 763 }, { 764 /* gpio2a2_sel */ 765 .num = 2, 766 .pin = 2, 767 .reg = 0x40, 768 .bit = 4, 769 .mask = 0x3 770 }, { 771 /* gpio2a3_sel */ 772 .num = 2, 773 .pin = 3, 774 .reg = 0x40, 775 .bit = 6, 776 .mask = 0x3 777 }, { 778 /* gpio2c0_sel */ 779 .num = 2, 780 .pin = 16, 781 .reg = 0x50, 782 .bit = 0, 783 .mask = 0x3 784 }, { 785 /* gpio3b2_sel */ 786 .num = 3, 787 .pin = 10, 788 .reg = 0x68, 789 .bit = 4, 790 .mask = 0x3 791 }, { 792 /* gpio3b3_sel */ 793 .num = 3, 794 .pin = 11, 795 .reg = 0x68, 796 .bit = 6, 797 .mask = 0x3 798 }, 799}; 800 801static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 802 { 803 .num = 2, 804 .pin = 12, 805 .reg = 0x24, 806 .bit = 8, 807 .mask = 0x3 808 }, { 809 .num = 2, 810 .pin = 15, 811 .reg = 0x28, 812 .bit = 0, 813 .mask = 0x7 814 }, { 815 .num = 2, 816 .pin = 23, 817 .reg = 0x30, 818 .bit = 14, 819 .mask = 0x3 820 }, 821}; 822 823static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 824 int *reg, u8 *bit, int *mask) 825{ 826 struct rockchip_pinctrl *info = bank->drvdata; 827 struct rockchip_pin_ctrl *ctrl = info->ctrl; 828 struct rockchip_mux_recalced_data *data; 829 int i; 830 831 for (i = 0; i < ctrl->niomux_recalced; i++) { 832 data = &ctrl->iomux_recalced[i]; 833 if (data->num == bank->bank_num && 834 data->pin == pin) 835 break; 836 } 837 838 if (i >= ctrl->niomux_recalced) 839 return; 840 841 *reg = data->reg; 842 *mask = data->mask; 843 *bit = data->bit; 844} 845 846static struct rockchip_mux_route_data px30_mux_route_data[] = { 847 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */ 848 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */ 849 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */ 850 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */ 851 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */ 852 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */ 853 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */ 854 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */ 855}; 856 857static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 858 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */ 859 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */ 860 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */ 861 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */ 862 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */ 863 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */ 864 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */ 865}; 866 867static struct rockchip_mux_route_data rk3188_mux_route_data[] = { 868 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */ 869 RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */ 870}; 871 872static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 873 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */ 874 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */ 875 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */ 876 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */ 877 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */ 878 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */ 879 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */ 880 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */ 881 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */ 882 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */ 883 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */ 884 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */ 885 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */ 886 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */ 887 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */ 888 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */ 889 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */ 890 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */ 891}; 892 893static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 894 RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */ 895 RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */ 896}; 897 898static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 899 RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */ 900 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */ 901 RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */ 902 RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */ 903 RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */ 904 RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */ 905 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */ 906 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */ 907 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */ 908 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */ 909 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */ 910 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */ 911 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */ 912 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */ 913 RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */ 914 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */ 915 RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */ 916 RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */ 917 RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */ 918 RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */ 919 RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */ 920 RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */ 921 RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */ 922 RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */ 923 RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */ 924 RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */ 925}; 926 927static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 928 RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */ 929 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */ 930 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */ 931 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */ 932 RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */ 933 RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */ 934 RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */ 935 RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */ 936 RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */ 937 RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */ 938 RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */ 939 RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */ 940}; 941 942static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 943 RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */ 944 RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */ 945 RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */ 946 RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */ 947 RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */ 948}; 949 950static struct rockchip_mux_route_data rk3568_mux_route_data[] = { 951 RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */ 952 RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */ 953 RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */ 954 RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */ 955 RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */ 956 RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */ 957 RK_MUXROUTE_GRF(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */ 958 RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */ 959 RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */ 960 RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */ 961 RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */ 962 RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */ 963 RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */ 964 RK_MUXROUTE_GRF(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */ 965 RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */ 966 RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */ 967 RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */ 968 RK_MUXROUTE_GRF(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */ 969 RK_MUXROUTE_GRF(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */ 970 RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */ 971 RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */ 972 RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */ 973 RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */ 974 RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */ 975 RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */ 976 RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */ 977 RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */ 978 RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */ 979 RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */ 980 RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */ 981 RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */ 982 RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */ 983 RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */ 984 RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */ 985 RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */ 986 RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */ 987 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */ 988 RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */ 989 RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */ 990 RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */ 991 RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */ 992 RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */ 993 RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */ 994 RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */ 995 RK_MUXROUTE_GRF(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */ 996 RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */ 997 RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */ 998 RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */ 999 RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */ 1000 RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */ 1001 RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */ 1002 RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */ 1003 RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */ 1004 RK_MUXROUTE_GRF(3, RK_PD6, 4, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */ 1005 RK_MUXROUTE_GRF(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */ 1006 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */ 1007 RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */ 1008 RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */ 1009 RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */ 1010 RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */ 1011 RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */ 1012 RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */ 1013 RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */ 1014 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */ 1015 RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */ 1016 RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */ 1017 RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */ 1018 RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */ 1019 RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */ 1020 RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */ 1021 RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */ 1022 RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */ 1023 RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */ 1024 RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */ 1025 RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */ 1026 RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */ 1027 RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */ 1028 RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */ 1029 RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */ 1030 RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */ 1031 RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */ 1032 RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */ 1033 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */ 1034 RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */ 1035 RK_MUXROUTE_GRF(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */ 1036 RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */ 1037 RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */ 1038 RK_MUXROUTE_GRF(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */ 1039 RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */ 1040 RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */ 1041 RK_MUXROUTE_GRF(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */ 1042 RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */ 1043 RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */ 1044}; 1045 1046static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 1047 int mux, u32 *loc, u32 *reg, u32 *value) 1048{ 1049 struct rockchip_pinctrl *info = bank->drvdata; 1050 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1051 struct rockchip_mux_route_data *data; 1052 int i; 1053 1054 for (i = 0; i < ctrl->niomux_routes; i++) { 1055 data = &ctrl->iomux_routes[i]; 1056 if ((data->bank_num == bank->bank_num) && 1057 (data->pin == pin) && (data->func == mux)) 1058 break; 1059 } 1060 1061 if (i >= ctrl->niomux_routes) 1062 return false; 1063 1064 *loc = data->route_location; 1065 *reg = data->route_offset; 1066 *value = data->route_val; 1067 1068 return true; 1069} 1070 1071static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 1072{ 1073 struct rockchip_pinctrl *info = bank->drvdata; 1074 int iomux_num = (pin / 8); 1075 struct regmap *regmap; 1076 unsigned int val; 1077 int reg, ret, mask, mux_type; 1078 u8 bit; 1079 1080 if (iomux_num > 3) 1081 return -EINVAL; 1082 1083 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1084 dev_err(info->dev, "pin %d is unrouted\n", pin); 1085 return -EINVAL; 1086 } 1087 1088 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1089 return RK_FUNC_GPIO; 1090 1091 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1092 ? info->regmap_pmu : info->regmap_base; 1093 1094 /* get basic quadrupel of mux registers and the correct reg inside */ 1095 mux_type = bank->iomux[iomux_num].type; 1096 reg = bank->iomux[iomux_num].offset; 1097 if (mux_type & IOMUX_WIDTH_4BIT) { 1098 if ((pin % 8) >= 4) 1099 reg += 0x4; 1100 bit = (pin % 4) * 4; 1101 mask = 0xf; 1102 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1103 if ((pin % 8) >= 5) 1104 reg += 0x4; 1105 bit = (pin % 8 % 5) * 3; 1106 mask = 0x7; 1107 } else { 1108 bit = (pin % 8) * 2; 1109 mask = 0x3; 1110 } 1111 1112 if (bank->recalced_mask & BIT(pin)) 1113 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1114 1115 ret = regmap_read(regmap, reg, &val); 1116 if (ret) 1117 return ret; 1118 1119 return ((val >> bit) & mask); 1120} 1121 1122static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1123 int pin, int mux) 1124{ 1125 struct rockchip_pinctrl *info = bank->drvdata; 1126 int iomux_num = (pin / 8); 1127 1128 if (iomux_num > 3) 1129 return -EINVAL; 1130 1131 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1132 dev_err(info->dev, "pin %d is unrouted\n", pin); 1133 return -EINVAL; 1134 } 1135 1136 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1137 if (mux != RK_FUNC_GPIO) { 1138 dev_err(info->dev, 1139 "pin %d only supports a gpio mux\n", pin); 1140 return -ENOTSUPP; 1141 } 1142 } 1143 1144 return 0; 1145} 1146 1147/* 1148 * Set a new mux function for a pin. 1149 * 1150 * The register is divided into the upper and lower 16 bit. When changing 1151 * a value, the previous register value is not read and changed. Instead 1152 * it seems the changed bits are marked in the upper 16 bit, while the 1153 * changed value gets set in the same offset in the lower 16 bit. 1154 * All pin settings seem to be 2 bit wide in both the upper and lower 1155 * parts. 1156 * @bank: pin bank to change 1157 * @pin: pin to change 1158 * @mux: new mux function to set 1159 */ 1160static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1161{ 1162 struct rockchip_pinctrl *info = bank->drvdata; 1163 int iomux_num = (pin / 8); 1164 struct regmap *regmap; 1165 int reg, ret, mask, mux_type; 1166 u8 bit; 1167 u32 data, rmask, route_location, route_reg, route_val; 1168 1169 ret = rockchip_verify_mux(bank, pin, mux); 1170 if (ret < 0) 1171 return ret; 1172 1173 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1174 return 0; 1175 1176 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", 1177 bank->bank_num, pin, mux); 1178 1179 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1180 ? info->regmap_pmu : info->regmap_base; 1181 1182 /* get basic quadrupel of mux registers and the correct reg inside */ 1183 mux_type = bank->iomux[iomux_num].type; 1184 reg = bank->iomux[iomux_num].offset; 1185 if (mux_type & IOMUX_WIDTH_4BIT) { 1186 if ((pin % 8) >= 4) 1187 reg += 0x4; 1188 bit = (pin % 4) * 4; 1189 mask = 0xf; 1190 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1191 if ((pin % 8) >= 5) 1192 reg += 0x4; 1193 bit = (pin % 8 % 5) * 3; 1194 mask = 0x7; 1195 } else { 1196 bit = (pin % 8) * 2; 1197 mask = 0x3; 1198 } 1199 1200 if (bank->recalced_mask & BIT(pin)) 1201 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1202 1203 if (bank->route_mask & BIT(pin)) { 1204 if (rockchip_get_mux_route(bank, pin, mux, &route_location, 1205 &route_reg, &route_val)) { 1206 struct regmap *route_regmap = regmap; 1207 1208 /* handle special locations */ 1209 switch (route_location) { 1210 case ROCKCHIP_ROUTE_PMU: 1211 route_regmap = info->regmap_pmu; 1212 break; 1213 case ROCKCHIP_ROUTE_GRF: 1214 route_regmap = info->regmap_base; 1215 break; 1216 } 1217 1218 ret = regmap_write(route_regmap, route_reg, route_val); 1219 if (ret) 1220 return ret; 1221 } 1222 } 1223 1224 data = (mask << (bit + 16)); 1225 rmask = data | (data >> 16); 1226 data |= (mux & mask) << bit; 1227 ret = regmap_update_bits(regmap, reg, rmask, data); 1228 1229 return ret; 1230} 1231 1232#define PX30_PULL_PMU_OFFSET 0x10 1233#define PX30_PULL_GRF_OFFSET 0x60 1234#define PX30_PULL_BITS_PER_PIN 2 1235#define PX30_PULL_PINS_PER_REG 8 1236#define PX30_PULL_BANK_STRIDE 16 1237 1238static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1239 int pin_num, struct regmap **regmap, 1240 int *reg, u8 *bit) 1241{ 1242 struct rockchip_pinctrl *info = bank->drvdata; 1243 1244 /* The first 32 pins of the first bank are located in PMU */ 1245 if (bank->bank_num == 0) { 1246 *regmap = info->regmap_pmu; 1247 *reg = PX30_PULL_PMU_OFFSET; 1248 } else { 1249 *regmap = info->regmap_base; 1250 *reg = PX30_PULL_GRF_OFFSET; 1251 1252 /* correct the offset, as we're starting with the 2nd bank */ 1253 *reg -= 0x10; 1254 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1255 } 1256 1257 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1258 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1259 *bit *= PX30_PULL_BITS_PER_PIN; 1260} 1261 1262#define PX30_DRV_PMU_OFFSET 0x20 1263#define PX30_DRV_GRF_OFFSET 0xf0 1264#define PX30_DRV_BITS_PER_PIN 2 1265#define PX30_DRV_PINS_PER_REG 8 1266#define PX30_DRV_BANK_STRIDE 16 1267 1268static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1269 int pin_num, struct regmap **regmap, 1270 int *reg, u8 *bit) 1271{ 1272 struct rockchip_pinctrl *info = bank->drvdata; 1273 1274 /* The first 32 pins of the first bank are located in PMU */ 1275 if (bank->bank_num == 0) { 1276 *regmap = info->regmap_pmu; 1277 *reg = PX30_DRV_PMU_OFFSET; 1278 } else { 1279 *regmap = info->regmap_base; 1280 *reg = PX30_DRV_GRF_OFFSET; 1281 1282 /* correct the offset, as we're starting with the 2nd bank */ 1283 *reg -= 0x10; 1284 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1285 } 1286 1287 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1288 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1289 *bit *= PX30_DRV_BITS_PER_PIN; 1290} 1291 1292#define PX30_SCHMITT_PMU_OFFSET 0x38 1293#define PX30_SCHMITT_GRF_OFFSET 0xc0 1294#define PX30_SCHMITT_PINS_PER_PMU_REG 16 1295#define PX30_SCHMITT_BANK_STRIDE 16 1296#define PX30_SCHMITT_PINS_PER_GRF_REG 8 1297 1298static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1299 int pin_num, 1300 struct regmap **regmap, 1301 int *reg, u8 *bit) 1302{ 1303 struct rockchip_pinctrl *info = bank->drvdata; 1304 int pins_per_reg; 1305 1306 if (bank->bank_num == 0) { 1307 *regmap = info->regmap_pmu; 1308 *reg = PX30_SCHMITT_PMU_OFFSET; 1309 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1310 } else { 1311 *regmap = info->regmap_base; 1312 *reg = PX30_SCHMITT_GRF_OFFSET; 1313 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1314 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1315 } 1316 1317 *reg += ((pin_num / pins_per_reg) * 4); 1318 *bit = pin_num % pins_per_reg; 1319 1320 return 0; 1321} 1322 1323#define RV1108_PULL_PMU_OFFSET 0x10 1324#define RV1108_PULL_OFFSET 0x110 1325#define RV1108_PULL_PINS_PER_REG 8 1326#define RV1108_PULL_BITS_PER_PIN 2 1327#define RV1108_PULL_BANK_STRIDE 16 1328 1329static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1330 int pin_num, struct regmap **regmap, 1331 int *reg, u8 *bit) 1332{ 1333 struct rockchip_pinctrl *info = bank->drvdata; 1334 1335 /* The first 24 pins of the first bank are located in PMU */ 1336 if (bank->bank_num == 0) { 1337 *regmap = info->regmap_pmu; 1338 *reg = RV1108_PULL_PMU_OFFSET; 1339 } else { 1340 *reg = RV1108_PULL_OFFSET; 1341 *regmap = info->regmap_base; 1342 /* correct the offset, as we're starting with the 2nd bank */ 1343 *reg -= 0x10; 1344 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1345 } 1346 1347 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1348 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1349 *bit *= RV1108_PULL_BITS_PER_PIN; 1350} 1351 1352#define RV1108_DRV_PMU_OFFSET 0x20 1353#define RV1108_DRV_GRF_OFFSET 0x210 1354#define RV1108_DRV_BITS_PER_PIN 2 1355#define RV1108_DRV_PINS_PER_REG 8 1356#define RV1108_DRV_BANK_STRIDE 16 1357 1358static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1359 int pin_num, struct regmap **regmap, 1360 int *reg, u8 *bit) 1361{ 1362 struct rockchip_pinctrl *info = bank->drvdata; 1363 1364 /* The first 24 pins of the first bank are located in PMU */ 1365 if (bank->bank_num == 0) { 1366 *regmap = info->regmap_pmu; 1367 *reg = RV1108_DRV_PMU_OFFSET; 1368 } else { 1369 *regmap = info->regmap_base; 1370 *reg = RV1108_DRV_GRF_OFFSET; 1371 1372 /* correct the offset, as we're starting with the 2nd bank */ 1373 *reg -= 0x10; 1374 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1375 } 1376 1377 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1378 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1379 *bit *= RV1108_DRV_BITS_PER_PIN; 1380} 1381 1382#define RV1108_SCHMITT_PMU_OFFSET 0x30 1383#define RV1108_SCHMITT_GRF_OFFSET 0x388 1384#define RV1108_SCHMITT_BANK_STRIDE 8 1385#define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1386#define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1387 1388static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1389 int pin_num, 1390 struct regmap **regmap, 1391 int *reg, u8 *bit) 1392{ 1393 struct rockchip_pinctrl *info = bank->drvdata; 1394 int pins_per_reg; 1395 1396 if (bank->bank_num == 0) { 1397 *regmap = info->regmap_pmu; 1398 *reg = RV1108_SCHMITT_PMU_OFFSET; 1399 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1400 } else { 1401 *regmap = info->regmap_base; 1402 *reg = RV1108_SCHMITT_GRF_OFFSET; 1403 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1404 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1405 } 1406 *reg += ((pin_num / pins_per_reg) * 4); 1407 *bit = pin_num % pins_per_reg; 1408 1409 return 0; 1410} 1411 1412#define RK3308_SCHMITT_PINS_PER_REG 8 1413#define RK3308_SCHMITT_BANK_STRIDE 16 1414#define RK3308_SCHMITT_GRF_OFFSET 0x1a0 1415 1416static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1417 int pin_num, struct regmap **regmap, 1418 int *reg, u8 *bit) 1419{ 1420 struct rockchip_pinctrl *info = bank->drvdata; 1421 1422 *regmap = info->regmap_base; 1423 *reg = RK3308_SCHMITT_GRF_OFFSET; 1424 1425 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 1426 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 1427 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 1428 1429 return 0; 1430} 1431 1432#define RK2928_PULL_OFFSET 0x118 1433#define RK2928_PULL_PINS_PER_REG 16 1434#define RK2928_PULL_BANK_STRIDE 8 1435 1436static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1437 int pin_num, struct regmap **regmap, 1438 int *reg, u8 *bit) 1439{ 1440 struct rockchip_pinctrl *info = bank->drvdata; 1441 1442 *regmap = info->regmap_base; 1443 *reg = RK2928_PULL_OFFSET; 1444 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1445 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1446 1447 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1448}; 1449 1450#define RK3128_PULL_OFFSET 0x118 1451 1452static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1453 int pin_num, struct regmap **regmap, 1454 int *reg, u8 *bit) 1455{ 1456 struct rockchip_pinctrl *info = bank->drvdata; 1457 1458 *regmap = info->regmap_base; 1459 *reg = RK3128_PULL_OFFSET; 1460 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1461 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1462 1463 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1464} 1465 1466#define RK3188_PULL_OFFSET 0x164 1467#define RK3188_PULL_BITS_PER_PIN 2 1468#define RK3188_PULL_PINS_PER_REG 8 1469#define RK3188_PULL_BANK_STRIDE 16 1470#define RK3188_PULL_PMU_OFFSET 0x64 1471 1472static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1473 int pin_num, struct regmap **regmap, 1474 int *reg, u8 *bit) 1475{ 1476 struct rockchip_pinctrl *info = bank->drvdata; 1477 1478 /* The first 12 pins of the first bank are located elsewhere */ 1479 if (bank->bank_num == 0 && pin_num < 12) { 1480 *regmap = info->regmap_pmu ? info->regmap_pmu 1481 : bank->regmap_pull; 1482 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; 1483 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1484 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1485 *bit *= RK3188_PULL_BITS_PER_PIN; 1486 } else { 1487 *regmap = info->regmap_pull ? info->regmap_pull 1488 : info->regmap_base; 1489 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; 1490 1491 /* correct the offset, as it is the 2nd pull register */ 1492 *reg -= 4; 1493 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1494 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1495 1496 /* 1497 * The bits in these registers have an inverse ordering 1498 * with the lowest pin being in bits 15:14 and the highest 1499 * pin in bits 1:0 1500 */ 1501 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1502 *bit *= RK3188_PULL_BITS_PER_PIN; 1503 } 1504} 1505 1506#define RK3288_PULL_OFFSET 0x140 1507static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1508 int pin_num, struct regmap **regmap, 1509 int *reg, u8 *bit) 1510{ 1511 struct rockchip_pinctrl *info = bank->drvdata; 1512 1513 /* The first 24 pins of the first bank are located in PMU */ 1514 if (bank->bank_num == 0) { 1515 *regmap = info->regmap_pmu; 1516 *reg = RK3188_PULL_PMU_OFFSET; 1517 1518 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1519 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1520 *bit *= RK3188_PULL_BITS_PER_PIN; 1521 } else { 1522 *regmap = info->regmap_base; 1523 *reg = RK3288_PULL_OFFSET; 1524 1525 /* correct the offset, as we're starting with the 2nd bank */ 1526 *reg -= 0x10; 1527 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1528 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1529 1530 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1531 *bit *= RK3188_PULL_BITS_PER_PIN; 1532 } 1533} 1534 1535#define RK3288_DRV_PMU_OFFSET 0x70 1536#define RK3288_DRV_GRF_OFFSET 0x1c0 1537#define RK3288_DRV_BITS_PER_PIN 2 1538#define RK3288_DRV_PINS_PER_REG 8 1539#define RK3288_DRV_BANK_STRIDE 16 1540 1541static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1542 int pin_num, struct regmap **regmap, 1543 int *reg, u8 *bit) 1544{ 1545 struct rockchip_pinctrl *info = bank->drvdata; 1546 1547 /* The first 24 pins of the first bank are located in PMU */ 1548 if (bank->bank_num == 0) { 1549 *regmap = info->regmap_pmu; 1550 *reg = RK3288_DRV_PMU_OFFSET; 1551 1552 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1553 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1554 *bit *= RK3288_DRV_BITS_PER_PIN; 1555 } else { 1556 *regmap = info->regmap_base; 1557 *reg = RK3288_DRV_GRF_OFFSET; 1558 1559 /* correct the offset, as we're starting with the 2nd bank */ 1560 *reg -= 0x10; 1561 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1562 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1563 1564 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1565 *bit *= RK3288_DRV_BITS_PER_PIN; 1566 } 1567} 1568 1569#define RK3228_PULL_OFFSET 0x100 1570 1571static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1572 int pin_num, struct regmap **regmap, 1573 int *reg, u8 *bit) 1574{ 1575 struct rockchip_pinctrl *info = bank->drvdata; 1576 1577 *regmap = info->regmap_base; 1578 *reg = RK3228_PULL_OFFSET; 1579 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1580 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1581 1582 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1583 *bit *= RK3188_PULL_BITS_PER_PIN; 1584} 1585 1586#define RK3228_DRV_GRF_OFFSET 0x200 1587 1588static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1589 int pin_num, struct regmap **regmap, 1590 int *reg, u8 *bit) 1591{ 1592 struct rockchip_pinctrl *info = bank->drvdata; 1593 1594 *regmap = info->regmap_base; 1595 *reg = RK3228_DRV_GRF_OFFSET; 1596 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1597 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1598 1599 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1600 *bit *= RK3288_DRV_BITS_PER_PIN; 1601} 1602 1603#define RK3308_PULL_OFFSET 0xa0 1604 1605static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1606 int pin_num, struct regmap **regmap, 1607 int *reg, u8 *bit) 1608{ 1609 struct rockchip_pinctrl *info = bank->drvdata; 1610 1611 *regmap = info->regmap_base; 1612 *reg = RK3308_PULL_OFFSET; 1613 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1614 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1615 1616 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1617 *bit *= RK3188_PULL_BITS_PER_PIN; 1618} 1619 1620#define RK3308_DRV_GRF_OFFSET 0x100 1621 1622static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1623 int pin_num, struct regmap **regmap, 1624 int *reg, u8 *bit) 1625{ 1626 struct rockchip_pinctrl *info = bank->drvdata; 1627 1628 *regmap = info->regmap_base; 1629 *reg = RK3308_DRV_GRF_OFFSET; 1630 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1631 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1632 1633 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1634 *bit *= RK3288_DRV_BITS_PER_PIN; 1635} 1636 1637#define RK3368_PULL_GRF_OFFSET 0x100 1638#define RK3368_PULL_PMU_OFFSET 0x10 1639 1640static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1641 int pin_num, struct regmap **regmap, 1642 int *reg, u8 *bit) 1643{ 1644 struct rockchip_pinctrl *info = bank->drvdata; 1645 1646 /* The first 32 pins of the first bank are located in PMU */ 1647 if (bank->bank_num == 0) { 1648 *regmap = info->regmap_pmu; 1649 *reg = RK3368_PULL_PMU_OFFSET; 1650 1651 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1652 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1653 *bit *= RK3188_PULL_BITS_PER_PIN; 1654 } else { 1655 *regmap = info->regmap_base; 1656 *reg = RK3368_PULL_GRF_OFFSET; 1657 1658 /* correct the offset, as we're starting with the 2nd bank */ 1659 *reg -= 0x10; 1660 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1661 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1662 1663 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1664 *bit *= RK3188_PULL_BITS_PER_PIN; 1665 } 1666} 1667 1668#define RK3368_DRV_PMU_OFFSET 0x20 1669#define RK3368_DRV_GRF_OFFSET 0x200 1670 1671static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1672 int pin_num, struct regmap **regmap, 1673 int *reg, u8 *bit) 1674{ 1675 struct rockchip_pinctrl *info = bank->drvdata; 1676 1677 /* The first 32 pins of the first bank are located in PMU */ 1678 if (bank->bank_num == 0) { 1679 *regmap = info->regmap_pmu; 1680 *reg = RK3368_DRV_PMU_OFFSET; 1681 1682 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1683 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1684 *bit *= RK3288_DRV_BITS_PER_PIN; 1685 } else { 1686 *regmap = info->regmap_base; 1687 *reg = RK3368_DRV_GRF_OFFSET; 1688 1689 /* correct the offset, as we're starting with the 2nd bank */ 1690 *reg -= 0x10; 1691 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1692 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1693 1694 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1695 *bit *= RK3288_DRV_BITS_PER_PIN; 1696 } 1697} 1698 1699#define RK3399_PULL_GRF_OFFSET 0xe040 1700#define RK3399_PULL_PMU_OFFSET 0x40 1701#define RK3399_DRV_3BITS_PER_PIN 3 1702 1703static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1704 int pin_num, struct regmap **regmap, 1705 int *reg, u8 *bit) 1706{ 1707 struct rockchip_pinctrl *info = bank->drvdata; 1708 1709 /* The bank0:16 and bank1:32 pins are located in PMU */ 1710 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 1711 *regmap = info->regmap_pmu; 1712 *reg = RK3399_PULL_PMU_OFFSET; 1713 1714 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1715 1716 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1717 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1718 *bit *= RK3188_PULL_BITS_PER_PIN; 1719 } else { 1720 *regmap = info->regmap_base; 1721 *reg = RK3399_PULL_GRF_OFFSET; 1722 1723 /* correct the offset, as we're starting with the 3rd bank */ 1724 *reg -= 0x20; 1725 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1726 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1727 1728 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1729 *bit *= RK3188_PULL_BITS_PER_PIN; 1730 } 1731} 1732 1733static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1734 int pin_num, struct regmap **regmap, 1735 int *reg, u8 *bit) 1736{ 1737 struct rockchip_pinctrl *info = bank->drvdata; 1738 int drv_num = (pin_num / 8); 1739 1740 /* The bank0:16 and bank1:32 pins are located in PMU */ 1741 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 1742 *regmap = info->regmap_pmu; 1743 else 1744 *regmap = info->regmap_base; 1745 1746 *reg = bank->drv[drv_num].offset; 1747 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 1748 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 1749 *bit = (pin_num % 8) * 3; 1750 else 1751 *bit = (pin_num % 8) * 2; 1752} 1753 1754#define RK3568_PULL_PMU_OFFSET 0x20 1755#define RK3568_PULL_GRF_OFFSET 0x80 1756#define RK3568_PULL_BITS_PER_PIN 2 1757#define RK3568_PULL_PINS_PER_REG 8 1758#define RK3568_PULL_BANK_STRIDE 0x10 1759 1760static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1761 int pin_num, struct regmap **regmap, 1762 int *reg, u8 *bit) 1763{ 1764 struct rockchip_pinctrl *info = bank->drvdata; 1765 1766 if (bank->bank_num == 0) { 1767 *regmap = info->regmap_pmu; 1768 *reg = RK3568_PULL_PMU_OFFSET; 1769 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE; 1770 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); 1771 1772 *bit = pin_num % RK3568_PULL_PINS_PER_REG; 1773 *bit *= RK3568_PULL_BITS_PER_PIN; 1774 } else { 1775 *regmap = info->regmap_base; 1776 *reg = RK3568_PULL_GRF_OFFSET; 1777 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE; 1778 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); 1779 1780 *bit = (pin_num % RK3568_PULL_PINS_PER_REG); 1781 *bit *= RK3568_PULL_BITS_PER_PIN; 1782 } 1783} 1784 1785#define RK3568_DRV_PMU_OFFSET 0x70 1786#define RK3568_DRV_GRF_OFFSET 0x200 1787#define RK3568_DRV_BITS_PER_PIN 8 1788#define RK3568_DRV_PINS_PER_REG 2 1789#define RK3568_DRV_BANK_STRIDE 0x40 1790 1791static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1792 int pin_num, struct regmap **regmap, 1793 int *reg, u8 *bit) 1794{ 1795 struct rockchip_pinctrl *info = bank->drvdata; 1796 1797 /* The first 32 pins of the first bank are located in PMU */ 1798 if (bank->bank_num == 0) { 1799 *regmap = info->regmap_pmu; 1800 *reg = RK3568_DRV_PMU_OFFSET; 1801 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); 1802 1803 *bit = pin_num % RK3568_DRV_PINS_PER_REG; 1804 *bit *= RK3568_DRV_BITS_PER_PIN; 1805 } else { 1806 *regmap = info->regmap_base; 1807 *reg = RK3568_DRV_GRF_OFFSET; 1808 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE; 1809 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); 1810 1811 *bit = (pin_num % RK3568_DRV_PINS_PER_REG); 1812 *bit *= RK3568_DRV_BITS_PER_PIN; 1813 } 1814} 1815 1816static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 1817 { 2, 4, 8, 12, -1, -1, -1, -1 }, 1818 { 3, 6, 9, 12, -1, -1, -1, -1 }, 1819 { 5, 10, 15, 20, -1, -1, -1, -1 }, 1820 { 4, 6, 8, 10, 12, 14, 16, 18 }, 1821 { 4, 7, 10, 13, 16, 19, 22, 26 } 1822}; 1823 1824static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, 1825 int pin_num) 1826{ 1827 struct rockchip_pinctrl *info = bank->drvdata; 1828 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1829 struct regmap *regmap; 1830 int reg, ret; 1831 u32 data, temp, rmask_bits; 1832 u8 bit; 1833 int drv_type = bank->drv[pin_num / 8].drv_type; 1834 1835 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 1836 1837 switch (drv_type) { 1838 case DRV_TYPE_IO_1V8_3V0_AUTO: 1839 case DRV_TYPE_IO_3V3_ONLY: 1840 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 1841 switch (bit) { 1842 case 0 ... 12: 1843 /* regular case, nothing to do */ 1844 break; 1845 case 15: 1846 /* 1847 * drive-strength offset is special, as it is 1848 * spread over 2 registers 1849 */ 1850 ret = regmap_read(regmap, reg, &data); 1851 if (ret) 1852 return ret; 1853 1854 ret = regmap_read(regmap, reg + 0x4, &temp); 1855 if (ret) 1856 return ret; 1857 1858 /* 1859 * the bit data[15] contains bit 0 of the value 1860 * while temp[1:0] contains bits 2 and 1 1861 */ 1862 data >>= 15; 1863 temp &= 0x3; 1864 temp <<= 1; 1865 data |= temp; 1866 1867 return rockchip_perpin_drv_list[drv_type][data]; 1868 case 18 ... 21: 1869 /* setting fully enclosed in the second register */ 1870 reg += 4; 1871 bit -= 16; 1872 break; 1873 default: 1874 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", 1875 bit, drv_type); 1876 return -EINVAL; 1877 } 1878 1879 break; 1880 case DRV_TYPE_IO_DEFAULT: 1881 case DRV_TYPE_IO_1V8_OR_3V0: 1882 case DRV_TYPE_IO_1V8_ONLY: 1883 rmask_bits = RK3288_DRV_BITS_PER_PIN; 1884 break; 1885 default: 1886 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", 1887 drv_type); 1888 return -EINVAL; 1889 } 1890 1891 ret = regmap_read(regmap, reg, &data); 1892 if (ret) 1893 return ret; 1894 1895 data >>= bit; 1896 data &= (1 << rmask_bits) - 1; 1897 1898 return rockchip_perpin_drv_list[drv_type][data]; 1899} 1900 1901static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 1902 int pin_num, int strength) 1903{ 1904 struct rockchip_pinctrl *info = bank->drvdata; 1905 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1906 struct regmap *regmap; 1907 int reg, ret, i; 1908 u32 data, rmask, rmask_bits, temp; 1909 u8 bit; 1910 int drv_type = bank->drv[pin_num / 8].drv_type; 1911 1912 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n", 1913 bank->bank_num, pin_num, strength); 1914 1915 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 1916 if (ctrl->type == RK3568) { 1917 rmask_bits = RK3568_DRV_BITS_PER_PIN; 1918 ret = (1 << (strength + 1)) - 1; 1919 goto config; 1920 } 1921 1922 ret = -EINVAL; 1923 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 1924 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 1925 ret = i; 1926 break; 1927 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 1928 ret = rockchip_perpin_drv_list[drv_type][i]; 1929 break; 1930 } 1931 } 1932 1933 if (ret < 0) { 1934 dev_err(info->dev, "unsupported driver strength %d\n", 1935 strength); 1936 return ret; 1937 } 1938 1939 switch (drv_type) { 1940 case DRV_TYPE_IO_1V8_3V0_AUTO: 1941 case DRV_TYPE_IO_3V3_ONLY: 1942 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 1943 switch (bit) { 1944 case 0 ... 12: 1945 /* regular case, nothing to do */ 1946 break; 1947 case 15: 1948 /* 1949 * drive-strength offset is special, as it is spread 1950 * over 2 registers, the bit data[15] contains bit 0 1951 * of the value while temp[1:0] contains bits 2 and 1 1952 */ 1953 data = (ret & 0x1) << 15; 1954 temp = (ret >> 0x1) & 0x3; 1955 1956 rmask = BIT(15) | BIT(31); 1957 data |= BIT(31); 1958 ret = regmap_update_bits(regmap, reg, rmask, data); 1959 if (ret) 1960 return ret; 1961 1962 rmask = 0x3 | (0x3 << 16); 1963 temp |= (0x3 << 16); 1964 reg += 0x4; 1965 ret = regmap_update_bits(regmap, reg, rmask, temp); 1966 1967 return ret; 1968 case 18 ... 21: 1969 /* setting fully enclosed in the second register */ 1970 reg += 4; 1971 bit -= 16; 1972 break; 1973 default: 1974 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", 1975 bit, drv_type); 1976 return -EINVAL; 1977 } 1978 break; 1979 case DRV_TYPE_IO_DEFAULT: 1980 case DRV_TYPE_IO_1V8_OR_3V0: 1981 case DRV_TYPE_IO_1V8_ONLY: 1982 rmask_bits = RK3288_DRV_BITS_PER_PIN; 1983 break; 1984 default: 1985 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", 1986 drv_type); 1987 return -EINVAL; 1988 } 1989 1990config: 1991 /* enable the write to the equivalent lower bits */ 1992 data = ((1 << rmask_bits) - 1) << (bit + 16); 1993 rmask = data | (data >> 16); 1994 data |= (ret << bit); 1995 1996 ret = regmap_update_bits(regmap, reg, rmask, data); 1997 1998 return ret; 1999} 2000 2001static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 2002 { 2003 PIN_CONFIG_BIAS_DISABLE, 2004 PIN_CONFIG_BIAS_PULL_UP, 2005 PIN_CONFIG_BIAS_PULL_DOWN, 2006 PIN_CONFIG_BIAS_BUS_HOLD 2007 }, 2008 { 2009 PIN_CONFIG_BIAS_DISABLE, 2010 PIN_CONFIG_BIAS_PULL_DOWN, 2011 PIN_CONFIG_BIAS_DISABLE, 2012 PIN_CONFIG_BIAS_PULL_UP 2013 }, 2014}; 2015 2016static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 2017{ 2018 struct rockchip_pinctrl *info = bank->drvdata; 2019 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2020 struct regmap *regmap; 2021 int reg, ret, pull_type; 2022 u8 bit; 2023 u32 data; 2024 2025 /* rk3066b does support any pulls */ 2026 if (ctrl->type == RK3066B) 2027 return PIN_CONFIG_BIAS_DISABLE; 2028 2029 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2030 2031 ret = regmap_read(regmap, reg, &data); 2032 if (ret) 2033 return ret; 2034 2035 switch (ctrl->type) { 2036 case RK2928: 2037 case RK3128: 2038 return !(data & BIT(bit)) 2039 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 2040 : PIN_CONFIG_BIAS_DISABLE; 2041 case PX30: 2042 case RV1108: 2043 case RK3188: 2044 case RK3288: 2045 case RK3308: 2046 case RK3368: 2047 case RK3399: 2048 case RK3568: 2049 pull_type = bank->pull_type[pin_num / 8]; 2050 data >>= bit; 2051 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; 2052 /* 2053 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, 2054 * where that pull up value becomes 3. 2055 */ 2056 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { 2057 if (data == 3) 2058 data = 1; 2059 } 2060 2061 return rockchip_pull_list[pull_type][data]; 2062 default: 2063 dev_err(info->dev, "unsupported pinctrl type\n"); 2064 return -EINVAL; 2065 }; 2066} 2067 2068static int rockchip_set_pull(struct rockchip_pin_bank *bank, 2069 int pin_num, int pull) 2070{ 2071 struct rockchip_pinctrl *info = bank->drvdata; 2072 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2073 struct regmap *regmap; 2074 int reg, ret, i, pull_type; 2075 u8 bit; 2076 u32 data, rmask; 2077 2078 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", 2079 bank->bank_num, pin_num, pull); 2080 2081 /* rk3066b does support any pulls */ 2082 if (ctrl->type == RK3066B) 2083 return pull ? -EINVAL : 0; 2084 2085 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2086 2087 switch (ctrl->type) { 2088 case RK2928: 2089 case RK3128: 2090 data = BIT(bit + 16); 2091 if (pull == PIN_CONFIG_BIAS_DISABLE) 2092 data |= BIT(bit); 2093 ret = regmap_write(regmap, reg, data); 2094 break; 2095 case PX30: 2096 case RV1108: 2097 case RK3188: 2098 case RK3288: 2099 case RK3308: 2100 case RK3368: 2101 case RK3399: 2102 case RK3568: 2103 pull_type = bank->pull_type[pin_num / 8]; 2104 ret = -EINVAL; 2105 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 2106 i++) { 2107 if (rockchip_pull_list[pull_type][i] == pull) { 2108 ret = i; 2109 break; 2110 } 2111 } 2112 /* 2113 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, 2114 * where that pull up value becomes 3. 2115 */ 2116 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { 2117 if (ret == 1) 2118 ret = 3; 2119 } 2120 2121 if (ret < 0) { 2122 dev_err(info->dev, "unsupported pull setting %d\n", 2123 pull); 2124 return ret; 2125 } 2126 2127 /* enable the write to the equivalent lower bits */ 2128 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 2129 rmask = data | (data >> 16); 2130 data |= (ret << bit); 2131 2132 ret = regmap_update_bits(regmap, reg, rmask, data); 2133 break; 2134 default: 2135 dev_err(info->dev, "unsupported pinctrl type\n"); 2136 return -EINVAL; 2137 } 2138 2139 return ret; 2140} 2141 2142#define RK3328_SCHMITT_BITS_PER_PIN 1 2143#define RK3328_SCHMITT_PINS_PER_REG 16 2144#define RK3328_SCHMITT_BANK_STRIDE 8 2145#define RK3328_SCHMITT_GRF_OFFSET 0x380 2146 2147static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2148 int pin_num, 2149 struct regmap **regmap, 2150 int *reg, u8 *bit) 2151{ 2152 struct rockchip_pinctrl *info = bank->drvdata; 2153 2154 *regmap = info->regmap_base; 2155 *reg = RK3328_SCHMITT_GRF_OFFSET; 2156 2157 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 2158 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 2159 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 2160 2161 return 0; 2162} 2163 2164#define RK3568_SCHMITT_BITS_PER_PIN 2 2165#define RK3568_SCHMITT_PINS_PER_REG 8 2166#define RK3568_SCHMITT_BANK_STRIDE 0x10 2167#define RK3568_SCHMITT_GRF_OFFSET 0xc0 2168#define RK3568_SCHMITT_PMUGRF_OFFSET 0x30 2169 2170static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2171 int pin_num, 2172 struct regmap **regmap, 2173 int *reg, u8 *bit) 2174{ 2175 struct rockchip_pinctrl *info = bank->drvdata; 2176 2177 if (bank->bank_num == 0) { 2178 *regmap = info->regmap_pmu; 2179 *reg = RK3568_SCHMITT_PMUGRF_OFFSET; 2180 } else { 2181 *regmap = info->regmap_base; 2182 *reg = RK3568_SCHMITT_GRF_OFFSET; 2183 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE; 2184 } 2185 2186 *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4); 2187 *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG; 2188 *bit *= RK3568_SCHMITT_BITS_PER_PIN; 2189 2190 return 0; 2191} 2192 2193static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) 2194{ 2195 struct rockchip_pinctrl *info = bank->drvdata; 2196 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2197 struct regmap *regmap; 2198 int reg, ret; 2199 u8 bit; 2200 u32 data; 2201 2202 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2203 if (ret) 2204 return ret; 2205 2206 ret = regmap_read(regmap, reg, &data); 2207 if (ret) 2208 return ret; 2209 2210 data >>= bit; 2211 switch (ctrl->type) { 2212 case RK3568: 2213 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1); 2214 default: 2215 break; 2216 } 2217 2218 return data & 0x1; 2219} 2220 2221static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 2222 int pin_num, int enable) 2223{ 2224 struct rockchip_pinctrl *info = bank->drvdata; 2225 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2226 struct regmap *regmap; 2227 int reg, ret; 2228 u8 bit; 2229 u32 data, rmask; 2230 2231 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n", 2232 bank->bank_num, pin_num, enable); 2233 2234 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2235 if (ret) 2236 return ret; 2237 2238 /* enable the write to the equivalent lower bits */ 2239 switch (ctrl->type) { 2240 case RK3568: 2241 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16); 2242 rmask = data | (data >> 16); 2243 data |= ((enable ? 0x2 : 0x1) << bit); 2244 break; 2245 default: 2246 data = BIT(bit + 16) | (enable << bit); 2247 rmask = BIT(bit + 16) | BIT(bit); 2248 break; 2249 } 2250 2251 return regmap_update_bits(regmap, reg, rmask, data); 2252} 2253 2254/* 2255 * Pinmux_ops handling 2256 */ 2257 2258static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 2259{ 2260 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2261 2262 return info->nfunctions; 2263} 2264 2265static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, 2266 unsigned selector) 2267{ 2268 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2269 2270 return info->functions[selector].name; 2271} 2272 2273static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, 2274 unsigned selector, const char * const **groups, 2275 unsigned * const num_groups) 2276{ 2277 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2278 2279 *groups = info->functions[selector].groups; 2280 *num_groups = info->functions[selector].ngroups; 2281 2282 return 0; 2283} 2284 2285static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 2286 unsigned group) 2287{ 2288 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2289 const unsigned int *pins = info->groups[group].pins; 2290 const struct rockchip_pin_config *data = info->groups[group].data; 2291 struct rockchip_pin_bank *bank; 2292 int cnt, ret = 0; 2293 2294 dev_dbg(info->dev, "enable function %s group %s\n", 2295 info->functions[selector].name, info->groups[group].name); 2296 2297 /* 2298 * for each pin in the pin group selected, program the corresponding 2299 * pin function number in the config register. 2300 */ 2301 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { 2302 bank = pin_to_bank(info, pins[cnt]); 2303 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 2304 data[cnt].func); 2305 if (ret) 2306 break; 2307 } 2308 2309 if (ret) { 2310 /* revert the already done pin settings */ 2311 for (cnt--; cnt >= 0; cnt--) 2312 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); 2313 2314 return ret; 2315 } 2316 2317 return 0; 2318} 2319 2320static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 2321{ 2322 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); 2323 u32 data; 2324 int ret; 2325 2326 ret = clk_enable(bank->clk); 2327 if (ret < 0) { 2328 dev_err(bank->drvdata->dev, 2329 "failed to enable clock for bank %s\n", bank->name); 2330 return ret; 2331 } 2332 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 2333 clk_disable(bank->clk); 2334 2335 if (data & BIT(offset)) 2336 return GPIO_LINE_DIRECTION_OUT; 2337 2338 return GPIO_LINE_DIRECTION_IN; 2339} 2340 2341/* 2342 * The calls to gpio_direction_output() and gpio_direction_input() 2343 * leads to this function call (via the pinctrl_gpio_direction_{input|output}() 2344 * function called from the gpiolib interface). 2345 */ 2346static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip, 2347 int pin, bool input) 2348{ 2349 struct rockchip_pin_bank *bank; 2350 int ret; 2351 unsigned long flags; 2352 u32 data; 2353 2354 bank = gpiochip_get_data(chip); 2355 2356 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); 2357 if (ret < 0) 2358 return ret; 2359 2360 clk_enable(bank->clk); 2361 raw_spin_lock_irqsave(&bank->slock, flags); 2362 2363 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 2364 /* set bit to 1 for output, 0 for input */ 2365 if (!input) 2366 data |= BIT(pin); 2367 else 2368 data &= ~BIT(pin); 2369 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 2370 2371 raw_spin_unlock_irqrestore(&bank->slock, flags); 2372 clk_disable(bank->clk); 2373 2374 return 0; 2375} 2376 2377static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 2378 struct pinctrl_gpio_range *range, 2379 unsigned offset, bool input) 2380{ 2381 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2382 struct gpio_chip *chip; 2383 int pin; 2384 2385 chip = range->gc; 2386 pin = offset - chip->base; 2387 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", 2388 offset, range->name, pin, input ? "input" : "output"); 2389 2390 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base, 2391 input); 2392} 2393 2394static const struct pinmux_ops rockchip_pmx_ops = { 2395 .get_functions_count = rockchip_pmx_get_funcs_count, 2396 .get_function_name = rockchip_pmx_get_func_name, 2397 .get_function_groups = rockchip_pmx_get_groups, 2398 .set_mux = rockchip_pmx_set, 2399 .gpio_set_direction = rockchip_pmx_gpio_set_direction, 2400}; 2401 2402/* 2403 * Pinconf_ops handling 2404 */ 2405 2406static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 2407 enum pin_config_param pull) 2408{ 2409 switch (ctrl->type) { 2410 case RK2928: 2411 case RK3128: 2412 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 2413 pull == PIN_CONFIG_BIAS_DISABLE); 2414 case RK3066B: 2415 return pull ? false : true; 2416 case PX30: 2417 case RV1108: 2418 case RK3188: 2419 case RK3288: 2420 case RK3308: 2421 case RK3368: 2422 case RK3399: 2423 case RK3568: 2424 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 2425 } 2426 2427 return false; 2428} 2429 2430static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value); 2431static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset); 2432 2433/* set the pin config settings for a specified pin */ 2434static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 2435 unsigned long *configs, unsigned num_configs) 2436{ 2437 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2438 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 2439 enum pin_config_param param; 2440 u32 arg; 2441 int i; 2442 int rc; 2443 2444 for (i = 0; i < num_configs; i++) { 2445 param = pinconf_to_config_param(configs[i]); 2446 arg = pinconf_to_config_argument(configs[i]); 2447 2448 switch (param) { 2449 case PIN_CONFIG_BIAS_DISABLE: 2450 rc = rockchip_set_pull(bank, pin - bank->pin_base, 2451 param); 2452 if (rc) 2453 return rc; 2454 break; 2455 case PIN_CONFIG_BIAS_PULL_UP: 2456 case PIN_CONFIG_BIAS_PULL_DOWN: 2457 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2458 case PIN_CONFIG_BIAS_BUS_HOLD: 2459 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 2460 return -ENOTSUPP; 2461 2462 if (!arg) 2463 return -EINVAL; 2464 2465 rc = rockchip_set_pull(bank, pin - bank->pin_base, 2466 param); 2467 if (rc) 2468 return rc; 2469 break; 2470 case PIN_CONFIG_OUTPUT: 2471 rockchip_gpio_set(&bank->gpio_chip, 2472 pin - bank->pin_base, arg); 2473 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip, 2474 pin - bank->pin_base, false); 2475 if (rc) 2476 return rc; 2477 break; 2478 case PIN_CONFIG_DRIVE_STRENGTH: 2479 /* rk3288 is the first with per-pin drive-strength */ 2480 if (!info->ctrl->drv_calc_reg) 2481 return -ENOTSUPP; 2482 2483 rc = rockchip_set_drive_perpin(bank, 2484 pin - bank->pin_base, arg); 2485 if (rc < 0) 2486 return rc; 2487 break; 2488 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2489 if (!info->ctrl->schmitt_calc_reg) 2490 return -ENOTSUPP; 2491 2492 rc = rockchip_set_schmitt(bank, 2493 pin - bank->pin_base, arg); 2494 if (rc < 0) 2495 return rc; 2496 break; 2497 default: 2498 return -ENOTSUPP; 2499 break; 2500 } 2501 } /* for each config */ 2502 2503 return 0; 2504} 2505 2506/* get the pin config settings for a specified pin */ 2507static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 2508 unsigned long *config) 2509{ 2510 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2511 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 2512 enum pin_config_param param = pinconf_to_config_param(*config); 2513 u16 arg; 2514 int rc; 2515 2516 switch (param) { 2517 case PIN_CONFIG_BIAS_DISABLE: 2518 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 2519 return -EINVAL; 2520 2521 arg = 0; 2522 break; 2523 case PIN_CONFIG_BIAS_PULL_UP: 2524 case PIN_CONFIG_BIAS_PULL_DOWN: 2525 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2526 case PIN_CONFIG_BIAS_BUS_HOLD: 2527 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 2528 return -ENOTSUPP; 2529 2530 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 2531 return -EINVAL; 2532 2533 arg = 1; 2534 break; 2535 case PIN_CONFIG_OUTPUT: 2536 rc = rockchip_get_mux(bank, pin - bank->pin_base); 2537 if (rc != RK_FUNC_GPIO) 2538 return -EINVAL; 2539 2540 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); 2541 if (rc < 0) 2542 return rc; 2543 2544 arg = rc ? 1 : 0; 2545 break; 2546 case PIN_CONFIG_DRIVE_STRENGTH: 2547 /* rk3288 is the first with per-pin drive-strength */ 2548 if (!info->ctrl->drv_calc_reg) 2549 return -ENOTSUPP; 2550 2551 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); 2552 if (rc < 0) 2553 return rc; 2554 2555 arg = rc; 2556 break; 2557 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2558 if (!info->ctrl->schmitt_calc_reg) 2559 return -ENOTSUPP; 2560 2561 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); 2562 if (rc < 0) 2563 return rc; 2564 2565 arg = rc; 2566 break; 2567 default: 2568 return -ENOTSUPP; 2569 break; 2570 } 2571 2572 *config = pinconf_to_config_packed(param, arg); 2573 2574 return 0; 2575} 2576 2577static const struct pinconf_ops rockchip_pinconf_ops = { 2578 .pin_config_get = rockchip_pinconf_get, 2579 .pin_config_set = rockchip_pinconf_set, 2580 .is_generic = true, 2581}; 2582 2583static const struct of_device_id rockchip_bank_match[] = { 2584 { .compatible = "rockchip,gpio-bank" }, 2585 { .compatible = "rockchip,rk3188-gpio-bank0" }, 2586 {}, 2587}; 2588 2589static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, 2590 struct device_node *np) 2591{ 2592 struct device_node *child; 2593 2594 for_each_child_of_node(np, child) { 2595 if (of_match_node(rockchip_bank_match, child)) 2596 continue; 2597 2598 info->nfunctions++; 2599 info->ngroups += of_get_child_count(child); 2600 } 2601} 2602 2603static int rockchip_pinctrl_parse_groups(struct device_node *np, 2604 struct rockchip_pin_group *grp, 2605 struct rockchip_pinctrl *info, 2606 u32 index) 2607{ 2608 struct rockchip_pin_bank *bank; 2609 int size; 2610 const __be32 *list; 2611 int num; 2612 int i, j; 2613 int ret; 2614 2615 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np); 2616 2617 /* Initialise group */ 2618 grp->name = np->name; 2619 2620 /* 2621 * the binding format is rockchip,pins = <bank pin mux CONFIG>, 2622 * do sanity check and calculate pins number 2623 */ 2624 list = of_get_property(np, "rockchip,pins", &size); 2625 /* we do not check return since it's safe node passed down */ 2626 size /= sizeof(*list); 2627 if (!size || size % 4) { 2628 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); 2629 return -EINVAL; 2630 } 2631 2632 grp->npins = size / 4; 2633 2634 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int), 2635 GFP_KERNEL); 2636 grp->data = devm_kcalloc(info->dev, 2637 grp->npins, 2638 sizeof(struct rockchip_pin_config), 2639 GFP_KERNEL); 2640 if (!grp->pins || !grp->data) 2641 return -ENOMEM; 2642 2643 for (i = 0, j = 0; i < size; i += 4, j++) { 2644 const __be32 *phandle; 2645 struct device_node *np_config; 2646 2647 num = be32_to_cpu(*list++); 2648 bank = bank_num_to_bank(info, num); 2649 if (IS_ERR(bank)) 2650 return PTR_ERR(bank); 2651 2652 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); 2653 grp->data[j].func = be32_to_cpu(*list++); 2654 2655 phandle = list++; 2656 if (!phandle) 2657 return -EINVAL; 2658 2659 np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); 2660 ret = pinconf_generic_parse_dt_config(np_config, NULL, 2661 &grp->data[j].configs, &grp->data[j].nconfigs); 2662 of_node_put(np_config); 2663 if (ret) 2664 return ret; 2665 } 2666 2667 return 0; 2668} 2669 2670static int rockchip_pinctrl_parse_functions(struct device_node *np, 2671 struct rockchip_pinctrl *info, 2672 u32 index) 2673{ 2674 struct device_node *child; 2675 struct rockchip_pmx_func *func; 2676 struct rockchip_pin_group *grp; 2677 int ret; 2678 static u32 grp_index; 2679 u32 i = 0; 2680 2681 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np); 2682 2683 func = &info->functions[index]; 2684 2685 /* Initialise function */ 2686 func->name = np->name; 2687 func->ngroups = of_get_child_count(np); 2688 if (func->ngroups <= 0) 2689 return 0; 2690 2691 func->groups = devm_kcalloc(info->dev, 2692 func->ngroups, sizeof(char *), GFP_KERNEL); 2693 if (!func->groups) 2694 return -ENOMEM; 2695 2696 for_each_child_of_node(np, child) { 2697 func->groups[i] = child->name; 2698 grp = &info->groups[grp_index++]; 2699 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); 2700 if (ret) { 2701 of_node_put(child); 2702 return ret; 2703 } 2704 } 2705 2706 return 0; 2707} 2708 2709static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, 2710 struct rockchip_pinctrl *info) 2711{ 2712 struct device *dev = &pdev->dev; 2713 struct device_node *np = dev->of_node; 2714 struct device_node *child; 2715 int ret; 2716 int i; 2717 2718 rockchip_pinctrl_child_count(info, np); 2719 2720 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 2721 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 2722 2723 info->functions = devm_kcalloc(dev, 2724 info->nfunctions, 2725 sizeof(struct rockchip_pmx_func), 2726 GFP_KERNEL); 2727 if (!info->functions) 2728 return -ENOMEM; 2729 2730 info->groups = devm_kcalloc(dev, 2731 info->ngroups, 2732 sizeof(struct rockchip_pin_group), 2733 GFP_KERNEL); 2734 if (!info->groups) 2735 return -ENOMEM; 2736 2737 i = 0; 2738 2739 for_each_child_of_node(np, child) { 2740 if (of_match_node(rockchip_bank_match, child)) 2741 continue; 2742 2743 ret = rockchip_pinctrl_parse_functions(child, info, i++); 2744 if (ret) { 2745 dev_err(&pdev->dev, "failed to parse function\n"); 2746 of_node_put(child); 2747 return ret; 2748 } 2749 } 2750 2751 return 0; 2752} 2753 2754static int rockchip_pinctrl_register(struct platform_device *pdev, 2755 struct rockchip_pinctrl *info) 2756{ 2757 struct pinctrl_desc *ctrldesc = &info->pctl; 2758 struct pinctrl_pin_desc *pindesc, *pdesc; 2759 struct rockchip_pin_bank *pin_bank; 2760 int pin, bank, ret; 2761 int k; 2762 2763 ctrldesc->name = "rockchip-pinctrl"; 2764 ctrldesc->owner = THIS_MODULE; 2765 ctrldesc->pctlops = &rockchip_pctrl_ops; 2766 ctrldesc->pmxops = &rockchip_pmx_ops; 2767 ctrldesc->confops = &rockchip_pinconf_ops; 2768 2769 pindesc = devm_kcalloc(&pdev->dev, 2770 info->ctrl->nr_pins, sizeof(*pindesc), 2771 GFP_KERNEL); 2772 if (!pindesc) 2773 return -ENOMEM; 2774 2775 ctrldesc->pins = pindesc; 2776 ctrldesc->npins = info->ctrl->nr_pins; 2777 2778 pdesc = pindesc; 2779 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { 2780 pin_bank = &info->ctrl->pin_banks[bank]; 2781 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { 2782 pdesc->number = k; 2783 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", 2784 pin_bank->name, pin); 2785 pdesc++; 2786 } 2787 } 2788 2789 ret = rockchip_pinctrl_parse_dt(pdev, info); 2790 if (ret) 2791 return ret; 2792 2793 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info); 2794 if (IS_ERR(info->pctl_dev)) { 2795 dev_err(&pdev->dev, "could not register pinctrl driver\n"); 2796 return PTR_ERR(info->pctl_dev); 2797 } 2798 2799 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { 2800 pin_bank = &info->ctrl->pin_banks[bank]; 2801 pin_bank->grange.name = pin_bank->name; 2802 pin_bank->grange.id = bank; 2803 pin_bank->grange.pin_base = pin_bank->pin_base; 2804 pin_bank->grange.base = pin_bank->gpio_chip.base; 2805 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; 2806 pin_bank->grange.gc = &pin_bank->gpio_chip; 2807 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); 2808 } 2809 2810 return 0; 2811} 2812 2813/* 2814 * GPIO handling 2815 */ 2816 2817static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 2818{ 2819 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 2820 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; 2821 unsigned long flags; 2822 u32 data; 2823 2824 clk_enable(bank->clk); 2825 raw_spin_lock_irqsave(&bank->slock, flags); 2826 2827 data = readl(reg); 2828 data &= ~BIT(offset); 2829 if (value) 2830 data |= BIT(offset); 2831 writel(data, reg); 2832 2833 raw_spin_unlock_irqrestore(&bank->slock, flags); 2834 clk_disable(bank->clk); 2835} 2836 2837/* 2838 * Returns the level of the pin for input direction and setting of the DR 2839 * register for output gpios. 2840 */ 2841static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) 2842{ 2843 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 2844 u32 data; 2845 2846 clk_enable(bank->clk); 2847 data = readl(bank->reg_base + GPIO_EXT_PORT); 2848 clk_disable(bank->clk); 2849 data >>= offset; 2850 data &= 1; 2851 return data; 2852} 2853 2854/* 2855 * gpiolib gpio_direction_input callback function. The setting of the pin 2856 * mux function as 'gpio input' will be handled by the pinctrl subsystem 2857 * interface. 2858 */ 2859static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 2860{ 2861 return pinctrl_gpio_direction_input(gc->base + offset); 2862} 2863 2864/* 2865 * gpiolib gpio_direction_output callback function. The setting of the pin 2866 * mux function as 'gpio output' will be handled by the pinctrl subsystem 2867 * interface. 2868 */ 2869static int rockchip_gpio_direction_output(struct gpio_chip *gc, 2870 unsigned offset, int value) 2871{ 2872 rockchip_gpio_set(gc, offset, value); 2873 return pinctrl_gpio_direction_output(gc->base + offset); 2874} 2875 2876static void rockchip_gpio_set_debounce(struct gpio_chip *gc, 2877 unsigned int offset, bool enable) 2878{ 2879 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 2880 void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE; 2881 unsigned long flags; 2882 u32 data; 2883 2884 clk_enable(bank->clk); 2885 raw_spin_lock_irqsave(&bank->slock, flags); 2886 2887 data = readl(reg); 2888 if (enable) 2889 data |= BIT(offset); 2890 else 2891 data &= ~BIT(offset); 2892 writel(data, reg); 2893 2894 raw_spin_unlock_irqrestore(&bank->slock, flags); 2895 clk_disable(bank->clk); 2896} 2897 2898/* 2899 * gpiolib set_config callback function. The setting of the pin 2900 * mux function as 'gpio output' will be handled by the pinctrl subsystem 2901 * interface. 2902 */ 2903static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset, 2904 unsigned long config) 2905{ 2906 enum pin_config_param param = pinconf_to_config_param(config); 2907 2908 switch (param) { 2909 case PIN_CONFIG_INPUT_DEBOUNCE: 2910 rockchip_gpio_set_debounce(gc, offset, true); 2911 /* 2912 * Rockchip's gpio could only support up to one period 2913 * of the debounce clock(pclk), which is far away from 2914 * satisftying the requirement, as pclk is usually near 2915 * 100MHz shared by all peripherals. So the fact is it 2916 * has crippled debounce capability could only be useful 2917 * to prevent any spurious glitches from waking up the system 2918 * if the gpio is conguired as wakeup interrupt source. Let's 2919 * still return -ENOTSUPP as before, to make sure the caller 2920 * of gpiod_set_debounce won't change its behaviour. 2921 */ 2922 return -ENOTSUPP; 2923 default: 2924 return -ENOTSUPP; 2925 } 2926} 2927 2928/* 2929 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin 2930 * and a virtual IRQ, if not already present. 2931 */ 2932static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 2933{ 2934 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 2935 unsigned int virq; 2936 2937 if (!bank->domain) 2938 return -ENXIO; 2939 2940 clk_enable(bank->clk); 2941 virq = irq_create_mapping(bank->domain, offset); 2942 clk_disable(bank->clk); 2943 2944 return (virq) ? : -ENXIO; 2945} 2946 2947static const struct gpio_chip rockchip_gpiolib_chip = { 2948 .request = gpiochip_generic_request, 2949 .free = gpiochip_generic_free, 2950 .set = rockchip_gpio_set, 2951 .get = rockchip_gpio_get, 2952 .get_direction = rockchip_gpio_get_direction, 2953 .direction_input = rockchip_gpio_direction_input, 2954 .direction_output = rockchip_gpio_direction_output, 2955 .set_config = rockchip_gpio_set_config, 2956 .to_irq = rockchip_gpio_to_irq, 2957 .owner = THIS_MODULE, 2958}; 2959 2960/* 2961 * Interrupt handling 2962 */ 2963 2964static void rockchip_irq_demux(struct irq_desc *desc) 2965{ 2966 struct irq_chip *chip = irq_desc_get_chip(desc); 2967 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); 2968 u32 pend; 2969 2970 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); 2971 2972 chained_irq_enter(chip, desc); 2973 2974 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); 2975 2976 while (pend) { 2977 unsigned int irq, virq; 2978 2979 irq = __ffs(pend); 2980 pend &= ~BIT(irq); 2981 virq = irq_find_mapping(bank->domain, irq); 2982 2983 if (!virq) { 2984 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); 2985 continue; 2986 } 2987 2988 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); 2989 2990 /* 2991 * Triggering IRQ on both rising and falling edge 2992 * needs manual intervention. 2993 */ 2994 if (bank->toggle_edge_mode & BIT(irq)) { 2995 u32 data, data_old, polarity; 2996 unsigned long flags; 2997 2998 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); 2999 do { 3000 raw_spin_lock_irqsave(&bank->slock, flags); 3001 3002 polarity = readl_relaxed(bank->reg_base + 3003 GPIO_INT_POLARITY); 3004 if (data & BIT(irq)) 3005 polarity &= ~BIT(irq); 3006 else 3007 polarity |= BIT(irq); 3008 writel(polarity, 3009 bank->reg_base + GPIO_INT_POLARITY); 3010 3011 raw_spin_unlock_irqrestore(&bank->slock, flags); 3012 3013 data_old = data; 3014 data = readl_relaxed(bank->reg_base + 3015 GPIO_EXT_PORT); 3016 } while ((data & BIT(irq)) != (data_old & BIT(irq))); 3017 } 3018 3019 generic_handle_irq(virq); 3020 } 3021 3022 chained_irq_exit(chip, desc); 3023} 3024 3025static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) 3026{ 3027 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 3028 struct rockchip_pin_bank *bank = gc->private; 3029 u32 mask = BIT(d->hwirq); 3030 u32 polarity; 3031 u32 level; 3032 u32 data; 3033 unsigned long flags; 3034 int ret; 3035 3036 /* make sure the pin is configured as gpio input */ 3037 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); 3038 if (ret < 0) 3039 return ret; 3040 3041 clk_enable(bank->clk); 3042 raw_spin_lock_irqsave(&bank->slock, flags); 3043 3044 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 3045 data &= ~mask; 3046 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 3047 3048 raw_spin_unlock_irqrestore(&bank->slock, flags); 3049 3050 if (type & IRQ_TYPE_EDGE_BOTH) 3051 irq_set_handler_locked(d, handle_edge_irq); 3052 else 3053 irq_set_handler_locked(d, handle_level_irq); 3054 3055 raw_spin_lock_irqsave(&bank->slock, flags); 3056 irq_gc_lock(gc); 3057 3058 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); 3059 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); 3060 3061 switch (type) { 3062 case IRQ_TYPE_EDGE_BOTH: 3063 bank->toggle_edge_mode |= mask; 3064 level |= mask; 3065 3066 /* 3067 * Determine gpio state. If 1 next interrupt should be falling 3068 * otherwise rising. 3069 */ 3070 data = readl(bank->reg_base + GPIO_EXT_PORT); 3071 if (data & mask) 3072 polarity &= ~mask; 3073 else 3074 polarity |= mask; 3075 break; 3076 case IRQ_TYPE_EDGE_RISING: 3077 bank->toggle_edge_mode &= ~mask; 3078 level |= mask; 3079 polarity |= mask; 3080 break; 3081 case IRQ_TYPE_EDGE_FALLING: 3082 bank->toggle_edge_mode &= ~mask; 3083 level |= mask; 3084 polarity &= ~mask; 3085 break; 3086 case IRQ_TYPE_LEVEL_HIGH: 3087 bank->toggle_edge_mode &= ~mask; 3088 level &= ~mask; 3089 polarity |= mask; 3090 break; 3091 case IRQ_TYPE_LEVEL_LOW: 3092 bank->toggle_edge_mode &= ~mask; 3093 level &= ~mask; 3094 polarity &= ~mask; 3095 break; 3096 default: 3097 irq_gc_unlock(gc); 3098 raw_spin_unlock_irqrestore(&bank->slock, flags); 3099 clk_disable(bank->clk); 3100 return -EINVAL; 3101 } 3102 3103 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); 3104 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); 3105 3106 irq_gc_unlock(gc); 3107 raw_spin_unlock_irqrestore(&bank->slock, flags); 3108 clk_disable(bank->clk); 3109 3110 return 0; 3111} 3112 3113static void rockchip_irq_suspend(struct irq_data *d) 3114{ 3115 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 3116 struct rockchip_pin_bank *bank = gc->private; 3117 3118 clk_enable(bank->clk); 3119 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); 3120 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK); 3121 clk_disable(bank->clk); 3122} 3123 3124static void rockchip_irq_resume(struct irq_data *d) 3125{ 3126 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 3127 struct rockchip_pin_bank *bank = gc->private; 3128 3129 clk_enable(bank->clk); 3130 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); 3131 clk_disable(bank->clk); 3132} 3133 3134static void rockchip_irq_enable(struct irq_data *d) 3135{ 3136 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 3137 struct rockchip_pin_bank *bank = gc->private; 3138 3139 clk_enable(bank->clk); 3140 irq_gc_mask_clr_bit(d); 3141} 3142 3143static void rockchip_irq_disable(struct irq_data *d) 3144{ 3145 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 3146 struct rockchip_pin_bank *bank = gc->private; 3147 3148 irq_gc_mask_set_bit(d); 3149 clk_disable(bank->clk); 3150} 3151 3152static int rockchip_interrupts_register(struct platform_device *pdev, 3153 struct rockchip_pinctrl *info) 3154{ 3155 struct rockchip_pin_ctrl *ctrl = info->ctrl; 3156 struct rockchip_pin_bank *bank = ctrl->pin_banks; 3157 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 3158 struct irq_chip_generic *gc; 3159 int ret; 3160 int i; 3161 3162 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3163 if (!bank->valid) { 3164 dev_warn(&pdev->dev, "bank %s is not valid\n", 3165 bank->name); 3166 continue; 3167 } 3168 3169 ret = clk_enable(bank->clk); 3170 if (ret) { 3171 dev_err(&pdev->dev, "failed to enable clock for bank %s\n", 3172 bank->name); 3173 continue; 3174 } 3175 3176 bank->domain = irq_domain_add_linear(bank->of_node, 32, 3177 &irq_generic_chip_ops, NULL); 3178 if (!bank->domain) { 3179 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", 3180 bank->name); 3181 clk_disable(bank->clk); 3182 continue; 3183 } 3184 3185 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, 3186 "rockchip_gpio_irq", handle_level_irq, 3187 clr, 0, 0); 3188 if (ret) { 3189 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", 3190 bank->name); 3191 irq_domain_remove(bank->domain); 3192 clk_disable(bank->clk); 3193 continue; 3194 } 3195 3196 gc = irq_get_domain_generic_chip(bank->domain, 0); 3197 gc->reg_base = bank->reg_base; 3198 gc->private = bank; 3199 gc->chip_types[0].regs.mask = GPIO_INTMASK; 3200 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; 3201 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; 3202 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; 3203 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; 3204 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable; 3205 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable; 3206 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; 3207 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; 3208 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; 3209 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; 3210 gc->wake_enabled = IRQ_MSK(bank->nr_pins); 3211 3212 /* 3213 * Linux assumes that all interrupts start out disabled/masked. 3214 * Our driver only uses the concept of masked and always keeps 3215 * things enabled, so for us that's all masked and all enabled. 3216 */ 3217 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); 3218 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); 3219 gc->mask_cache = 0xffffffff; 3220 3221 irq_set_chained_handler_and_data(bank->irq, 3222 rockchip_irq_demux, bank); 3223 clk_disable(bank->clk); 3224 } 3225 3226 return 0; 3227} 3228 3229static int rockchip_gpiolib_register(struct platform_device *pdev, 3230 struct rockchip_pinctrl *info) 3231{ 3232 struct rockchip_pin_ctrl *ctrl = info->ctrl; 3233 struct rockchip_pin_bank *bank = ctrl->pin_banks; 3234 struct gpio_chip *gc; 3235 int ret; 3236 int i; 3237 3238 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3239 if (!bank->valid) { 3240 dev_warn(&pdev->dev, "bank %s is not valid\n", 3241 bank->name); 3242 continue; 3243 } 3244 3245 bank->gpio_chip = rockchip_gpiolib_chip; 3246 3247 gc = &bank->gpio_chip; 3248 gc->base = bank->pin_base; 3249 gc->ngpio = bank->nr_pins; 3250 gc->parent = &pdev->dev; 3251 gc->of_node = bank->of_node; 3252 gc->label = bank->name; 3253 3254 ret = gpiochip_add_data(gc, bank); 3255 if (ret) { 3256 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", 3257 gc->label, ret); 3258 goto fail; 3259 } 3260 } 3261 3262 rockchip_interrupts_register(pdev, info); 3263 3264 return 0; 3265 3266fail: 3267 for (--i, --bank; i >= 0; --i, --bank) { 3268 if (!bank->valid) 3269 continue; 3270 gpiochip_remove(&bank->gpio_chip); 3271 } 3272 return ret; 3273} 3274 3275static int rockchip_gpiolib_unregister(struct platform_device *pdev, 3276 struct rockchip_pinctrl *info) 3277{ 3278 struct rockchip_pin_ctrl *ctrl = info->ctrl; 3279 struct rockchip_pin_bank *bank = ctrl->pin_banks; 3280 int i; 3281 3282 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3283 if (!bank->valid) 3284 continue; 3285 gpiochip_remove(&bank->gpio_chip); 3286 } 3287 3288 return 0; 3289} 3290 3291static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, 3292 struct rockchip_pinctrl *info) 3293{ 3294 struct resource res; 3295 void __iomem *base; 3296 3297 if (of_address_to_resource(bank->of_node, 0, &res)) { 3298 dev_err(info->dev, "cannot find IO resource for bank\n"); 3299 return -ENOENT; 3300 } 3301 3302 bank->reg_base = devm_ioremap_resource(info->dev, &res); 3303 if (IS_ERR(bank->reg_base)) 3304 return PTR_ERR(bank->reg_base); 3305 3306 /* 3307 * special case, where parts of the pull setting-registers are 3308 * part of the PMU register space 3309 */ 3310 if (of_device_is_compatible(bank->of_node, 3311 "rockchip,rk3188-gpio-bank0")) { 3312 struct device_node *node; 3313 3314 node = of_parse_phandle(bank->of_node->parent, 3315 "rockchip,pmu", 0); 3316 if (!node) { 3317 if (of_address_to_resource(bank->of_node, 1, &res)) { 3318 dev_err(info->dev, "cannot find IO resource for bank\n"); 3319 return -ENOENT; 3320 } 3321 3322 base = devm_ioremap_resource(info->dev, &res); 3323 if (IS_ERR(base)) 3324 return PTR_ERR(base); 3325 rockchip_regmap_config.max_register = 3326 resource_size(&res) - 4; 3327 rockchip_regmap_config.name = 3328 "rockchip,rk3188-gpio-bank0-pull"; 3329 bank->regmap_pull = devm_regmap_init_mmio(info->dev, 3330 base, 3331 &rockchip_regmap_config); 3332 } 3333 of_node_put(node); 3334 } 3335 3336 bank->irq = irq_of_parse_and_map(bank->of_node, 0); 3337 3338 bank->clk = of_clk_get(bank->of_node, 0); 3339 if (IS_ERR(bank->clk)) 3340 return PTR_ERR(bank->clk); 3341 3342 return clk_prepare(bank->clk); 3343} 3344 3345static const struct of_device_id rockchip_pinctrl_dt_match[]; 3346 3347/* retrieve the soc specific data */ 3348static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( 3349 struct rockchip_pinctrl *d, 3350 struct platform_device *pdev) 3351{ 3352 const struct of_device_id *match; 3353 struct device_node *node = pdev->dev.of_node; 3354 struct device_node *np; 3355 struct rockchip_pin_ctrl *ctrl; 3356 struct rockchip_pin_bank *bank; 3357 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 3358 3359 match = of_match_node(rockchip_pinctrl_dt_match, node); 3360 ctrl = (struct rockchip_pin_ctrl *)match->data; 3361 3362 for_each_child_of_node(node, np) { 3363 if (!of_find_property(np, "gpio-controller", NULL)) 3364 continue; 3365 3366 bank = ctrl->pin_banks; 3367 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3368 if (!strcmp(bank->name, np->name)) { 3369 bank->of_node = np; 3370 3371 if (!rockchip_get_bank_data(bank, d)) 3372 bank->valid = true; 3373 3374 break; 3375 } 3376 } 3377 } 3378 3379 grf_offs = ctrl->grf_mux_offset; 3380 pmu_offs = ctrl->pmu_mux_offset; 3381 drv_pmu_offs = ctrl->pmu_drv_offset; 3382 drv_grf_offs = ctrl->grf_drv_offset; 3383 bank = ctrl->pin_banks; 3384 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3385 int bank_pins = 0; 3386 3387 raw_spin_lock_init(&bank->slock); 3388 bank->drvdata = d; 3389 bank->pin_base = ctrl->nr_pins; 3390 ctrl->nr_pins += bank->nr_pins; 3391 3392 /* calculate iomux and drv offsets */ 3393 for (j = 0; j < 4; j++) { 3394 struct rockchip_iomux *iom = &bank->iomux[j]; 3395 struct rockchip_drv *drv = &bank->drv[j]; 3396 int inc; 3397 3398 if (bank_pins >= bank->nr_pins) 3399 break; 3400 3401 /* preset iomux offset value, set new start value */ 3402 if (iom->offset >= 0) { 3403 if (iom->type & IOMUX_SOURCE_PMU) 3404 pmu_offs = iom->offset; 3405 else 3406 grf_offs = iom->offset; 3407 } else { /* set current iomux offset */ 3408 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 3409 pmu_offs : grf_offs; 3410 } 3411 3412 /* preset drv offset value, set new start value */ 3413 if (drv->offset >= 0) { 3414 if (iom->type & IOMUX_SOURCE_PMU) 3415 drv_pmu_offs = drv->offset; 3416 else 3417 drv_grf_offs = drv->offset; 3418 } else { /* set current drv offset */ 3419 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 3420 drv_pmu_offs : drv_grf_offs; 3421 } 3422 3423 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 3424 i, j, iom->offset, drv->offset); 3425 3426 /* 3427 * Increase offset according to iomux width. 3428 * 4bit iomux'es are spread over two registers. 3429 */ 3430 inc = (iom->type & (IOMUX_WIDTH_4BIT | 3431 IOMUX_WIDTH_3BIT | 3432 IOMUX_WIDTH_2BIT)) ? 8 : 4; 3433 if (iom->type & IOMUX_SOURCE_PMU) 3434 pmu_offs += inc; 3435 else 3436 grf_offs += inc; 3437 3438 /* 3439 * Increase offset according to drv width. 3440 * 3bit drive-strenth'es are spread over two registers. 3441 */ 3442 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 3443 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 3444 inc = 8; 3445 else 3446 inc = 4; 3447 3448 if (iom->type & IOMUX_SOURCE_PMU) 3449 drv_pmu_offs += inc; 3450 else 3451 drv_grf_offs += inc; 3452 3453 bank_pins += 8; 3454 } 3455 3456 /* calculate the per-bank recalced_mask */ 3457 for (j = 0; j < ctrl->niomux_recalced; j++) { 3458 int pin = 0; 3459 3460 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 3461 pin = ctrl->iomux_recalced[j].pin; 3462 bank->recalced_mask |= BIT(pin); 3463 } 3464 } 3465 3466 /* calculate the per-bank route_mask */ 3467 for (j = 0; j < ctrl->niomux_routes; j++) { 3468 int pin = 0; 3469 3470 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 3471 pin = ctrl->iomux_routes[j].pin; 3472 bank->route_mask |= BIT(pin); 3473 } 3474 } 3475 } 3476 3477 return ctrl; 3478} 3479 3480#define RK3288_GRF_GPIO6C_IOMUX 0x64 3481#define GPIO6C6_SEL_WRITE_ENABLE BIT(28) 3482 3483static u32 rk3288_grf_gpio6c_iomux; 3484 3485static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev) 3486{ 3487 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 3488 int ret = pinctrl_force_sleep(info->pctl_dev); 3489 3490 if (ret) 3491 return ret; 3492 3493 /* 3494 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save 3495 * the setting here, and restore it at resume. 3496 */ 3497 if (info->ctrl->type == RK3288) { 3498 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 3499 &rk3288_grf_gpio6c_iomux); 3500 if (ret) { 3501 pinctrl_force_default(info->pctl_dev); 3502 return ret; 3503 } 3504 } 3505 3506 return 0; 3507} 3508 3509static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) 3510{ 3511 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 3512 int ret; 3513 3514 if (info->ctrl->type == RK3288) { 3515 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 3516 rk3288_grf_gpio6c_iomux | 3517 GPIO6C6_SEL_WRITE_ENABLE); 3518 if (ret) 3519 return ret; 3520 } 3521 3522 return pinctrl_force_default(info->pctl_dev); 3523} 3524 3525static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, 3526 rockchip_pinctrl_resume); 3527 3528static int rockchip_pinctrl_probe(struct platform_device *pdev) 3529{ 3530 struct rockchip_pinctrl *info; 3531 struct device *dev = &pdev->dev; 3532 struct rockchip_pin_ctrl *ctrl; 3533 struct device_node *np = pdev->dev.of_node, *node; 3534 struct resource *res; 3535 void __iomem *base; 3536 int ret; 3537 3538 if (!dev->of_node) { 3539 dev_err(dev, "device tree node not found\n"); 3540 return -ENODEV; 3541 } 3542 3543 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 3544 if (!info) 3545 return -ENOMEM; 3546 3547 info->dev = dev; 3548 3549 ctrl = rockchip_pinctrl_get_soc_data(info, pdev); 3550 if (!ctrl) { 3551 dev_err(dev, "driver data not available\n"); 3552 return -EINVAL; 3553 } 3554 info->ctrl = ctrl; 3555 3556 node = of_parse_phandle(np, "rockchip,grf", 0); 3557 if (node) { 3558 info->regmap_base = syscon_node_to_regmap(node); 3559 of_node_put(node); 3560 if (IS_ERR(info->regmap_base)) 3561 return PTR_ERR(info->regmap_base); 3562 } else { 3563 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3564 base = devm_ioremap_resource(&pdev->dev, res); 3565 if (IS_ERR(base)) 3566 return PTR_ERR(base); 3567 3568 rockchip_regmap_config.max_register = resource_size(res) - 4; 3569 rockchip_regmap_config.name = "rockchip,pinctrl"; 3570 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, 3571 &rockchip_regmap_config); 3572 3573 /* to check for the old dt-bindings */ 3574 info->reg_size = resource_size(res); 3575 3576 /* Honor the old binding, with pull registers as 2nd resource */ 3577 if (ctrl->type == RK3188 && info->reg_size < 0x200) { 3578 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 3579 base = devm_ioremap_resource(&pdev->dev, res); 3580 if (IS_ERR(base)) 3581 return PTR_ERR(base); 3582 3583 rockchip_regmap_config.max_register = 3584 resource_size(res) - 4; 3585 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; 3586 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, 3587 base, 3588 &rockchip_regmap_config); 3589 } 3590 } 3591 3592 /* try to find the optional reference to the pmu syscon */ 3593 node = of_parse_phandle(np, "rockchip,pmu", 0); 3594 if (node) { 3595 info->regmap_pmu = syscon_node_to_regmap(node); 3596 of_node_put(node); 3597 if (IS_ERR(info->regmap_pmu)) 3598 return PTR_ERR(info->regmap_pmu); 3599 } 3600 3601 ret = rockchip_gpiolib_register(pdev, info); 3602 if (ret) 3603 return ret; 3604 3605 ret = rockchip_pinctrl_register(pdev, info); 3606 if (ret) { 3607 rockchip_gpiolib_unregister(pdev, info); 3608 return ret; 3609 } 3610 3611 platform_set_drvdata(pdev, info); 3612 3613 return 0; 3614} 3615 3616static struct rockchip_pin_bank px30_pin_banks[] = { 3617 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3618 IOMUX_SOURCE_PMU, 3619 IOMUX_SOURCE_PMU, 3620 IOMUX_SOURCE_PMU 3621 ), 3622 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 3623 IOMUX_WIDTH_4BIT, 3624 IOMUX_WIDTH_4BIT, 3625 IOMUX_WIDTH_4BIT 3626 ), 3627 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 3628 IOMUX_WIDTH_4BIT, 3629 IOMUX_WIDTH_4BIT, 3630 IOMUX_WIDTH_4BIT 3631 ), 3632 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 3633 IOMUX_WIDTH_4BIT, 3634 IOMUX_WIDTH_4BIT, 3635 IOMUX_WIDTH_4BIT 3636 ), 3637}; 3638 3639static struct rockchip_pin_ctrl px30_pin_ctrl = { 3640 .pin_banks = px30_pin_banks, 3641 .nr_banks = ARRAY_SIZE(px30_pin_banks), 3642 .label = "PX30-GPIO", 3643 .type = PX30, 3644 .grf_mux_offset = 0x0, 3645 .pmu_mux_offset = 0x0, 3646 .iomux_routes = px30_mux_route_data, 3647 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 3648 .pull_calc_reg = px30_calc_pull_reg_and_bit, 3649 .drv_calc_reg = px30_calc_drv_reg_and_bit, 3650 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 3651}; 3652 3653static struct rockchip_pin_bank rv1108_pin_banks[] = { 3654 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3655 IOMUX_SOURCE_PMU, 3656 IOMUX_SOURCE_PMU, 3657 IOMUX_SOURCE_PMU), 3658 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3659 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 3660 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 3661}; 3662 3663static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 3664 .pin_banks = rv1108_pin_banks, 3665 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 3666 .label = "RV1108-GPIO", 3667 .type = RV1108, 3668 .grf_mux_offset = 0x10, 3669 .pmu_mux_offset = 0x0, 3670 .iomux_recalced = rv1108_mux_recalced_data, 3671 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 3672 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 3673 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 3674 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 3675}; 3676 3677static struct rockchip_pin_bank rk2928_pin_banks[] = { 3678 PIN_BANK(0, 32, "gpio0"), 3679 PIN_BANK(1, 32, "gpio1"), 3680 PIN_BANK(2, 32, "gpio2"), 3681 PIN_BANK(3, 32, "gpio3"), 3682}; 3683 3684static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 3685 .pin_banks = rk2928_pin_banks, 3686 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 3687 .label = "RK2928-GPIO", 3688 .type = RK2928, 3689 .grf_mux_offset = 0xa8, 3690 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3691}; 3692 3693static struct rockchip_pin_bank rk3036_pin_banks[] = { 3694 PIN_BANK(0, 32, "gpio0"), 3695 PIN_BANK(1, 32, "gpio1"), 3696 PIN_BANK(2, 32, "gpio2"), 3697}; 3698 3699static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 3700 .pin_banks = rk3036_pin_banks, 3701 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 3702 .label = "RK3036-GPIO", 3703 .type = RK2928, 3704 .grf_mux_offset = 0xa8, 3705 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3706}; 3707 3708static struct rockchip_pin_bank rk3066a_pin_banks[] = { 3709 PIN_BANK(0, 32, "gpio0"), 3710 PIN_BANK(1, 32, "gpio1"), 3711 PIN_BANK(2, 32, "gpio2"), 3712 PIN_BANK(3, 32, "gpio3"), 3713 PIN_BANK(4, 32, "gpio4"), 3714 PIN_BANK(6, 16, "gpio6"), 3715}; 3716 3717static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 3718 .pin_banks = rk3066a_pin_banks, 3719 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 3720 .label = "RK3066a-GPIO", 3721 .type = RK2928, 3722 .grf_mux_offset = 0xa8, 3723 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3724}; 3725 3726static struct rockchip_pin_bank rk3066b_pin_banks[] = { 3727 PIN_BANK(0, 32, "gpio0"), 3728 PIN_BANK(1, 32, "gpio1"), 3729 PIN_BANK(2, 32, "gpio2"), 3730 PIN_BANK(3, 32, "gpio3"), 3731}; 3732 3733static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 3734 .pin_banks = rk3066b_pin_banks, 3735 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 3736 .label = "RK3066b-GPIO", 3737 .type = RK3066B, 3738 .grf_mux_offset = 0x60, 3739}; 3740 3741static struct rockchip_pin_bank rk3128_pin_banks[] = { 3742 PIN_BANK(0, 32, "gpio0"), 3743 PIN_BANK(1, 32, "gpio1"), 3744 PIN_BANK(2, 32, "gpio2"), 3745 PIN_BANK(3, 32, "gpio3"), 3746}; 3747 3748static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 3749 .pin_banks = rk3128_pin_banks, 3750 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 3751 .label = "RK3128-GPIO", 3752 .type = RK3128, 3753 .grf_mux_offset = 0xa8, 3754 .iomux_recalced = rk3128_mux_recalced_data, 3755 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 3756 .iomux_routes = rk3128_mux_route_data, 3757 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 3758 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 3759}; 3760 3761static struct rockchip_pin_bank rk3188_pin_banks[] = { 3762 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 3763 PIN_BANK(1, 32, "gpio1"), 3764 PIN_BANK(2, 32, "gpio2"), 3765 PIN_BANK(3, 32, "gpio3"), 3766}; 3767 3768static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 3769 .pin_banks = rk3188_pin_banks, 3770 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 3771 .label = "RK3188-GPIO", 3772 .type = RK3188, 3773 .grf_mux_offset = 0x60, 3774 .iomux_routes = rk3188_mux_route_data, 3775 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data), 3776 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 3777}; 3778 3779static struct rockchip_pin_bank rk3228_pin_banks[] = { 3780 PIN_BANK(0, 32, "gpio0"), 3781 PIN_BANK(1, 32, "gpio1"), 3782 PIN_BANK(2, 32, "gpio2"), 3783 PIN_BANK(3, 32, "gpio3"), 3784}; 3785 3786static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 3787 .pin_banks = rk3228_pin_banks, 3788 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 3789 .label = "RK3228-GPIO", 3790 .type = RK3288, 3791 .grf_mux_offset = 0x0, 3792 .iomux_routes = rk3228_mux_route_data, 3793 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 3794 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3795 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3796}; 3797 3798static struct rockchip_pin_bank rk3288_pin_banks[] = { 3799 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 3800 IOMUX_SOURCE_PMU, 3801 IOMUX_SOURCE_PMU, 3802 IOMUX_UNROUTED 3803 ), 3804 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 3805 IOMUX_UNROUTED, 3806 IOMUX_UNROUTED, 3807 0 3808 ), 3809 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 3810 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 3811 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 3812 IOMUX_WIDTH_4BIT, 3813 0, 3814 0 3815 ), 3816 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 3817 0, 3818 0, 3819 IOMUX_UNROUTED 3820 ), 3821 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 3822 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 3823 0, 3824 IOMUX_WIDTH_4BIT, 3825 IOMUX_UNROUTED 3826 ), 3827 PIN_BANK(8, 16, "gpio8"), 3828}; 3829 3830static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 3831 .pin_banks = rk3288_pin_banks, 3832 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 3833 .label = "RK3288-GPIO", 3834 .type = RK3288, 3835 .grf_mux_offset = 0x0, 3836 .pmu_mux_offset = 0x84, 3837 .iomux_routes = rk3288_mux_route_data, 3838 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 3839 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 3840 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 3841}; 3842 3843static struct rockchip_pin_bank rk3308_pin_banks[] = { 3844 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT, 3845 IOMUX_WIDTH_2BIT, 3846 IOMUX_WIDTH_2BIT, 3847 IOMUX_WIDTH_2BIT), 3848 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT, 3849 IOMUX_WIDTH_2BIT, 3850 IOMUX_WIDTH_2BIT, 3851 IOMUX_WIDTH_2BIT), 3852 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT, 3853 IOMUX_WIDTH_2BIT, 3854 IOMUX_WIDTH_2BIT, 3855 IOMUX_WIDTH_2BIT), 3856 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT, 3857 IOMUX_WIDTH_2BIT, 3858 IOMUX_WIDTH_2BIT, 3859 IOMUX_WIDTH_2BIT), 3860 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT, 3861 IOMUX_WIDTH_2BIT, 3862 IOMUX_WIDTH_2BIT, 3863 IOMUX_WIDTH_2BIT), 3864}; 3865 3866static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 3867 .pin_banks = rk3308_pin_banks, 3868 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 3869 .label = "RK3308-GPIO", 3870 .type = RK3308, 3871 .grf_mux_offset = 0x0, 3872 .iomux_recalced = rk3308_mux_recalced_data, 3873 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 3874 .iomux_routes = rk3308_mux_route_data, 3875 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 3876 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 3877 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 3878 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 3879}; 3880 3881static struct rockchip_pin_bank rk3328_pin_banks[] = { 3882 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 3883 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3884 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 3885 IOMUX_WIDTH_3BIT, 3886 IOMUX_WIDTH_3BIT, 3887 0), 3888 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3889 IOMUX_WIDTH_3BIT, 3890 IOMUX_WIDTH_3BIT, 3891 0, 3892 0), 3893}; 3894 3895static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 3896 .pin_banks = rk3328_pin_banks, 3897 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 3898 .label = "RK3328-GPIO", 3899 .type = RK3288, 3900 .grf_mux_offset = 0x0, 3901 .iomux_recalced = rk3328_mux_recalced_data, 3902 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 3903 .iomux_routes = rk3328_mux_route_data, 3904 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 3905 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3906 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3907 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 3908}; 3909 3910static struct rockchip_pin_bank rk3368_pin_banks[] = { 3911 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3912 IOMUX_SOURCE_PMU, 3913 IOMUX_SOURCE_PMU, 3914 IOMUX_SOURCE_PMU 3915 ), 3916 PIN_BANK(1, 32, "gpio1"), 3917 PIN_BANK(2, 32, "gpio2"), 3918 PIN_BANK(3, 32, "gpio3"), 3919}; 3920 3921static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 3922 .pin_banks = rk3368_pin_banks, 3923 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 3924 .label = "RK3368-GPIO", 3925 .type = RK3368, 3926 .grf_mux_offset = 0x0, 3927 .pmu_mux_offset = 0x0, 3928 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 3929 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 3930}; 3931 3932static struct rockchip_pin_bank rk3399_pin_banks[] = { 3933 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 3934 IOMUX_SOURCE_PMU, 3935 IOMUX_SOURCE_PMU, 3936 IOMUX_SOURCE_PMU, 3937 IOMUX_SOURCE_PMU, 3938 DRV_TYPE_IO_1V8_ONLY, 3939 DRV_TYPE_IO_1V8_ONLY, 3940 DRV_TYPE_IO_DEFAULT, 3941 DRV_TYPE_IO_DEFAULT, 3942 0x80, 3943 0x88, 3944 -1, 3945 -1, 3946 PULL_TYPE_IO_1V8_ONLY, 3947 PULL_TYPE_IO_1V8_ONLY, 3948 PULL_TYPE_IO_DEFAULT, 3949 PULL_TYPE_IO_DEFAULT 3950 ), 3951 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 3952 IOMUX_SOURCE_PMU, 3953 IOMUX_SOURCE_PMU, 3954 IOMUX_SOURCE_PMU, 3955 DRV_TYPE_IO_1V8_OR_3V0, 3956 DRV_TYPE_IO_1V8_OR_3V0, 3957 DRV_TYPE_IO_1V8_OR_3V0, 3958 DRV_TYPE_IO_1V8_OR_3V0, 3959 0xa0, 3960 0xa8, 3961 0xb0, 3962 0xb8 3963 ), 3964 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 3965 DRV_TYPE_IO_1V8_OR_3V0, 3966 DRV_TYPE_IO_1V8_ONLY, 3967 DRV_TYPE_IO_1V8_ONLY, 3968 PULL_TYPE_IO_DEFAULT, 3969 PULL_TYPE_IO_DEFAULT, 3970 PULL_TYPE_IO_1V8_ONLY, 3971 PULL_TYPE_IO_1V8_ONLY 3972 ), 3973 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 3974 DRV_TYPE_IO_3V3_ONLY, 3975 DRV_TYPE_IO_3V3_ONLY, 3976 DRV_TYPE_IO_1V8_OR_3V0 3977 ), 3978 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 3979 DRV_TYPE_IO_1V8_3V0_AUTO, 3980 DRV_TYPE_IO_1V8_OR_3V0, 3981 DRV_TYPE_IO_1V8_OR_3V0 3982 ), 3983}; 3984 3985static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 3986 .pin_banks = rk3399_pin_banks, 3987 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 3988 .label = "RK3399-GPIO", 3989 .type = RK3399, 3990 .grf_mux_offset = 0xe000, 3991 .pmu_mux_offset = 0x0, 3992 .grf_drv_offset = 0xe100, 3993 .pmu_drv_offset = 0x80, 3994 .iomux_routes = rk3399_mux_route_data, 3995 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 3996 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 3997 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 3998}; 3999 4000static struct rockchip_pin_bank rk3568_pin_banks[] = { 4001 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 4002 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 4003 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 4004 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT), 4005 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 4006 IOMUX_WIDTH_4BIT, 4007 IOMUX_WIDTH_4BIT, 4008 IOMUX_WIDTH_4BIT), 4009 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 4010 IOMUX_WIDTH_4BIT, 4011 IOMUX_WIDTH_4BIT, 4012 IOMUX_WIDTH_4BIT), 4013 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 4014 IOMUX_WIDTH_4BIT, 4015 IOMUX_WIDTH_4BIT, 4016 IOMUX_WIDTH_4BIT), 4017 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 4018 IOMUX_WIDTH_4BIT, 4019 IOMUX_WIDTH_4BIT, 4020 IOMUX_WIDTH_4BIT), 4021}; 4022 4023static struct rockchip_pin_ctrl rk3568_pin_ctrl = { 4024 .pin_banks = rk3568_pin_banks, 4025 .nr_banks = ARRAY_SIZE(rk3568_pin_banks), 4026 .label = "RK3568-GPIO", 4027 .type = RK3568, 4028 .grf_mux_offset = 0x0, 4029 .pmu_mux_offset = 0x0, 4030 .grf_drv_offset = 0x0200, 4031 .pmu_drv_offset = 0x0070, 4032 .iomux_routes = rk3568_mux_route_data, 4033 .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data), 4034 .pull_calc_reg = rk3568_calc_pull_reg_and_bit, 4035 .drv_calc_reg = rk3568_calc_drv_reg_and_bit, 4036 .schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit, 4037}; 4038 4039static const struct of_device_id rockchip_pinctrl_dt_match[] = { 4040 { .compatible = "rockchip,px30-pinctrl", 4041 .data = &px30_pin_ctrl }, 4042 { .compatible = "rockchip,rv1108-pinctrl", 4043 .data = &rv1108_pin_ctrl }, 4044 { .compatible = "rockchip,rk2928-pinctrl", 4045 .data = &rk2928_pin_ctrl }, 4046 { .compatible = "rockchip,rk3036-pinctrl", 4047 .data = &rk3036_pin_ctrl }, 4048 { .compatible = "rockchip,rk3066a-pinctrl", 4049 .data = &rk3066a_pin_ctrl }, 4050 { .compatible = "rockchip,rk3066b-pinctrl", 4051 .data = &rk3066b_pin_ctrl }, 4052 { .compatible = "rockchip,rk3128-pinctrl", 4053 .data = (void *)&rk3128_pin_ctrl }, 4054 { .compatible = "rockchip,rk3188-pinctrl", 4055 .data = &rk3188_pin_ctrl }, 4056 { .compatible = "rockchip,rk3228-pinctrl", 4057 .data = &rk3228_pin_ctrl }, 4058 { .compatible = "rockchip,rk3288-pinctrl", 4059 .data = &rk3288_pin_ctrl }, 4060 { .compatible = "rockchip,rk3308-pinctrl", 4061 .data = &rk3308_pin_ctrl }, 4062 { .compatible = "rockchip,rk3328-pinctrl", 4063 .data = &rk3328_pin_ctrl }, 4064 { .compatible = "rockchip,rk3368-pinctrl", 4065 .data = &rk3368_pin_ctrl }, 4066 { .compatible = "rockchip,rk3399-pinctrl", 4067 .data = &rk3399_pin_ctrl }, 4068 { .compatible = "rockchip,rk3568-pinctrl", 4069 .data = &rk3568_pin_ctrl }, 4070 {}, 4071}; 4072 4073static struct platform_driver rockchip_pinctrl_driver = { 4074 .probe = rockchip_pinctrl_probe, 4075 .driver = { 4076 .name = "rockchip-pinctrl", 4077 .pm = &rockchip_pinctrl_dev_pm_ops, 4078 .of_match_table = rockchip_pinctrl_dt_match, 4079 }, 4080}; 4081 4082static int __init rockchip_pinctrl_drv_register(void) 4083{ 4084 return platform_driver_register(&rockchip_pinctrl_driver); 4085} 4086postcore_initcall(rockchip_pinctrl_drv_register); 4087