1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Microsemi SoCs pinctrl driver 4 * 5 * Author: <alexandre.belloni@free-electrons.com> 6 * License: Dual MIT/GPL 7 * Copyright (c) 2017 Microsemi Corporation 8 */ 9 10#include <linux/gpio/driver.h> 11#include <linux/interrupt.h> 12#include <linux/io.h> 13#include <linux/of_device.h> 14#include <linux/of_irq.h> 15#include <linux/of_platform.h> 16#include <linux/pinctrl/pinctrl.h> 17#include <linux/pinctrl/pinmux.h> 18#include <linux/pinctrl/pinconf.h> 19#include <linux/pinctrl/pinconf-generic.h> 20#include <linux/platform_device.h> 21#include <linux/regmap.h> 22#include <linux/slab.h> 23 24#include "core.h" 25#include "pinconf.h" 26#include "pinmux.h" 27 28#define ocelot_clrsetbits(addr, clear, set) \ 29 writel((readl(addr) & ~(clear)) | (set), (addr)) 30 31/* PINCONFIG bits (sparx5 only) */ 32enum { 33 PINCONF_BIAS, 34 PINCONF_SCHMITT, 35 PINCONF_DRIVE_STRENGTH, 36}; 37 38#define BIAS_PD_BIT BIT(4) 39#define BIAS_PU_BIT BIT(3) 40#define BIAS_BITS (BIAS_PD_BIT|BIAS_PU_BIT) 41#define SCHMITT_BIT BIT(2) 42#define DRIVE_BITS GENMASK(1, 0) 43 44/* GPIO standard registers */ 45#define OCELOT_GPIO_OUT_SET 0x0 46#define OCELOT_GPIO_OUT_CLR 0x4 47#define OCELOT_GPIO_OUT 0x8 48#define OCELOT_GPIO_IN 0xc 49#define OCELOT_GPIO_OE 0x10 50#define OCELOT_GPIO_INTR 0x14 51#define OCELOT_GPIO_INTR_ENA 0x18 52#define OCELOT_GPIO_INTR_IDENT 0x1c 53#define OCELOT_GPIO_ALT0 0x20 54#define OCELOT_GPIO_ALT1 0x24 55#define OCELOT_GPIO_SD_MAP 0x28 56 57#define OCELOT_FUNC_PER_PIN 4 58 59enum { 60 FUNC_NONE, 61 FUNC_GPIO, 62 FUNC_IRQ0, 63 FUNC_IRQ0_IN, 64 FUNC_IRQ0_OUT, 65 FUNC_IRQ1, 66 FUNC_IRQ1_IN, 67 FUNC_IRQ1_OUT, 68 FUNC_EXT_IRQ, 69 FUNC_MIIM, 70 FUNC_PHY_LED, 71 FUNC_PCI_WAKE, 72 FUNC_MD, 73 FUNC_PTP0, 74 FUNC_PTP1, 75 FUNC_PTP2, 76 FUNC_PTP3, 77 FUNC_PWM, 78 FUNC_RECO_CLK, 79 FUNC_SFP, 80 FUNC_SG0, 81 FUNC_SG1, 82 FUNC_SG2, 83 FUNC_SI, 84 FUNC_SI2, 85 FUNC_TACHO, 86 FUNC_TWI, 87 FUNC_TWI2, 88 FUNC_TWI3, 89 FUNC_TWI_SCL_M, 90 FUNC_UART, 91 FUNC_UART2, 92 FUNC_UART3, 93 FUNC_PLL_STAT, 94 FUNC_EMMC, 95 FUNC_REF_CLK, 96 FUNC_RCVRD_CLK, 97 FUNC_MAX 98}; 99 100static const char *const ocelot_function_names[] = { 101 [FUNC_NONE] = "none", 102 [FUNC_GPIO] = "gpio", 103 [FUNC_IRQ0] = "irq0", 104 [FUNC_IRQ0_IN] = "irq0_in", 105 [FUNC_IRQ0_OUT] = "irq0_out", 106 [FUNC_IRQ1] = "irq1", 107 [FUNC_IRQ1_IN] = "irq1_in", 108 [FUNC_IRQ1_OUT] = "irq1_out", 109 [FUNC_EXT_IRQ] = "ext_irq", 110 [FUNC_MIIM] = "miim", 111 [FUNC_PHY_LED] = "phy_led", 112 [FUNC_PCI_WAKE] = "pci_wake", 113 [FUNC_MD] = "md", 114 [FUNC_PTP0] = "ptp0", 115 [FUNC_PTP1] = "ptp1", 116 [FUNC_PTP2] = "ptp2", 117 [FUNC_PTP3] = "ptp3", 118 [FUNC_PWM] = "pwm", 119 [FUNC_RECO_CLK] = "reco_clk", 120 [FUNC_SFP] = "sfp", 121 [FUNC_SG0] = "sg0", 122 [FUNC_SG1] = "sg1", 123 [FUNC_SG2] = "sg2", 124 [FUNC_SI] = "si", 125 [FUNC_SI2] = "si2", 126 [FUNC_TACHO] = "tacho", 127 [FUNC_TWI] = "twi", 128 [FUNC_TWI2] = "twi2", 129 [FUNC_TWI3] = "twi3", 130 [FUNC_TWI_SCL_M] = "twi_scl_m", 131 [FUNC_UART] = "uart", 132 [FUNC_UART2] = "uart2", 133 [FUNC_UART3] = "uart3", 134 [FUNC_PLL_STAT] = "pll_stat", 135 [FUNC_EMMC] = "emmc", 136 [FUNC_REF_CLK] = "ref_clk", 137 [FUNC_RCVRD_CLK] = "rcvrd_clk", 138}; 139 140struct ocelot_pmx_func { 141 const char **groups; 142 unsigned int ngroups; 143}; 144 145struct ocelot_pin_caps { 146 unsigned int pin; 147 unsigned char functions[OCELOT_FUNC_PER_PIN]; 148}; 149 150struct ocelot_pinctrl { 151 struct device *dev; 152 struct pinctrl_dev *pctl; 153 struct gpio_chip gpio_chip; 154 struct regmap *map; 155 void __iomem *pincfg; 156 struct pinctrl_desc *desc; 157 struct ocelot_pmx_func func[FUNC_MAX]; 158 u8 stride; 159}; 160 161#define OCELOT_P(p, f0, f1, f2) \ 162static struct ocelot_pin_caps ocelot_pin_##p = { \ 163 .pin = p, \ 164 .functions = { \ 165 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 166 }, \ 167} 168 169OCELOT_P(0, SG0, NONE, NONE); 170OCELOT_P(1, SG0, NONE, NONE); 171OCELOT_P(2, SG0, NONE, NONE); 172OCELOT_P(3, SG0, NONE, NONE); 173OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 174OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE); 175OCELOT_P(6, UART, TWI_SCL_M, NONE); 176OCELOT_P(7, UART, TWI_SCL_M, NONE); 177OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT); 178OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT); 179OCELOT_P(10, PTP2, TWI_SCL_M, SFP); 180OCELOT_P(11, PTP3, TWI_SCL_M, SFP); 181OCELOT_P(12, UART2, TWI_SCL_M, SFP); 182OCELOT_P(13, UART2, TWI_SCL_M, SFP); 183OCELOT_P(14, MIIM, TWI_SCL_M, SFP); 184OCELOT_P(15, MIIM, TWI_SCL_M, SFP); 185OCELOT_P(16, TWI, NONE, SI); 186OCELOT_P(17, TWI, TWI_SCL_M, SI); 187OCELOT_P(18, PTP0, TWI_SCL_M, NONE); 188OCELOT_P(19, PTP1, TWI_SCL_M, NONE); 189OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M); 190OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M); 191 192#define OCELOT_PIN(n) { \ 193 .number = n, \ 194 .name = "GPIO_"#n, \ 195 .drv_data = &ocelot_pin_##n \ 196} 197 198static const struct pinctrl_pin_desc ocelot_pins[] = { 199 OCELOT_PIN(0), 200 OCELOT_PIN(1), 201 OCELOT_PIN(2), 202 OCELOT_PIN(3), 203 OCELOT_PIN(4), 204 OCELOT_PIN(5), 205 OCELOT_PIN(6), 206 OCELOT_PIN(7), 207 OCELOT_PIN(8), 208 OCELOT_PIN(9), 209 OCELOT_PIN(10), 210 OCELOT_PIN(11), 211 OCELOT_PIN(12), 212 OCELOT_PIN(13), 213 OCELOT_PIN(14), 214 OCELOT_PIN(15), 215 OCELOT_PIN(16), 216 OCELOT_PIN(17), 217 OCELOT_PIN(18), 218 OCELOT_PIN(19), 219 OCELOT_PIN(20), 220 OCELOT_PIN(21), 221}; 222 223#define JAGUAR2_P(p, f0, f1) \ 224static struct ocelot_pin_caps jaguar2_pin_##p = { \ 225 .pin = p, \ 226 .functions = { \ 227 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \ 228 }, \ 229} 230 231JAGUAR2_P(0, SG0, NONE); 232JAGUAR2_P(1, SG0, NONE); 233JAGUAR2_P(2, SG0, NONE); 234JAGUAR2_P(3, SG0, NONE); 235JAGUAR2_P(4, SG1, NONE); 236JAGUAR2_P(5, SG1, NONE); 237JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT); 238JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT); 239JAGUAR2_P(8, PTP0, NONE); 240JAGUAR2_P(9, PTP1, NONE); 241JAGUAR2_P(10, UART, NONE); 242JAGUAR2_P(11, UART, NONE); 243JAGUAR2_P(12, SG1, NONE); 244JAGUAR2_P(13, SG1, NONE); 245JAGUAR2_P(14, TWI, TWI_SCL_M); 246JAGUAR2_P(15, TWI, NONE); 247JAGUAR2_P(16, SI, TWI_SCL_M); 248JAGUAR2_P(17, SI, TWI_SCL_M); 249JAGUAR2_P(18, SI, TWI_SCL_M); 250JAGUAR2_P(19, PCI_WAKE, NONE); 251JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M); 252JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M); 253JAGUAR2_P(22, TACHO, NONE); 254JAGUAR2_P(23, PWM, NONE); 255JAGUAR2_P(24, UART2, NONE); 256JAGUAR2_P(25, UART2, SI); 257JAGUAR2_P(26, PTP2, SI); 258JAGUAR2_P(27, PTP3, SI); 259JAGUAR2_P(28, TWI2, SI); 260JAGUAR2_P(29, TWI2, SI); 261JAGUAR2_P(30, SG2, SI); 262JAGUAR2_P(31, SG2, SI); 263JAGUAR2_P(32, SG2, SI); 264JAGUAR2_P(33, SG2, SI); 265JAGUAR2_P(34, NONE, TWI_SCL_M); 266JAGUAR2_P(35, NONE, TWI_SCL_M); 267JAGUAR2_P(36, NONE, TWI_SCL_M); 268JAGUAR2_P(37, NONE, TWI_SCL_M); 269JAGUAR2_P(38, NONE, TWI_SCL_M); 270JAGUAR2_P(39, NONE, TWI_SCL_M); 271JAGUAR2_P(40, NONE, TWI_SCL_M); 272JAGUAR2_P(41, NONE, TWI_SCL_M); 273JAGUAR2_P(42, NONE, TWI_SCL_M); 274JAGUAR2_P(43, NONE, TWI_SCL_M); 275JAGUAR2_P(44, NONE, SFP); 276JAGUAR2_P(45, NONE, SFP); 277JAGUAR2_P(46, NONE, SFP); 278JAGUAR2_P(47, NONE, SFP); 279JAGUAR2_P(48, SFP, NONE); 280JAGUAR2_P(49, SFP, SI); 281JAGUAR2_P(50, SFP, SI); 282JAGUAR2_P(51, SFP, SI); 283JAGUAR2_P(52, SFP, NONE); 284JAGUAR2_P(53, SFP, NONE); 285JAGUAR2_P(54, SFP, NONE); 286JAGUAR2_P(55, SFP, NONE); 287JAGUAR2_P(56, MIIM, SFP); 288JAGUAR2_P(57, MIIM, SFP); 289JAGUAR2_P(58, MIIM, SFP); 290JAGUAR2_P(59, MIIM, SFP); 291JAGUAR2_P(60, NONE, NONE); 292JAGUAR2_P(61, NONE, NONE); 293JAGUAR2_P(62, NONE, NONE); 294JAGUAR2_P(63, NONE, NONE); 295 296#define JAGUAR2_PIN(n) { \ 297 .number = n, \ 298 .name = "GPIO_"#n, \ 299 .drv_data = &jaguar2_pin_##n \ 300} 301 302static const struct pinctrl_pin_desc jaguar2_pins[] = { 303 JAGUAR2_PIN(0), 304 JAGUAR2_PIN(1), 305 JAGUAR2_PIN(2), 306 JAGUAR2_PIN(3), 307 JAGUAR2_PIN(4), 308 JAGUAR2_PIN(5), 309 JAGUAR2_PIN(6), 310 JAGUAR2_PIN(7), 311 JAGUAR2_PIN(8), 312 JAGUAR2_PIN(9), 313 JAGUAR2_PIN(10), 314 JAGUAR2_PIN(11), 315 JAGUAR2_PIN(12), 316 JAGUAR2_PIN(13), 317 JAGUAR2_PIN(14), 318 JAGUAR2_PIN(15), 319 JAGUAR2_PIN(16), 320 JAGUAR2_PIN(17), 321 JAGUAR2_PIN(18), 322 JAGUAR2_PIN(19), 323 JAGUAR2_PIN(20), 324 JAGUAR2_PIN(21), 325 JAGUAR2_PIN(22), 326 JAGUAR2_PIN(23), 327 JAGUAR2_PIN(24), 328 JAGUAR2_PIN(25), 329 JAGUAR2_PIN(26), 330 JAGUAR2_PIN(27), 331 JAGUAR2_PIN(28), 332 JAGUAR2_PIN(29), 333 JAGUAR2_PIN(30), 334 JAGUAR2_PIN(31), 335 JAGUAR2_PIN(32), 336 JAGUAR2_PIN(33), 337 JAGUAR2_PIN(34), 338 JAGUAR2_PIN(35), 339 JAGUAR2_PIN(36), 340 JAGUAR2_PIN(37), 341 JAGUAR2_PIN(38), 342 JAGUAR2_PIN(39), 343 JAGUAR2_PIN(40), 344 JAGUAR2_PIN(41), 345 JAGUAR2_PIN(42), 346 JAGUAR2_PIN(43), 347 JAGUAR2_PIN(44), 348 JAGUAR2_PIN(45), 349 JAGUAR2_PIN(46), 350 JAGUAR2_PIN(47), 351 JAGUAR2_PIN(48), 352 JAGUAR2_PIN(49), 353 JAGUAR2_PIN(50), 354 JAGUAR2_PIN(51), 355 JAGUAR2_PIN(52), 356 JAGUAR2_PIN(53), 357 JAGUAR2_PIN(54), 358 JAGUAR2_PIN(55), 359 JAGUAR2_PIN(56), 360 JAGUAR2_PIN(57), 361 JAGUAR2_PIN(58), 362 JAGUAR2_PIN(59), 363 JAGUAR2_PIN(60), 364 JAGUAR2_PIN(61), 365 JAGUAR2_PIN(62), 366 JAGUAR2_PIN(63), 367}; 368 369#define SPARX5_P(p, f0, f1, f2) \ 370static struct ocelot_pin_caps sparx5_pin_##p = { \ 371 .pin = p, \ 372 .functions = { \ 373 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ 374 }, \ 375} 376 377SPARX5_P(0, SG0, PLL_STAT, NONE); 378SPARX5_P(1, SG0, NONE, NONE); 379SPARX5_P(2, SG0, NONE, NONE); 380SPARX5_P(3, SG0, NONE, NONE); 381SPARX5_P(4, SG1, NONE, NONE); 382SPARX5_P(5, SG1, NONE, NONE); 383SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP); 384SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP); 385SPARX5_P(8, PTP0, NONE, SFP); 386SPARX5_P(9, PTP1, SFP, TWI_SCL_M); 387SPARX5_P(10, UART, NONE, NONE); 388SPARX5_P(11, UART, NONE, NONE); 389SPARX5_P(12, SG1, NONE, NONE); 390SPARX5_P(13, SG1, NONE, NONE); 391SPARX5_P(14, TWI, TWI_SCL_M, NONE); 392SPARX5_P(15, TWI, NONE, NONE); 393SPARX5_P(16, SI, TWI_SCL_M, SFP); 394SPARX5_P(17, SI, TWI_SCL_M, SFP); 395SPARX5_P(18, SI, TWI_SCL_M, SFP); 396SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP); 397SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP); 398SPARX5_P(21, IRQ1_OUT, TACHO, SFP); 399SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M); 400SPARX5_P(23, PWM, UART3, TWI_SCL_M); 401SPARX5_P(24, PTP2, UART3, TWI_SCL_M); 402SPARX5_P(25, PTP3, SI, TWI_SCL_M); 403SPARX5_P(26, UART2, SI, TWI_SCL_M); 404SPARX5_P(27, UART2, SI, TWI_SCL_M); 405SPARX5_P(28, TWI2, SI, SFP); 406SPARX5_P(29, TWI2, SI, SFP); 407SPARX5_P(30, SG2, SI, PWM); 408SPARX5_P(31, SG2, SI, TWI_SCL_M); 409SPARX5_P(32, SG2, SI, TWI_SCL_M); 410SPARX5_P(33, SG2, SI, SFP); 411SPARX5_P(34, NONE, TWI_SCL_M, EMMC); 412SPARX5_P(35, SFP, TWI_SCL_M, EMMC); 413SPARX5_P(36, SFP, TWI_SCL_M, EMMC); 414SPARX5_P(37, SFP, NONE, EMMC); 415SPARX5_P(38, NONE, TWI_SCL_M, EMMC); 416SPARX5_P(39, SI2, TWI_SCL_M, EMMC); 417SPARX5_P(40, SI2, TWI_SCL_M, EMMC); 418SPARX5_P(41, SI2, TWI_SCL_M, EMMC); 419SPARX5_P(42, SI2, TWI_SCL_M, EMMC); 420SPARX5_P(43, SI2, TWI_SCL_M, EMMC); 421SPARX5_P(44, SI, SFP, EMMC); 422SPARX5_P(45, SI, SFP, EMMC); 423SPARX5_P(46, NONE, SFP, EMMC); 424SPARX5_P(47, NONE, SFP, EMMC); 425SPARX5_P(48, TWI3, SI, SFP); 426SPARX5_P(49, TWI3, NONE, SFP); 427SPARX5_P(50, SFP, NONE, TWI_SCL_M); 428SPARX5_P(51, SFP, SI, TWI_SCL_M); 429SPARX5_P(52, SFP, MIIM, TWI_SCL_M); 430SPARX5_P(53, SFP, MIIM, TWI_SCL_M); 431SPARX5_P(54, SFP, PTP2, TWI_SCL_M); 432SPARX5_P(55, SFP, PTP3, PCI_WAKE); 433SPARX5_P(56, MIIM, SFP, TWI_SCL_M); 434SPARX5_P(57, MIIM, SFP, TWI_SCL_M); 435SPARX5_P(58, MIIM, SFP, TWI_SCL_M); 436SPARX5_P(59, MIIM, SFP, NONE); 437SPARX5_P(60, RECO_CLK, NONE, NONE); 438SPARX5_P(61, RECO_CLK, NONE, NONE); 439SPARX5_P(62, RECO_CLK, PLL_STAT, NONE); 440SPARX5_P(63, RECO_CLK, NONE, NONE); 441 442#define SPARX5_PIN(n) { \ 443 .number = n, \ 444 .name = "GPIO_"#n, \ 445 .drv_data = &sparx5_pin_##n \ 446} 447 448static const struct pinctrl_pin_desc sparx5_pins[] = { 449 SPARX5_PIN(0), 450 SPARX5_PIN(1), 451 SPARX5_PIN(2), 452 SPARX5_PIN(3), 453 SPARX5_PIN(4), 454 SPARX5_PIN(5), 455 SPARX5_PIN(6), 456 SPARX5_PIN(7), 457 SPARX5_PIN(8), 458 SPARX5_PIN(9), 459 SPARX5_PIN(10), 460 SPARX5_PIN(11), 461 SPARX5_PIN(12), 462 SPARX5_PIN(13), 463 SPARX5_PIN(14), 464 SPARX5_PIN(15), 465 SPARX5_PIN(16), 466 SPARX5_PIN(17), 467 SPARX5_PIN(18), 468 SPARX5_PIN(19), 469 SPARX5_PIN(20), 470 SPARX5_PIN(21), 471 SPARX5_PIN(22), 472 SPARX5_PIN(23), 473 SPARX5_PIN(24), 474 SPARX5_PIN(25), 475 SPARX5_PIN(26), 476 SPARX5_PIN(27), 477 SPARX5_PIN(28), 478 SPARX5_PIN(29), 479 SPARX5_PIN(30), 480 SPARX5_PIN(31), 481 SPARX5_PIN(32), 482 SPARX5_PIN(33), 483 SPARX5_PIN(34), 484 SPARX5_PIN(35), 485 SPARX5_PIN(36), 486 SPARX5_PIN(37), 487 SPARX5_PIN(38), 488 SPARX5_PIN(39), 489 SPARX5_PIN(40), 490 SPARX5_PIN(41), 491 SPARX5_PIN(42), 492 SPARX5_PIN(43), 493 SPARX5_PIN(44), 494 SPARX5_PIN(45), 495 SPARX5_PIN(46), 496 SPARX5_PIN(47), 497 SPARX5_PIN(48), 498 SPARX5_PIN(49), 499 SPARX5_PIN(50), 500 SPARX5_PIN(51), 501 SPARX5_PIN(52), 502 SPARX5_PIN(53), 503 SPARX5_PIN(54), 504 SPARX5_PIN(55), 505 SPARX5_PIN(56), 506 SPARX5_PIN(57), 507 SPARX5_PIN(58), 508 SPARX5_PIN(59), 509 SPARX5_PIN(60), 510 SPARX5_PIN(61), 511 SPARX5_PIN(62), 512 SPARX5_PIN(63), 513}; 514 515static int ocelot_get_functions_count(struct pinctrl_dev *pctldev) 516{ 517 return ARRAY_SIZE(ocelot_function_names); 518} 519 520static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev, 521 unsigned int function) 522{ 523 return ocelot_function_names[function]; 524} 525 526static int ocelot_get_function_groups(struct pinctrl_dev *pctldev, 527 unsigned int function, 528 const char *const **groups, 529 unsigned *const num_groups) 530{ 531 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 532 533 *groups = info->func[function].groups; 534 *num_groups = info->func[function].ngroups; 535 536 return 0; 537} 538 539static int ocelot_pin_function_idx(struct ocelot_pinctrl *info, 540 unsigned int pin, unsigned int function) 541{ 542 struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data; 543 int i; 544 545 for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) { 546 if (function == p->functions[i]) 547 return i; 548 } 549 550 return -1; 551} 552 553#define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32)))) 554 555static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev, 556 unsigned int selector, unsigned int group) 557{ 558 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 559 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 560 unsigned int p = pin->pin % 32; 561 int f; 562 563 f = ocelot_pin_function_idx(info, group, selector); 564 if (f < 0) 565 return -EINVAL; 566 567 /* 568 * f is encoded on two bits. 569 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 570 * ALT[1] 571 * This is racy because both registers can't be updated at the same time 572 * but it doesn't matter much for now. 573 * Note: ALT0/ALT1 are organized specially for 64 gpio targets 574 */ 575 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 576 BIT(p), f << p); 577 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 578 BIT(p), (f >> 1) << p); 579 580 return 0; 581} 582 583#define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32))) 584 585static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev, 586 struct pinctrl_gpio_range *range, 587 unsigned int pin, bool input) 588{ 589 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 590 unsigned int p = pin % 32; 591 592 regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p), 593 input ? 0 : BIT(p)); 594 595 return 0; 596} 597 598static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev, 599 struct pinctrl_gpio_range *range, 600 unsigned int offset) 601{ 602 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 603 unsigned int p = offset % 32; 604 605 regmap_update_bits(info->map, REG_ALT(0, info, offset), 606 BIT(p), 0); 607 regmap_update_bits(info->map, REG_ALT(1, info, offset), 608 BIT(p), 0); 609 610 return 0; 611} 612 613static const struct pinmux_ops ocelot_pmx_ops = { 614 .get_functions_count = ocelot_get_functions_count, 615 .get_function_name = ocelot_get_function_name, 616 .get_function_groups = ocelot_get_function_groups, 617 .set_mux = ocelot_pinmux_set_mux, 618 .gpio_set_direction = ocelot_gpio_set_direction, 619 .gpio_request_enable = ocelot_gpio_request_enable, 620}; 621 622static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev) 623{ 624 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 625 626 return info->desc->npins; 627} 628 629static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev, 630 unsigned int group) 631{ 632 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 633 634 return info->desc->pins[group].name; 635} 636 637static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev, 638 unsigned int group, 639 const unsigned int **pins, 640 unsigned int *num_pins) 641{ 642 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 643 644 *pins = &info->desc->pins[group].number; 645 *num_pins = 1; 646 647 return 0; 648} 649 650static int ocelot_hw_get_value(struct ocelot_pinctrl *info, 651 unsigned int pin, 652 unsigned int reg, 653 int *val) 654{ 655 int ret = -EOPNOTSUPP; 656 657 if (info->pincfg) { 658 u32 regcfg = readl(info->pincfg + (pin * sizeof(u32))); 659 660 ret = 0; 661 switch (reg) { 662 case PINCONF_BIAS: 663 *val = regcfg & BIAS_BITS; 664 break; 665 666 case PINCONF_SCHMITT: 667 *val = regcfg & SCHMITT_BIT; 668 break; 669 670 case PINCONF_DRIVE_STRENGTH: 671 *val = regcfg & DRIVE_BITS; 672 break; 673 674 default: 675 ret = -EOPNOTSUPP; 676 break; 677 } 678 } 679 return ret; 680} 681 682static int ocelot_hw_set_value(struct ocelot_pinctrl *info, 683 unsigned int pin, 684 unsigned int reg, 685 int val) 686{ 687 int ret = -EOPNOTSUPP; 688 689 if (info->pincfg) { 690 void __iomem *regaddr = info->pincfg + (pin * sizeof(u32)); 691 692 ret = 0; 693 switch (reg) { 694 case PINCONF_BIAS: 695 ocelot_clrsetbits(regaddr, BIAS_BITS, val); 696 break; 697 698 case PINCONF_SCHMITT: 699 ocelot_clrsetbits(regaddr, SCHMITT_BIT, val); 700 break; 701 702 case PINCONF_DRIVE_STRENGTH: 703 if (val <= 3) 704 ocelot_clrsetbits(regaddr, DRIVE_BITS, val); 705 else 706 ret = -EINVAL; 707 break; 708 709 default: 710 ret = -EOPNOTSUPP; 711 break; 712 } 713 } 714 return ret; 715} 716 717static int ocelot_pinconf_get(struct pinctrl_dev *pctldev, 718 unsigned int pin, unsigned long *config) 719{ 720 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 721 u32 param = pinconf_to_config_param(*config); 722 int val, err; 723 724 switch (param) { 725 case PIN_CONFIG_BIAS_DISABLE: 726 case PIN_CONFIG_BIAS_PULL_UP: 727 case PIN_CONFIG_BIAS_PULL_DOWN: 728 err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val); 729 if (err) 730 return err; 731 if (param == PIN_CONFIG_BIAS_DISABLE) 732 val = (val == 0 ? true : false); 733 else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 734 val = (val & BIAS_PD_BIT ? true : false); 735 else /* PIN_CONFIG_BIAS_PULL_UP */ 736 val = (val & BIAS_PU_BIT ? true : false); 737 break; 738 739 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 740 err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val); 741 if (err) 742 return err; 743 744 val = (val & SCHMITT_BIT ? true : false); 745 break; 746 747 case PIN_CONFIG_DRIVE_STRENGTH: 748 err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH, 749 &val); 750 if (err) 751 return err; 752 break; 753 754 case PIN_CONFIG_OUTPUT: 755 err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin), 756 &val); 757 if (err) 758 return err; 759 val = !!(val & BIT(pin % 32)); 760 break; 761 762 case PIN_CONFIG_INPUT_ENABLE: 763 case PIN_CONFIG_OUTPUT_ENABLE: 764 err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin), 765 &val); 766 if (err) 767 return err; 768 val = val & BIT(pin % 32); 769 if (param == PIN_CONFIG_OUTPUT_ENABLE) 770 val = !!val; 771 else 772 val = !val; 773 break; 774 775 default: 776 return -EOPNOTSUPP; 777 } 778 779 *config = pinconf_to_config_packed(param, val); 780 781 return 0; 782} 783 784static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 785 unsigned long *configs, unsigned int num_configs) 786{ 787 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 788 u32 param, arg, p; 789 int cfg, err = 0; 790 791 for (cfg = 0; cfg < num_configs; cfg++) { 792 param = pinconf_to_config_param(configs[cfg]); 793 arg = pinconf_to_config_argument(configs[cfg]); 794 795 switch (param) { 796 case PIN_CONFIG_BIAS_DISABLE: 797 case PIN_CONFIG_BIAS_PULL_UP: 798 case PIN_CONFIG_BIAS_PULL_DOWN: 799 arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 : 800 (param == PIN_CONFIG_BIAS_PULL_UP) ? BIAS_PU_BIT : 801 BIAS_PD_BIT; 802 803 err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg); 804 if (err) 805 goto err; 806 807 break; 808 809 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 810 arg = arg ? SCHMITT_BIT : 0; 811 err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT, 812 arg); 813 if (err) 814 goto err; 815 816 break; 817 818 case PIN_CONFIG_DRIVE_STRENGTH: 819 err = ocelot_hw_set_value(info, pin, 820 PINCONF_DRIVE_STRENGTH, 821 arg); 822 if (err) 823 goto err; 824 825 break; 826 827 case PIN_CONFIG_OUTPUT_ENABLE: 828 case PIN_CONFIG_INPUT_ENABLE: 829 case PIN_CONFIG_OUTPUT: 830 p = pin % 32; 831 if (arg) 832 regmap_write(info->map, 833 REG(OCELOT_GPIO_OUT_SET, info, 834 pin), 835 BIT(p)); 836 else 837 regmap_write(info->map, 838 REG(OCELOT_GPIO_OUT_CLR, info, 839 pin), 840 BIT(p)); 841 regmap_update_bits(info->map, 842 REG(OCELOT_GPIO_OE, info, pin), 843 BIT(p), 844 param == PIN_CONFIG_INPUT_ENABLE ? 845 0 : BIT(p)); 846 break; 847 848 default: 849 err = -EOPNOTSUPP; 850 } 851 } 852err: 853 return err; 854} 855 856static const struct pinconf_ops ocelot_confops = { 857 .is_generic = true, 858 .pin_config_get = ocelot_pinconf_get, 859 .pin_config_set = ocelot_pinconf_set, 860 .pin_config_config_dbg_show = pinconf_generic_dump_config, 861}; 862 863static const struct pinctrl_ops ocelot_pctl_ops = { 864 .get_groups_count = ocelot_pctl_get_groups_count, 865 .get_group_name = ocelot_pctl_get_group_name, 866 .get_group_pins = ocelot_pctl_get_group_pins, 867 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 868 .dt_free_map = pinconf_generic_dt_free_map, 869}; 870 871static struct pinctrl_desc ocelot_desc = { 872 .name = "ocelot-pinctrl", 873 .pins = ocelot_pins, 874 .npins = ARRAY_SIZE(ocelot_pins), 875 .pctlops = &ocelot_pctl_ops, 876 .pmxops = &ocelot_pmx_ops, 877 .owner = THIS_MODULE, 878}; 879 880static struct pinctrl_desc jaguar2_desc = { 881 .name = "jaguar2-pinctrl", 882 .pins = jaguar2_pins, 883 .npins = ARRAY_SIZE(jaguar2_pins), 884 .pctlops = &ocelot_pctl_ops, 885 .pmxops = &ocelot_pmx_ops, 886 .owner = THIS_MODULE, 887}; 888 889static struct pinctrl_desc sparx5_desc = { 890 .name = "sparx5-pinctrl", 891 .pins = sparx5_pins, 892 .npins = ARRAY_SIZE(sparx5_pins), 893 .pctlops = &ocelot_pctl_ops, 894 .pmxops = &ocelot_pmx_ops, 895 .confops = &ocelot_confops, 896 .owner = THIS_MODULE, 897}; 898 899static int ocelot_create_group_func_map(struct device *dev, 900 struct ocelot_pinctrl *info) 901{ 902 int f, npins, i; 903 u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL); 904 905 if (!pins) 906 return -ENOMEM; 907 908 for (f = 0; f < FUNC_MAX; f++) { 909 for (npins = 0, i = 0; i < info->desc->npins; i++) { 910 if (ocelot_pin_function_idx(info, i, f) >= 0) 911 pins[npins++] = i; 912 } 913 914 if (!npins) 915 continue; 916 917 info->func[f].ngroups = npins; 918 info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *), 919 GFP_KERNEL); 920 if (!info->func[f].groups) { 921 kfree(pins); 922 return -ENOMEM; 923 } 924 925 for (i = 0; i < npins; i++) 926 info->func[f].groups[i] = 927 info->desc->pins[pins[i]].name; 928 } 929 930 kfree(pins); 931 932 return 0; 933} 934 935static int ocelot_pinctrl_register(struct platform_device *pdev, 936 struct ocelot_pinctrl *info) 937{ 938 int ret; 939 940 ret = ocelot_create_group_func_map(&pdev->dev, info); 941 if (ret) { 942 dev_err(&pdev->dev, "Unable to create group func map.\n"); 943 return ret; 944 } 945 946 info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info); 947 if (IS_ERR(info->pctl)) { 948 dev_err(&pdev->dev, "Failed to register pinctrl\n"); 949 return PTR_ERR(info->pctl); 950 } 951 952 return 0; 953} 954 955static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset) 956{ 957 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 958 unsigned int val; 959 960 regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val); 961 962 return !!(val & BIT(offset % 32)); 963} 964 965static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset, 966 int value) 967{ 968 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 969 970 if (value) 971 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 972 BIT(offset % 32)); 973 else 974 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 975 BIT(offset % 32)); 976} 977 978static int ocelot_gpio_get_direction(struct gpio_chip *chip, 979 unsigned int offset) 980{ 981 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 982 unsigned int val; 983 984 regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val); 985 986 if (val & BIT(offset % 32)) 987 return GPIO_LINE_DIRECTION_OUT; 988 989 return GPIO_LINE_DIRECTION_IN; 990} 991 992static int ocelot_gpio_direction_input(struct gpio_chip *chip, 993 unsigned int offset) 994{ 995 return pinctrl_gpio_direction_input(chip->base + offset); 996} 997 998static int ocelot_gpio_direction_output(struct gpio_chip *chip, 999 unsigned int offset, int value) 1000{ 1001 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1002 unsigned int pin = BIT(offset % 32); 1003 1004 if (value) 1005 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 1006 pin); 1007 else 1008 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 1009 pin); 1010 1011 return pinctrl_gpio_direction_output(chip->base + offset); 1012} 1013 1014static const struct gpio_chip ocelot_gpiolib_chip = { 1015 .request = gpiochip_generic_request, 1016 .free = gpiochip_generic_free, 1017 .set = ocelot_gpio_set, 1018 .get = ocelot_gpio_get, 1019 .get_direction = ocelot_gpio_get_direction, 1020 .direction_input = ocelot_gpio_direction_input, 1021 .direction_output = ocelot_gpio_direction_output, 1022 .owner = THIS_MODULE, 1023}; 1024 1025static void ocelot_irq_mask(struct irq_data *data) 1026{ 1027 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1028 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1029 unsigned int gpio = irqd_to_hwirq(data); 1030 1031 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1032 BIT(gpio % 32), 0); 1033} 1034 1035static void ocelot_irq_unmask(struct irq_data *data) 1036{ 1037 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1038 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1039 unsigned int gpio = irqd_to_hwirq(data); 1040 1041 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 1042 BIT(gpio % 32), BIT(gpio % 32)); 1043} 1044 1045static void ocelot_irq_ack(struct irq_data *data) 1046{ 1047 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 1048 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1049 unsigned int gpio = irqd_to_hwirq(data); 1050 1051 regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio), 1052 BIT(gpio % 32), BIT(gpio % 32)); 1053} 1054 1055static int ocelot_irq_set_type(struct irq_data *data, unsigned int type); 1056 1057static struct irq_chip ocelot_eoi_irqchip = { 1058 .name = "gpio", 1059 .irq_mask = ocelot_irq_mask, 1060 .irq_eoi = ocelot_irq_ack, 1061 .irq_unmask = ocelot_irq_unmask, 1062 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED, 1063 .irq_set_type = ocelot_irq_set_type, 1064}; 1065 1066static struct irq_chip ocelot_irqchip = { 1067 .name = "gpio", 1068 .irq_mask = ocelot_irq_mask, 1069 .irq_ack = ocelot_irq_ack, 1070 .irq_unmask = ocelot_irq_unmask, 1071 .irq_set_type = ocelot_irq_set_type, 1072}; 1073 1074static int ocelot_irq_set_type(struct irq_data *data, unsigned int type) 1075{ 1076 type &= IRQ_TYPE_SENSE_MASK; 1077 1078 if (!(type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_HIGH))) 1079 return -EINVAL; 1080 1081 if (type & IRQ_TYPE_LEVEL_HIGH) 1082 irq_set_chip_handler_name_locked(data, &ocelot_eoi_irqchip, 1083 handle_fasteoi_irq, NULL); 1084 if (type & IRQ_TYPE_EDGE_BOTH) 1085 irq_set_chip_handler_name_locked(data, &ocelot_irqchip, 1086 handle_edge_irq, NULL); 1087 1088 return 0; 1089} 1090 1091static void ocelot_irq_handler(struct irq_desc *desc) 1092{ 1093 struct irq_chip *parent_chip = irq_desc_get_chip(desc); 1094 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 1095 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1096 unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride; 1097 unsigned int reg = 0, irq, i; 1098 unsigned long irqs; 1099 1100 for (i = 0; i < info->stride; i++) { 1101 regmap_read(info->map, id_reg + 4 * i, ®); 1102 if (!reg) 1103 continue; 1104 1105 chained_irq_enter(parent_chip, desc); 1106 1107 irqs = reg; 1108 1109 for_each_set_bit(irq, &irqs, 1110 min(32U, info->desc->npins - 32 * i)) 1111 generic_handle_irq(irq_linear_revmap(chip->irq.domain, 1112 irq + 32 * i)); 1113 1114 chained_irq_exit(parent_chip, desc); 1115 } 1116} 1117 1118static int ocelot_gpiochip_register(struct platform_device *pdev, 1119 struct ocelot_pinctrl *info) 1120{ 1121 struct gpio_chip *gc; 1122 struct gpio_irq_chip *girq; 1123 int irq; 1124 1125 info->gpio_chip = ocelot_gpiolib_chip; 1126 1127 gc = &info->gpio_chip; 1128 gc->ngpio = info->desc->npins; 1129 gc->parent = &pdev->dev; 1130 gc->base = 0; 1131 gc->of_node = info->dev->of_node; 1132 gc->label = "ocelot-gpio"; 1133 1134 irq = irq_of_parse_and_map(gc->of_node, 0); 1135 if (irq) { 1136 girq = &gc->irq; 1137 girq->chip = &ocelot_irqchip; 1138 girq->parent_handler = ocelot_irq_handler; 1139 girq->num_parents = 1; 1140 girq->parents = devm_kcalloc(&pdev->dev, 1, 1141 sizeof(*girq->parents), 1142 GFP_KERNEL); 1143 if (!girq->parents) 1144 return -ENOMEM; 1145 girq->parents[0] = irq; 1146 girq->default_type = IRQ_TYPE_NONE; 1147 girq->handler = handle_edge_irq; 1148 } 1149 1150 return devm_gpiochip_add_data(&pdev->dev, gc, info); 1151} 1152 1153static const struct of_device_id ocelot_pinctrl_of_match[] = { 1154 { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc }, 1155 { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc }, 1156 { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, 1157 {}, 1158}; 1159 1160static int ocelot_pinctrl_probe(struct platform_device *pdev) 1161{ 1162 struct device *dev = &pdev->dev; 1163 struct ocelot_pinctrl *info; 1164 void __iomem *base; 1165 struct resource *res; 1166 int ret; 1167 struct regmap_config regmap_config = { 1168 .reg_bits = 32, 1169 .val_bits = 32, 1170 .reg_stride = 4, 1171 }; 1172 1173 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 1174 if (!info) 1175 return -ENOMEM; 1176 1177 info->desc = (struct pinctrl_desc *)device_get_match_data(dev); 1178 1179 base = devm_ioremap_resource(dev, 1180 platform_get_resource(pdev, IORESOURCE_MEM, 0)); 1181 if (IS_ERR(base)) { 1182 dev_err(dev, "Failed to ioremap registers\n"); 1183 return PTR_ERR(base); 1184 } 1185 1186 info->stride = 1 + (info->desc->npins - 1) / 32; 1187 1188 regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4; 1189 1190 info->map = devm_regmap_init_mmio(dev, base, ®map_config); 1191 if (IS_ERR(info->map)) { 1192 dev_err(dev, "Failed to create regmap\n"); 1193 return PTR_ERR(info->map); 1194 } 1195 dev_set_drvdata(dev, info->map); 1196 info->dev = dev; 1197 1198 /* Pinconf registers */ 1199 if (info->desc->confops) { 1200 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1201 base = devm_ioremap_resource(dev, res); 1202 if (IS_ERR(base)) 1203 dev_dbg(dev, "Failed to ioremap config registers (no extended pinconf)\n"); 1204 else 1205 info->pincfg = base; 1206 } 1207 1208 ret = ocelot_pinctrl_register(pdev, info); 1209 if (ret) 1210 return ret; 1211 1212 ret = ocelot_gpiochip_register(pdev, info); 1213 if (ret) 1214 return ret; 1215 1216 dev_info(dev, "driver registered\n"); 1217 1218 return 0; 1219} 1220 1221static struct platform_driver ocelot_pinctrl_driver = { 1222 .driver = { 1223 .name = "pinctrl-ocelot", 1224 .of_match_table = of_match_ptr(ocelot_pinctrl_of_match), 1225 .suppress_bind_attrs = true, 1226 }, 1227 .probe = ocelot_pinctrl_probe, 1228}; 1229builtin_platform_driver(ocelot_pinctrl_driver); 1230