1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * U300 GPIO module. 4 * 5 * Copyright (C) 2007-2012 ST-Ericsson AB 6 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0) 7 * Author: Linus Walleij <linus.walleij@linaro.org> 8 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> 9 */ 10#include <linux/module.h> 11#include <linux/interrupt.h> 12#include <linux/delay.h> 13#include <linux/errno.h> 14#include <linux/io.h> 15#include <linux/clk.h> 16#include <linux/err.h> 17#include <linux/platform_device.h> 18#include <linux/gpio/driver.h> 19#include <linux/slab.h> 20#include <linux/pinctrl/consumer.h> 21#include <linux/pinctrl/pinconf-generic.h> 22#include "pinctrl-coh901.h" 23 24#define U300_GPIO_PORT_STRIDE (0x30) 25/* 26 * Control Register 32bit (R/W) 27 * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores 28 * gives the number of GPIO pins. 29 * bit 8-2 (mask 0x000001FC) contains the core version ID. 30 */ 31#define U300_GPIO_CR (0x00) 32#define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL) 33#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL) 34#define U300_GPIO_PXPDIR (0x04) 35#define U300_GPIO_PXPDOR (0x08) 36#define U300_GPIO_PXPCR (0x0C) 37#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL) 38#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL) 39#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL) 40#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL) 41#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL) 42#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL) 43#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL) 44#define U300_GPIO_PXPER (0x10) 45#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL) 46#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL) 47#define U300_GPIO_PXIEV (0x14) 48#define U300_GPIO_PXIEN (0x18) 49#define U300_GPIO_PXIFR (0x1C) 50#define U300_GPIO_PXICR (0x20) 51#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL) 52#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL) 53#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL) 54#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL) 55 56/* 8 bits per port, no version has more than 7 ports */ 57#define U300_GPIO_NUM_PORTS 7 58#define U300_GPIO_PINS_PER_PORT 8 59#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS) 60 61struct u300_gpio_port { 62 struct u300_gpio *gpio; 63 char name[8]; 64 int irq; 65 int number; 66 u8 toggle_edge_mode; 67}; 68 69struct u300_gpio { 70 struct gpio_chip chip; 71 struct u300_gpio_port ports[U300_GPIO_NUM_PORTS]; 72 struct clk *clk; 73 void __iomem *base; 74 struct device *dev; 75 u32 stride; 76 /* Register offsets */ 77 u32 pcr; 78 u32 dor; 79 u32 dir; 80 u32 per; 81 u32 icr; 82 u32 ien; 83 u32 iev; 84}; 85 86/* 87 * Macro to expand to read a specific register found in the "gpio" 88 * struct. It requires the struct u300_gpio *gpio variable to exist in 89 * its context. It calculates the port offset from the given pin 90 * offset, muliplies by the port stride and adds the register offset 91 * so it provides a pointer to the desired register. 92 */ 93#define U300_PIN_REG(pin, reg) \ 94 (gpio->base + (pin >> 3) * gpio->stride + gpio->reg) 95 96/* 97 * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO 98 * register. 99 */ 100#define U300_PIN_BIT(pin) \ 101 (1 << (pin & 0x07)) 102 103struct u300_gpio_confdata { 104 u16 bias_mode; 105 bool output; 106 int outval; 107}; 108 109#define U300_FLOATING_INPUT { \ 110 .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \ 111 .output = false, \ 112} 113 114#define U300_PULL_UP_INPUT { \ 115 .bias_mode = PIN_CONFIG_BIAS_PULL_UP, \ 116 .output = false, \ 117} 118 119#define U300_OUTPUT_LOW { \ 120 .output = true, \ 121 .outval = 0, \ 122} 123 124#define U300_OUTPUT_HIGH { \ 125 .output = true, \ 126 .outval = 1, \ 127} 128 129/* Initial configuration */ 130static const struct u300_gpio_confdata __initconst 131bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { 132 /* Port 0, pins 0-7 */ 133 { 134 U300_FLOATING_INPUT, 135 U300_OUTPUT_HIGH, 136 U300_FLOATING_INPUT, 137 U300_OUTPUT_LOW, 138 U300_OUTPUT_LOW, 139 U300_OUTPUT_LOW, 140 U300_OUTPUT_LOW, 141 U300_OUTPUT_LOW, 142 }, 143 /* Port 1, pins 0-7 */ 144 { 145 U300_OUTPUT_LOW, 146 U300_OUTPUT_LOW, 147 U300_OUTPUT_LOW, 148 U300_PULL_UP_INPUT, 149 U300_FLOATING_INPUT, 150 U300_OUTPUT_HIGH, 151 U300_OUTPUT_LOW, 152 U300_OUTPUT_LOW, 153 }, 154 /* Port 2, pins 0-7 */ 155 { 156 U300_FLOATING_INPUT, 157 U300_FLOATING_INPUT, 158 U300_FLOATING_INPUT, 159 U300_FLOATING_INPUT, 160 U300_OUTPUT_LOW, 161 U300_PULL_UP_INPUT, 162 U300_OUTPUT_LOW, 163 U300_PULL_UP_INPUT, 164 }, 165 /* Port 3, pins 0-7 */ 166 { 167 U300_PULL_UP_INPUT, 168 U300_OUTPUT_LOW, 169 U300_FLOATING_INPUT, 170 U300_FLOATING_INPUT, 171 U300_FLOATING_INPUT, 172 U300_FLOATING_INPUT, 173 U300_FLOATING_INPUT, 174 U300_FLOATING_INPUT, 175 }, 176 /* Port 4, pins 0-7 */ 177 { 178 U300_FLOATING_INPUT, 179 U300_FLOATING_INPUT, 180 U300_FLOATING_INPUT, 181 U300_FLOATING_INPUT, 182 U300_FLOATING_INPUT, 183 U300_FLOATING_INPUT, 184 U300_FLOATING_INPUT, 185 U300_FLOATING_INPUT, 186 }, 187 /* Port 5, pins 0-7 */ 188 { 189 U300_FLOATING_INPUT, 190 U300_FLOATING_INPUT, 191 U300_FLOATING_INPUT, 192 U300_FLOATING_INPUT, 193 U300_FLOATING_INPUT, 194 U300_FLOATING_INPUT, 195 U300_FLOATING_INPUT, 196 U300_FLOATING_INPUT, 197 }, 198 /* Port 6, pind 0-7 */ 199 { 200 U300_FLOATING_INPUT, 201 U300_FLOATING_INPUT, 202 U300_FLOATING_INPUT, 203 U300_FLOATING_INPUT, 204 U300_FLOATING_INPUT, 205 U300_FLOATING_INPUT, 206 U300_FLOATING_INPUT, 207 U300_FLOATING_INPUT, 208 } 209}; 210 211static int u300_gpio_get(struct gpio_chip *chip, unsigned offset) 212{ 213 struct u300_gpio *gpio = gpiochip_get_data(chip); 214 215 return !!(readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset)); 216} 217 218static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 219{ 220 struct u300_gpio *gpio = gpiochip_get_data(chip); 221 unsigned long flags; 222 u32 val; 223 224 local_irq_save(flags); 225 226 val = readl(U300_PIN_REG(offset, dor)); 227 if (value) 228 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); 229 else 230 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); 231 232 local_irq_restore(flags); 233} 234 235static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 236{ 237 struct u300_gpio *gpio = gpiochip_get_data(chip); 238 unsigned long flags; 239 u32 val; 240 241 local_irq_save(flags); 242 val = readl(U300_PIN_REG(offset, pcr)); 243 /* Mask out this pin, note 2 bits per setting */ 244 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); 245 writel(val, U300_PIN_REG(offset, pcr)); 246 local_irq_restore(flags); 247 return 0; 248} 249 250static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 251 int value) 252{ 253 struct u300_gpio *gpio = gpiochip_get_data(chip); 254 unsigned long flags; 255 u32 oldmode; 256 u32 val; 257 258 local_irq_save(flags); 259 val = readl(U300_PIN_REG(offset, pcr)); 260 /* 261 * Drive mode must be set by the special mode set function, set 262 * push/pull mode by default if no mode has been selected. 263 */ 264 oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK << 265 ((offset & 0x07) << 1)); 266 /* mode = 0 means input, else some mode is already set */ 267 if (oldmode == 0) { 268 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << 269 ((offset & 0x07) << 1)); 270 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL 271 << ((offset & 0x07) << 1)); 272 writel(val, U300_PIN_REG(offset, pcr)); 273 } 274 u300_gpio_set(chip, offset, value); 275 local_irq_restore(flags); 276 return 0; 277} 278 279/* Returning -EINVAL means "supported but not available" */ 280int u300_gpio_config_get(struct gpio_chip *chip, 281 unsigned offset, 282 unsigned long *config) 283{ 284 struct u300_gpio *gpio = gpiochip_get_data(chip); 285 enum pin_config_param param = (enum pin_config_param) *config; 286 bool biasmode; 287 u32 drmode; 288 289 /* One bit per pin, clamp to bool range */ 290 biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset)); 291 292 /* Mask out the two bits for this pin and shift to bits 0,1 */ 293 drmode = readl(U300_PIN_REG(offset, pcr)); 294 drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); 295 drmode >>= ((offset & 0x07) << 1); 296 297 switch (param) { 298 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 299 *config = 0; 300 if (biasmode) 301 return 0; 302 else 303 return -EINVAL; 304 break; 305 case PIN_CONFIG_BIAS_PULL_UP: 306 *config = 0; 307 if (!biasmode) 308 return 0; 309 else 310 return -EINVAL; 311 break; 312 case PIN_CONFIG_DRIVE_PUSH_PULL: 313 *config = 0; 314 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL) 315 return 0; 316 else 317 return -EINVAL; 318 break; 319 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 320 *config = 0; 321 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN) 322 return 0; 323 else 324 return -EINVAL; 325 break; 326 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 327 *config = 0; 328 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE) 329 return 0; 330 else 331 return -EINVAL; 332 break; 333 default: 334 break; 335 } 336 return -ENOTSUPP; 337} 338 339int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset, 340 enum pin_config_param param) 341{ 342 struct u300_gpio *gpio = gpiochip_get_data(chip); 343 unsigned long flags; 344 u32 val; 345 346 local_irq_save(flags); 347 switch (param) { 348 case PIN_CONFIG_BIAS_DISABLE: 349 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 350 val = readl(U300_PIN_REG(offset, per)); 351 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); 352 break; 353 case PIN_CONFIG_BIAS_PULL_UP: 354 val = readl(U300_PIN_REG(offset, per)); 355 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); 356 break; 357 case PIN_CONFIG_DRIVE_PUSH_PULL: 358 val = readl(U300_PIN_REG(offset, pcr)); 359 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK 360 << ((offset & 0x07) << 1)); 361 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL 362 << ((offset & 0x07) << 1)); 363 writel(val, U300_PIN_REG(offset, pcr)); 364 break; 365 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 366 val = readl(U300_PIN_REG(offset, pcr)); 367 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK 368 << ((offset & 0x07) << 1)); 369 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN 370 << ((offset & 0x07) << 1)); 371 writel(val, U300_PIN_REG(offset, pcr)); 372 break; 373 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 374 val = readl(U300_PIN_REG(offset, pcr)); 375 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK 376 << ((offset & 0x07) << 1)); 377 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE 378 << ((offset & 0x07) << 1)); 379 writel(val, U300_PIN_REG(offset, pcr)); 380 break; 381 default: 382 local_irq_restore(flags); 383 dev_err(gpio->dev, "illegal configuration requested\n"); 384 return -EINVAL; 385 } 386 local_irq_restore(flags); 387 return 0; 388} 389 390static const struct gpio_chip u300_gpio_chip = { 391 .label = "u300-gpio-chip", 392 .owner = THIS_MODULE, 393 .request = gpiochip_generic_request, 394 .free = gpiochip_generic_free, 395 .get = u300_gpio_get, 396 .set = u300_gpio_set, 397 .direction_input = u300_gpio_direction_input, 398 .direction_output = u300_gpio_direction_output, 399}; 400 401static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset) 402{ 403 u32 val; 404 405 val = readl(U300_PIN_REG(offset, icr)); 406 /* Set mode depending on state */ 407 if (u300_gpio_get(&gpio->chip, offset)) { 408 /* High now, let's trigger on falling edge next then */ 409 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); 410 dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n", 411 offset); 412 } else { 413 /* Low now, let's trigger on rising edge next then */ 414 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); 415 dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n", 416 offset); 417 } 418} 419 420static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger) 421{ 422 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 423 struct u300_gpio *gpio = gpiochip_get_data(chip); 424 struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3]; 425 int offset = d->hwirq; 426 u32 val; 427 428 if ((trigger & IRQF_TRIGGER_RISING) && 429 (trigger & IRQF_TRIGGER_FALLING)) { 430 /* 431 * The GPIO block can only trigger on falling OR rising edges, 432 * not both. So we need to toggle the mode whenever the pin 433 * goes from one state to the other with a special state flag 434 */ 435 dev_dbg(gpio->dev, 436 "trigger on both rising and falling edge on pin %d\n", 437 offset); 438 port->toggle_edge_mode |= U300_PIN_BIT(offset); 439 u300_toggle_trigger(gpio, offset); 440 } else if (trigger & IRQF_TRIGGER_RISING) { 441 dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n", 442 offset); 443 val = readl(U300_PIN_REG(offset, icr)); 444 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); 445 port->toggle_edge_mode &= ~U300_PIN_BIT(offset); 446 } else if (trigger & IRQF_TRIGGER_FALLING) { 447 dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n", 448 offset); 449 val = readl(U300_PIN_REG(offset, icr)); 450 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); 451 port->toggle_edge_mode &= ~U300_PIN_BIT(offset); 452 } 453 454 return 0; 455} 456 457static void u300_gpio_irq_enable(struct irq_data *d) 458{ 459 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 460 struct u300_gpio *gpio = gpiochip_get_data(chip); 461 struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3]; 462 int offset = d->hwirq; 463 u32 val; 464 unsigned long flags; 465 466 dev_dbg(gpio->dev, "enable IRQ for hwirq %lu on port %s, offset %d\n", 467 d->hwirq, port->name, offset); 468 local_irq_save(flags); 469 val = readl(U300_PIN_REG(offset, ien)); 470 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); 471 local_irq_restore(flags); 472} 473 474static void u300_gpio_irq_disable(struct irq_data *d) 475{ 476 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 477 struct u300_gpio *gpio = gpiochip_get_data(chip); 478 int offset = d->hwirq; 479 u32 val; 480 unsigned long flags; 481 482 local_irq_save(flags); 483 val = readl(U300_PIN_REG(offset, ien)); 484 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); 485 local_irq_restore(flags); 486} 487 488static struct irq_chip u300_gpio_irqchip = { 489 .name = "u300-gpio-irqchip", 490 .irq_enable = u300_gpio_irq_enable, 491 .irq_disable = u300_gpio_irq_disable, 492 .irq_set_type = u300_gpio_irq_type, 493}; 494 495static void u300_gpio_irq_handler(struct irq_desc *desc) 496{ 497 unsigned int irq = irq_desc_get_irq(desc); 498 struct irq_chip *parent_chip = irq_desc_get_chip(desc); 499 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 500 struct u300_gpio *gpio = gpiochip_get_data(chip); 501 struct u300_gpio_port *port = &gpio->ports[irq - chip->base]; 502 int pinoffset = port->number << 3; /* get the right stride */ 503 unsigned long val; 504 505 chained_irq_enter(parent_chip, desc); 506 507 /* Read event register */ 508 val = readl(U300_PIN_REG(pinoffset, iev)); 509 /* Mask relevant bits */ 510 val &= 0xFFU; /* 8 bits per port */ 511 /* ACK IRQ (clear event) */ 512 writel(val, U300_PIN_REG(pinoffset, iev)); 513 514 /* Call IRQ handler */ 515 if (val != 0) { 516 int irqoffset; 517 518 for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) { 519 int offset = pinoffset + irqoffset; 520 int pin_irq = irq_find_mapping(chip->irq.domain, offset); 521 522 dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n", 523 pin_irq, offset); 524 generic_handle_irq(pin_irq); 525 /* 526 * Triggering IRQ on both rising and falling edge 527 * needs mockery 528 */ 529 if (port->toggle_edge_mode & U300_PIN_BIT(offset)) 530 u300_toggle_trigger(gpio, offset); 531 } 532 } 533 534 chained_irq_exit(parent_chip, desc); 535} 536 537static void __init u300_gpio_init_pin(struct u300_gpio *gpio, 538 int offset, 539 const struct u300_gpio_confdata *conf) 540{ 541 /* Set mode: input or output */ 542 if (conf->output) { 543 u300_gpio_direction_output(&gpio->chip, offset, conf->outval); 544 545 /* Deactivate bias mode for output */ 546 u300_gpio_config_set(&gpio->chip, offset, 547 PIN_CONFIG_BIAS_HIGH_IMPEDANCE); 548 549 /* Set drive mode for output */ 550 u300_gpio_config_set(&gpio->chip, offset, 551 PIN_CONFIG_DRIVE_PUSH_PULL); 552 553 dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n", 554 offset, conf->outval); 555 } else { 556 u300_gpio_direction_input(&gpio->chip, offset); 557 558 /* Always set output low on input pins */ 559 u300_gpio_set(&gpio->chip, offset, 0); 560 561 /* Set bias mode for input */ 562 u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode); 563 564 dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n", 565 offset, conf->bias_mode); 566 } 567} 568 569static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio) 570{ 571 int i, j; 572 573 /* Write default config and values to all pins */ 574 for (i = 0; i < U300_GPIO_NUM_PORTS; i++) { 575 for (j = 0; j < 8; j++) { 576 const struct u300_gpio_confdata *conf; 577 int offset = (i*8) + j; 578 579 conf = &bs335_gpio_config[i][j]; 580 u300_gpio_init_pin(gpio, offset, conf); 581 } 582 } 583} 584 585/* 586 * Here we map a GPIO in the local gpio_chip pin space to a pin in 587 * the local pinctrl pin space. The pin controller used is 588 * pinctrl-u300. 589 */ 590struct coh901_pinpair { 591 unsigned int offset; 592 unsigned int pin_base; 593}; 594 595#define COH901_PINRANGE(a, b) { .offset = a, .pin_base = b } 596 597static struct coh901_pinpair coh901_pintable[] = { 598 COH901_PINRANGE(10, 426), 599 COH901_PINRANGE(11, 180), 600 COH901_PINRANGE(12, 165), /* MS/MMC card insertion */ 601 COH901_PINRANGE(13, 179), 602 COH901_PINRANGE(14, 178), 603 COH901_PINRANGE(16, 194), 604 COH901_PINRANGE(17, 193), 605 COH901_PINRANGE(18, 192), 606 COH901_PINRANGE(19, 191), 607 COH901_PINRANGE(20, 186), 608 COH901_PINRANGE(21, 185), 609 COH901_PINRANGE(22, 184), 610 COH901_PINRANGE(23, 183), 611 COH901_PINRANGE(24, 182), 612 COH901_PINRANGE(25, 181), 613}; 614 615static int __init u300_gpio_probe(struct platform_device *pdev) 616{ 617 struct u300_gpio *gpio; 618 struct gpio_irq_chip *girq; 619 int err = 0; 620 int portno; 621 u32 val; 622 u32 ifr; 623 int i; 624 625 gpio = devm_kzalloc(&pdev->dev, sizeof(struct u300_gpio), GFP_KERNEL); 626 if (gpio == NULL) 627 return -ENOMEM; 628 629 gpio->chip = u300_gpio_chip; 630 gpio->chip.ngpio = U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT; 631 gpio->chip.parent = &pdev->dev; 632 gpio->chip.base = 0; 633 gpio->dev = &pdev->dev; 634 635 gpio->base = devm_platform_ioremap_resource(pdev, 0); 636 if (IS_ERR(gpio->base)) 637 return PTR_ERR(gpio->base); 638 639 gpio->clk = devm_clk_get(gpio->dev, NULL); 640 if (IS_ERR(gpio->clk)) { 641 err = PTR_ERR(gpio->clk); 642 dev_err(gpio->dev, "could not get GPIO clock\n"); 643 return err; 644 } 645 646 err = clk_prepare_enable(gpio->clk); 647 if (err) { 648 dev_err(gpio->dev, "could not enable GPIO clock\n"); 649 return err; 650 } 651 652 dev_info(gpio->dev, 653 "initializing GPIO Controller COH 901 571/3\n"); 654 gpio->stride = U300_GPIO_PORT_STRIDE; 655 gpio->pcr = U300_GPIO_PXPCR; 656 gpio->dor = U300_GPIO_PXPDOR; 657 gpio->dir = U300_GPIO_PXPDIR; 658 gpio->per = U300_GPIO_PXPER; 659 gpio->icr = U300_GPIO_PXICR; 660 gpio->ien = U300_GPIO_PXIEN; 661 gpio->iev = U300_GPIO_PXIEV; 662 ifr = U300_GPIO_PXIFR; 663 664 val = readl(gpio->base + U300_GPIO_CR); 665 dev_info(gpio->dev, "COH901571/3 block version: %d, " \ 666 "number of cores: %d totalling %d pins\n", 667 ((val & 0x000001FC) >> 2), 668 ((val & 0x0000FE00) >> 9), 669 ((val & 0x0000FE00) >> 9) * 8); 670 writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, 671 gpio->base + U300_GPIO_CR); 672 u300_gpio_init_coh901571(gpio); 673 674 girq = &gpio->chip.irq; 675 girq->chip = &u300_gpio_irqchip; 676 girq->parent_handler = u300_gpio_irq_handler; 677 girq->num_parents = U300_GPIO_NUM_PORTS; 678 girq->parents = devm_kcalloc(gpio->dev, U300_GPIO_NUM_PORTS, 679 sizeof(*girq->parents), 680 GFP_KERNEL); 681 if (!girq->parents) { 682 err = -ENOMEM; 683 goto err_dis_clk; 684 } 685 for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) { 686 struct u300_gpio_port *port = &gpio->ports[portno]; 687 688 snprintf(port->name, 8, "gpio%d", portno); 689 port->number = portno; 690 port->gpio = gpio; 691 692 port->irq = platform_get_irq(pdev, portno); 693 girq->parents[portno] = port->irq; 694 695 /* Turns off irq force (test register) for this port */ 696 writel(0x0, gpio->base + portno * gpio->stride + ifr); 697 } 698 girq->default_type = IRQ_TYPE_EDGE_FALLING; 699 girq->handler = handle_simple_irq; 700#ifdef CONFIG_OF_GPIO 701 gpio->chip.of_node = pdev->dev.of_node; 702#endif 703 err = gpiochip_add_data(&gpio->chip, gpio); 704 if (err) { 705 dev_err(gpio->dev, "unable to add gpiochip: %d\n", err); 706 goto err_dis_clk; 707 } 708 709 /* 710 * Add pinctrl pin ranges, the pin controller must be registered 711 * at this point 712 */ 713 for (i = 0; i < ARRAY_SIZE(coh901_pintable); i++) { 714 struct coh901_pinpair *p = &coh901_pintable[i]; 715 716 err = gpiochip_add_pin_range(&gpio->chip, "pinctrl-u300", 717 p->offset, p->pin_base, 1); 718 if (err) 719 goto err_no_range; 720 } 721 722 platform_set_drvdata(pdev, gpio); 723 724 return 0; 725 726err_no_range: 727 gpiochip_remove(&gpio->chip); 728err_dis_clk: 729 clk_disable_unprepare(gpio->clk); 730 dev_err(&pdev->dev, "module ERROR:%d\n", err); 731 return err; 732} 733 734static int __exit u300_gpio_remove(struct platform_device *pdev) 735{ 736 struct u300_gpio *gpio = platform_get_drvdata(pdev); 737 738 /* Turn off the GPIO block */ 739 writel(0x00000000U, gpio->base + U300_GPIO_CR); 740 741 gpiochip_remove(&gpio->chip); 742 clk_disable_unprepare(gpio->clk); 743 return 0; 744} 745 746static const struct of_device_id u300_gpio_match[] = { 747 { .compatible = "stericsson,gpio-coh901" }, 748 {}, 749}; 750 751static struct platform_driver u300_gpio_driver = { 752 .driver = { 753 .name = "u300-gpio", 754 .of_match_table = u300_gpio_match, 755 }, 756 .remove = __exit_p(u300_gpio_remove), 757}; 758 759static int __init u300_gpio_init(void) 760{ 761 return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe); 762} 763 764static void __exit u300_gpio_exit(void) 765{ 766 platform_driver_unregister(&u300_gpio_driver); 767} 768 769arch_initcall(u300_gpio_init); 770module_exit(u300_gpio_exit); 771 772MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 773MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver"); 774MODULE_LICENSE("GPL"); 775