1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * at91 pinctrl driver based on at91 pinmux core 4 * 5 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 6 */ 7 8#include <linux/clk.h> 9#include <linux/err.h> 10#include <linux/init.h> 11#include <linux/of.h> 12#include <linux/of_device.h> 13#include <linux/of_address.h> 14#include <linux/of_irq.h> 15#include <linux/slab.h> 16#include <linux/interrupt.h> 17#include <linux/io.h> 18#include <linux/gpio/driver.h> 19#include <linux/pinctrl/machine.h> 20#include <linux/pinctrl/pinconf.h> 21#include <linux/pinctrl/pinctrl.h> 22#include <linux/pinctrl/pinmux.h> 23/* Since we request GPIOs from ourself */ 24#include <linux/pinctrl/consumer.h> 25 26#include "pinctrl-at91.h" 27#include "core.h" 28 29#define MAX_GPIO_BANKS 5 30#define MAX_NB_GPIO_PER_BANK 32 31 32struct at91_pinctrl_mux_ops; 33 34struct at91_gpio_chip { 35 struct gpio_chip chip; 36 struct pinctrl_gpio_range range; 37 struct at91_gpio_chip *next; /* Bank sharing same clock */ 38 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */ 39 int pioc_virq; /* PIO bank Linux virtual interrupt */ 40 int pioc_idx; /* PIO bank index */ 41 void __iomem *regbase; /* PIO bank virtual address */ 42 struct clk *clock; /* associated clock */ 43 struct at91_pinctrl_mux_ops *ops; /* ops */ 44}; 45 46static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS]; 47 48static int gpio_banks; 49 50#define PULL_UP (1 << 0) 51#define MULTI_DRIVE (1 << 1) 52#define DEGLITCH (1 << 2) 53#define PULL_DOWN (1 << 3) 54#define DIS_SCHMIT (1 << 4) 55#define DRIVE_STRENGTH_SHIFT 5 56#define DRIVE_STRENGTH_MASK 0x3 57#define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT) 58#define OUTPUT (1 << 7) 59#define OUTPUT_VAL_SHIFT 8 60#define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT) 61#define SLEWRATE_SHIFT 9 62#define SLEWRATE_MASK 0x1 63#define SLEWRATE (SLEWRATE_MASK << SLEWRATE_SHIFT) 64#define DEBOUNCE (1 << 16) 65#define DEBOUNCE_VAL_SHIFT 17 66#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT) 67 68/* 69 * These defines will translated the dt binding settings to our internal 70 * settings. They are not necessarily the same value as the register setting. 71 * The actual drive strength current of low, medium and high must be looked up 72 * from the corresponding device datasheet. This value is different for pins 73 * that are even in the same banks. It is also dependent on VCC. 74 * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive 75 * strength when there is no dt config for it. 76 */ 77enum drive_strength_bit { 78 DRIVE_STRENGTH_BIT_DEF, 79 DRIVE_STRENGTH_BIT_LOW, 80 DRIVE_STRENGTH_BIT_MED, 81 DRIVE_STRENGTH_BIT_HI, 82}; 83 84#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \ 85 DRIVE_STRENGTH_SHIFT) 86 87enum slewrate_bit { 88 SLEWRATE_BIT_ENA, 89 SLEWRATE_BIT_DIS, 90}; 91 92#define SLEWRATE_BIT_MSK(name) (SLEWRATE_BIT_##name << SLEWRATE_SHIFT) 93 94/** 95 * struct at91_pmx_func - describes AT91 pinmux functions 96 * @name: the name of this specific function 97 * @groups: corresponding pin groups 98 * @ngroups: the number of groups 99 */ 100struct at91_pmx_func { 101 const char *name; 102 const char **groups; 103 unsigned ngroups; 104}; 105 106enum at91_mux { 107 AT91_MUX_GPIO = 0, 108 AT91_MUX_PERIPH_A = 1, 109 AT91_MUX_PERIPH_B = 2, 110 AT91_MUX_PERIPH_C = 3, 111 AT91_MUX_PERIPH_D = 4, 112}; 113 114/** 115 * struct at91_pmx_pin - describes an At91 pin mux 116 * @bank: the bank of the pin 117 * @pin: the pin number in the @bank 118 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function. 119 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc... 120 */ 121struct at91_pmx_pin { 122 uint32_t bank; 123 uint32_t pin; 124 enum at91_mux mux; 125 unsigned long conf; 126}; 127 128/** 129 * struct at91_pin_group - describes an At91 pin group 130 * @name: the name of this specific pin group 131 * @pins_conf: the mux mode for each pin in this group. The size of this 132 * array is the same as pins. 133 * @pins: an array of discrete physical pins used in this group, taken 134 * from the driver-local pin enumeration space 135 * @npins: the number of pins in this group array, i.e. the number of 136 * elements in .pins so we can iterate over that array 137 */ 138struct at91_pin_group { 139 const char *name; 140 struct at91_pmx_pin *pins_conf; 141 unsigned int *pins; 142 unsigned npins; 143}; 144 145/** 146 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group 147 * on new IP with support for periph C and D the way to mux in 148 * periph A and B has changed 149 * So provide the right call back 150 * if not present means the IP does not support it 151 * @get_periph: return the periph mode configured 152 * @mux_A_periph: mux as periph A 153 * @mux_B_periph: mux as periph B 154 * @mux_C_periph: mux as periph C 155 * @mux_D_periph: mux as periph D 156 * @get_deglitch: get deglitch status 157 * @set_deglitch: enable/disable deglitch 158 * @get_debounce: get debounce status 159 * @set_debounce: enable/disable debounce 160 * @get_pulldown: get pulldown status 161 * @set_pulldown: enable/disable pulldown 162 * @get_schmitt_trig: get schmitt trigger status 163 * @disable_schmitt_trig: disable schmitt trigger 164 * @get_drivestrength: get driver strength 165 * @set_drivestrength: set driver strength 166 * @get_slewrate: get slew rate 167 * @set_slewrate: set slew rate 168 * @irq_type: return irq type 169 */ 170struct at91_pinctrl_mux_ops { 171 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask); 172 void (*mux_A_periph)(void __iomem *pio, unsigned mask); 173 void (*mux_B_periph)(void __iomem *pio, unsigned mask); 174 void (*mux_C_periph)(void __iomem *pio, unsigned mask); 175 void (*mux_D_periph)(void __iomem *pio, unsigned mask); 176 bool (*get_deglitch)(void __iomem *pio, unsigned pin); 177 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on); 178 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div); 179 void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div); 180 bool (*get_pulldown)(void __iomem *pio, unsigned pin); 181 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on); 182 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin); 183 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask); 184 unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin); 185 void (*set_drivestrength)(void __iomem *pio, unsigned pin, 186 u32 strength); 187 unsigned (*get_slewrate)(void __iomem *pio, unsigned pin); 188 void (*set_slewrate)(void __iomem *pio, unsigned pin, u32 slewrate); 189 /* irq */ 190 int (*irq_type)(struct irq_data *d, unsigned type); 191}; 192 193static int gpio_irq_type(struct irq_data *d, unsigned type); 194static int alt_gpio_irq_type(struct irq_data *d, unsigned type); 195 196struct at91_pinctrl { 197 struct device *dev; 198 struct pinctrl_dev *pctl; 199 200 int nactive_banks; 201 202 uint32_t *mux_mask; 203 int nmux; 204 205 struct at91_pmx_func *functions; 206 int nfunctions; 207 208 struct at91_pin_group *groups; 209 int ngroups; 210 211 struct at91_pinctrl_mux_ops *ops; 212}; 213 214static inline const struct at91_pin_group *at91_pinctrl_find_group_by_name( 215 const struct at91_pinctrl *info, 216 const char *name) 217{ 218 const struct at91_pin_group *grp = NULL; 219 int i; 220 221 for (i = 0; i < info->ngroups; i++) { 222 if (strcmp(info->groups[i].name, name)) 223 continue; 224 225 grp = &info->groups[i]; 226 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]); 227 break; 228 } 229 230 return grp; 231} 232 233static int at91_get_groups_count(struct pinctrl_dev *pctldev) 234{ 235 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 236 237 return info->ngroups; 238} 239 240static const char *at91_get_group_name(struct pinctrl_dev *pctldev, 241 unsigned selector) 242{ 243 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 244 245 return info->groups[selector].name; 246} 247 248static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 249 const unsigned **pins, 250 unsigned *npins) 251{ 252 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 253 254 if (selector >= info->ngroups) 255 return -EINVAL; 256 257 *pins = info->groups[selector].pins; 258 *npins = info->groups[selector].npins; 259 260 return 0; 261} 262 263static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 264 unsigned offset) 265{ 266 seq_printf(s, "%s", dev_name(pctldev->dev)); 267} 268 269static int at91_dt_node_to_map(struct pinctrl_dev *pctldev, 270 struct device_node *np, 271 struct pinctrl_map **map, unsigned *num_maps) 272{ 273 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 274 const struct at91_pin_group *grp; 275 struct pinctrl_map *new_map; 276 struct device_node *parent; 277 int map_num = 1; 278 int i; 279 280 /* 281 * first find the group of this node and check if we need to create 282 * config maps for pins 283 */ 284 grp = at91_pinctrl_find_group_by_name(info, np->name); 285 if (!grp) { 286 dev_err(info->dev, "unable to find group for node %pOFn\n", 287 np); 288 return -EINVAL; 289 } 290 291 map_num += grp->npins; 292 new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map), 293 GFP_KERNEL); 294 if (!new_map) 295 return -ENOMEM; 296 297 *map = new_map; 298 *num_maps = map_num; 299 300 /* create mux map */ 301 parent = of_get_parent(np); 302 if (!parent) { 303 devm_kfree(pctldev->dev, new_map); 304 return -EINVAL; 305 } 306 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 307 new_map[0].data.mux.function = parent->name; 308 new_map[0].data.mux.group = np->name; 309 of_node_put(parent); 310 311 /* create config map */ 312 new_map++; 313 for (i = 0; i < grp->npins; i++) { 314 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 315 new_map[i].data.configs.group_or_pin = 316 pin_get_name(pctldev, grp->pins[i]); 317 new_map[i].data.configs.configs = &grp->pins_conf[i].conf; 318 new_map[i].data.configs.num_configs = 1; 319 } 320 321 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 322 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 323 324 return 0; 325} 326 327static void at91_dt_free_map(struct pinctrl_dev *pctldev, 328 struct pinctrl_map *map, unsigned num_maps) 329{ 330} 331 332static const struct pinctrl_ops at91_pctrl_ops = { 333 .get_groups_count = at91_get_groups_count, 334 .get_group_name = at91_get_group_name, 335 .get_group_pins = at91_get_group_pins, 336 .pin_dbg_show = at91_pin_dbg_show, 337 .dt_node_to_map = at91_dt_node_to_map, 338 .dt_free_map = at91_dt_free_map, 339}; 340 341static void __iomem *pin_to_controller(struct at91_pinctrl *info, 342 unsigned int bank) 343{ 344 if (!gpio_chips[bank]) 345 return NULL; 346 347 return gpio_chips[bank]->regbase; 348} 349 350static inline int pin_to_bank(unsigned pin) 351{ 352 return pin /= MAX_NB_GPIO_PER_BANK; 353} 354 355static unsigned pin_to_mask(unsigned int pin) 356{ 357 return 1 << pin; 358} 359 360static unsigned two_bit_pin_value_shift_amount(unsigned int pin) 361{ 362 /* return the shift value for a pin for "two bit" per pin registers, 363 * i.e. drive strength */ 364 return 2*((pin >= MAX_NB_GPIO_PER_BANK/2) 365 ? pin - MAX_NB_GPIO_PER_BANK/2 : pin); 366} 367 368static unsigned sama5d3_get_drive_register(unsigned int pin) 369{ 370 /* drive strength is split between two registers 371 * with two bits per pin */ 372 return (pin >= MAX_NB_GPIO_PER_BANK/2) 373 ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1; 374} 375 376static unsigned at91sam9x5_get_drive_register(unsigned int pin) 377{ 378 /* drive strength is split between two registers 379 * with two bits per pin */ 380 return (pin >= MAX_NB_GPIO_PER_BANK/2) 381 ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1; 382} 383 384static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) 385{ 386 writel_relaxed(mask, pio + PIO_IDR); 387} 388 389static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin) 390{ 391 return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1); 392} 393 394static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) 395{ 396 if (on) 397 writel_relaxed(mask, pio + PIO_PPDDR); 398 399 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); 400} 401 402static bool at91_mux_get_output(void __iomem *pio, unsigned int pin, bool *val) 403{ 404 *val = (readl_relaxed(pio + PIO_ODSR) >> pin) & 0x1; 405 return (readl_relaxed(pio + PIO_OSR) >> pin) & 0x1; 406} 407 408static void at91_mux_set_output(void __iomem *pio, unsigned int mask, 409 bool is_on, bool val) 410{ 411 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); 412 writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR)); 413} 414 415static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin) 416{ 417 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1; 418} 419 420static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on) 421{ 422 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR)); 423} 424 425static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask) 426{ 427 writel_relaxed(mask, pio + PIO_ASR); 428} 429 430static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask) 431{ 432 writel_relaxed(mask, pio + PIO_BSR); 433} 434 435static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask) 436{ 437 438 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, 439 pio + PIO_ABCDSR1); 440 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, 441 pio + PIO_ABCDSR2); 442} 443 444static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask) 445{ 446 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, 447 pio + PIO_ABCDSR1); 448 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, 449 pio + PIO_ABCDSR2); 450} 451 452static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask) 453{ 454 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); 455 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); 456} 457 458static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask) 459{ 460 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); 461 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); 462} 463 464static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask) 465{ 466 unsigned select; 467 468 if (readl_relaxed(pio + PIO_PSR) & mask) 469 return AT91_MUX_GPIO; 470 471 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask); 472 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1); 473 474 return select + 1; 475} 476 477static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask) 478{ 479 unsigned select; 480 481 if (readl_relaxed(pio + PIO_PSR) & mask) 482 return AT91_MUX_GPIO; 483 484 select = readl_relaxed(pio + PIO_ABSR) & mask; 485 486 return select + 1; 487} 488 489static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin) 490{ 491 return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1; 492} 493 494static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) 495{ 496 writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); 497} 498 499static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin) 500{ 501 if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) 502 return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1); 503 504 return false; 505} 506 507static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) 508{ 509 if (is_on) 510 writel_relaxed(mask, pio + PIO_IFSCDR); 511 at91_mux_set_deglitch(pio, mask, is_on); 512} 513 514static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div) 515{ 516 *div = readl_relaxed(pio + PIO_SCDR); 517 518 return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) && 519 ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1); 520} 521 522static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, 523 bool is_on, u32 div) 524{ 525 if (is_on) { 526 writel_relaxed(mask, pio + PIO_IFSCER); 527 writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR); 528 writel_relaxed(mask, pio + PIO_IFER); 529 } else 530 writel_relaxed(mask, pio + PIO_IFSCDR); 531} 532 533static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin) 534{ 535 return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1); 536} 537 538static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) 539{ 540 if (is_on) 541 writel_relaxed(mask, pio + PIO_PUDR); 542 543 writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); 544} 545 546static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask) 547{ 548 writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); 549} 550 551static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin) 552{ 553 return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1; 554} 555 556static inline u32 read_drive_strength(void __iomem *reg, unsigned pin) 557{ 558 unsigned tmp = readl_relaxed(reg); 559 560 tmp = tmp >> two_bit_pin_value_shift_amount(pin); 561 562 return tmp & DRIVE_STRENGTH_MASK; 563} 564 565static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio, 566 unsigned pin) 567{ 568 unsigned tmp = read_drive_strength(pio + 569 sama5d3_get_drive_register(pin), pin); 570 571 /* SAMA5 strength is 1:1 with our defines, 572 * except 0 is equivalent to low per datasheet */ 573 if (!tmp) 574 tmp = DRIVE_STRENGTH_BIT_MSK(LOW); 575 576 return tmp; 577} 578 579static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio, 580 unsigned pin) 581{ 582 unsigned tmp = read_drive_strength(pio + 583 at91sam9x5_get_drive_register(pin), pin); 584 585 /* strength is inverse in SAM9x5s hardware with the pinctrl defines 586 * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */ 587 tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp; 588 589 return tmp; 590} 591 592static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio, 593 unsigned pin) 594{ 595 unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1); 596 597 if (tmp & BIT(pin)) 598 return DRIVE_STRENGTH_BIT_HI; 599 600 return DRIVE_STRENGTH_BIT_LOW; 601} 602 603static unsigned at91_mux_sam9x60_get_slewrate(void __iomem *pio, unsigned pin) 604{ 605 unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR); 606 607 if ((tmp & BIT(pin))) 608 return SLEWRATE_BIT_ENA; 609 610 return SLEWRATE_BIT_DIS; 611} 612 613static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength) 614{ 615 unsigned tmp = readl_relaxed(reg); 616 unsigned shift = two_bit_pin_value_shift_amount(pin); 617 618 tmp &= ~(DRIVE_STRENGTH_MASK << shift); 619 tmp |= strength << shift; 620 621 writel_relaxed(tmp, reg); 622} 623 624static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin, 625 u32 setting) 626{ 627 /* do nothing if setting is zero */ 628 if (!setting) 629 return; 630 631 /* strength is 1 to 1 with setting for SAMA5 */ 632 set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting); 633} 634 635static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin, 636 u32 setting) 637{ 638 /* do nothing if setting is zero */ 639 if (!setting) 640 return; 641 642 /* strength is inverse on SAM9x5s with our defines 643 * 0 = hi, 1 = med, 2 = low, 3 = rsvd */ 644 setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting; 645 646 set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin, 647 setting); 648} 649 650static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin, 651 u32 setting) 652{ 653 unsigned int tmp; 654 655 if (setting <= DRIVE_STRENGTH_BIT_DEF || 656 setting == DRIVE_STRENGTH_BIT_MED || 657 setting > DRIVE_STRENGTH_BIT_HI) 658 return; 659 660 tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1); 661 662 /* Strength is 0: low, 1: hi */ 663 if (setting == DRIVE_STRENGTH_BIT_LOW) 664 tmp &= ~BIT(pin); 665 else 666 tmp |= BIT(pin); 667 668 writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1); 669} 670 671static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin, 672 u32 setting) 673{ 674 unsigned int tmp; 675 676 if (setting < SLEWRATE_BIT_ENA || setting > SLEWRATE_BIT_DIS) 677 return; 678 679 tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR); 680 681 if (setting == SLEWRATE_BIT_DIS) 682 tmp &= ~BIT(pin); 683 else 684 tmp |= BIT(pin); 685 686 writel_relaxed(tmp, pio + SAM9X60_PIO_SLEWR); 687} 688 689static struct at91_pinctrl_mux_ops at91rm9200_ops = { 690 .get_periph = at91_mux_get_periph, 691 .mux_A_periph = at91_mux_set_A_periph, 692 .mux_B_periph = at91_mux_set_B_periph, 693 .get_deglitch = at91_mux_get_deglitch, 694 .set_deglitch = at91_mux_set_deglitch, 695 .irq_type = gpio_irq_type, 696}; 697 698static struct at91_pinctrl_mux_ops at91sam9x5_ops = { 699 .get_periph = at91_mux_pio3_get_periph, 700 .mux_A_periph = at91_mux_pio3_set_A_periph, 701 .mux_B_periph = at91_mux_pio3_set_B_periph, 702 .mux_C_periph = at91_mux_pio3_set_C_periph, 703 .mux_D_periph = at91_mux_pio3_set_D_periph, 704 .get_deglitch = at91_mux_pio3_get_deglitch, 705 .set_deglitch = at91_mux_pio3_set_deglitch, 706 .get_debounce = at91_mux_pio3_get_debounce, 707 .set_debounce = at91_mux_pio3_set_debounce, 708 .get_pulldown = at91_mux_pio3_get_pulldown, 709 .set_pulldown = at91_mux_pio3_set_pulldown, 710 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, 711 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, 712 .get_drivestrength = at91_mux_sam9x5_get_drivestrength, 713 .set_drivestrength = at91_mux_sam9x5_set_drivestrength, 714 .irq_type = alt_gpio_irq_type, 715}; 716 717static const struct at91_pinctrl_mux_ops sam9x60_ops = { 718 .get_periph = at91_mux_pio3_get_periph, 719 .mux_A_periph = at91_mux_pio3_set_A_periph, 720 .mux_B_periph = at91_mux_pio3_set_B_periph, 721 .mux_C_periph = at91_mux_pio3_set_C_periph, 722 .mux_D_periph = at91_mux_pio3_set_D_periph, 723 .get_deglitch = at91_mux_pio3_get_deglitch, 724 .set_deglitch = at91_mux_pio3_set_deglitch, 725 .get_debounce = at91_mux_pio3_get_debounce, 726 .set_debounce = at91_mux_pio3_set_debounce, 727 .get_pulldown = at91_mux_pio3_get_pulldown, 728 .set_pulldown = at91_mux_pio3_set_pulldown, 729 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, 730 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, 731 .get_drivestrength = at91_mux_sam9x60_get_drivestrength, 732 .set_drivestrength = at91_mux_sam9x60_set_drivestrength, 733 .get_slewrate = at91_mux_sam9x60_get_slewrate, 734 .set_slewrate = at91_mux_sam9x60_set_slewrate, 735 .irq_type = alt_gpio_irq_type, 736}; 737 738static struct at91_pinctrl_mux_ops sama5d3_ops = { 739 .get_periph = at91_mux_pio3_get_periph, 740 .mux_A_periph = at91_mux_pio3_set_A_periph, 741 .mux_B_periph = at91_mux_pio3_set_B_periph, 742 .mux_C_periph = at91_mux_pio3_set_C_periph, 743 .mux_D_periph = at91_mux_pio3_set_D_periph, 744 .get_deglitch = at91_mux_pio3_get_deglitch, 745 .set_deglitch = at91_mux_pio3_set_deglitch, 746 .get_debounce = at91_mux_pio3_get_debounce, 747 .set_debounce = at91_mux_pio3_set_debounce, 748 .get_pulldown = at91_mux_pio3_get_pulldown, 749 .set_pulldown = at91_mux_pio3_set_pulldown, 750 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, 751 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, 752 .get_drivestrength = at91_mux_sama5d3_get_drivestrength, 753 .set_drivestrength = at91_mux_sama5d3_set_drivestrength, 754 .irq_type = alt_gpio_irq_type, 755}; 756 757static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin) 758{ 759 if (pin->mux) { 760 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n", 761 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf); 762 } else { 763 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n", 764 pin->bank + 'A', pin->pin, pin->conf); 765 } 766} 767 768static int pin_check_config(struct at91_pinctrl *info, const char *name, 769 int index, const struct at91_pmx_pin *pin) 770{ 771 int mux; 772 773 /* check if it's a valid config */ 774 if (pin->bank >= gpio_banks) { 775 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n", 776 name, index, pin->bank, gpio_banks); 777 return -EINVAL; 778 } 779 780 if (!gpio_chips[pin->bank]) { 781 dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n", 782 name, index, pin->bank); 783 return -ENXIO; 784 } 785 786 if (pin->pin >= MAX_NB_GPIO_PER_BANK) { 787 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n", 788 name, index, pin->pin, MAX_NB_GPIO_PER_BANK); 789 return -EINVAL; 790 } 791 792 if (!pin->mux) 793 return 0; 794 795 mux = pin->mux - 1; 796 797 if (mux >= info->nmux) { 798 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n", 799 name, index, mux, info->nmux); 800 return -EINVAL; 801 } 802 803 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { 804 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n", 805 name, index, mux, pin->bank + 'A', pin->pin); 806 return -EINVAL; 807 } 808 809 return 0; 810} 811 812static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask) 813{ 814 writel_relaxed(mask, pio + PIO_PDR); 815} 816 817static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input) 818{ 819 writel_relaxed(mask, pio + PIO_PER); 820 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER)); 821} 822 823static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 824 unsigned group) 825{ 826 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 827 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; 828 const struct at91_pmx_pin *pin; 829 uint32_t npins = info->groups[group].npins; 830 int i, ret; 831 unsigned mask; 832 void __iomem *pio; 833 834 dev_dbg(info->dev, "enable function %s group %s\n", 835 info->functions[selector].name, info->groups[group].name); 836 837 /* first check that all the pins of the group are valid with a valid 838 * parameter */ 839 for (i = 0; i < npins; i++) { 840 pin = &pins_conf[i]; 841 ret = pin_check_config(info, info->groups[group].name, i, pin); 842 if (ret) 843 return ret; 844 } 845 846 for (i = 0; i < npins; i++) { 847 pin = &pins_conf[i]; 848 at91_pin_dbg(info->dev, pin); 849 pio = pin_to_controller(info, pin->bank); 850 851 if (!pio) 852 continue; 853 854 mask = pin_to_mask(pin->pin); 855 at91_mux_disable_interrupt(pio, mask); 856 switch (pin->mux) { 857 case AT91_MUX_GPIO: 858 at91_mux_gpio_enable(pio, mask, 1); 859 break; 860 case AT91_MUX_PERIPH_A: 861 info->ops->mux_A_periph(pio, mask); 862 break; 863 case AT91_MUX_PERIPH_B: 864 info->ops->mux_B_periph(pio, mask); 865 break; 866 case AT91_MUX_PERIPH_C: 867 if (!info->ops->mux_C_periph) 868 return -EINVAL; 869 info->ops->mux_C_periph(pio, mask); 870 break; 871 case AT91_MUX_PERIPH_D: 872 if (!info->ops->mux_D_periph) 873 return -EINVAL; 874 info->ops->mux_D_periph(pio, mask); 875 break; 876 } 877 if (pin->mux) 878 at91_mux_gpio_disable(pio, mask); 879 } 880 881 return 0; 882} 883 884static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 885{ 886 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 887 888 return info->nfunctions; 889} 890 891static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev, 892 unsigned selector) 893{ 894 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 895 896 return info->functions[selector].name; 897} 898 899static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, 900 const char * const **groups, 901 unsigned * const num_groups) 902{ 903 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 904 905 *groups = info->functions[selector].groups; 906 *num_groups = info->functions[selector].ngroups; 907 908 return 0; 909} 910 911static int at91_gpio_request_enable(struct pinctrl_dev *pctldev, 912 struct pinctrl_gpio_range *range, 913 unsigned offset) 914{ 915 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 916 struct at91_gpio_chip *at91_chip; 917 struct gpio_chip *chip; 918 unsigned mask; 919 920 if (!range) { 921 dev_err(npct->dev, "invalid range\n"); 922 return -EINVAL; 923 } 924 if (!range->gc) { 925 dev_err(npct->dev, "missing GPIO chip in range\n"); 926 return -EINVAL; 927 } 928 chip = range->gc; 929 at91_chip = gpiochip_get_data(chip); 930 931 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); 932 933 mask = 1 << (offset - chip->base); 934 935 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n", 936 offset, 'A' + range->id, offset - chip->base, mask); 937 938 writel_relaxed(mask, at91_chip->regbase + PIO_PER); 939 940 return 0; 941} 942 943static void at91_gpio_disable_free(struct pinctrl_dev *pctldev, 944 struct pinctrl_gpio_range *range, 945 unsigned offset) 946{ 947 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 948 949 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); 950 /* Set the pin to some default state, GPIO is usually default */ 951} 952 953static const struct pinmux_ops at91_pmx_ops = { 954 .get_functions_count = at91_pmx_get_funcs_count, 955 .get_function_name = at91_pmx_get_func_name, 956 .get_function_groups = at91_pmx_get_groups, 957 .set_mux = at91_pmx_set, 958 .gpio_request_enable = at91_gpio_request_enable, 959 .gpio_disable_free = at91_gpio_disable_free, 960}; 961 962static int at91_pinconf_get(struct pinctrl_dev *pctldev, 963 unsigned pin_id, unsigned long *config) 964{ 965 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 966 void __iomem *pio; 967 unsigned pin; 968 int div; 969 bool out; 970 971 *config = 0; 972 dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id); 973 pio = pin_to_controller(info, pin_to_bank(pin_id)); 974 975 if (!pio) 976 return -EINVAL; 977 978 pin = pin_id % MAX_NB_GPIO_PER_BANK; 979 980 if (at91_mux_get_multidrive(pio, pin)) 981 *config |= MULTI_DRIVE; 982 983 if (at91_mux_get_pullup(pio, pin)) 984 *config |= PULL_UP; 985 986 if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin)) 987 *config |= DEGLITCH; 988 if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div)) 989 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT); 990 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin)) 991 *config |= PULL_DOWN; 992 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin)) 993 *config |= DIS_SCHMIT; 994 if (info->ops->get_drivestrength) 995 *config |= (info->ops->get_drivestrength(pio, pin) 996 << DRIVE_STRENGTH_SHIFT); 997 if (info->ops->get_slewrate) 998 *config |= (info->ops->get_slewrate(pio, pin) << SLEWRATE_SHIFT); 999 if (at91_mux_get_output(pio, pin, &out)) 1000 *config |= OUTPUT | (out << OUTPUT_VAL_SHIFT); 1001 1002 return 0; 1003} 1004 1005static int at91_pinconf_set(struct pinctrl_dev *pctldev, 1006 unsigned pin_id, unsigned long *configs, 1007 unsigned num_configs) 1008{ 1009 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1010 unsigned mask; 1011 void __iomem *pio; 1012 int i; 1013 unsigned long config; 1014 unsigned pin; 1015 1016 for (i = 0; i < num_configs; i++) { 1017 config = configs[i]; 1018 1019 dev_dbg(info->dev, 1020 "%s:%d, pin_id=%d, config=0x%lx", 1021 __func__, __LINE__, pin_id, config); 1022 pio = pin_to_controller(info, pin_to_bank(pin_id)); 1023 1024 if (!pio) 1025 return -EINVAL; 1026 1027 pin = pin_id % MAX_NB_GPIO_PER_BANK; 1028 mask = pin_to_mask(pin); 1029 1030 if (config & PULL_UP && config & PULL_DOWN) 1031 return -EINVAL; 1032 1033 at91_mux_set_output(pio, mask, config & OUTPUT, 1034 (config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT); 1035 at91_mux_set_pullup(pio, mask, config & PULL_UP); 1036 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE); 1037 if (info->ops->set_deglitch) 1038 info->ops->set_deglitch(pio, mask, config & DEGLITCH); 1039 if (info->ops->set_debounce) 1040 info->ops->set_debounce(pio, mask, config & DEBOUNCE, 1041 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT); 1042 if (info->ops->set_pulldown) 1043 info->ops->set_pulldown(pio, mask, config & PULL_DOWN); 1044 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT) 1045 info->ops->disable_schmitt_trig(pio, mask); 1046 if (info->ops->set_drivestrength) 1047 info->ops->set_drivestrength(pio, pin, 1048 (config & DRIVE_STRENGTH) 1049 >> DRIVE_STRENGTH_SHIFT); 1050 if (info->ops->set_slewrate) 1051 info->ops->set_slewrate(pio, pin, 1052 (config & SLEWRATE) >> SLEWRATE_SHIFT); 1053 1054 } /* for each config */ 1055 1056 return 0; 1057} 1058 1059#define DBG_SHOW_FLAG(flag) do { \ 1060 if (config & flag) { \ 1061 if (num_conf) \ 1062 seq_puts(s, "|"); \ 1063 seq_puts(s, #flag); \ 1064 num_conf++; \ 1065 } \ 1066} while (0) 1067 1068#define DBG_SHOW_FLAG_MASKED(mask, flag, name) do { \ 1069 if ((config & mask) == flag) { \ 1070 if (num_conf) \ 1071 seq_puts(s, "|"); \ 1072 seq_puts(s, #name); \ 1073 num_conf++; \ 1074 } \ 1075} while (0) 1076 1077static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev, 1078 struct seq_file *s, unsigned pin_id) 1079{ 1080 unsigned long config; 1081 int val, num_conf = 0; 1082 1083 at91_pinconf_get(pctldev, pin_id, &config); 1084 1085 DBG_SHOW_FLAG(MULTI_DRIVE); 1086 DBG_SHOW_FLAG(PULL_UP); 1087 DBG_SHOW_FLAG(PULL_DOWN); 1088 DBG_SHOW_FLAG(DIS_SCHMIT); 1089 DBG_SHOW_FLAG(DEGLITCH); 1090 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW), 1091 DRIVE_STRENGTH_LOW); 1092 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED), 1093 DRIVE_STRENGTH_MED); 1094 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI), 1095 DRIVE_STRENGTH_HI); 1096 DBG_SHOW_FLAG(SLEWRATE); 1097 DBG_SHOW_FLAG(DEBOUNCE); 1098 if (config & DEBOUNCE) { 1099 val = config >> DEBOUNCE_VAL_SHIFT; 1100 seq_printf(s, "(%d)", val); 1101 } 1102 1103 return; 1104} 1105 1106static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 1107 struct seq_file *s, unsigned group) 1108{ 1109} 1110 1111static const struct pinconf_ops at91_pinconf_ops = { 1112 .pin_config_get = at91_pinconf_get, 1113 .pin_config_set = at91_pinconf_set, 1114 .pin_config_dbg_show = at91_pinconf_dbg_show, 1115 .pin_config_group_dbg_show = at91_pinconf_group_dbg_show, 1116}; 1117 1118static struct pinctrl_desc at91_pinctrl_desc = { 1119 .pctlops = &at91_pctrl_ops, 1120 .pmxops = &at91_pmx_ops, 1121 .confops = &at91_pinconf_ops, 1122 .owner = THIS_MODULE, 1123}; 1124 1125static const char *gpio_compat = "atmel,at91rm9200-gpio"; 1126 1127static void at91_pinctrl_child_count(struct at91_pinctrl *info, 1128 struct device_node *np) 1129{ 1130 struct device_node *child; 1131 1132 for_each_child_of_node(np, child) { 1133 if (of_device_is_compatible(child, gpio_compat)) { 1134 if (of_device_is_available(child)) 1135 info->nactive_banks++; 1136 } else { 1137 info->nfunctions++; 1138 info->ngroups += of_get_child_count(child); 1139 } 1140 } 1141} 1142 1143static int at91_pinctrl_mux_mask(struct at91_pinctrl *info, 1144 struct device_node *np) 1145{ 1146 int ret = 0; 1147 int size; 1148 const __be32 *list; 1149 1150 list = of_get_property(np, "atmel,mux-mask", &size); 1151 if (!list) { 1152 dev_err(info->dev, "can not read the mux-mask of %d\n", size); 1153 return -EINVAL; 1154 } 1155 1156 size /= sizeof(*list); 1157 if (!size || size % gpio_banks) { 1158 dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks); 1159 return -EINVAL; 1160 } 1161 info->nmux = size / gpio_banks; 1162 1163 info->mux_mask = devm_kcalloc(info->dev, size, sizeof(u32), 1164 GFP_KERNEL); 1165 if (!info->mux_mask) 1166 return -ENOMEM; 1167 1168 ret = of_property_read_u32_array(np, "atmel,mux-mask", 1169 info->mux_mask, size); 1170 if (ret) 1171 dev_err(info->dev, "can not read the mux-mask of %d\n", size); 1172 return ret; 1173} 1174 1175static int at91_pinctrl_parse_groups(struct device_node *np, 1176 struct at91_pin_group *grp, 1177 struct at91_pinctrl *info, u32 index) 1178{ 1179 struct at91_pmx_pin *pin; 1180 int size; 1181 const __be32 *list; 1182 int i, j; 1183 1184 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np); 1185 1186 /* Initialise group */ 1187 grp->name = np->name; 1188 1189 /* 1190 * the binding format is atmel,pins = <bank pin mux CONFIG ...>, 1191 * do sanity check and calculate pins number 1192 */ 1193 list = of_get_property(np, "atmel,pins", &size); 1194 /* we do not check return since it's safe node passed down */ 1195 size /= sizeof(*list); 1196 if (!size || size % 4) { 1197 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); 1198 return -EINVAL; 1199 } 1200 1201 grp->npins = size / 4; 1202 pin = grp->pins_conf = devm_kcalloc(info->dev, 1203 grp->npins, 1204 sizeof(struct at91_pmx_pin), 1205 GFP_KERNEL); 1206 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int), 1207 GFP_KERNEL); 1208 if (!grp->pins_conf || !grp->pins) 1209 return -ENOMEM; 1210 1211 for (i = 0, j = 0; i < size; i += 4, j++) { 1212 pin->bank = be32_to_cpu(*list++); 1213 pin->pin = be32_to_cpu(*list++); 1214 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin; 1215 pin->mux = be32_to_cpu(*list++); 1216 pin->conf = be32_to_cpu(*list++); 1217 1218 at91_pin_dbg(info->dev, pin); 1219 pin++; 1220 } 1221 1222 return 0; 1223} 1224 1225static int at91_pinctrl_parse_functions(struct device_node *np, 1226 struct at91_pinctrl *info, u32 index) 1227{ 1228 struct device_node *child; 1229 struct at91_pmx_func *func; 1230 struct at91_pin_group *grp; 1231 int ret; 1232 static u32 grp_index; 1233 u32 i = 0; 1234 1235 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np); 1236 1237 func = &info->functions[index]; 1238 1239 /* Initialise function */ 1240 func->name = np->name; 1241 func->ngroups = of_get_child_count(np); 1242 if (func->ngroups == 0) { 1243 dev_err(info->dev, "no groups defined\n"); 1244 return -EINVAL; 1245 } 1246 func->groups = devm_kcalloc(info->dev, 1247 func->ngroups, sizeof(char *), GFP_KERNEL); 1248 if (!func->groups) 1249 return -ENOMEM; 1250 1251 for_each_child_of_node(np, child) { 1252 func->groups[i] = child->name; 1253 grp = &info->groups[grp_index++]; 1254 ret = at91_pinctrl_parse_groups(child, grp, info, i++); 1255 if (ret) { 1256 of_node_put(child); 1257 return ret; 1258 } 1259 } 1260 1261 return 0; 1262} 1263 1264static const struct of_device_id at91_pinctrl_of_match[] = { 1265 { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops }, 1266 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops }, 1267 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops }, 1268 { .compatible = "microchip,sam9x60-pinctrl", .data = &sam9x60_ops }, 1269 { /* sentinel */ } 1270}; 1271 1272static int at91_pinctrl_probe_dt(struct platform_device *pdev, 1273 struct at91_pinctrl *info) 1274{ 1275 int ret = 0; 1276 int i, j; 1277 uint32_t *tmp; 1278 struct device_node *np = pdev->dev.of_node; 1279 struct device_node *child; 1280 1281 if (!np) 1282 return -ENODEV; 1283 1284 info->dev = &pdev->dev; 1285 info->ops = (struct at91_pinctrl_mux_ops *) 1286 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data; 1287 at91_pinctrl_child_count(info, np); 1288 1289 if (gpio_banks < 1) { 1290 dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n"); 1291 return -EINVAL; 1292 } 1293 1294 ret = at91_pinctrl_mux_mask(info, np); 1295 if (ret) 1296 return ret; 1297 1298 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux); 1299 1300 dev_dbg(&pdev->dev, "mux-mask\n"); 1301 tmp = info->mux_mask; 1302 for (i = 0; i < gpio_banks; i++) { 1303 for (j = 0; j < info->nmux; j++, tmp++) { 1304 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]); 1305 } 1306 } 1307 1308 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 1309 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 1310 info->functions = devm_kcalloc(&pdev->dev, 1311 info->nfunctions, 1312 sizeof(struct at91_pmx_func), 1313 GFP_KERNEL); 1314 if (!info->functions) 1315 return -ENOMEM; 1316 1317 info->groups = devm_kcalloc(&pdev->dev, 1318 info->ngroups, 1319 sizeof(struct at91_pin_group), 1320 GFP_KERNEL); 1321 if (!info->groups) 1322 return -ENOMEM; 1323 1324 dev_dbg(&pdev->dev, "nbanks = %d\n", gpio_banks); 1325 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 1326 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 1327 1328 i = 0; 1329 1330 for_each_child_of_node(np, child) { 1331 if (of_device_is_compatible(child, gpio_compat)) 1332 continue; 1333 ret = at91_pinctrl_parse_functions(child, info, i++); 1334 if (ret) { 1335 dev_err(&pdev->dev, "failed to parse function\n"); 1336 of_node_put(child); 1337 return ret; 1338 } 1339 } 1340 1341 return 0; 1342} 1343 1344static int at91_pinctrl_probe(struct platform_device *pdev) 1345{ 1346 struct at91_pinctrl *info; 1347 struct pinctrl_pin_desc *pdesc; 1348 int ret, i, j, k, ngpio_chips_enabled = 0; 1349 1350 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 1351 if (!info) 1352 return -ENOMEM; 1353 1354 ret = at91_pinctrl_probe_dt(pdev, info); 1355 if (ret) 1356 return ret; 1357 1358 /* 1359 * We need all the GPIO drivers to probe FIRST, or we will not be able 1360 * to obtain references to the struct gpio_chip * for them, and we 1361 * need this to proceed. 1362 */ 1363 for (i = 0; i < gpio_banks; i++) 1364 if (gpio_chips[i]) 1365 ngpio_chips_enabled++; 1366 1367 if (ngpio_chips_enabled < info->nactive_banks) { 1368 dev_warn(&pdev->dev, 1369 "All GPIO chips are not registered yet (%d/%d)\n", 1370 ngpio_chips_enabled, info->nactive_banks); 1371 devm_kfree(&pdev->dev, info); 1372 return -EPROBE_DEFER; 1373 } 1374 1375 at91_pinctrl_desc.name = dev_name(&pdev->dev); 1376 at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK; 1377 at91_pinctrl_desc.pins = pdesc = 1378 devm_kcalloc(&pdev->dev, 1379 at91_pinctrl_desc.npins, sizeof(*pdesc), 1380 GFP_KERNEL); 1381 1382 if (!at91_pinctrl_desc.pins) 1383 return -ENOMEM; 1384 1385 for (i = 0, k = 0; i < gpio_banks; i++) { 1386 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) { 1387 pdesc->number = k; 1388 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j); 1389 pdesc++; 1390 } 1391 } 1392 1393 platform_set_drvdata(pdev, info); 1394 info->pctl = devm_pinctrl_register(&pdev->dev, &at91_pinctrl_desc, 1395 info); 1396 1397 if (IS_ERR(info->pctl)) { 1398 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n"); 1399 return PTR_ERR(info->pctl); 1400 } 1401 1402 /* We will handle a range of GPIO pins */ 1403 for (i = 0; i < gpio_banks; i++) 1404 if (gpio_chips[i]) 1405 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range); 1406 1407 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n"); 1408 1409 return 0; 1410} 1411 1412static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 1413{ 1414 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); 1415 void __iomem *pio = at91_gpio->regbase; 1416 unsigned mask = 1 << offset; 1417 u32 osr; 1418 1419 osr = readl_relaxed(pio + PIO_OSR); 1420 if (osr & mask) 1421 return GPIO_LINE_DIRECTION_OUT; 1422 1423 return GPIO_LINE_DIRECTION_IN; 1424} 1425 1426static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 1427{ 1428 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); 1429 void __iomem *pio = at91_gpio->regbase; 1430 unsigned mask = 1 << offset; 1431 1432 writel_relaxed(mask, pio + PIO_ODR); 1433 return 0; 1434} 1435 1436static int at91_gpio_get(struct gpio_chip *chip, unsigned offset) 1437{ 1438 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); 1439 void __iomem *pio = at91_gpio->regbase; 1440 unsigned mask = 1 << offset; 1441 u32 pdsr; 1442 1443 pdsr = readl_relaxed(pio + PIO_PDSR); 1444 return (pdsr & mask) != 0; 1445} 1446 1447static void at91_gpio_set(struct gpio_chip *chip, unsigned offset, 1448 int val) 1449{ 1450 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); 1451 void __iomem *pio = at91_gpio->regbase; 1452 unsigned mask = 1 << offset; 1453 1454 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); 1455} 1456 1457static void at91_gpio_set_multiple(struct gpio_chip *chip, 1458 unsigned long *mask, unsigned long *bits) 1459{ 1460 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); 1461 void __iomem *pio = at91_gpio->regbase; 1462 1463#define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1)) 1464 /* Mask additionally to ngpio as not all GPIO controllers have 32 pins */ 1465 uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio); 1466 uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio); 1467 1468 writel_relaxed(set_mask, pio + PIO_SODR); 1469 writel_relaxed(clear_mask, pio + PIO_CODR); 1470} 1471 1472static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 1473 int val) 1474{ 1475 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); 1476 void __iomem *pio = at91_gpio->regbase; 1477 unsigned mask = 1 << offset; 1478 1479 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); 1480 writel_relaxed(mask, pio + PIO_OER); 1481 1482 return 0; 1483} 1484 1485#ifdef CONFIG_DEBUG_FS 1486static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 1487{ 1488 enum at91_mux mode; 1489 int i; 1490 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); 1491 void __iomem *pio = at91_gpio->regbase; 1492 const char *gpio_label; 1493 1494 for_each_requested_gpio(chip, i, gpio_label) { 1495 unsigned mask = pin_to_mask(i); 1496 1497 mode = at91_gpio->ops->get_periph(pio, mask); 1498 seq_printf(s, "[%s] GPIO%s%d: ", 1499 gpio_label, chip->label, i); 1500 if (mode == AT91_MUX_GPIO) { 1501 seq_printf(s, "[gpio] "); 1502 seq_printf(s, "%s ", 1503 readl_relaxed(pio + PIO_OSR) & mask ? 1504 "output" : "input"); 1505 seq_printf(s, "%s\n", 1506 readl_relaxed(pio + PIO_PDSR) & mask ? 1507 "set" : "clear"); 1508 } else { 1509 seq_printf(s, "[periph %c]\n", 1510 mode + 'A' - 1); 1511 } 1512 } 1513} 1514#else 1515#define at91_gpio_dbg_show NULL 1516#endif 1517 1518/* Several AIC controller irqs are dispatched through this GPIO handler. 1519 * To use any AT91_PIN_* as an externally triggered IRQ, first call 1520 * at91_set_gpio_input() then maybe enable its glitch filter. 1521 * Then just request_irq() with the pin ID; it works like any ARM IRQ 1522 * handler. 1523 * First implementation always triggers on rising and falling edges 1524 * whereas the newer PIO3 can be additionally configured to trigger on 1525 * level, edge with any polarity. 1526 * 1527 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after 1528 * configuring them with at91_set_a_periph() or at91_set_b_periph(). 1529 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. 1530 */ 1531 1532static void gpio_irq_mask(struct irq_data *d) 1533{ 1534 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 1535 void __iomem *pio = at91_gpio->regbase; 1536 unsigned mask = 1 << d->hwirq; 1537 1538 if (pio) 1539 writel_relaxed(mask, pio + PIO_IDR); 1540} 1541 1542static void gpio_irq_unmask(struct irq_data *d) 1543{ 1544 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 1545 void __iomem *pio = at91_gpio->regbase; 1546 unsigned mask = 1 << d->hwirq; 1547 1548 if (pio) 1549 writel_relaxed(mask, pio + PIO_IER); 1550} 1551 1552static int gpio_irq_type(struct irq_data *d, unsigned type) 1553{ 1554 switch (type) { 1555 case IRQ_TYPE_NONE: 1556 case IRQ_TYPE_EDGE_BOTH: 1557 return 0; 1558 default: 1559 return -EINVAL; 1560 } 1561} 1562 1563/* Alternate irq type for PIO3 support */ 1564static int alt_gpio_irq_type(struct irq_data *d, unsigned type) 1565{ 1566 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 1567 void __iomem *pio = at91_gpio->regbase; 1568 unsigned mask = 1 << d->hwirq; 1569 1570 switch (type) { 1571 case IRQ_TYPE_EDGE_RISING: 1572 irq_set_handler_locked(d, handle_simple_irq); 1573 writel_relaxed(mask, pio + PIO_ESR); 1574 writel_relaxed(mask, pio + PIO_REHLSR); 1575 break; 1576 case IRQ_TYPE_EDGE_FALLING: 1577 irq_set_handler_locked(d, handle_simple_irq); 1578 writel_relaxed(mask, pio + PIO_ESR); 1579 writel_relaxed(mask, pio + PIO_FELLSR); 1580 break; 1581 case IRQ_TYPE_LEVEL_LOW: 1582 irq_set_handler_locked(d, handle_level_irq); 1583 writel_relaxed(mask, pio + PIO_LSR); 1584 writel_relaxed(mask, pio + PIO_FELLSR); 1585 break; 1586 case IRQ_TYPE_LEVEL_HIGH: 1587 irq_set_handler_locked(d, handle_level_irq); 1588 writel_relaxed(mask, pio + PIO_LSR); 1589 writel_relaxed(mask, pio + PIO_REHLSR); 1590 break; 1591 case IRQ_TYPE_EDGE_BOTH: 1592 /* 1593 * disable additional interrupt modes: 1594 * fall back to default behavior 1595 */ 1596 irq_set_handler_locked(d, handle_simple_irq); 1597 writel_relaxed(mask, pio + PIO_AIMDR); 1598 return 0; 1599 case IRQ_TYPE_NONE: 1600 default: 1601 pr_warn("AT91: No type for GPIO irq offset %d\n", d->irq); 1602 return -EINVAL; 1603 } 1604 1605 /* enable additional interrupt modes */ 1606 writel_relaxed(mask, pio + PIO_AIMER); 1607 1608 return 0; 1609} 1610 1611static void gpio_irq_ack(struct irq_data *d) 1612{ 1613 /* the interrupt is already cleared before by reading ISR */ 1614} 1615 1616#ifdef CONFIG_PM 1617 1618static u32 wakeups[MAX_GPIO_BANKS]; 1619static u32 backups[MAX_GPIO_BANKS]; 1620 1621static int gpio_irq_set_wake(struct irq_data *d, unsigned state) 1622{ 1623 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 1624 unsigned bank = at91_gpio->pioc_idx; 1625 unsigned mask = 1 << d->hwirq; 1626 1627 if (unlikely(bank >= MAX_GPIO_BANKS)) 1628 return -EINVAL; 1629 1630 if (state) 1631 wakeups[bank] |= mask; 1632 else 1633 wakeups[bank] &= ~mask; 1634 1635 irq_set_irq_wake(at91_gpio->pioc_virq, state); 1636 1637 return 0; 1638} 1639 1640void at91_pinctrl_gpio_suspend(void) 1641{ 1642 int i; 1643 1644 for (i = 0; i < gpio_banks; i++) { 1645 void __iomem *pio; 1646 1647 if (!gpio_chips[i]) 1648 continue; 1649 1650 pio = gpio_chips[i]->regbase; 1651 1652 backups[i] = readl_relaxed(pio + PIO_IMR); 1653 writel_relaxed(backups[i], pio + PIO_IDR); 1654 writel_relaxed(wakeups[i], pio + PIO_IER); 1655 1656 if (!wakeups[i]) 1657 clk_disable_unprepare(gpio_chips[i]->clock); 1658 else 1659 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 1660 'A'+i, wakeups[i]); 1661 } 1662} 1663 1664void at91_pinctrl_gpio_resume(void) 1665{ 1666 int i; 1667 1668 for (i = 0; i < gpio_banks; i++) { 1669 void __iomem *pio; 1670 1671 if (!gpio_chips[i]) 1672 continue; 1673 1674 pio = gpio_chips[i]->regbase; 1675 1676 if (!wakeups[i]) 1677 clk_prepare_enable(gpio_chips[i]->clock); 1678 1679 writel_relaxed(wakeups[i], pio + PIO_IDR); 1680 writel_relaxed(backups[i], pio + PIO_IER); 1681 } 1682} 1683 1684#else 1685#define gpio_irq_set_wake NULL 1686#endif /* CONFIG_PM */ 1687 1688static void gpio_irq_handler(struct irq_desc *desc) 1689{ 1690 struct irq_chip *chip = irq_desc_get_chip(desc); 1691 struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc); 1692 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gpio_chip); 1693 void __iomem *pio = at91_gpio->regbase; 1694 unsigned long isr; 1695 int n; 1696 1697 chained_irq_enter(chip, desc); 1698 for (;;) { 1699 /* Reading ISR acks pending (edge triggered) GPIO interrupts. 1700 * When there are none pending, we're finished unless we need 1701 * to process multiple banks (like ID_PIOCDE on sam9263). 1702 */ 1703 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR); 1704 if (!isr) { 1705 if (!at91_gpio->next) 1706 break; 1707 at91_gpio = at91_gpio->next; 1708 pio = at91_gpio->regbase; 1709 gpio_chip = &at91_gpio->chip; 1710 continue; 1711 } 1712 1713 for_each_set_bit(n, &isr, BITS_PER_LONG) { 1714 generic_handle_irq(irq_find_mapping( 1715 gpio_chip->irq.domain, n)); 1716 } 1717 } 1718 chained_irq_exit(chip, desc); 1719 /* now it may re-trigger */ 1720} 1721 1722static int at91_gpio_of_irq_setup(struct platform_device *pdev, 1723 struct at91_gpio_chip *at91_gpio) 1724{ 1725 struct gpio_chip *gpiochip_prev = NULL; 1726 struct at91_gpio_chip *prev = NULL; 1727 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq); 1728 struct irq_chip *gpio_irqchip; 1729 struct gpio_irq_chip *girq; 1730 int i; 1731 1732 gpio_irqchip = devm_kzalloc(&pdev->dev, sizeof(*gpio_irqchip), 1733 GFP_KERNEL); 1734 if (!gpio_irqchip) 1735 return -ENOMEM; 1736 1737 at91_gpio->pioc_hwirq = irqd_to_hwirq(d); 1738 1739 gpio_irqchip->name = "GPIO"; 1740 gpio_irqchip->irq_ack = gpio_irq_ack; 1741 gpio_irqchip->irq_disable = gpio_irq_mask; 1742 gpio_irqchip->irq_mask = gpio_irq_mask; 1743 gpio_irqchip->irq_unmask = gpio_irq_unmask; 1744 gpio_irqchip->irq_set_wake = gpio_irq_set_wake, 1745 gpio_irqchip->irq_set_type = at91_gpio->ops->irq_type; 1746 1747 /* Disable irqs of this PIO controller */ 1748 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR); 1749 1750 /* 1751 * Let the generic code handle this edge IRQ, the the chained 1752 * handler will perform the actual work of handling the parent 1753 * interrupt. 1754 */ 1755 girq = &at91_gpio->chip.irq; 1756 girq->chip = gpio_irqchip; 1757 girq->default_type = IRQ_TYPE_NONE; 1758 girq->handler = handle_edge_irq; 1759 1760 /* 1761 * The top level handler handles one bank of GPIOs, except 1762 * on some SoC it can handle up to three... 1763 * We only set up the handler for the first of the list. 1764 */ 1765 gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq); 1766 if (!gpiochip_prev) { 1767 girq->parent_handler = gpio_irq_handler; 1768 girq->num_parents = 1; 1769 girq->parents = devm_kcalloc(&pdev->dev, 1, 1770 sizeof(*girq->parents), 1771 GFP_KERNEL); 1772 if (!girq->parents) 1773 return -ENOMEM; 1774 girq->parents[0] = at91_gpio->pioc_virq; 1775 return 0; 1776 } 1777 1778 prev = gpiochip_get_data(gpiochip_prev); 1779 /* we can only have 2 banks before */ 1780 for (i = 0; i < 2; i++) { 1781 if (prev->next) { 1782 prev = prev->next; 1783 } else { 1784 prev->next = at91_gpio; 1785 return 0; 1786 } 1787 } 1788 1789 return -EINVAL; 1790} 1791 1792/* This structure is replicated for each GPIO block allocated at probe time */ 1793static const struct gpio_chip at91_gpio_template = { 1794 .request = gpiochip_generic_request, 1795 .free = gpiochip_generic_free, 1796 .get_direction = at91_gpio_get_direction, 1797 .direction_input = at91_gpio_direction_input, 1798 .get = at91_gpio_get, 1799 .direction_output = at91_gpio_direction_output, 1800 .set = at91_gpio_set, 1801 .set_multiple = at91_gpio_set_multiple, 1802 .dbg_show = at91_gpio_dbg_show, 1803 .can_sleep = false, 1804 .ngpio = MAX_NB_GPIO_PER_BANK, 1805}; 1806 1807static const struct of_device_id at91_gpio_of_match[] = { 1808 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, }, 1809 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops }, 1810 { .compatible = "microchip,sam9x60-gpio", .data = &sam9x60_ops }, 1811 { /* sentinel */ } 1812}; 1813 1814static int at91_gpio_probe(struct platform_device *pdev) 1815{ 1816 struct device_node *np = pdev->dev.of_node; 1817 struct at91_gpio_chip *at91_chip = NULL; 1818 struct gpio_chip *chip; 1819 struct pinctrl_gpio_range *range; 1820 int ret = 0; 1821 int irq, i; 1822 int alias_idx = of_alias_get_id(np, "gpio"); 1823 uint32_t ngpio; 1824 char **names; 1825 1826 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips)); 1827 if (gpio_chips[alias_idx]) { 1828 ret = -EBUSY; 1829 goto err; 1830 } 1831 1832 irq = platform_get_irq(pdev, 0); 1833 if (irq < 0) { 1834 ret = irq; 1835 goto err; 1836 } 1837 1838 at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL); 1839 if (!at91_chip) { 1840 ret = -ENOMEM; 1841 goto err; 1842 } 1843 1844 at91_chip->regbase = devm_platform_ioremap_resource(pdev, 0); 1845 if (IS_ERR(at91_chip->regbase)) { 1846 ret = PTR_ERR(at91_chip->regbase); 1847 goto err; 1848 } 1849 1850 at91_chip->ops = (struct at91_pinctrl_mux_ops *) 1851 of_match_device(at91_gpio_of_match, &pdev->dev)->data; 1852 at91_chip->pioc_virq = irq; 1853 at91_chip->pioc_idx = alias_idx; 1854 1855 at91_chip->clock = devm_clk_get(&pdev->dev, NULL); 1856 if (IS_ERR(at91_chip->clock)) { 1857 dev_err(&pdev->dev, "failed to get clock, ignoring.\n"); 1858 ret = PTR_ERR(at91_chip->clock); 1859 goto err; 1860 } 1861 1862 ret = clk_prepare_enable(at91_chip->clock); 1863 if (ret) { 1864 dev_err(&pdev->dev, "failed to prepare and enable clock, ignoring.\n"); 1865 goto clk_enable_err; 1866 } 1867 1868 at91_chip->chip = at91_gpio_template; 1869 1870 chip = &at91_chip->chip; 1871 chip->of_node = np; 1872 chip->label = dev_name(&pdev->dev); 1873 chip->parent = &pdev->dev; 1874 chip->owner = THIS_MODULE; 1875 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK; 1876 1877 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) { 1878 if (ngpio >= MAX_NB_GPIO_PER_BANK) 1879 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n", 1880 alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK); 1881 else 1882 chip->ngpio = ngpio; 1883 } 1884 1885 names = devm_kcalloc(&pdev->dev, chip->ngpio, sizeof(char *), 1886 GFP_KERNEL); 1887 1888 if (!names) { 1889 ret = -ENOMEM; 1890 goto clk_enable_err; 1891 } 1892 1893 for (i = 0; i < chip->ngpio; i++) 1894 names[i] = devm_kasprintf(&pdev->dev, GFP_KERNEL, "pio%c%d", alias_idx + 'A', i); 1895 1896 chip->names = (const char *const *)names; 1897 1898 range = &at91_chip->range; 1899 range->name = chip->label; 1900 range->id = alias_idx; 1901 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK; 1902 1903 range->npins = chip->ngpio; 1904 range->gc = chip; 1905 1906 ret = at91_gpio_of_irq_setup(pdev, at91_chip); 1907 if (ret) 1908 goto gpiochip_add_err; 1909 1910 ret = gpiochip_add_data(chip, at91_chip); 1911 if (ret) 1912 goto gpiochip_add_err; 1913 1914 gpio_chips[alias_idx] = at91_chip; 1915 gpio_banks = max(gpio_banks, alias_idx + 1); 1916 1917 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase); 1918 1919 return 0; 1920 1921gpiochip_add_err: 1922clk_enable_err: 1923 clk_disable_unprepare(at91_chip->clock); 1924err: 1925 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx); 1926 1927 return ret; 1928} 1929 1930static struct platform_driver at91_gpio_driver = { 1931 .driver = { 1932 .name = "gpio-at91", 1933 .of_match_table = at91_gpio_of_match, 1934 }, 1935 .probe = at91_gpio_probe, 1936}; 1937 1938static struct platform_driver at91_pinctrl_driver = { 1939 .driver = { 1940 .name = "pinctrl-at91", 1941 .of_match_table = at91_pinctrl_of_match, 1942 }, 1943 .probe = at91_pinctrl_probe, 1944}; 1945 1946static struct platform_driver * const drivers[] = { 1947 &at91_gpio_driver, 1948 &at91_pinctrl_driver, 1949}; 1950 1951static int __init at91_pinctrl_init(void) 1952{ 1953 return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); 1954} 1955arch_initcall(at91_pinctrl_init); 1956