1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * GPIO driver for AMD 4 * 5 * Copyright (c) 2014,2015 AMD Corporation. 6 * Authors: Ken Xue <Ken.Xue@amd.com> 7 * Wu, Jeff <Jeff.Wu@amd.com> 8 * 9 * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com> 10 * Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 11 */ 12 13#include <linux/err.h> 14#include <linux/bug.h> 15#include <linux/kernel.h> 16#include <linux/module.h> 17#include <linux/spinlock.h> 18#include <linux/compiler.h> 19#include <linux/types.h> 20#include <linux/errno.h> 21#include <linux/log2.h> 22#include <linux/io.h> 23#include <linux/gpio/driver.h> 24#include <linux/slab.h> 25#include <linux/platform_device.h> 26#include <linux/mutex.h> 27#include <linux/acpi.h> 28#include <linux/seq_file.h> 29#include <linux/interrupt.h> 30#include <linux/list.h> 31#include <linux/bitops.h> 32#include <linux/pinctrl/pinconf.h> 33#include <linux/pinctrl/pinconf-generic.h> 34 35#include "core.h" 36#include "pinctrl-utils.h" 37#include "pinctrl-amd.h" 38 39static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) 40{ 41 unsigned long flags; 42 u32 pin_reg; 43 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 44 45 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 46 pin_reg = readl(gpio_dev->base + offset * 4); 47 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 48 49 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) 50 return GPIO_LINE_DIRECTION_OUT; 51 52 return GPIO_LINE_DIRECTION_IN; 53} 54 55static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 56{ 57 unsigned long flags; 58 u32 pin_reg; 59 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 60 61 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 62 pin_reg = readl(gpio_dev->base + offset * 4); 63 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 64 writel(pin_reg, gpio_dev->base + offset * 4); 65 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 66 67 return 0; 68} 69 70static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 71 int value) 72{ 73 u32 pin_reg; 74 unsigned long flags; 75 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 76 77 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 78 pin_reg = readl(gpio_dev->base + offset * 4); 79 pin_reg |= BIT(OUTPUT_ENABLE_OFF); 80 if (value) 81 pin_reg |= BIT(OUTPUT_VALUE_OFF); 82 else 83 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 84 writel(pin_reg, gpio_dev->base + offset * 4); 85 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 86 87 return 0; 88} 89 90static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 91{ 92 u32 pin_reg; 93 unsigned long flags; 94 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 95 96 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 97 pin_reg = readl(gpio_dev->base + offset * 4); 98 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 99 100 return !!(pin_reg & BIT(PIN_STS_OFF)); 101} 102 103static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) 104{ 105 u32 pin_reg; 106 unsigned long flags; 107 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 108 109 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 110 pin_reg = readl(gpio_dev->base + offset * 4); 111 if (value) 112 pin_reg |= BIT(OUTPUT_VALUE_OFF); 113 else 114 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 115 writel(pin_reg, gpio_dev->base + offset * 4); 116 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 117} 118 119static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, 120 unsigned debounce) 121{ 122 u32 time; 123 u32 pin_reg; 124 int ret = 0; 125 unsigned long flags; 126 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 127 128 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 129 130 /* Use special handling for Pin0 debounce */ 131 if (offset == 0) { 132 pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 133 if (pin_reg & INTERNAL_GPIO0_DEBOUNCE) 134 debounce = 0; 135 } 136 137 pin_reg = readl(gpio_dev->base + offset * 4); 138 139 if (debounce) { 140 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 141 pin_reg &= ~DB_TMR_OUT_MASK; 142 /* 143 Debounce Debounce Timer Max 144 TmrLarge TmrOutUnit Unit Debounce 145 Time 146 0 0 61 usec (2 RtcClk) 976 usec 147 0 1 244 usec (8 RtcClk) 3.9 msec 148 1 0 15.6 msec (512 RtcClk) 250 msec 149 1 1 62.5 msec (2048 RtcClk) 1 sec 150 */ 151 152 if (debounce < 61) { 153 pin_reg |= 1; 154 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 155 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 156 } else if (debounce < 976) { 157 time = debounce / 61; 158 pin_reg |= time & DB_TMR_OUT_MASK; 159 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 160 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 161 } else if (debounce < 3900) { 162 time = debounce / 244; 163 pin_reg |= time & DB_TMR_OUT_MASK; 164 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 165 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 166 } else if (debounce < 250000) { 167 time = debounce / 15625; 168 pin_reg |= time & DB_TMR_OUT_MASK; 169 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 170 pin_reg |= BIT(DB_TMR_LARGE_OFF); 171 } else if (debounce < 1000000) { 172 time = debounce / 62500; 173 pin_reg |= time & DB_TMR_OUT_MASK; 174 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 175 pin_reg |= BIT(DB_TMR_LARGE_OFF); 176 } else { 177 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 178 ret = -EINVAL; 179 } 180 } else { 181 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 182 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 183 pin_reg &= ~DB_TMR_OUT_MASK; 184 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 185 } 186 writel(pin_reg, gpio_dev->base + offset * 4); 187 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 188 189 return ret; 190} 191 192#ifdef CONFIG_DEBUG_FS 193static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 194{ 195 u32 pin_reg; 196 unsigned long flags; 197 unsigned int bank, i, pin_num; 198 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 199 200 char *level_trig; 201 char *active_level; 202 char *interrupt_enable; 203 char *interrupt_mask; 204 char *wake_cntrl0; 205 char *wake_cntrl1; 206 char *wake_cntrl2; 207 char *pin_sts; 208 char *pull_up_sel; 209 char *pull_up_enable; 210 char *pull_down_enable; 211 char *output_value; 212 char *output_enable; 213 214 seq_printf(s, "WAKE_INT_MASTER_REG: 0x%08x\n", readl(gpio_dev->base + WAKE_INT_MASTER_REG)); 215 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { 216 seq_printf(s, "GPIO bank%d\t", bank); 217 218 switch (bank) { 219 case 0: 220 i = 0; 221 pin_num = AMD_GPIO_PINS_BANK0; 222 break; 223 case 1: 224 i = 64; 225 pin_num = AMD_GPIO_PINS_BANK1 + i; 226 break; 227 case 2: 228 i = 128; 229 pin_num = AMD_GPIO_PINS_BANK2 + i; 230 break; 231 case 3: 232 i = 192; 233 pin_num = AMD_GPIO_PINS_BANK3 + i; 234 break; 235 default: 236 /* Illegal bank number, ignore */ 237 continue; 238 } 239 for (; i < pin_num; i++) { 240 seq_printf(s, "pin%d\t", i); 241 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 242 pin_reg = readl(gpio_dev->base + i * 4); 243 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 244 245 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 246 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & 247 ACTIVE_LEVEL_MASK; 248 interrupt_enable = "interrupt is enabled|"; 249 250 if (level == ACTIVE_LEVEL_HIGH) 251 active_level = "Active high|"; 252 else if (level == ACTIVE_LEVEL_LOW) 253 active_level = "Active low|"; 254 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && 255 level == ACTIVE_LEVEL_BOTH) 256 active_level = "Active on both|"; 257 else 258 active_level = "Unknown Active level|"; 259 260 if (pin_reg & BIT(LEVEL_TRIG_OFF)) 261 level_trig = "Level trigger|"; 262 else 263 level_trig = "Edge trigger|"; 264 265 } else { 266 interrupt_enable = 267 "interrupt is disabled|"; 268 active_level = " "; 269 level_trig = " "; 270 } 271 272 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 273 interrupt_mask = 274 "interrupt is unmasked|"; 275 else 276 interrupt_mask = 277 "interrupt is masked|"; 278 279 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) 280 wake_cntrl0 = "enable wakeup in S0i3 state|"; 281 else 282 wake_cntrl0 = "disable wakeup in S0i3 state|"; 283 284 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) 285 wake_cntrl1 = "enable wakeup in S3 state|"; 286 else 287 wake_cntrl1 = "disable wakeup in S3 state|"; 288 289 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) 290 wake_cntrl2 = "enable wakeup in S4/S5 state|"; 291 else 292 wake_cntrl2 = "disable wakeup in S4/S5 state|"; 293 294 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 295 pull_up_enable = "pull-up is enabled|"; 296 if (pin_reg & BIT(PULL_UP_SEL_OFF)) 297 pull_up_sel = "8k pull-up|"; 298 else 299 pull_up_sel = "4k pull-up|"; 300 } else { 301 pull_up_enable = "pull-up is disabled|"; 302 pull_up_sel = " "; 303 } 304 305 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) 306 pull_down_enable = "pull-down is enabled|"; 307 else 308 pull_down_enable = "Pull-down is disabled|"; 309 310 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 311 pin_sts = " "; 312 output_enable = "output is enabled|"; 313 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 314 output_value = "output is high|"; 315 else 316 output_value = "output is low|"; 317 } else { 318 output_enable = "output is disabled|"; 319 output_value = " "; 320 321 if (pin_reg & BIT(PIN_STS_OFF)) 322 pin_sts = "input is high|"; 323 else 324 pin_sts = "input is low|"; 325 } 326 327 seq_printf(s, "%s %s %s %s %s %s\n" 328 " %s %s %s %s %s %s %s 0x%x\n", 329 level_trig, active_level, interrupt_enable, 330 interrupt_mask, wake_cntrl0, wake_cntrl1, 331 wake_cntrl2, pin_sts, pull_up_sel, 332 pull_up_enable, pull_down_enable, 333 output_value, output_enable, pin_reg); 334 } 335 } 336} 337#else 338#define amd_gpio_dbg_show NULL 339#endif 340 341static void amd_gpio_irq_enable(struct irq_data *d) 342{ 343 u32 pin_reg; 344 unsigned long flags; 345 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 346 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 347 348 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 349 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 350 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 351 pin_reg |= BIT(INTERRUPT_MASK_OFF); 352 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 353 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 354} 355 356static void amd_gpio_irq_disable(struct irq_data *d) 357{ 358 u32 pin_reg; 359 unsigned long flags; 360 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 361 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 362 363 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 364 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 365 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 366 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 367 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 368 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 369} 370 371static void amd_gpio_irq_mask(struct irq_data *d) 372{ 373 u32 pin_reg; 374 unsigned long flags; 375 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 376 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 377 378 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 379 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 380 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 381 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 382 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 383} 384 385static void amd_gpio_irq_unmask(struct irq_data *d) 386{ 387 u32 pin_reg; 388 unsigned long flags; 389 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 390 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 391 392 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 393 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 394 pin_reg |= BIT(INTERRUPT_MASK_OFF); 395 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 396 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 397} 398 399static void amd_gpio_irq_eoi(struct irq_data *d) 400{ 401 u32 reg; 402 unsigned long flags; 403 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 404 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 405 406 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 407 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 408 reg |= EOI_MASK; 409 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 410 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 411} 412 413static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 414{ 415 int ret = 0; 416 u32 pin_reg, pin_reg_irq_en, mask; 417 unsigned long flags; 418 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 419 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 420 421 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 422 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 423 424 switch (type & IRQ_TYPE_SENSE_MASK) { 425 case IRQ_TYPE_EDGE_RISING: 426 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 427 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 428 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 429 irq_set_handler_locked(d, handle_edge_irq); 430 break; 431 432 case IRQ_TYPE_EDGE_FALLING: 433 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 434 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 435 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 436 irq_set_handler_locked(d, handle_edge_irq); 437 break; 438 439 case IRQ_TYPE_EDGE_BOTH: 440 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 441 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 442 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; 443 irq_set_handler_locked(d, handle_edge_irq); 444 break; 445 446 case IRQ_TYPE_LEVEL_HIGH: 447 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 448 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 449 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 450 irq_set_handler_locked(d, handle_level_irq); 451 break; 452 453 case IRQ_TYPE_LEVEL_LOW: 454 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 455 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 456 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 457 irq_set_handler_locked(d, handle_level_irq); 458 break; 459 460 case IRQ_TYPE_NONE: 461 break; 462 463 default: 464 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 465 ret = -EINVAL; 466 } 467 468 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 469 /* 470 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the 471 * debounce registers of any GPIO will block wake/interrupt status 472 * generation for *all* GPIOs for a length of time that depends on 473 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the 474 * INTERRUPT_ENABLE bit will read as 0. 475 * 476 * We temporarily enable irq for the GPIO whose configuration is 477 * changing, and then wait for it to read back as 1 to know when 478 * debounce has settled and then disable the irq again. 479 * We do this polling with the spinlock held to ensure other GPIO 480 * access routines do not read an incorrect value for the irq enable 481 * bit of other GPIOs. We keep the GPIO masked while polling to avoid 482 * spurious irqs, and disable the irq again after polling. 483 */ 484 mask = BIT(INTERRUPT_ENABLE_OFF); 485 pin_reg_irq_en = pin_reg; 486 pin_reg_irq_en |= mask; 487 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF); 488 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4); 489 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) 490 continue; 491 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 492 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 493 494 return ret; 495} 496 497static void amd_irq_ack(struct irq_data *d) 498{ 499 /* 500 * based on HW design,there is no need to ack HW 501 * before handle current irq. But this routine is 502 * necessary for handle_edge_irq 503 */ 504} 505 506static struct irq_chip amd_gpio_irqchip = { 507 .name = "amd_gpio", 508 .irq_ack = amd_irq_ack, 509 .irq_enable = amd_gpio_irq_enable, 510 .irq_disable = amd_gpio_irq_disable, 511 .irq_mask = amd_gpio_irq_mask, 512 .irq_unmask = amd_gpio_irq_unmask, 513 .irq_eoi = amd_gpio_irq_eoi, 514 .irq_set_type = amd_gpio_irq_set_type, 515 .flags = IRQCHIP_SKIP_SET_WAKE, 516}; 517 518#define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) 519 520static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) 521{ 522 struct amd_gpio *gpio_dev = dev_id; 523 struct gpio_chip *gc = &gpio_dev->gc; 524 irqreturn_t ret = IRQ_NONE; 525 unsigned int i, irqnr; 526 unsigned long flags; 527 u32 __iomem *regs; 528 u32 regval; 529 u64 status, mask; 530 531 /* Read the wake status */ 532 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 533 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 534 status <<= 32; 535 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 536 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 537 538 /* Bit 0-45 contain the relevant status bits */ 539 status &= (1ULL << 46) - 1; 540 regs = gpio_dev->base; 541 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { 542 if (!(status & mask)) 543 continue; 544 status &= ~mask; 545 546 /* Each status bit covers four pins */ 547 for (i = 0; i < 4; i++) { 548 regval = readl(regs + i); 549 if (!(regval & PIN_IRQ_PENDING) || 550 !(regval & BIT(INTERRUPT_MASK_OFF))) 551 continue; 552 irq = irq_find_mapping(gc->irq.domain, irqnr + i); 553 if (irq != 0) 554 generic_handle_irq(irq); 555 556 /* Clear interrupt. 557 * We must read the pin register again, in case the 558 * value was changed while executing 559 * generic_handle_irq() above. 560 * If we didn't find a mapping for the interrupt, 561 * disable it in order to avoid a system hang caused 562 * by an interrupt storm. 563 */ 564 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 565 regval = readl(regs + i); 566 if (irq == 0) { 567 regval &= ~BIT(INTERRUPT_ENABLE_OFF); 568 dev_dbg(&gpio_dev->pdev->dev, 569 "Disabling spurious GPIO IRQ %d\n", 570 irqnr + i); 571 } 572 writel(regval, regs + i); 573 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 574 ret = IRQ_HANDLED; 575 } 576 } 577 578 /* Signal EOI to the GPIO unit */ 579 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 580 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 581 regval |= EOI_MASK; 582 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); 583 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 584 585 return ret; 586} 587 588static int amd_get_groups_count(struct pinctrl_dev *pctldev) 589{ 590 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 591 592 return gpio_dev->ngroups; 593} 594 595static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 596 unsigned group) 597{ 598 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 599 600 return gpio_dev->groups[group].name; 601} 602 603static int amd_get_group_pins(struct pinctrl_dev *pctldev, 604 unsigned group, 605 const unsigned **pins, 606 unsigned *num_pins) 607{ 608 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 609 610 *pins = gpio_dev->groups[group].pins; 611 *num_pins = gpio_dev->groups[group].npins; 612 return 0; 613} 614 615static const struct pinctrl_ops amd_pinctrl_ops = { 616 .get_groups_count = amd_get_groups_count, 617 .get_group_name = amd_get_group_name, 618 .get_group_pins = amd_get_group_pins, 619#ifdef CONFIG_OF 620 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 621 .dt_free_map = pinctrl_utils_free_map, 622#endif 623}; 624 625static int amd_pinconf_get(struct pinctrl_dev *pctldev, 626 unsigned int pin, 627 unsigned long *config) 628{ 629 u32 pin_reg; 630 unsigned arg; 631 unsigned long flags; 632 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 633 enum pin_config_param param = pinconf_to_config_param(*config); 634 635 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 636 pin_reg = readl(gpio_dev->base + pin*4); 637 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 638 switch (param) { 639 case PIN_CONFIG_INPUT_DEBOUNCE: 640 arg = pin_reg & DB_TMR_OUT_MASK; 641 break; 642 643 case PIN_CONFIG_BIAS_PULL_DOWN: 644 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 645 break; 646 647 case PIN_CONFIG_BIAS_PULL_UP: 648 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); 649 break; 650 651 case PIN_CONFIG_DRIVE_STRENGTH: 652 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 653 break; 654 655 default: 656 dev_dbg(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 657 param); 658 return -ENOTSUPP; 659 } 660 661 *config = pinconf_to_config_packed(param, arg); 662 663 return 0; 664} 665 666static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 667 unsigned long *configs, unsigned int num_configs) 668{ 669 int i; 670 u32 arg; 671 int ret = 0; 672 u32 pin_reg; 673 unsigned long flags; 674 enum pin_config_param param; 675 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 676 677 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 678 for (i = 0; i < num_configs; i++) { 679 param = pinconf_to_config_param(configs[i]); 680 arg = pinconf_to_config_argument(configs[i]); 681 pin_reg = readl(gpio_dev->base + pin*4); 682 683 switch (param) { 684 case PIN_CONFIG_INPUT_DEBOUNCE: 685 pin_reg &= ~DB_TMR_OUT_MASK; 686 pin_reg |= arg & DB_TMR_OUT_MASK; 687 break; 688 689 case PIN_CONFIG_BIAS_PULL_DOWN: 690 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 691 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 692 break; 693 694 case PIN_CONFIG_BIAS_PULL_UP: 695 pin_reg &= ~BIT(PULL_UP_SEL_OFF); 696 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; 697 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 698 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; 699 break; 700 701 case PIN_CONFIG_DRIVE_STRENGTH: 702 pin_reg &= ~(DRV_STRENGTH_SEL_MASK 703 << DRV_STRENGTH_SEL_OFF); 704 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 705 << DRV_STRENGTH_SEL_OFF; 706 break; 707 708 default: 709 dev_dbg(&gpio_dev->pdev->dev, 710 "Invalid config param %04x\n", param); 711 ret = -ENOTSUPP; 712 } 713 714 writel(pin_reg, gpio_dev->base + pin*4); 715 } 716 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 717 718 return ret; 719} 720 721static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 722 unsigned int group, 723 unsigned long *config) 724{ 725 const unsigned *pins; 726 unsigned npins; 727 int ret; 728 729 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 730 if (ret) 731 return ret; 732 733 if (amd_pinconf_get(pctldev, pins[0], config)) 734 return -ENOTSUPP; 735 736 return 0; 737} 738 739static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 740 unsigned group, unsigned long *configs, 741 unsigned num_configs) 742{ 743 const unsigned *pins; 744 unsigned npins; 745 int i, ret; 746 747 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 748 if (ret) 749 return ret; 750 for (i = 0; i < npins; i++) { 751 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 752 return -ENOTSUPP; 753 } 754 return 0; 755} 756 757static int amd_gpio_set_config(struct gpio_chip *gc, unsigned int pin, 758 unsigned long config) 759{ 760 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 761 762 if (pinconf_to_config_param(config) == PIN_CONFIG_INPUT_DEBOUNCE) { 763 u32 debounce = pinconf_to_config_argument(config); 764 765 return amd_gpio_set_debounce(gc, pin, debounce); 766 } 767 768 return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1); 769} 770 771static const struct pinconf_ops amd_pinconf_ops = { 772 .pin_config_get = amd_pinconf_get, 773 .pin_config_set = amd_pinconf_set, 774 .pin_config_group_get = amd_pinconf_group_get, 775 .pin_config_group_set = amd_pinconf_group_set, 776}; 777 778static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) 779{ 780 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 781 unsigned long flags; 782 u32 pin_reg, mask; 783 int i; 784 785 mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | 786 BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) | 787 BIT(WAKE_CNTRL_OFF_S4); 788 789 for (i = 0; i < desc->npins; i++) { 790 int pin = desc->pins[i].number; 791 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 792 793 if (!pd) 794 continue; 795 796 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 797 798 pin_reg = readl(gpio_dev->base + pin * 4); 799 pin_reg &= ~mask; 800 writel(pin_reg, gpio_dev->base + pin * 4); 801 802 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 803 } 804} 805 806#ifdef CONFIG_PM_SLEEP 807static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) 808{ 809 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 810 811 if (!pd) 812 return false; 813 814 /* 815 * Only restore the pin if it is actually in use by the kernel (or 816 * by userspace). 817 */ 818 if (pd->mux_owner || pd->gpio_owner || 819 gpiochip_line_is_irq(&gpio_dev->gc, pin)) 820 return true; 821 822 return false; 823} 824 825static int amd_gpio_suspend(struct device *dev) 826{ 827 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 828 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 829 unsigned long flags; 830 int i; 831 832 for (i = 0; i < desc->npins; i++) { 833 int pin = desc->pins[i].number; 834 835 if (!amd_gpio_should_save(gpio_dev, pin)) 836 continue; 837 838 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 839 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING; 840 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 841 } 842 843 return 0; 844} 845 846static int amd_gpio_resume(struct device *dev) 847{ 848 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 849 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 850 unsigned long flags; 851 int i; 852 853 for (i = 0; i < desc->npins; i++) { 854 int pin = desc->pins[i].number; 855 856 if (!amd_gpio_should_save(gpio_dev, pin)) 857 continue; 858 859 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 860 gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING; 861 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4); 862 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 863 } 864 865 return 0; 866} 867 868static const struct dev_pm_ops amd_gpio_pm_ops = { 869 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend, 870 amd_gpio_resume) 871}; 872#endif 873 874static struct pinctrl_desc amd_pinctrl_desc = { 875 .pins = kerncz_pins, 876 .npins = ARRAY_SIZE(kerncz_pins), 877 .pctlops = &amd_pinctrl_ops, 878 .confops = &amd_pinconf_ops, 879 .owner = THIS_MODULE, 880}; 881 882static int amd_gpio_probe(struct platform_device *pdev) 883{ 884 int ret = 0; 885 int irq_base; 886 struct resource *res; 887 struct amd_gpio *gpio_dev; 888 struct gpio_irq_chip *girq; 889 890 gpio_dev = devm_kzalloc(&pdev->dev, 891 sizeof(struct amd_gpio), GFP_KERNEL); 892 if (!gpio_dev) 893 return -ENOMEM; 894 895 raw_spin_lock_init(&gpio_dev->lock); 896 897 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 898 if (!res) { 899 dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 900 return -EINVAL; 901 } 902 903 gpio_dev->base = devm_ioremap(&pdev->dev, res->start, 904 resource_size(res)); 905 if (!gpio_dev->base) 906 return -ENOMEM; 907 908 irq_base = platform_get_irq(pdev, 0); 909 if (irq_base < 0) 910 return irq_base; 911 912#ifdef CONFIG_PM_SLEEP 913 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, 914 sizeof(*gpio_dev->saved_regs), 915 GFP_KERNEL); 916 if (!gpio_dev->saved_regs) 917 return -ENOMEM; 918#endif 919 920 gpio_dev->pdev = pdev; 921 gpio_dev->gc.get_direction = amd_gpio_get_direction; 922 gpio_dev->gc.direction_input = amd_gpio_direction_input; 923 gpio_dev->gc.direction_output = amd_gpio_direction_output; 924 gpio_dev->gc.get = amd_gpio_get_value; 925 gpio_dev->gc.set = amd_gpio_set_value; 926 gpio_dev->gc.set_config = amd_gpio_set_config; 927 gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 928 929 gpio_dev->gc.base = -1; 930 gpio_dev->gc.label = pdev->name; 931 gpio_dev->gc.owner = THIS_MODULE; 932 gpio_dev->gc.parent = &pdev->dev; 933 gpio_dev->gc.ngpio = resource_size(res) / 4; 934#if defined(CONFIG_OF_GPIO) 935 gpio_dev->gc.of_node = pdev->dev.of_node; 936#endif 937 938 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; 939 gpio_dev->groups = kerncz_groups; 940 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 941 942 amd_pinctrl_desc.name = dev_name(&pdev->dev); 943 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 944 gpio_dev); 945 if (IS_ERR(gpio_dev->pctrl)) { 946 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 947 return PTR_ERR(gpio_dev->pctrl); 948 } 949 950 /* Disable and mask interrupts */ 951 amd_gpio_irq_init(gpio_dev); 952 953 girq = &gpio_dev->gc.irq; 954 girq->chip = &amd_gpio_irqchip; 955 /* This will let us handle the parent IRQ in the driver */ 956 girq->parent_handler = NULL; 957 girq->num_parents = 0; 958 girq->parents = NULL; 959 girq->default_type = IRQ_TYPE_NONE; 960 girq->handler = handle_simple_irq; 961 962 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 963 if (ret) 964 return ret; 965 966 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 967 0, 0, gpio_dev->gc.ngpio); 968 if (ret) { 969 dev_err(&pdev->dev, "Failed to add pin range\n"); 970 goto out2; 971 } 972 973 ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 974 IRQF_SHARED, KBUILD_MODNAME, gpio_dev); 975 if (ret) 976 goto out2; 977 978 platform_set_drvdata(pdev, gpio_dev); 979 980 dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 981 return ret; 982 983out2: 984 gpiochip_remove(&gpio_dev->gc); 985 986 return ret; 987} 988 989static int amd_gpio_remove(struct platform_device *pdev) 990{ 991 struct amd_gpio *gpio_dev; 992 993 gpio_dev = platform_get_drvdata(pdev); 994 995 gpiochip_remove(&gpio_dev->gc); 996 997 return 0; 998} 999 1000#ifdef CONFIG_ACPI 1001static const struct acpi_device_id amd_gpio_acpi_match[] = { 1002 { "AMD0030", 0 }, 1003 { "AMDI0030", 0}, 1004 { "AMDI0031", 0}, 1005 { }, 1006}; 1007MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 1008#endif 1009 1010static struct platform_driver amd_gpio_driver = { 1011 .driver = { 1012 .name = "amd_gpio", 1013 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 1014#ifdef CONFIG_PM_SLEEP 1015 .pm = &amd_gpio_pm_ops, 1016#endif 1017 }, 1018 .probe = amd_gpio_probe, 1019 .remove = amd_gpio_remove, 1020}; 1021 1022module_platform_driver(amd_gpio_driver); 1023 1024MODULE_LICENSE("GPL v2"); 1025MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 1026MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 1027