1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Pin controller and GPIO driver for Amlogic Meson SoCs 4 * 5 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> 6 */ 7 8/* 9 * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO, 10 * BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and 11 * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a 12 * variable number of pins. 13 * 14 * The AO bank is special because it belongs to the Always-On power 15 * domain which can't be powered off; the bank also uses a set of 16 * registers different from the other banks. 17 * 18 * For each pin controller there are 4 different register ranges that 19 * control the following properties of the pins: 20 * 1) pin muxing 21 * 2) pull enable/disable 22 * 3) pull up/down 23 * 4) GPIO direction, output value, input value 24 * 25 * In some cases the register ranges for pull enable and pull 26 * direction are the same and thus there are only 3 register ranges. 27 * 28 * Since Meson G12A SoC, the ao register ranges for gpio, pull enable 29 * and pull direction are the same, so there are only 2 register ranges. 30 * 31 * For the pull and GPIO configuration every bank uses a contiguous 32 * set of bits in the register sets described above; the same register 33 * can be shared by more banks with different offsets. 34 * 35 * In addition to this there are some registers shared between all 36 * banks that control the IRQ functionality. This feature is not 37 * supported at the moment by the driver. 38 */ 39 40#include <linux/device.h> 41#include <linux/gpio/driver.h> 42#include <linux/init.h> 43#include <linux/io.h> 44#include <linux/of.h> 45#include <linux/of_address.h> 46#include <linux/of_device.h> 47#include <linux/pinctrl/pinconf-generic.h> 48#include <linux/pinctrl/pinconf.h> 49#include <linux/pinctrl/pinctrl.h> 50#include <linux/pinctrl/pinmux.h> 51#include <linux/platform_device.h> 52#include <linux/regmap.h> 53#include <linux/seq_file.h> 54 55#include "../core.h" 56#include "../pinctrl-utils.h" 57#include "pinctrl-meson.h" 58 59static const unsigned int meson_bit_strides[] = { 60 1, 1, 1, 1, 1, 2, 1 61}; 62 63/** 64 * meson_get_bank() - find the bank containing a given pin 65 * 66 * @pc: the pinctrl instance 67 * @pin: the pin number 68 * @bank: the found bank 69 * 70 * Return: 0 on success, a negative value on error 71 */ 72static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin, 73 struct meson_bank **bank) 74{ 75 int i; 76 77 for (i = 0; i < pc->data->num_banks; i++) { 78 if (pin >= pc->data->banks[i].first && 79 pin <= pc->data->banks[i].last) { 80 *bank = &pc->data->banks[i]; 81 return 0; 82 } 83 } 84 85 return -EINVAL; 86} 87 88/** 89 * meson_calc_reg_and_bit() - calculate register and bit for a pin 90 * 91 * @bank: the bank containing the pin 92 * @pin: the pin number 93 * @reg_type: the type of register needed (pull-enable, pull, etc...) 94 * @reg: the computed register offset 95 * @bit: the computed bit 96 */ 97static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin, 98 enum meson_reg_type reg_type, 99 unsigned int *reg, unsigned int *bit) 100{ 101 struct meson_reg_desc *desc = &bank->regs[reg_type]; 102 103 *bit = (desc->bit + pin - bank->first) * meson_bit_strides[reg_type]; 104 *reg = (desc->reg + (*bit / 32)) * 4; 105 *bit &= 0x1f; 106} 107 108static int meson_get_groups_count(struct pinctrl_dev *pcdev) 109{ 110 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 111 112 return pc->data->num_groups; 113} 114 115static const char *meson_get_group_name(struct pinctrl_dev *pcdev, 116 unsigned selector) 117{ 118 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 119 120 return pc->data->groups[selector].name; 121} 122 123static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector, 124 const unsigned **pins, unsigned *num_pins) 125{ 126 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 127 128 *pins = pc->data->groups[selector].pins; 129 *num_pins = pc->data->groups[selector].num_pins; 130 131 return 0; 132} 133 134static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s, 135 unsigned offset) 136{ 137 seq_printf(s, " %s", dev_name(pcdev->dev)); 138} 139 140static const struct pinctrl_ops meson_pctrl_ops = { 141 .get_groups_count = meson_get_groups_count, 142 .get_group_name = meson_get_group_name, 143 .get_group_pins = meson_get_group_pins, 144 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 145 .dt_free_map = pinctrl_utils_free_map, 146 .pin_dbg_show = meson_pin_dbg_show, 147}; 148 149int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev) 150{ 151 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 152 153 return pc->data->num_funcs; 154} 155 156const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, 157 unsigned selector) 158{ 159 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 160 161 return pc->data->funcs[selector].name; 162} 163 164int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector, 165 const char * const **groups, 166 unsigned * const num_groups) 167{ 168 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 169 170 *groups = pc->data->funcs[selector].groups; 171 *num_groups = pc->data->funcs[selector].num_groups; 172 173 return 0; 174} 175 176static int meson_pinconf_set_gpio_bit(struct meson_pinctrl *pc, 177 unsigned int pin, 178 unsigned int reg_type, 179 bool arg) 180{ 181 struct meson_bank *bank; 182 unsigned int reg, bit; 183 int ret; 184 185 ret = meson_get_bank(pc, pin, &bank); 186 if (ret) 187 return ret; 188 189 meson_calc_reg_and_bit(bank, pin, reg_type, ®, &bit); 190 return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 191 arg ? BIT(bit) : 0); 192} 193 194static int meson_pinconf_get_gpio_bit(struct meson_pinctrl *pc, 195 unsigned int pin, 196 unsigned int reg_type) 197{ 198 struct meson_bank *bank; 199 unsigned int reg, bit, val; 200 int ret; 201 202 ret = meson_get_bank(pc, pin, &bank); 203 if (ret) 204 return ret; 205 206 meson_calc_reg_and_bit(bank, pin, reg_type, ®, &bit); 207 ret = regmap_read(pc->reg_gpio, reg, &val); 208 if (ret) 209 return ret; 210 211 return BIT(bit) & val ? 1 : 0; 212} 213 214static int meson_pinconf_set_output(struct meson_pinctrl *pc, 215 unsigned int pin, 216 bool out) 217{ 218 return meson_pinconf_set_gpio_bit(pc, pin, REG_DIR, !out); 219} 220 221static int meson_pinconf_get_output(struct meson_pinctrl *pc, 222 unsigned int pin) 223{ 224 int ret = meson_pinconf_get_gpio_bit(pc, pin, REG_DIR); 225 226 if (ret < 0) 227 return ret; 228 229 return !ret; 230} 231 232static int meson_pinconf_set_drive(struct meson_pinctrl *pc, 233 unsigned int pin, 234 bool high) 235{ 236 return meson_pinconf_set_gpio_bit(pc, pin, REG_OUT, high); 237} 238 239static int meson_pinconf_get_drive(struct meson_pinctrl *pc, 240 unsigned int pin) 241{ 242 return meson_pinconf_get_gpio_bit(pc, pin, REG_OUT); 243} 244 245static int meson_pinconf_set_output_drive(struct meson_pinctrl *pc, 246 unsigned int pin, 247 bool high) 248{ 249 int ret; 250 251 ret = meson_pinconf_set_output(pc, pin, true); 252 if (ret) 253 return ret; 254 255 return meson_pinconf_set_drive(pc, pin, high); 256} 257 258static int meson_pinconf_disable_bias(struct meson_pinctrl *pc, 259 unsigned int pin) 260{ 261 struct meson_bank *bank; 262 unsigned int reg, bit = 0; 263 int ret; 264 265 ret = meson_get_bank(pc, pin, &bank); 266 if (ret) 267 return ret; 268 269 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); 270 ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), 0); 271 if (ret) 272 return ret; 273 274 return 0; 275} 276 277static int meson_pinconf_enable_bias(struct meson_pinctrl *pc, unsigned int pin, 278 bool pull_up) 279{ 280 struct meson_bank *bank; 281 unsigned int reg, bit, val = 0; 282 int ret; 283 284 ret = meson_get_bank(pc, pin, &bank); 285 if (ret) 286 return ret; 287 288 meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); 289 if (pull_up) 290 val = BIT(bit); 291 292 ret = regmap_update_bits(pc->reg_pull, reg, BIT(bit), val); 293 if (ret) 294 return ret; 295 296 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); 297 ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), BIT(bit)); 298 if (ret) 299 return ret; 300 301 return 0; 302} 303 304static int meson_pinconf_set_drive_strength(struct meson_pinctrl *pc, 305 unsigned int pin, 306 u16 drive_strength_ua) 307{ 308 struct meson_bank *bank; 309 unsigned int reg, bit, ds_val; 310 int ret; 311 312 if (!pc->reg_ds) { 313 dev_err(pc->dev, "drive-strength not supported\n"); 314 return -ENOTSUPP; 315 } 316 317 ret = meson_get_bank(pc, pin, &bank); 318 if (ret) 319 return ret; 320 321 meson_calc_reg_and_bit(bank, pin, REG_DS, ®, &bit); 322 323 if (drive_strength_ua <= 500) { 324 ds_val = MESON_PINCONF_DRV_500UA; 325 } else if (drive_strength_ua <= 2500) { 326 ds_val = MESON_PINCONF_DRV_2500UA; 327 } else if (drive_strength_ua <= 3000) { 328 ds_val = MESON_PINCONF_DRV_3000UA; 329 } else if (drive_strength_ua <= 4000) { 330 ds_val = MESON_PINCONF_DRV_4000UA; 331 } else { 332 dev_warn_once(pc->dev, 333 "pin %u: invalid drive-strength : %d , default to 4mA\n", 334 pin, drive_strength_ua); 335 ds_val = MESON_PINCONF_DRV_4000UA; 336 } 337 338 ret = regmap_update_bits(pc->reg_ds, reg, 0x3 << bit, ds_val << bit); 339 if (ret) 340 return ret; 341 342 return 0; 343} 344 345static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, 346 unsigned long *configs, unsigned num_configs) 347{ 348 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 349 enum pin_config_param param; 350 unsigned int arg = 0; 351 int i, ret; 352 353 for (i = 0; i < num_configs; i++) { 354 param = pinconf_to_config_param(configs[i]); 355 356 switch (param) { 357 case PIN_CONFIG_DRIVE_STRENGTH_UA: 358 case PIN_CONFIG_OUTPUT_ENABLE: 359 case PIN_CONFIG_OUTPUT: 360 arg = pinconf_to_config_argument(configs[i]); 361 break; 362 363 default: 364 break; 365 } 366 367 switch (param) { 368 case PIN_CONFIG_BIAS_DISABLE: 369 ret = meson_pinconf_disable_bias(pc, pin); 370 break; 371 case PIN_CONFIG_BIAS_PULL_UP: 372 ret = meson_pinconf_enable_bias(pc, pin, true); 373 break; 374 case PIN_CONFIG_BIAS_PULL_DOWN: 375 ret = meson_pinconf_enable_bias(pc, pin, false); 376 break; 377 case PIN_CONFIG_DRIVE_STRENGTH_UA: 378 ret = meson_pinconf_set_drive_strength(pc, pin, arg); 379 break; 380 case PIN_CONFIG_OUTPUT_ENABLE: 381 ret = meson_pinconf_set_output(pc, pin, arg); 382 break; 383 case PIN_CONFIG_OUTPUT: 384 ret = meson_pinconf_set_output_drive(pc, pin, arg); 385 break; 386 default: 387 ret = -ENOTSUPP; 388 } 389 390 if (ret) 391 return ret; 392 } 393 394 return 0; 395} 396 397static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin) 398{ 399 struct meson_bank *bank; 400 unsigned int reg, bit, val; 401 int ret, conf; 402 403 ret = meson_get_bank(pc, pin, &bank); 404 if (ret) 405 return ret; 406 407 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); 408 409 ret = regmap_read(pc->reg_pullen, reg, &val); 410 if (ret) 411 return ret; 412 413 if (!(val & BIT(bit))) { 414 conf = PIN_CONFIG_BIAS_DISABLE; 415 } else { 416 meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); 417 418 ret = regmap_read(pc->reg_pull, reg, &val); 419 if (ret) 420 return ret; 421 422 if (val & BIT(bit)) 423 conf = PIN_CONFIG_BIAS_PULL_UP; 424 else 425 conf = PIN_CONFIG_BIAS_PULL_DOWN; 426 } 427 428 return conf; 429} 430 431static int meson_pinconf_get_drive_strength(struct meson_pinctrl *pc, 432 unsigned int pin, 433 u16 *drive_strength_ua) 434{ 435 struct meson_bank *bank; 436 unsigned int reg, bit; 437 unsigned int val; 438 int ret; 439 440 if (!pc->reg_ds) 441 return -ENOTSUPP; 442 443 ret = meson_get_bank(pc, pin, &bank); 444 if (ret) 445 return ret; 446 447 meson_calc_reg_and_bit(bank, pin, REG_DS, ®, &bit); 448 449 ret = regmap_read(pc->reg_ds, reg, &val); 450 if (ret) 451 return ret; 452 453 switch ((val >> bit) & 0x3) { 454 case MESON_PINCONF_DRV_500UA: 455 *drive_strength_ua = 500; 456 break; 457 case MESON_PINCONF_DRV_2500UA: 458 *drive_strength_ua = 2500; 459 break; 460 case MESON_PINCONF_DRV_3000UA: 461 *drive_strength_ua = 3000; 462 break; 463 case MESON_PINCONF_DRV_4000UA: 464 *drive_strength_ua = 4000; 465 break; 466 default: 467 return -EINVAL; 468 } 469 470 return 0; 471} 472 473static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, 474 unsigned long *config) 475{ 476 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 477 enum pin_config_param param = pinconf_to_config_param(*config); 478 u16 arg; 479 int ret; 480 481 switch (param) { 482 case PIN_CONFIG_BIAS_DISABLE: 483 case PIN_CONFIG_BIAS_PULL_DOWN: 484 case PIN_CONFIG_BIAS_PULL_UP: 485 if (meson_pinconf_get_pull(pc, pin) == param) 486 arg = 1; 487 else 488 return -EINVAL; 489 break; 490 case PIN_CONFIG_DRIVE_STRENGTH_UA: 491 ret = meson_pinconf_get_drive_strength(pc, pin, &arg); 492 if (ret) 493 return ret; 494 break; 495 case PIN_CONFIG_OUTPUT_ENABLE: 496 ret = meson_pinconf_get_output(pc, pin); 497 if (ret <= 0) 498 return -EINVAL; 499 arg = 1; 500 break; 501 case PIN_CONFIG_OUTPUT: 502 ret = meson_pinconf_get_output(pc, pin); 503 if (ret <= 0) 504 return -EINVAL; 505 506 ret = meson_pinconf_get_drive(pc, pin); 507 if (ret < 0) 508 return -EINVAL; 509 510 arg = ret; 511 break; 512 513 default: 514 return -ENOTSUPP; 515 } 516 517 *config = pinconf_to_config_packed(param, arg); 518 dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config); 519 520 return 0; 521} 522 523static int meson_pinconf_group_set(struct pinctrl_dev *pcdev, 524 unsigned int num_group, 525 unsigned long *configs, unsigned num_configs) 526{ 527 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 528 struct meson_pmx_group *group = &pc->data->groups[num_group]; 529 int i; 530 531 dev_dbg(pc->dev, "set pinconf for group %s\n", group->name); 532 533 for (i = 0; i < group->num_pins; i++) { 534 meson_pinconf_set(pcdev, group->pins[i], configs, 535 num_configs); 536 } 537 538 return 0; 539} 540 541static int meson_pinconf_group_get(struct pinctrl_dev *pcdev, 542 unsigned int group, unsigned long *config) 543{ 544 return -ENOTSUPP; 545} 546 547static const struct pinconf_ops meson_pinconf_ops = { 548 .pin_config_get = meson_pinconf_get, 549 .pin_config_set = meson_pinconf_set, 550 .pin_config_group_get = meson_pinconf_group_get, 551 .pin_config_group_set = meson_pinconf_group_set, 552 .is_generic = true, 553}; 554 555static int meson_gpio_get_direction(struct gpio_chip *chip, unsigned gpio) 556{ 557 struct meson_pinctrl *pc = gpiochip_get_data(chip); 558 int ret; 559 560 ret = meson_pinconf_get_output(pc, gpio); 561 if (ret < 0) 562 return ret; 563 564 return ret ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 565} 566 567static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 568{ 569 return meson_pinconf_set_output(gpiochip_get_data(chip), gpio, false); 570} 571 572static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, 573 int value) 574{ 575 return meson_pinconf_set_output_drive(gpiochip_get_data(chip), 576 gpio, value); 577} 578 579static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) 580{ 581 meson_pinconf_set_drive(gpiochip_get_data(chip), gpio, value); 582} 583 584static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) 585{ 586 struct meson_pinctrl *pc = gpiochip_get_data(chip); 587 unsigned int reg, bit, val; 588 struct meson_bank *bank; 589 int ret; 590 591 ret = meson_get_bank(pc, gpio, &bank); 592 if (ret) 593 return ret; 594 595 meson_calc_reg_and_bit(bank, gpio, REG_IN, ®, &bit); 596 regmap_read(pc->reg_gpio, reg, &val); 597 598 return !!(val & BIT(bit)); 599} 600 601static int meson_gpiolib_register(struct meson_pinctrl *pc) 602{ 603 int ret; 604 605 pc->chip.label = pc->data->name; 606 pc->chip.parent = pc->dev; 607 pc->chip.request = gpiochip_generic_request; 608 pc->chip.free = gpiochip_generic_free; 609 pc->chip.set_config = gpiochip_generic_config; 610 pc->chip.get_direction = meson_gpio_get_direction; 611 pc->chip.direction_input = meson_gpio_direction_input; 612 pc->chip.direction_output = meson_gpio_direction_output; 613 pc->chip.get = meson_gpio_get; 614 pc->chip.set = meson_gpio_set; 615 pc->chip.base = -1; 616 pc->chip.ngpio = pc->data->num_pins; 617 pc->chip.can_sleep = false; 618 pc->chip.of_node = pc->of_node; 619 pc->chip.of_gpio_n_cells = 2; 620 621 ret = gpiochip_add_data(&pc->chip, pc); 622 if (ret) { 623 dev_err(pc->dev, "can't add gpio chip %s\n", 624 pc->data->name); 625 return ret; 626 } 627 628 return 0; 629} 630 631static struct regmap_config meson_regmap_config = { 632 .reg_bits = 32, 633 .val_bits = 32, 634 .reg_stride = 4, 635}; 636 637static struct regmap *meson_map_resource(struct meson_pinctrl *pc, 638 struct device_node *node, char *name) 639{ 640 struct resource res; 641 void __iomem *base; 642 int i; 643 644 i = of_property_match_string(node, "reg-names", name); 645 if (of_address_to_resource(node, i, &res)) 646 return NULL; 647 648 base = devm_ioremap_resource(pc->dev, &res); 649 if (IS_ERR(base)) 650 return ERR_CAST(base); 651 652 meson_regmap_config.max_register = resource_size(&res) - 4; 653 meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL, 654 "%pOFn-%s", node, 655 name); 656 if (!meson_regmap_config.name) 657 return ERR_PTR(-ENOMEM); 658 659 return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config); 660} 661 662static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, 663 struct device_node *node) 664{ 665 struct device_node *np, *gpio_np = NULL; 666 667 for_each_child_of_node(node, np) { 668 if (!of_find_property(np, "gpio-controller", NULL)) 669 continue; 670 if (gpio_np) { 671 dev_err(pc->dev, "multiple gpio nodes\n"); 672 of_node_put(np); 673 return -EINVAL; 674 } 675 gpio_np = np; 676 } 677 678 if (!gpio_np) { 679 dev_err(pc->dev, "no gpio node found\n"); 680 return -EINVAL; 681 } 682 683 pc->of_node = gpio_np; 684 685 pc->reg_mux = meson_map_resource(pc, gpio_np, "mux"); 686 if (IS_ERR_OR_NULL(pc->reg_mux)) { 687 dev_err(pc->dev, "mux registers not found\n"); 688 return pc->reg_mux ? PTR_ERR(pc->reg_mux) : -ENOENT; 689 } 690 691 pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio"); 692 if (IS_ERR_OR_NULL(pc->reg_gpio)) { 693 dev_err(pc->dev, "gpio registers not found\n"); 694 return pc->reg_gpio ? PTR_ERR(pc->reg_gpio) : -ENOENT; 695 } 696 697 pc->reg_pull = meson_map_resource(pc, gpio_np, "pull"); 698 if (IS_ERR(pc->reg_pull)) 699 pc->reg_pull = NULL; 700 701 pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable"); 702 if (IS_ERR(pc->reg_pullen)) 703 pc->reg_pullen = NULL; 704 705 pc->reg_ds = meson_map_resource(pc, gpio_np, "ds"); 706 if (IS_ERR(pc->reg_ds)) { 707 dev_dbg(pc->dev, "ds registers not found - skipping\n"); 708 pc->reg_ds = NULL; 709 } 710 711 if (pc->data->parse_dt) 712 return pc->data->parse_dt(pc); 713 714 return 0; 715} 716 717int meson8_aobus_parse_dt_extra(struct meson_pinctrl *pc) 718{ 719 if (!pc->reg_pull) 720 return -EINVAL; 721 722 pc->reg_pullen = pc->reg_pull; 723 724 return 0; 725} 726 727int meson_a1_parse_dt_extra(struct meson_pinctrl *pc) 728{ 729 pc->reg_pull = pc->reg_gpio; 730 pc->reg_pullen = pc->reg_gpio; 731 pc->reg_ds = pc->reg_gpio; 732 733 return 0; 734} 735 736int meson_pinctrl_probe(struct platform_device *pdev) 737{ 738 struct device *dev = &pdev->dev; 739 struct meson_pinctrl *pc; 740 int ret; 741 742 pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL); 743 if (!pc) 744 return -ENOMEM; 745 746 pc->dev = dev; 747 pc->data = (struct meson_pinctrl_data *) of_device_get_match_data(dev); 748 749 ret = meson_pinctrl_parse_dt(pc, dev->of_node); 750 if (ret) 751 return ret; 752 753 pc->desc.name = "pinctrl-meson"; 754 pc->desc.owner = THIS_MODULE; 755 pc->desc.pctlops = &meson_pctrl_ops; 756 pc->desc.pmxops = pc->data->pmx_ops; 757 pc->desc.confops = &meson_pinconf_ops; 758 pc->desc.pins = pc->data->pins; 759 pc->desc.npins = pc->data->num_pins; 760 761 pc->pcdev = devm_pinctrl_register(pc->dev, &pc->desc, pc); 762 if (IS_ERR(pc->pcdev)) { 763 dev_err(pc->dev, "can't register pinctrl device"); 764 return PTR_ERR(pc->pcdev); 765 } 766 767 return meson_gpiolib_register(pc); 768} 769