18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (c) 2014 MediaTek Inc. 48c2ecf20Sopenharmony_ci * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> 58c2ecf20Sopenharmony_ci */ 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ci#ifndef __PINCTRL_MTK_COMMON_H 88c2ecf20Sopenharmony_ci#define __PINCTRL_MTK_COMMON_H 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci#include <linux/pinctrl/pinctrl.h> 118c2ecf20Sopenharmony_ci#include <linux/regmap.h> 128c2ecf20Sopenharmony_ci#include <linux/pinctrl/pinconf-generic.h> 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci#include "mtk-eint.h" 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci#define NO_EINT_SUPPORT 255 178c2ecf20Sopenharmony_ci#define MT_EDGE_SENSITIVE 0 188c2ecf20Sopenharmony_ci#define MT_LEVEL_SENSITIVE 1 198c2ecf20Sopenharmony_ci#define EINT_DBNC_SET_DBNC_BITS 4 208c2ecf20Sopenharmony_ci#define EINT_DBNC_RST_BIT (0x1 << 1) 218c2ecf20Sopenharmony_ci#define EINT_DBNC_SET_EN (0x1 << 0) 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci#define MTK_PINCTRL_NOT_SUPPORT (0xffff) 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_cistruct mtk_desc_function { 268c2ecf20Sopenharmony_ci const char *name; 278c2ecf20Sopenharmony_ci unsigned char muxval; 288c2ecf20Sopenharmony_ci}; 298c2ecf20Sopenharmony_ci 308c2ecf20Sopenharmony_cistruct mtk_desc_eint { 318c2ecf20Sopenharmony_ci unsigned char eintmux; 328c2ecf20Sopenharmony_ci unsigned char eintnum; 338c2ecf20Sopenharmony_ci}; 348c2ecf20Sopenharmony_ci 358c2ecf20Sopenharmony_cistruct mtk_desc_pin { 368c2ecf20Sopenharmony_ci struct pinctrl_pin_desc pin; 378c2ecf20Sopenharmony_ci const struct mtk_desc_eint eint; 388c2ecf20Sopenharmony_ci const struct mtk_desc_function *functions; 398c2ecf20Sopenharmony_ci}; 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ci#define MTK_PIN(_pin, _pad, _chip, _eint, ...) \ 428c2ecf20Sopenharmony_ci { \ 438c2ecf20Sopenharmony_ci .pin = _pin, \ 448c2ecf20Sopenharmony_ci .eint = _eint, \ 458c2ecf20Sopenharmony_ci .functions = (struct mtk_desc_function[]){ \ 468c2ecf20Sopenharmony_ci __VA_ARGS__, { } }, \ 478c2ecf20Sopenharmony_ci } 488c2ecf20Sopenharmony_ci 498c2ecf20Sopenharmony_ci#define MTK_EINT_FUNCTION(_eintmux, _eintnum) \ 508c2ecf20Sopenharmony_ci { \ 518c2ecf20Sopenharmony_ci .eintmux = _eintmux, \ 528c2ecf20Sopenharmony_ci .eintnum = _eintnum, \ 538c2ecf20Sopenharmony_ci } 548c2ecf20Sopenharmony_ci 558c2ecf20Sopenharmony_ci#define MTK_FUNCTION(_val, _name) \ 568c2ecf20Sopenharmony_ci { \ 578c2ecf20Sopenharmony_ci .muxval = _val, \ 588c2ecf20Sopenharmony_ci .name = _name, \ 598c2ecf20Sopenharmony_ci } 608c2ecf20Sopenharmony_ci 618c2ecf20Sopenharmony_ci#define SET_ADDR(x, y) (x + (y->devdata->port_align)) 628c2ecf20Sopenharmony_ci#define CLR_ADDR(x, y) (x + (y->devdata->port_align << 1)) 638c2ecf20Sopenharmony_ci 648c2ecf20Sopenharmony_cistruct mtk_pinctrl_group { 658c2ecf20Sopenharmony_ci const char *name; 668c2ecf20Sopenharmony_ci unsigned long config; 678c2ecf20Sopenharmony_ci unsigned pin; 688c2ecf20Sopenharmony_ci}; 698c2ecf20Sopenharmony_ci 708c2ecf20Sopenharmony_ci/** 718c2ecf20Sopenharmony_ci * struct mtk_drv_group_desc - Provide driving group data. 728c2ecf20Sopenharmony_ci * @max_drv: The maximum current of this group. 738c2ecf20Sopenharmony_ci * @min_drv: The minimum current of this group. 748c2ecf20Sopenharmony_ci * @low_bit: The lowest bit of this group. 758c2ecf20Sopenharmony_ci * @high_bit: The highest bit of this group. 768c2ecf20Sopenharmony_ci * @step: The step current of this group. 778c2ecf20Sopenharmony_ci */ 788c2ecf20Sopenharmony_cistruct mtk_drv_group_desc { 798c2ecf20Sopenharmony_ci unsigned char min_drv; 808c2ecf20Sopenharmony_ci unsigned char max_drv; 818c2ecf20Sopenharmony_ci unsigned char low_bit; 828c2ecf20Sopenharmony_ci unsigned char high_bit; 838c2ecf20Sopenharmony_ci unsigned char step; 848c2ecf20Sopenharmony_ci}; 858c2ecf20Sopenharmony_ci 868c2ecf20Sopenharmony_ci#define MTK_DRV_GRP(_min, _max, _low, _high, _step) \ 878c2ecf20Sopenharmony_ci { \ 888c2ecf20Sopenharmony_ci .min_drv = _min, \ 898c2ecf20Sopenharmony_ci .max_drv = _max, \ 908c2ecf20Sopenharmony_ci .low_bit = _low, \ 918c2ecf20Sopenharmony_ci .high_bit = _high, \ 928c2ecf20Sopenharmony_ci .step = _step, \ 938c2ecf20Sopenharmony_ci } 948c2ecf20Sopenharmony_ci 958c2ecf20Sopenharmony_ci/** 968c2ecf20Sopenharmony_ci * struct mtk_pin_drv_grp - Provide each pin driving info. 978c2ecf20Sopenharmony_ci * @pin: The pin number. 988c2ecf20Sopenharmony_ci * @offset: The offset of driving register for this pin. 998c2ecf20Sopenharmony_ci * @bit: The bit of driving register for this pin. 1008c2ecf20Sopenharmony_ci * @grp: The group for this pin belongs to. 1018c2ecf20Sopenharmony_ci */ 1028c2ecf20Sopenharmony_cistruct mtk_pin_drv_grp { 1038c2ecf20Sopenharmony_ci unsigned short pin; 1048c2ecf20Sopenharmony_ci unsigned short offset; 1058c2ecf20Sopenharmony_ci unsigned char bit; 1068c2ecf20Sopenharmony_ci unsigned char grp; 1078c2ecf20Sopenharmony_ci}; 1088c2ecf20Sopenharmony_ci 1098c2ecf20Sopenharmony_ci#define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \ 1108c2ecf20Sopenharmony_ci { \ 1118c2ecf20Sopenharmony_ci .pin = _pin, \ 1128c2ecf20Sopenharmony_ci .offset = _offset, \ 1138c2ecf20Sopenharmony_ci .bit = _bit, \ 1148c2ecf20Sopenharmony_ci .grp = _grp, \ 1158c2ecf20Sopenharmony_ci } 1168c2ecf20Sopenharmony_ci 1178c2ecf20Sopenharmony_ci/** 1188c2ecf20Sopenharmony_ci * struct mtk_pin_spec_pupd_set_samereg 1198c2ecf20Sopenharmony_ci * - For special pins' pull up/down setting which resides in same register 1208c2ecf20Sopenharmony_ci * @pin: The pin number. 1218c2ecf20Sopenharmony_ci * @offset: The offset of special pull up/down setting register. 1228c2ecf20Sopenharmony_ci * @pupd_bit: The pull up/down bit in this register. 1238c2ecf20Sopenharmony_ci * @r0_bit: The r0 bit of pull resistor. 1248c2ecf20Sopenharmony_ci * @r1_bit: The r1 bit of pull resistor. 1258c2ecf20Sopenharmony_ci */ 1268c2ecf20Sopenharmony_cistruct mtk_pin_spec_pupd_set_samereg { 1278c2ecf20Sopenharmony_ci unsigned short pin; 1288c2ecf20Sopenharmony_ci unsigned short offset; 1298c2ecf20Sopenharmony_ci unsigned char pupd_bit; 1308c2ecf20Sopenharmony_ci unsigned char r1_bit; 1318c2ecf20Sopenharmony_ci unsigned char r0_bit; 1328c2ecf20Sopenharmony_ci}; 1338c2ecf20Sopenharmony_ci 1348c2ecf20Sopenharmony_ci#define MTK_PIN_PUPD_SPEC_SR(_pin, _offset, _pupd, _r1, _r0) \ 1358c2ecf20Sopenharmony_ci { \ 1368c2ecf20Sopenharmony_ci .pin = _pin, \ 1378c2ecf20Sopenharmony_ci .offset = _offset, \ 1388c2ecf20Sopenharmony_ci .pupd_bit = _pupd, \ 1398c2ecf20Sopenharmony_ci .r1_bit = _r1, \ 1408c2ecf20Sopenharmony_ci .r0_bit = _r0, \ 1418c2ecf20Sopenharmony_ci } 1428c2ecf20Sopenharmony_ci 1438c2ecf20Sopenharmony_ci/** 1448c2ecf20Sopenharmony_ci * struct mtk_pin_ies_set - For special pins' ies and smt setting. 1458c2ecf20Sopenharmony_ci * @start: The start pin number of those special pins. 1468c2ecf20Sopenharmony_ci * @end: The end pin number of those special pins. 1478c2ecf20Sopenharmony_ci * @offset: The offset of special setting register. 1488c2ecf20Sopenharmony_ci * @bit: The bit of special setting register. 1498c2ecf20Sopenharmony_ci */ 1508c2ecf20Sopenharmony_cistruct mtk_pin_ies_smt_set { 1518c2ecf20Sopenharmony_ci unsigned short start; 1528c2ecf20Sopenharmony_ci unsigned short end; 1538c2ecf20Sopenharmony_ci unsigned short offset; 1548c2ecf20Sopenharmony_ci unsigned char bit; 1558c2ecf20Sopenharmony_ci}; 1568c2ecf20Sopenharmony_ci 1578c2ecf20Sopenharmony_ci#define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \ 1588c2ecf20Sopenharmony_ci { \ 1598c2ecf20Sopenharmony_ci .start = _start, \ 1608c2ecf20Sopenharmony_ci .end = _end, \ 1618c2ecf20Sopenharmony_ci .bit = _bit, \ 1628c2ecf20Sopenharmony_ci .offset = _offset, \ 1638c2ecf20Sopenharmony_ci } 1648c2ecf20Sopenharmony_ci 1658c2ecf20Sopenharmony_cistruct mtk_eint_offsets { 1668c2ecf20Sopenharmony_ci const char *name; 1678c2ecf20Sopenharmony_ci unsigned int stat; 1688c2ecf20Sopenharmony_ci unsigned int ack; 1698c2ecf20Sopenharmony_ci unsigned int mask; 1708c2ecf20Sopenharmony_ci unsigned int mask_set; 1718c2ecf20Sopenharmony_ci unsigned int mask_clr; 1728c2ecf20Sopenharmony_ci unsigned int sens; 1738c2ecf20Sopenharmony_ci unsigned int sens_set; 1748c2ecf20Sopenharmony_ci unsigned int sens_clr; 1758c2ecf20Sopenharmony_ci unsigned int soft; 1768c2ecf20Sopenharmony_ci unsigned int soft_set; 1778c2ecf20Sopenharmony_ci unsigned int soft_clr; 1788c2ecf20Sopenharmony_ci unsigned int pol; 1798c2ecf20Sopenharmony_ci unsigned int pol_set; 1808c2ecf20Sopenharmony_ci unsigned int pol_clr; 1818c2ecf20Sopenharmony_ci unsigned int dom_en; 1828c2ecf20Sopenharmony_ci unsigned int dbnc_ctrl; 1838c2ecf20Sopenharmony_ci unsigned int dbnc_set; 1848c2ecf20Sopenharmony_ci unsigned int dbnc_clr; 1858c2ecf20Sopenharmony_ci u8 port_mask; 1868c2ecf20Sopenharmony_ci u8 ports; 1878c2ecf20Sopenharmony_ci}; 1888c2ecf20Sopenharmony_ci 1898c2ecf20Sopenharmony_ci/** 1908c2ecf20Sopenharmony_ci * struct mtk_pinctrl_devdata - Provide HW GPIO related data. 1918c2ecf20Sopenharmony_ci * @pins: An array describing all pins the pin controller affects. 1928c2ecf20Sopenharmony_ci * @npins: The number of entries in @pins. 1938c2ecf20Sopenharmony_ci * 1948c2ecf20Sopenharmony_ci * @grp_desc: The driving group info. 1958c2ecf20Sopenharmony_ci * @pin_drv_grp: The driving group for all pins. 1968c2ecf20Sopenharmony_ci * @spec_pull_set: Each SoC may have special pins for pull up/down setting, 1978c2ecf20Sopenharmony_ci * these pins' pull setting are very different, they have separate pull 1988c2ecf20Sopenharmony_ci * up/down bit, R0 and R1 resistor bit, so they need special pull setting. 1998c2ecf20Sopenharmony_ci * If special setting is success, this should return 0, otherwise it should 2008c2ecf20Sopenharmony_ci * return non-zero value. 2018c2ecf20Sopenharmony_ci * @spec_ies_smt_set: Some pins are irregular, their input enable and smt 2028c2ecf20Sopenharmony_ci * control register are discontinuous, but they are mapping together. That 2038c2ecf20Sopenharmony_ci * means when user set smt, input enable is set at the same time. So they 2048c2ecf20Sopenharmony_ci * also need special control. If special control is success, this should 2058c2ecf20Sopenharmony_ci * return 0, otherwise return non-zero value. 2068c2ecf20Sopenharmony_ci * @spec_pinmux_set: In some cases, there are two pinmux functions share 2078c2ecf20Sopenharmony_ci * the same value in the same segment of pinmux control register. If user 2088c2ecf20Sopenharmony_ci * want to use one of the two functions, they need an extra bit setting to 2098c2ecf20Sopenharmony_ci * select the right one. 2108c2ecf20Sopenharmony_ci * @spec_dir_set: In very few SoCs, direction control registers are not 2118c2ecf20Sopenharmony_ci * arranged continuously, they may be cut to parts. So they need special 2128c2ecf20Sopenharmony_ci * dir setting. 2138c2ecf20Sopenharmony_ci 2148c2ecf20Sopenharmony_ci * @dir_offset: The direction register offset. 2158c2ecf20Sopenharmony_ci * @pullen_offset: The pull-up/pull-down enable register offset. 2168c2ecf20Sopenharmony_ci * @pinmux_offset: The pinmux register offset. 2178c2ecf20Sopenharmony_ci * 2188c2ecf20Sopenharmony_ci * @type1_start: Some chips have two base addresses for pull select register, 2198c2ecf20Sopenharmony_ci * that means some pins use the first address and others use the second. This 2208c2ecf20Sopenharmony_ci * member record the start of pin number to use the second address. 2218c2ecf20Sopenharmony_ci * @type1_end: The end of pin number to use the second address. 2228c2ecf20Sopenharmony_ci * 2238c2ecf20Sopenharmony_ci * @port_shf: The shift between two registers. 2248c2ecf20Sopenharmony_ci * @port_mask: The mask of register. 2258c2ecf20Sopenharmony_ci * @port_align: Provide clear register and set register step. 2268c2ecf20Sopenharmony_ci */ 2278c2ecf20Sopenharmony_cistruct mtk_pinctrl_devdata { 2288c2ecf20Sopenharmony_ci const struct mtk_desc_pin *pins; 2298c2ecf20Sopenharmony_ci unsigned int npins; 2308c2ecf20Sopenharmony_ci const struct mtk_drv_group_desc *grp_desc; 2318c2ecf20Sopenharmony_ci unsigned int n_grp_cls; 2328c2ecf20Sopenharmony_ci const struct mtk_pin_drv_grp *pin_drv_grp; 2338c2ecf20Sopenharmony_ci unsigned int n_pin_drv_grps; 2348c2ecf20Sopenharmony_ci int (*spec_pull_set)(struct regmap *reg, unsigned int pin, 2358c2ecf20Sopenharmony_ci unsigned char align, bool isup, unsigned int arg); 2368c2ecf20Sopenharmony_ci int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin, 2378c2ecf20Sopenharmony_ci unsigned char align, int value, enum pin_config_param arg); 2388c2ecf20Sopenharmony_ci void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin, 2398c2ecf20Sopenharmony_ci unsigned int mode); 2408c2ecf20Sopenharmony_ci void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin); 2418c2ecf20Sopenharmony_ci unsigned int dir_offset; 2428c2ecf20Sopenharmony_ci unsigned int ies_offset; 2438c2ecf20Sopenharmony_ci unsigned int smt_offset; 2448c2ecf20Sopenharmony_ci unsigned int pullen_offset; 2458c2ecf20Sopenharmony_ci unsigned int pullsel_offset; 2468c2ecf20Sopenharmony_ci unsigned int drv_offset; 2478c2ecf20Sopenharmony_ci unsigned int dout_offset; 2488c2ecf20Sopenharmony_ci unsigned int din_offset; 2498c2ecf20Sopenharmony_ci unsigned int pinmux_offset; 2508c2ecf20Sopenharmony_ci unsigned short type1_start; 2518c2ecf20Sopenharmony_ci unsigned short type1_end; 2528c2ecf20Sopenharmony_ci unsigned char port_shf; 2538c2ecf20Sopenharmony_ci unsigned char port_mask; 2548c2ecf20Sopenharmony_ci unsigned char port_align; 2558c2ecf20Sopenharmony_ci struct mtk_eint_hw eint_hw; 2568c2ecf20Sopenharmony_ci struct mtk_eint_regs *eint_regs; 2578c2ecf20Sopenharmony_ci}; 2588c2ecf20Sopenharmony_ci 2598c2ecf20Sopenharmony_cistruct mtk_pinctrl { 2608c2ecf20Sopenharmony_ci struct regmap *regmap1; 2618c2ecf20Sopenharmony_ci struct regmap *regmap2; 2628c2ecf20Sopenharmony_ci struct pinctrl_desc pctl_desc; 2638c2ecf20Sopenharmony_ci struct device *dev; 2648c2ecf20Sopenharmony_ci struct gpio_chip *chip; 2658c2ecf20Sopenharmony_ci struct mtk_pinctrl_group *groups; 2668c2ecf20Sopenharmony_ci unsigned ngroups; 2678c2ecf20Sopenharmony_ci const char **grp_names; 2688c2ecf20Sopenharmony_ci struct pinctrl_dev *pctl_dev; 2698c2ecf20Sopenharmony_ci const struct mtk_pinctrl_devdata *devdata; 2708c2ecf20Sopenharmony_ci struct mtk_eint *eint; 2718c2ecf20Sopenharmony_ci}; 2728c2ecf20Sopenharmony_ci 2738c2ecf20Sopenharmony_ciint mtk_pctrl_init(struct platform_device *pdev, 2748c2ecf20Sopenharmony_ci const struct mtk_pinctrl_devdata *data, 2758c2ecf20Sopenharmony_ci struct regmap *regmap); 2768c2ecf20Sopenharmony_ci 2778c2ecf20Sopenharmony_ciint mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, 2788c2ecf20Sopenharmony_ci const struct mtk_pin_spec_pupd_set_samereg *pupd_infos, 2798c2ecf20Sopenharmony_ci unsigned int info_num, unsigned int pin, 2808c2ecf20Sopenharmony_ci unsigned char align, bool isup, unsigned int r1r0); 2818c2ecf20Sopenharmony_ci 2828c2ecf20Sopenharmony_ciint mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, 2838c2ecf20Sopenharmony_ci const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num, 2848c2ecf20Sopenharmony_ci unsigned int pin, unsigned char align, int value); 2858c2ecf20Sopenharmony_ci 2868c2ecf20Sopenharmony_ciextern const struct dev_pm_ops mtk_eint_pm_ops; 2878c2ecf20Sopenharmony_ci 2888c2ecf20Sopenharmony_ci#endif /* __PINCTRL_MTK_COMMON_H */ 289