18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-only 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (c) 2015 MediaTek Inc. 48c2ecf20Sopenharmony_ci * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> 58c2ecf20Sopenharmony_ci */ 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ci#include <linux/init.h> 88c2ecf20Sopenharmony_ci#include <linux/platform_device.h> 98c2ecf20Sopenharmony_ci#include <linux/of.h> 108c2ecf20Sopenharmony_ci#include <linux/of_device.h> 118c2ecf20Sopenharmony_ci#include <linux/pinctrl/pinctrl.h> 128c2ecf20Sopenharmony_ci#include <linux/pinctrl/pinconf-generic.h> 138c2ecf20Sopenharmony_ci#include <linux/mfd/mt6397/core.h> 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ci#include "pinctrl-mtk-common.h" 168c2ecf20Sopenharmony_ci#include "pinctrl-mtk-mt6397.h" 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ci#define MT6397_PIN_REG_BASE 0xc000 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_cistatic const struct mtk_pinctrl_devdata mt6397_pinctrl_data = { 218c2ecf20Sopenharmony_ci .pins = mtk_pins_mt6397, 228c2ecf20Sopenharmony_ci .npins = ARRAY_SIZE(mtk_pins_mt6397), 238c2ecf20Sopenharmony_ci .dir_offset = (MT6397_PIN_REG_BASE + 0x000), 248c2ecf20Sopenharmony_ci .ies_offset = MTK_PINCTRL_NOT_SUPPORT, 258c2ecf20Sopenharmony_ci .smt_offset = MTK_PINCTRL_NOT_SUPPORT, 268c2ecf20Sopenharmony_ci .pullen_offset = (MT6397_PIN_REG_BASE + 0x020), 278c2ecf20Sopenharmony_ci .pullsel_offset = (MT6397_PIN_REG_BASE + 0x040), 288c2ecf20Sopenharmony_ci .dout_offset = (MT6397_PIN_REG_BASE + 0x080), 298c2ecf20Sopenharmony_ci .din_offset = (MT6397_PIN_REG_BASE + 0x0a0), 308c2ecf20Sopenharmony_ci .pinmux_offset = (MT6397_PIN_REG_BASE + 0x0c0), 318c2ecf20Sopenharmony_ci .type1_start = 41, 328c2ecf20Sopenharmony_ci .type1_end = 41, 338c2ecf20Sopenharmony_ci .port_shf = 3, 348c2ecf20Sopenharmony_ci .port_mask = 0x3, 358c2ecf20Sopenharmony_ci .port_align = 2, 368c2ecf20Sopenharmony_ci}; 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_cistatic int mt6397_pinctrl_probe(struct platform_device *pdev) 398c2ecf20Sopenharmony_ci{ 408c2ecf20Sopenharmony_ci struct mt6397_chip *mt6397; 418c2ecf20Sopenharmony_ci 428c2ecf20Sopenharmony_ci mt6397 = dev_get_drvdata(pdev->dev.parent); 438c2ecf20Sopenharmony_ci return mtk_pctrl_init(pdev, &mt6397_pinctrl_data, mt6397->regmap); 448c2ecf20Sopenharmony_ci} 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_cistatic const struct of_device_id mt6397_pctrl_match[] = { 478c2ecf20Sopenharmony_ci { .compatible = "mediatek,mt6397-pinctrl", }, 488c2ecf20Sopenharmony_ci { } 498c2ecf20Sopenharmony_ci}; 508c2ecf20Sopenharmony_ci 518c2ecf20Sopenharmony_cistatic struct platform_driver mtk_pinctrl_driver = { 528c2ecf20Sopenharmony_ci .probe = mt6397_pinctrl_probe, 538c2ecf20Sopenharmony_ci .driver = { 548c2ecf20Sopenharmony_ci .name = "mediatek-mt6397-pinctrl", 558c2ecf20Sopenharmony_ci .of_match_table = mt6397_pctrl_match, 568c2ecf20Sopenharmony_ci }, 578c2ecf20Sopenharmony_ci}; 588c2ecf20Sopenharmony_ci 598c2ecf20Sopenharmony_cibuiltin_platform_driver(mtk_pinctrl_driver); 60