1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2014-2018 MediaTek Inc.
3
4/*
5 * Library for MediaTek External Interrupt Support
6 *
7 * Author: Maoguang Meng <maoguang.meng@mediatek.com>
8 *	   Sean Wang <sean.wang@mediatek.com>
9 *
10 */
11
12#include <linux/delay.h>
13#include <linux/err.h>
14#include <linux/gpio/driver.h>
15#include <linux/io.h>
16#include <linux/irqchip/chained_irq.h>
17#include <linux/irqdomain.h>
18#include <linux/module.h>
19#include <linux/of_irq.h>
20#include <linux/platform_device.h>
21
22#include "mtk-eint.h"
23
24#define MTK_EINT_EDGE_SENSITIVE           0
25#define MTK_EINT_LEVEL_SENSITIVE          1
26#define MTK_EINT_DBNC_SET_DBNC_BITS	  4
27#define MTK_EINT_DBNC_RST_BIT		  (0x1 << 1)
28#define MTK_EINT_DBNC_SET_EN		  (0x1 << 0)
29
30static const struct mtk_eint_regs mtk_generic_eint_regs = {
31	.stat      = 0x000,
32	.ack       = 0x040,
33	.mask      = 0x080,
34	.mask_set  = 0x0c0,
35	.mask_clr  = 0x100,
36	.sens      = 0x140,
37	.sens_set  = 0x180,
38	.sens_clr  = 0x1c0,
39	.soft      = 0x200,
40	.soft_set  = 0x240,
41	.soft_clr  = 0x280,
42	.pol       = 0x300,
43	.pol_set   = 0x340,
44	.pol_clr   = 0x380,
45	.dom_en    = 0x400,
46	.dbnc_ctrl = 0x500,
47	.dbnc_set  = 0x600,
48	.dbnc_clr  = 0x700,
49};
50
51static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint,
52					 unsigned int eint_num,
53					 unsigned int offset)
54{
55	unsigned int eint_base = 0;
56	void __iomem *reg;
57
58	if (eint_num >= eint->hw->ap_num)
59		eint_base = eint->hw->ap_num;
60
61	reg = eint->base + offset + ((eint_num - eint_base) / 32) * 4;
62
63	return reg;
64}
65
66static unsigned int mtk_eint_can_en_debounce(struct mtk_eint *eint,
67					     unsigned int eint_num)
68{
69	unsigned int sens;
70	unsigned int bit = BIT(eint_num % 32);
71	void __iomem *reg = mtk_eint_get_offset(eint, eint_num,
72						eint->regs->sens);
73
74	if (readl(reg) & bit)
75		sens = MTK_EINT_LEVEL_SENSITIVE;
76	else
77		sens = MTK_EINT_EDGE_SENSITIVE;
78
79	if (eint_num < eint->hw->db_cnt && sens != MTK_EINT_EDGE_SENSITIVE)
80		return 1;
81	else
82		return 0;
83}
84
85static int mtk_eint_flip_edge(struct mtk_eint *eint, int hwirq)
86{
87	int start_level, curr_level;
88	unsigned int reg_offset;
89	u32 mask = BIT(hwirq & 0x1f);
90	u32 port = (hwirq >> 5) & eint->hw->port_mask;
91	void __iomem *reg = eint->base + (port << 2);
92
93	curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl, hwirq);
94
95	do {
96		start_level = curr_level;
97		if (start_level)
98			reg_offset = eint->regs->pol_clr;
99		else
100			reg_offset = eint->regs->pol_set;
101		writel(mask, reg + reg_offset);
102
103		curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl,
104							      hwirq);
105	} while (start_level != curr_level);
106
107	return start_level;
108}
109
110static void mtk_eint_mask(struct irq_data *d)
111{
112	struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
113	u32 mask = BIT(d->hwirq & 0x1f);
114	void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
115						eint->regs->mask_set);
116
117	eint->cur_mask[d->hwirq >> 5] &= ~mask;
118
119	writel(mask, reg);
120}
121
122static void mtk_eint_unmask(struct irq_data *d)
123{
124	struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
125	u32 mask = BIT(d->hwirq & 0x1f);
126	void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
127						eint->regs->mask_clr);
128
129	eint->cur_mask[d->hwirq >> 5] |= mask;
130
131	writel(mask, reg);
132
133	if (eint->dual_edge[d->hwirq])
134		mtk_eint_flip_edge(eint, d->hwirq);
135}
136
137static unsigned int mtk_eint_get_mask(struct mtk_eint *eint,
138				      unsigned int eint_num)
139{
140	unsigned int bit = BIT(eint_num % 32);
141	void __iomem *reg = mtk_eint_get_offset(eint, eint_num,
142						eint->regs->mask);
143
144	return !!(readl(reg) & bit);
145}
146
147static void mtk_eint_ack(struct irq_data *d)
148{
149	struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
150	u32 mask = BIT(d->hwirq & 0x1f);
151	void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
152						eint->regs->ack);
153
154	writel(mask, reg);
155}
156
157static int mtk_eint_set_type(struct irq_data *d, unsigned int type)
158{
159	struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
160	u32 mask = BIT(d->hwirq & 0x1f);
161	void __iomem *reg;
162
163	if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) ||
164	    ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) {
165		dev_err(eint->dev,
166			"Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
167			d->irq, d->hwirq, type);
168		return -EINVAL;
169	}
170
171	if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
172		eint->dual_edge[d->hwirq] = 1;
173	else
174		eint->dual_edge[d->hwirq] = 0;
175
176	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
177		reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_clr);
178		writel(mask, reg);
179	} else {
180		reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_set);
181		writel(mask, reg);
182	}
183
184	if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
185		reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_clr);
186		writel(mask, reg);
187	} else {
188		reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_set);
189		writel(mask, reg);
190	}
191
192	if (eint->dual_edge[d->hwirq])
193		mtk_eint_flip_edge(eint, d->hwirq);
194
195	return 0;
196}
197
198static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on)
199{
200	struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
201	int shift = d->hwirq & 0x1f;
202	int reg = d->hwirq >> 5;
203
204	if (on)
205		eint->wake_mask[reg] |= BIT(shift);
206	else
207		eint->wake_mask[reg] &= ~BIT(shift);
208
209	return 0;
210}
211
212static void mtk_eint_chip_write_mask(const struct mtk_eint *eint,
213				     void __iomem *base, u32 *buf)
214{
215	int port;
216	void __iomem *reg;
217
218	for (port = 0; port < eint->hw->ports; port++) {
219		reg = base + (port << 2);
220		writel_relaxed(~buf[port], reg + eint->regs->mask_set);
221		writel_relaxed(buf[port], reg + eint->regs->mask_clr);
222	}
223}
224
225static int mtk_eint_irq_request_resources(struct irq_data *d)
226{
227	struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
228	struct gpio_chip *gpio_c;
229	unsigned int gpio_n;
230	int err;
231
232	err = eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq,
233					   &gpio_n, &gpio_c);
234	if (err < 0) {
235		dev_err(eint->dev, "Can not find pin\n");
236		return err;
237	}
238
239	err = gpiochip_lock_as_irq(gpio_c, gpio_n);
240	if (err < 0) {
241		dev_err(eint->dev, "unable to lock HW IRQ %lu for IRQ\n",
242			irqd_to_hwirq(d));
243		return err;
244	}
245
246	err = eint->gpio_xlate->set_gpio_as_eint(eint->pctl, d->hwirq);
247	if (err < 0) {
248		dev_err(eint->dev, "Can not eint mode\n");
249		return err;
250	}
251
252	return 0;
253}
254
255static void mtk_eint_irq_release_resources(struct irq_data *d)
256{
257	struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
258	struct gpio_chip *gpio_c;
259	unsigned int gpio_n;
260
261	eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq, &gpio_n,
262				     &gpio_c);
263
264	gpiochip_unlock_as_irq(gpio_c, gpio_n);
265}
266
267static struct irq_chip mtk_eint_irq_chip = {
268	.name = "mt-eint",
269	.irq_disable = mtk_eint_mask,
270	.irq_mask = mtk_eint_mask,
271	.irq_unmask = mtk_eint_unmask,
272	.irq_ack = mtk_eint_ack,
273	.irq_set_type = mtk_eint_set_type,
274	.irq_set_wake = mtk_eint_irq_set_wake,
275	.irq_request_resources = mtk_eint_irq_request_resources,
276	.irq_release_resources = mtk_eint_irq_release_resources,
277};
278
279static unsigned int mtk_eint_hw_init(struct mtk_eint *eint)
280{
281	void __iomem *dom_en = eint->base + eint->regs->dom_en;
282	void __iomem *mask_set = eint->base + eint->regs->mask_set;
283	unsigned int i;
284
285	for (i = 0; i < eint->hw->ap_num; i += 32) {
286		writel(0xffffffff, dom_en);
287		writel(0xffffffff, mask_set);
288		dom_en += 4;
289		mask_set += 4;
290	}
291
292	return 0;
293}
294
295static inline void
296mtk_eint_debounce_process(struct mtk_eint *eint, int index)
297{
298	unsigned int rst, ctrl_offset;
299	unsigned int bit, dbnc;
300
301	ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_ctrl;
302	dbnc = readl(eint->base + ctrl_offset);
303	bit = MTK_EINT_DBNC_SET_EN << ((index % 4) * 8);
304	if ((bit & dbnc) > 0) {
305		ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_set;
306		rst = MTK_EINT_DBNC_RST_BIT << ((index % 4) * 8);
307		writel(rst, eint->base + ctrl_offset);
308	}
309}
310
311static void mtk_eint_irq_handler(struct irq_desc *desc)
312{
313	struct irq_chip *chip = irq_desc_get_chip(desc);
314	struct mtk_eint *eint = irq_desc_get_handler_data(desc);
315	unsigned int status, eint_num;
316	int offset, mask_offset, index, virq;
317	void __iomem *reg =  mtk_eint_get_offset(eint, 0, eint->regs->stat);
318	int dual_edge, start_level, curr_level;
319
320	chained_irq_enter(chip, desc);
321	for (eint_num = 0; eint_num < eint->hw->ap_num; eint_num += 32,
322	     reg += 4) {
323		status = readl(reg);
324		while (status) {
325			offset = __ffs(status);
326			mask_offset = eint_num >> 5;
327			index = eint_num + offset;
328			virq = irq_find_mapping(eint->domain, index);
329			status &= ~BIT(offset);
330
331			/*
332			 * If we get an interrupt on pin that was only required
333			 * for wake (but no real interrupt requested), mask the
334			 * interrupt (as would mtk_eint_resume do anyway later
335			 * in the resume sequence).
336			 */
337			if (eint->wake_mask[mask_offset] & BIT(offset) &&
338			    !(eint->cur_mask[mask_offset] & BIT(offset))) {
339				writel_relaxed(BIT(offset), reg -
340					eint->regs->stat +
341					eint->regs->mask_set);
342			}
343
344			dual_edge = eint->dual_edge[index];
345			if (dual_edge) {
346				/*
347				 * Clear soft-irq in case we raised it last
348				 * time.
349				 */
350				writel(BIT(offset), reg - eint->regs->stat +
351				       eint->regs->soft_clr);
352
353				start_level =
354				eint->gpio_xlate->get_gpio_state(eint->pctl,
355								 index);
356			}
357
358			generic_handle_irq(virq);
359
360			if (dual_edge) {
361				curr_level = mtk_eint_flip_edge(eint, index);
362
363				/*
364				 * If level changed, we might lost one edge
365				 * interrupt, raised it through soft-irq.
366				 */
367				if (start_level != curr_level)
368					writel(BIT(offset), reg -
369					       eint->regs->stat +
370					       eint->regs->soft_set);
371			}
372
373			if (index < eint->hw->db_cnt)
374				mtk_eint_debounce_process(eint, index);
375		}
376	}
377	chained_irq_exit(chip, desc);
378}
379
380int mtk_eint_do_suspend(struct mtk_eint *eint)
381{
382	mtk_eint_chip_write_mask(eint, eint->base, eint->wake_mask);
383
384	return 0;
385}
386EXPORT_SYMBOL_GPL(mtk_eint_do_suspend);
387
388int mtk_eint_do_resume(struct mtk_eint *eint)
389{
390	mtk_eint_chip_write_mask(eint, eint->base, eint->cur_mask);
391
392	return 0;
393}
394EXPORT_SYMBOL_GPL(mtk_eint_do_resume);
395
396int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_num,
397			  unsigned int debounce)
398{
399	int virq, eint_offset;
400	unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask,
401		     dbnc;
402	static const unsigned int debounce_time[] = {500, 1000, 16000, 32000,
403						     64000, 128000, 256000};
404	struct irq_data *d;
405
406	virq = irq_find_mapping(eint->domain, eint_num);
407	eint_offset = (eint_num % 4) * 8;
408	d = irq_get_irq_data(virq);
409
410	set_offset = (eint_num / 4) * 4 + eint->regs->dbnc_set;
411	clr_offset = (eint_num / 4) * 4 + eint->regs->dbnc_clr;
412
413	if (!mtk_eint_can_en_debounce(eint, eint_num))
414		return -EINVAL;
415
416	dbnc = ARRAY_SIZE(debounce_time);
417	for (i = 0; i < ARRAY_SIZE(debounce_time); i++) {
418		if (debounce <= debounce_time[i]) {
419			dbnc = i;
420			break;
421		}
422	}
423
424	if (!mtk_eint_get_mask(eint, eint_num)) {
425		mtk_eint_mask(d);
426		unmask = 1;
427	} else {
428		unmask = 0;
429	}
430
431	clr_bit = 0xff << eint_offset;
432	writel(clr_bit, eint->base + clr_offset);
433
434	bit = ((dbnc << MTK_EINT_DBNC_SET_DBNC_BITS) | MTK_EINT_DBNC_SET_EN) <<
435		eint_offset;
436	rst = MTK_EINT_DBNC_RST_BIT << eint_offset;
437	writel(rst | bit, eint->base + set_offset);
438
439	/*
440	 * Delay a while (more than 2T) to wait for hw debounce counter reset
441	 * work correctly.
442	 */
443	udelay(1);
444	if (unmask == 1)
445		mtk_eint_unmask(d);
446
447	return 0;
448}
449EXPORT_SYMBOL_GPL(mtk_eint_set_debounce);
450
451int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n)
452{
453	int irq;
454
455	irq = irq_find_mapping(eint->domain, eint_n);
456	if (!irq)
457		return -EINVAL;
458
459	return irq;
460}
461EXPORT_SYMBOL_GPL(mtk_eint_find_irq);
462
463int mtk_eint_do_init(struct mtk_eint *eint)
464{
465	int i;
466
467	/* If clients don't assign a specific regs, let's use generic one */
468	if (!eint->regs)
469		eint->regs = &mtk_generic_eint_regs;
470
471	eint->wake_mask = devm_kcalloc(eint->dev, eint->hw->ports,
472				       sizeof(*eint->wake_mask), GFP_KERNEL);
473	if (!eint->wake_mask)
474		return -ENOMEM;
475
476	eint->cur_mask = devm_kcalloc(eint->dev, eint->hw->ports,
477				      sizeof(*eint->cur_mask), GFP_KERNEL);
478	if (!eint->cur_mask)
479		return -ENOMEM;
480
481	eint->dual_edge = devm_kcalloc(eint->dev, eint->hw->ap_num,
482				       sizeof(int), GFP_KERNEL);
483	if (!eint->dual_edge)
484		return -ENOMEM;
485
486	eint->domain = irq_domain_add_linear(eint->dev->of_node,
487					     eint->hw->ap_num,
488					     &irq_domain_simple_ops, NULL);
489	if (!eint->domain)
490		return -ENOMEM;
491
492	mtk_eint_hw_init(eint);
493	for (i = 0; i < eint->hw->ap_num; i++) {
494		int virq = irq_create_mapping(eint->domain, i);
495
496		irq_set_chip_and_handler(virq, &mtk_eint_irq_chip,
497					 handle_level_irq);
498		irq_set_chip_data(virq, eint);
499	}
500
501	irq_set_chained_handler_and_data(eint->irq, mtk_eint_irq_handler,
502					 eint);
503
504	return 0;
505}
506EXPORT_SYMBOL_GPL(mtk_eint_do_init);
507
508MODULE_LICENSE("GPL v2");
509MODULE_DESCRIPTION("MediaTek EINT Driver");
510