1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Intel Sunrisepoint PCH pinctrl/GPIO driver 4 * 5 * Copyright (C) 2015, Intel Corporation 6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 7 * Mika Westerberg <mika.westerberg@linux.intel.com> 8 */ 9 10#include <linux/mod_devicetable.h> 11#include <linux/module.h> 12#include <linux/platform_device.h> 13 14#include <linux/pinctrl/pinctrl.h> 15 16#include "pinctrl-intel.h" 17 18#define SPT_PAD_OWN 0x020 19#define SPT_H_PADCFGLOCK 0x090 20#define SPT_LP_PADCFGLOCK 0x0a0 21#define SPT_HOSTSW_OWN 0x0d0 22#define SPT_GPI_IS 0x100 23#define SPT_GPI_IE 0x120 24 25#define SPT_COMMUNITY(b, s, e, pl, gs, gn, g, n) \ 26 { \ 27 .barno = (b), \ 28 .padown_offset = SPT_PAD_OWN, \ 29 .padcfglock_offset = (pl), \ 30 .hostown_offset = SPT_HOSTSW_OWN, \ 31 .is_offset = SPT_GPI_IS, \ 32 .ie_offset = SPT_GPI_IE, \ 33 .gpp_size = (gs), \ 34 .gpp_num_padown_regs = (gn), \ 35 .pin_base = (s), \ 36 .npins = ((e) - (s) + 1), \ 37 .gpps = (g), \ 38 .ngpps = (n), \ 39 } 40 41#define SPT_LP_COMMUNITY(b, s, e) \ 42 SPT_COMMUNITY(b, s, e, SPT_LP_PADCFGLOCK, 24, 4, NULL, 0) 43 44#define SPT_H_GPP(r, s, e, g) \ 45 { \ 46 .reg_num = (r), \ 47 .base = (s), \ 48 .size = ((e) - (s) + 1), \ 49 .gpio_base = (g), \ 50 } 51 52#define SPT_H_COMMUNITY(b, s, e, g) \ 53 SPT_COMMUNITY(b, s, e, SPT_H_PADCFGLOCK, 0, 0, g, ARRAY_SIZE(g)) 54 55/* Sunrisepoint-LP */ 56static const struct pinctrl_pin_desc sptlp_pins[] = { 57 /* GPP_A */ 58 PINCTRL_PIN(0, "RCINB"), 59 PINCTRL_PIN(1, "LAD_0"), 60 PINCTRL_PIN(2, "LAD_1"), 61 PINCTRL_PIN(3, "LAD_2"), 62 PINCTRL_PIN(4, "LAD_3"), 63 PINCTRL_PIN(5, "LFRAMEB"), 64 PINCTRL_PIN(6, "SERIQ"), 65 PINCTRL_PIN(7, "PIRQAB"), 66 PINCTRL_PIN(8, "CLKRUNB"), 67 PINCTRL_PIN(9, "CLKOUT_LPC_0"), 68 PINCTRL_PIN(10, "CLKOUT_LPC_1"), 69 PINCTRL_PIN(11, "PMEB"), 70 PINCTRL_PIN(12, "BM_BUSYB"), 71 PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"), 72 PINCTRL_PIN(14, "SUS_STATB"), 73 PINCTRL_PIN(15, "SUSACKB"), 74 PINCTRL_PIN(16, "SD_1P8_SEL"), 75 PINCTRL_PIN(17, "SD_PWR_EN_B"), 76 PINCTRL_PIN(18, "ISH_GP_0"), 77 PINCTRL_PIN(19, "ISH_GP_1"), 78 PINCTRL_PIN(20, "ISH_GP_2"), 79 PINCTRL_PIN(21, "ISH_GP_3"), 80 PINCTRL_PIN(22, "ISH_GP_4"), 81 PINCTRL_PIN(23, "ISH_GP_5"), 82 /* GPP_B */ 83 PINCTRL_PIN(24, "CORE_VID_0"), 84 PINCTRL_PIN(25, "CORE_VID_1"), 85 PINCTRL_PIN(26, "VRALERTB"), 86 PINCTRL_PIN(27, "CPU_GP_2"), 87 PINCTRL_PIN(28, "CPU_GP_3"), 88 PINCTRL_PIN(29, "SRCCLKREQB_0"), 89 PINCTRL_PIN(30, "SRCCLKREQB_1"), 90 PINCTRL_PIN(31, "SRCCLKREQB_2"), 91 PINCTRL_PIN(32, "SRCCLKREQB_3"), 92 PINCTRL_PIN(33, "SRCCLKREQB_4"), 93 PINCTRL_PIN(34, "SRCCLKREQB_5"), 94 PINCTRL_PIN(35, "EXT_PWR_GATEB"), 95 PINCTRL_PIN(36, "SLP_S0B"), 96 PINCTRL_PIN(37, "PLTRSTB"), 97 PINCTRL_PIN(38, "SPKR"), 98 PINCTRL_PIN(39, "GSPI0_CSB"), 99 PINCTRL_PIN(40, "GSPI0_CLK"), 100 PINCTRL_PIN(41, "GSPI0_MISO"), 101 PINCTRL_PIN(42, "GSPI0_MOSI"), 102 PINCTRL_PIN(43, "GSPI1_CSB"), 103 PINCTRL_PIN(44, "GSPI1_CLK"), 104 PINCTRL_PIN(45, "GSPI1_MISO"), 105 PINCTRL_PIN(46, "GSPI1_MOSI"), 106 PINCTRL_PIN(47, "SML1ALERTB"), 107 /* GPP_C */ 108 PINCTRL_PIN(48, "SMBCLK"), 109 PINCTRL_PIN(49, "SMBDATA"), 110 PINCTRL_PIN(50, "SMBALERTB"), 111 PINCTRL_PIN(51, "SML0CLK"), 112 PINCTRL_PIN(52, "SML0DATA"), 113 PINCTRL_PIN(53, "SML0ALERTB"), 114 PINCTRL_PIN(54, "SML1CLK"), 115 PINCTRL_PIN(55, "SML1DATA"), 116 PINCTRL_PIN(56, "UART0_RXD"), 117 PINCTRL_PIN(57, "UART0_TXD"), 118 PINCTRL_PIN(58, "UART0_RTSB"), 119 PINCTRL_PIN(59, "UART0_CTSB"), 120 PINCTRL_PIN(60, "UART1_RXD"), 121 PINCTRL_PIN(61, "UART1_TXD"), 122 PINCTRL_PIN(62, "UART1_RTSB"), 123 PINCTRL_PIN(63, "UART1_CTSB"), 124 PINCTRL_PIN(64, "I2C0_SDA"), 125 PINCTRL_PIN(65, "I2C0_SCL"), 126 PINCTRL_PIN(66, "I2C1_SDA"), 127 PINCTRL_PIN(67, "I2C1_SCL"), 128 PINCTRL_PIN(68, "UART2_RXD"), 129 PINCTRL_PIN(69, "UART2_TXD"), 130 PINCTRL_PIN(70, "UART2_RTSB"), 131 PINCTRL_PIN(71, "UART2_CTSB"), 132 /* GPP_D */ 133 PINCTRL_PIN(72, "SPI1_CSB"), 134 PINCTRL_PIN(73, "SPI1_CLK"), 135 PINCTRL_PIN(74, "SPI1_MISO_IO_1"), 136 PINCTRL_PIN(75, "SPI1_MOSI_IO_0"), 137 PINCTRL_PIN(76, "FLASHTRIG"), 138 PINCTRL_PIN(77, "ISH_I2C0_SDA"), 139 PINCTRL_PIN(78, "ISH_I2C0_SCL"), 140 PINCTRL_PIN(79, "ISH_I2C1_SDA"), 141 PINCTRL_PIN(80, "ISH_I2C1_SCL"), 142 PINCTRL_PIN(81, "ISH_SPI_CSB"), 143 PINCTRL_PIN(82, "ISH_SPI_CLK"), 144 PINCTRL_PIN(83, "ISH_SPI_MISO"), 145 PINCTRL_PIN(84, "ISH_SPI_MOSI"), 146 PINCTRL_PIN(85, "ISH_UART0_RXD"), 147 PINCTRL_PIN(86, "ISH_UART0_TXD"), 148 PINCTRL_PIN(87, "ISH_UART0_RTSB"), 149 PINCTRL_PIN(88, "ISH_UART0_CTSB"), 150 PINCTRL_PIN(89, "DMIC_CLK_1"), 151 PINCTRL_PIN(90, "DMIC_DATA_1"), 152 PINCTRL_PIN(91, "DMIC_CLK_0"), 153 PINCTRL_PIN(92, "DMIC_DATA_0"), 154 PINCTRL_PIN(93, "SPI1_IO_2"), 155 PINCTRL_PIN(94, "SPI1_IO_3"), 156 PINCTRL_PIN(95, "SSP_MCLK"), 157 /* GPP_E */ 158 PINCTRL_PIN(96, "SATAXPCIE_0"), 159 PINCTRL_PIN(97, "SATAXPCIE_1"), 160 PINCTRL_PIN(98, "SATAXPCIE_2"), 161 PINCTRL_PIN(99, "CPU_GP_0"), 162 PINCTRL_PIN(100, "SATA_DEVSLP_0"), 163 PINCTRL_PIN(101, "SATA_DEVSLP_1"), 164 PINCTRL_PIN(102, "SATA_DEVSLP_2"), 165 PINCTRL_PIN(103, "CPU_GP_1"), 166 PINCTRL_PIN(104, "SATA_LEDB"), 167 PINCTRL_PIN(105, "USB2_OCB_0"), 168 PINCTRL_PIN(106, "USB2_OCB_1"), 169 PINCTRL_PIN(107, "USB2_OCB_2"), 170 PINCTRL_PIN(108, "USB2_OCB_3"), 171 PINCTRL_PIN(109, "DDSP_HPD_0"), 172 PINCTRL_PIN(110, "DDSP_HPD_1"), 173 PINCTRL_PIN(111, "DDSP_HPD_2"), 174 PINCTRL_PIN(112, "DDSP_HPD_3"), 175 PINCTRL_PIN(113, "EDP_HPD"), 176 PINCTRL_PIN(114, "DDPB_CTRLCLK"), 177 PINCTRL_PIN(115, "DDPB_CTRLDATA"), 178 PINCTRL_PIN(116, "DDPC_CTRLCLK"), 179 PINCTRL_PIN(117, "DDPC_CTRLDATA"), 180 PINCTRL_PIN(118, "DDPD_CTRLCLK"), 181 PINCTRL_PIN(119, "DDPD_CTRLDATA"), 182 /* GPP_F */ 183 PINCTRL_PIN(120, "SSP2_SCLK"), 184 PINCTRL_PIN(121, "SSP2_SFRM"), 185 PINCTRL_PIN(122, "SSP2_TXD"), 186 PINCTRL_PIN(123, "SSP2_RXD"), 187 PINCTRL_PIN(124, "I2C2_SDA"), 188 PINCTRL_PIN(125, "I2C2_SCL"), 189 PINCTRL_PIN(126, "I2C3_SDA"), 190 PINCTRL_PIN(127, "I2C3_SCL"), 191 PINCTRL_PIN(128, "I2C4_SDA"), 192 PINCTRL_PIN(129, "I2C4_SCL"), 193 PINCTRL_PIN(130, "I2C5_SDA"), 194 PINCTRL_PIN(131, "I2C5_SCL"), 195 PINCTRL_PIN(132, "EMMC_CMD"), 196 PINCTRL_PIN(133, "EMMC_DATA_0"), 197 PINCTRL_PIN(134, "EMMC_DATA_1"), 198 PINCTRL_PIN(135, "EMMC_DATA_2"), 199 PINCTRL_PIN(136, "EMMC_DATA_3"), 200 PINCTRL_PIN(137, "EMMC_DATA_4"), 201 PINCTRL_PIN(138, "EMMC_DATA_5"), 202 PINCTRL_PIN(139, "EMMC_DATA_6"), 203 PINCTRL_PIN(140, "EMMC_DATA_7"), 204 PINCTRL_PIN(141, "EMMC_RCLK"), 205 PINCTRL_PIN(142, "EMMC_CLK"), 206 PINCTRL_PIN(143, "GPP_F_23"), 207 /* GPP_G */ 208 PINCTRL_PIN(144, "SD_CMD"), 209 PINCTRL_PIN(145, "SD_DATA_0"), 210 PINCTRL_PIN(146, "SD_DATA_1"), 211 PINCTRL_PIN(147, "SD_DATA_2"), 212 PINCTRL_PIN(148, "SD_DATA_3"), 213 PINCTRL_PIN(149, "SD_CDB"), 214 PINCTRL_PIN(150, "SD_CLK"), 215 PINCTRL_PIN(151, "SD_WP"), 216}; 217 218static const unsigned sptlp_spi0_pins[] = { 39, 40, 41, 42 }; 219static const unsigned sptlp_spi1_pins[] = { 43, 44, 45, 46 }; 220static const unsigned sptlp_uart0_pins[] = { 56, 57, 58, 59 }; 221static const unsigned sptlp_uart1_pins[] = { 60, 61, 62, 63 }; 222static const unsigned sptlp_uart2_pins[] = { 68, 69, 71, 71 }; 223static const unsigned sptlp_i2c0_pins[] = { 64, 65 }; 224static const unsigned sptlp_i2c1_pins[] = { 66, 67 }; 225static const unsigned sptlp_i2c2_pins[] = { 124, 125 }; 226static const unsigned sptlp_i2c3_pins[] = { 126, 127 }; 227static const unsigned sptlp_i2c4_pins[] = { 128, 129 }; 228static const unsigned sptlp_i2c4b_pins[] = { 85, 86 }; 229static const unsigned sptlp_i2c5_pins[] = { 130, 131 }; 230static const unsigned sptlp_ssp2_pins[] = { 120, 121, 122, 123 }; 231static const unsigned sptlp_emmc_pins[] = { 232 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 233}; 234static const unsigned sptlp_sd_pins[] = { 235 144, 145, 146, 147, 148, 149, 150, 151, 236}; 237 238static const struct intel_pingroup sptlp_groups[] = { 239 PIN_GROUP("spi0_grp", sptlp_spi0_pins, 1), 240 PIN_GROUP("spi1_grp", sptlp_spi1_pins, 1), 241 PIN_GROUP("uart0_grp", sptlp_uart0_pins, 1), 242 PIN_GROUP("uart1_grp", sptlp_uart1_pins, 1), 243 PIN_GROUP("uart2_grp", sptlp_uart2_pins, 1), 244 PIN_GROUP("i2c0_grp", sptlp_i2c0_pins, 1), 245 PIN_GROUP("i2c1_grp", sptlp_i2c1_pins, 1), 246 PIN_GROUP("i2c2_grp", sptlp_i2c2_pins, 1), 247 PIN_GROUP("i2c3_grp", sptlp_i2c3_pins, 1), 248 PIN_GROUP("i2c4_grp", sptlp_i2c4_pins, 1), 249 PIN_GROUP("i2c4b_grp", sptlp_i2c4b_pins, 3), 250 PIN_GROUP("i2c5_grp", sptlp_i2c5_pins, 1), 251 PIN_GROUP("ssp2_grp", sptlp_ssp2_pins, 1), 252 PIN_GROUP("emmc_grp", sptlp_emmc_pins, 1), 253 PIN_GROUP("sd_grp", sptlp_sd_pins, 1), 254}; 255 256static const char * const sptlp_spi0_groups[] = { "spi0_grp" }; 257static const char * const sptlp_spi1_groups[] = { "spi0_grp" }; 258static const char * const sptlp_uart0_groups[] = { "uart0_grp" }; 259static const char * const sptlp_uart1_groups[] = { "uart1_grp" }; 260static const char * const sptlp_uart2_groups[] = { "uart2_grp" }; 261static const char * const sptlp_i2c0_groups[] = { "i2c0_grp" }; 262static const char * const sptlp_i2c1_groups[] = { "i2c1_grp" }; 263static const char * const sptlp_i2c2_groups[] = { "i2c2_grp" }; 264static const char * const sptlp_i2c3_groups[] = { "i2c3_grp" }; 265static const char * const sptlp_i2c4_groups[] = { "i2c4_grp", "i2c4b_grp" }; 266static const char * const sptlp_i2c5_groups[] = { "i2c5_grp" }; 267static const char * const sptlp_ssp2_groups[] = { "ssp2_grp" }; 268static const char * const sptlp_emmc_groups[] = { "emmc_grp" }; 269static const char * const sptlp_sd_groups[] = { "sd_grp" }; 270 271static const struct intel_function sptlp_functions[] = { 272 FUNCTION("spi0", sptlp_spi0_groups), 273 FUNCTION("spi1", sptlp_spi1_groups), 274 FUNCTION("uart0", sptlp_uart0_groups), 275 FUNCTION("uart1", sptlp_uart1_groups), 276 FUNCTION("uart2", sptlp_uart2_groups), 277 FUNCTION("i2c0", sptlp_i2c0_groups), 278 FUNCTION("i2c1", sptlp_i2c1_groups), 279 FUNCTION("i2c2", sptlp_i2c2_groups), 280 FUNCTION("i2c3", sptlp_i2c3_groups), 281 FUNCTION("i2c4", sptlp_i2c4_groups), 282 FUNCTION("i2c5", sptlp_i2c5_groups), 283 FUNCTION("ssp2", sptlp_ssp2_groups), 284 FUNCTION("emmc", sptlp_emmc_groups), 285 FUNCTION("sd", sptlp_sd_groups), 286}; 287 288static const struct intel_community sptlp_communities[] = { 289 SPT_LP_COMMUNITY(0, 0, 47), 290 SPT_LP_COMMUNITY(1, 48, 119), 291 SPT_LP_COMMUNITY(2, 120, 151), 292}; 293 294static const struct intel_pinctrl_soc_data sptlp_soc_data = { 295 .pins = sptlp_pins, 296 .npins = ARRAY_SIZE(sptlp_pins), 297 .groups = sptlp_groups, 298 .ngroups = ARRAY_SIZE(sptlp_groups), 299 .functions = sptlp_functions, 300 .nfunctions = ARRAY_SIZE(sptlp_functions), 301 .communities = sptlp_communities, 302 .ncommunities = ARRAY_SIZE(sptlp_communities), 303}; 304 305/* Sunrisepoint-H */ 306static const struct pinctrl_pin_desc spth_pins[] = { 307 /* GPP_A */ 308 PINCTRL_PIN(0, "RCINB"), 309 PINCTRL_PIN(1, "LAD_0"), 310 PINCTRL_PIN(2, "LAD_1"), 311 PINCTRL_PIN(3, "LAD_2"), 312 PINCTRL_PIN(4, "LAD_3"), 313 PINCTRL_PIN(5, "LFRAMEB"), 314 PINCTRL_PIN(6, "SERIQ"), 315 PINCTRL_PIN(7, "PIRQAB"), 316 PINCTRL_PIN(8, "CLKRUNB"), 317 PINCTRL_PIN(9, "CLKOUT_LPC_0"), 318 PINCTRL_PIN(10, "CLKOUT_LPC_1"), 319 PINCTRL_PIN(11, "PMEB"), 320 PINCTRL_PIN(12, "BM_BUSYB"), 321 PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"), 322 PINCTRL_PIN(14, "SUS_STATB"), 323 PINCTRL_PIN(15, "SUSACKB"), 324 PINCTRL_PIN(16, "CLKOUT_48"), 325 PINCTRL_PIN(17, "ISH_GP_7"), 326 PINCTRL_PIN(18, "ISH_GP_0"), 327 PINCTRL_PIN(19, "ISH_GP_1"), 328 PINCTRL_PIN(20, "ISH_GP_2"), 329 PINCTRL_PIN(21, "ISH_GP_3"), 330 PINCTRL_PIN(22, "ISH_GP_4"), 331 PINCTRL_PIN(23, "ISH_GP_5"), 332 /* GPP_B */ 333 PINCTRL_PIN(24, "CORE_VID_0"), 334 PINCTRL_PIN(25, "CORE_VID_1"), 335 PINCTRL_PIN(26, "VRALERTB"), 336 PINCTRL_PIN(27, "CPU_GP_2"), 337 PINCTRL_PIN(28, "CPU_GP_3"), 338 PINCTRL_PIN(29, "SRCCLKREQB_0"), 339 PINCTRL_PIN(30, "SRCCLKREQB_1"), 340 PINCTRL_PIN(31, "SRCCLKREQB_2"), 341 PINCTRL_PIN(32, "SRCCLKREQB_3"), 342 PINCTRL_PIN(33, "SRCCLKREQB_4"), 343 PINCTRL_PIN(34, "SRCCLKREQB_5"), 344 PINCTRL_PIN(35, "EXT_PWR_GATEB"), 345 PINCTRL_PIN(36, "SLP_S0B"), 346 PINCTRL_PIN(37, "PLTRSTB"), 347 PINCTRL_PIN(38, "SPKR"), 348 PINCTRL_PIN(39, "GSPI0_CSB"), 349 PINCTRL_PIN(40, "GSPI0_CLK"), 350 PINCTRL_PIN(41, "GSPI0_MISO"), 351 PINCTRL_PIN(42, "GSPI0_MOSI"), 352 PINCTRL_PIN(43, "GSPI1_CSB"), 353 PINCTRL_PIN(44, "GSPI1_CLK"), 354 PINCTRL_PIN(45, "GSPI1_MISO"), 355 PINCTRL_PIN(46, "GSPI1_MOSI"), 356 PINCTRL_PIN(47, "SML1ALERTB"), 357 /* GPP_C */ 358 PINCTRL_PIN(48, "SMBCLK"), 359 PINCTRL_PIN(49, "SMBDATA"), 360 PINCTRL_PIN(50, "SMBALERTB"), 361 PINCTRL_PIN(51, "SML0CLK"), 362 PINCTRL_PIN(52, "SML0DATA"), 363 PINCTRL_PIN(53, "SML0ALERTB"), 364 PINCTRL_PIN(54, "SML1CLK"), 365 PINCTRL_PIN(55, "SML1DATA"), 366 PINCTRL_PIN(56, "UART0_RXD"), 367 PINCTRL_PIN(57, "UART0_TXD"), 368 PINCTRL_PIN(58, "UART0_RTSB"), 369 PINCTRL_PIN(59, "UART0_CTSB"), 370 PINCTRL_PIN(60, "UART1_RXD"), 371 PINCTRL_PIN(61, "UART1_TXD"), 372 PINCTRL_PIN(62, "UART1_RTSB"), 373 PINCTRL_PIN(63, "UART1_CTSB"), 374 PINCTRL_PIN(64, "I2C0_SDA"), 375 PINCTRL_PIN(65, "I2C0_SCL"), 376 PINCTRL_PIN(66, "I2C1_SDA"), 377 PINCTRL_PIN(67, "I2C1_SCL"), 378 PINCTRL_PIN(68, "UART2_RXD"), 379 PINCTRL_PIN(69, "UART2_TXD"), 380 PINCTRL_PIN(70, "UART2_RTSB"), 381 PINCTRL_PIN(71, "UART2_CTSB"), 382 /* GPP_D */ 383 PINCTRL_PIN(72, "SPI1_CSB"), 384 PINCTRL_PIN(73, "SPI1_CLK"), 385 PINCTRL_PIN(74, "SPI1_MISO_IO_1"), 386 PINCTRL_PIN(75, "SPI1_MOSI_IO_0"), 387 PINCTRL_PIN(76, "ISH_I2C2_SDA"), 388 PINCTRL_PIN(77, "SSP0_SFRM"), 389 PINCTRL_PIN(78, "SSP0_TXD"), 390 PINCTRL_PIN(79, "SSP0_RXD"), 391 PINCTRL_PIN(80, "SSP0_SCLK"), 392 PINCTRL_PIN(81, "ISH_SPI_CSB"), 393 PINCTRL_PIN(82, "ISH_SPI_CLK"), 394 PINCTRL_PIN(83, "ISH_SPI_MISO"), 395 PINCTRL_PIN(84, "ISH_SPI_MOSI"), 396 PINCTRL_PIN(85, "ISH_UART0_RXD"), 397 PINCTRL_PIN(86, "ISH_UART0_TXD"), 398 PINCTRL_PIN(87, "ISH_UART0_RTSB"), 399 PINCTRL_PIN(88, "ISH_UART0_CTSB"), 400 PINCTRL_PIN(89, "DMIC_CLK_1"), 401 PINCTRL_PIN(90, "DMIC_DATA_1"), 402 PINCTRL_PIN(91, "DMIC_CLK_0"), 403 PINCTRL_PIN(92, "DMIC_DATA_0"), 404 PINCTRL_PIN(93, "SPI1_IO_2"), 405 PINCTRL_PIN(94, "SPI1_IO_3"), 406 PINCTRL_PIN(95, "ISH_I2C2_SCL"), 407 /* GPP_E */ 408 PINCTRL_PIN(96, "SATAXPCIE_0"), 409 PINCTRL_PIN(97, "SATAXPCIE_1"), 410 PINCTRL_PIN(98, "SATAXPCIE_2"), 411 PINCTRL_PIN(99, "CPU_GP_0"), 412 PINCTRL_PIN(100, "SATA_DEVSLP_0"), 413 PINCTRL_PIN(101, "SATA_DEVSLP_1"), 414 PINCTRL_PIN(102, "SATA_DEVSLP_2"), 415 PINCTRL_PIN(103, "CPU_GP_1"), 416 PINCTRL_PIN(104, "SATA_LEDB"), 417 PINCTRL_PIN(105, "USB2_OCB_0"), 418 PINCTRL_PIN(106, "USB2_OCB_1"), 419 PINCTRL_PIN(107, "USB2_OCB_2"), 420 PINCTRL_PIN(108, "USB2_OCB_3"), 421 /* GPP_F */ 422 PINCTRL_PIN(109, "SATAXPCIE_3"), 423 PINCTRL_PIN(110, "SATAXPCIE_4"), 424 PINCTRL_PIN(111, "SATAXPCIE_5"), 425 PINCTRL_PIN(112, "SATAXPCIE_6"), 426 PINCTRL_PIN(113, "SATAXPCIE_7"), 427 PINCTRL_PIN(114, "SATA_DEVSLP_3"), 428 PINCTRL_PIN(115, "SATA_DEVSLP_4"), 429 PINCTRL_PIN(116, "SATA_DEVSLP_5"), 430 PINCTRL_PIN(117, "SATA_DEVSLP_6"), 431 PINCTRL_PIN(118, "SATA_DEVSLP_7"), 432 PINCTRL_PIN(119, "SATA_SCLOCK"), 433 PINCTRL_PIN(120, "SATA_SLOAD"), 434 PINCTRL_PIN(121, "SATA_SDATAOUT1"), 435 PINCTRL_PIN(122, "SATA_SDATAOUT0"), 436 PINCTRL_PIN(123, "GPP_F_14"), 437 PINCTRL_PIN(124, "USB_OCB_4"), 438 PINCTRL_PIN(125, "USB_OCB_5"), 439 PINCTRL_PIN(126, "USB_OCB_6"), 440 PINCTRL_PIN(127, "USB_OCB_7"), 441 PINCTRL_PIN(128, "L_VDDEN"), 442 PINCTRL_PIN(129, "L_BKLTEN"), 443 PINCTRL_PIN(130, "L_BKLTCTL"), 444 PINCTRL_PIN(131, "GPP_F_22"), 445 PINCTRL_PIN(132, "GPP_F_23"), 446 /* GPP_G */ 447 PINCTRL_PIN(133, "FAN_TACH_0"), 448 PINCTRL_PIN(134, "FAN_TACH_1"), 449 PINCTRL_PIN(135, "FAN_TACH_2"), 450 PINCTRL_PIN(136, "FAN_TACH_3"), 451 PINCTRL_PIN(137, "FAN_TACH_4"), 452 PINCTRL_PIN(138, "FAN_TACH_5"), 453 PINCTRL_PIN(139, "FAN_TACH_6"), 454 PINCTRL_PIN(140, "FAN_TACH_7"), 455 PINCTRL_PIN(141, "FAN_PWM_0"), 456 PINCTRL_PIN(142, "FAN_PWM_1"), 457 PINCTRL_PIN(143, "FAN_PWM_2"), 458 PINCTRL_PIN(144, "FAN_PWM_3"), 459 PINCTRL_PIN(145, "GSXDOUT"), 460 PINCTRL_PIN(146, "GSXSLOAD"), 461 PINCTRL_PIN(147, "GSXDIN"), 462 PINCTRL_PIN(148, "GSXRESETB"), 463 PINCTRL_PIN(149, "GSXCLK"), 464 PINCTRL_PIN(150, "ADR_COMPLETE"), 465 PINCTRL_PIN(151, "NMIB"), 466 PINCTRL_PIN(152, "SMIB"), 467 PINCTRL_PIN(153, "GPP_G_20"), 468 PINCTRL_PIN(154, "GPP_G_21"), 469 PINCTRL_PIN(155, "GPP_G_22"), 470 PINCTRL_PIN(156, "GPP_G_23"), 471 /* GPP_H */ 472 PINCTRL_PIN(157, "SRCCLKREQB_6"), 473 PINCTRL_PIN(158, "SRCCLKREQB_7"), 474 PINCTRL_PIN(159, "SRCCLKREQB_8"), 475 PINCTRL_PIN(160, "SRCCLKREQB_9"), 476 PINCTRL_PIN(161, "SRCCLKREQB_10"), 477 PINCTRL_PIN(162, "SRCCLKREQB_11"), 478 PINCTRL_PIN(163, "SRCCLKREQB_12"), 479 PINCTRL_PIN(164, "SRCCLKREQB_13"), 480 PINCTRL_PIN(165, "SRCCLKREQB_14"), 481 PINCTRL_PIN(166, "SRCCLKREQB_15"), 482 PINCTRL_PIN(167, "SML2CLK"), 483 PINCTRL_PIN(168, "SML2DATA"), 484 PINCTRL_PIN(169, "SML2ALERTB"), 485 PINCTRL_PIN(170, "SML3CLK"), 486 PINCTRL_PIN(171, "SML3DATA"), 487 PINCTRL_PIN(172, "SML3ALERTB"), 488 PINCTRL_PIN(173, "SML4CLK"), 489 PINCTRL_PIN(174, "SML4DATA"), 490 PINCTRL_PIN(175, "SML4ALERTB"), 491 PINCTRL_PIN(176, "ISH_I2C0_SDA"), 492 PINCTRL_PIN(177, "ISH_I2C0_SCL"), 493 PINCTRL_PIN(178, "ISH_I2C1_SDA"), 494 PINCTRL_PIN(179, "ISH_I2C1_SCL"), 495 PINCTRL_PIN(180, "GPP_H_23"), 496 /* GPP_I */ 497 PINCTRL_PIN(181, "DDSP_HDP_0"), 498 PINCTRL_PIN(182, "DDSP_HDP_1"), 499 PINCTRL_PIN(183, "DDSP_HDP_2"), 500 PINCTRL_PIN(184, "DDSP_HDP_3"), 501 PINCTRL_PIN(185, "EDP_HPD"), 502 PINCTRL_PIN(186, "DDPB_CTRLCLK"), 503 PINCTRL_PIN(187, "DDPB_CTRLDATA"), 504 PINCTRL_PIN(188, "DDPC_CTRLCLK"), 505 PINCTRL_PIN(189, "DDPC_CTRLDATA"), 506 PINCTRL_PIN(190, "DDPD_CTRLCLK"), 507 PINCTRL_PIN(191, "DDPD_CTRLDATA"), 508}; 509 510static const unsigned spth_spi0_pins[] = { 39, 40, 41, 42 }; 511static const unsigned spth_spi1_pins[] = { 43, 44, 45, 46 }; 512static const unsigned spth_uart0_pins[] = { 56, 57, 58, 59 }; 513static const unsigned spth_uart1_pins[] = { 60, 61, 62, 63 }; 514static const unsigned spth_uart2_pins[] = { 68, 69, 71, 71 }; 515static const unsigned spth_i2c0_pins[] = { 64, 65 }; 516static const unsigned spth_i2c1_pins[] = { 66, 67 }; 517static const unsigned spth_i2c2_pins[] = { 76, 95 }; 518 519static const struct intel_pingroup spth_groups[] = { 520 PIN_GROUP("spi0_grp", spth_spi0_pins, 1), 521 PIN_GROUP("spi1_grp", spth_spi1_pins, 1), 522 PIN_GROUP("uart0_grp", spth_uart0_pins, 1), 523 PIN_GROUP("uart1_grp", spth_uart1_pins, 1), 524 PIN_GROUP("uart2_grp", spth_uart2_pins, 1), 525 PIN_GROUP("i2c0_grp", spth_i2c0_pins, 1), 526 PIN_GROUP("i2c1_grp", spth_i2c1_pins, 1), 527 PIN_GROUP("i2c2_grp", spth_i2c2_pins, 2), 528}; 529 530static const char * const spth_spi0_groups[] = { "spi0_grp" }; 531static const char * const spth_spi1_groups[] = { "spi0_grp" }; 532static const char * const spth_uart0_groups[] = { "uart0_grp" }; 533static const char * const spth_uart1_groups[] = { "uart1_grp" }; 534static const char * const spth_uart2_groups[] = { "uart2_grp" }; 535static const char * const spth_i2c0_groups[] = { "i2c0_grp" }; 536static const char * const spth_i2c1_groups[] = { "i2c1_grp" }; 537static const char * const spth_i2c2_groups[] = { "i2c2_grp" }; 538 539static const struct intel_function spth_functions[] = { 540 FUNCTION("spi0", spth_spi0_groups), 541 FUNCTION("spi1", spth_spi1_groups), 542 FUNCTION("uart0", spth_uart0_groups), 543 FUNCTION("uart1", spth_uart1_groups), 544 FUNCTION("uart2", spth_uart2_groups), 545 FUNCTION("i2c0", spth_i2c0_groups), 546 FUNCTION("i2c1", spth_i2c1_groups), 547 FUNCTION("i2c2", spth_i2c2_groups), 548}; 549 550static const struct intel_padgroup spth_community0_gpps[] = { 551 SPT_H_GPP(0, 0, 23, 0), /* GPP_A */ 552 SPT_H_GPP(1, 24, 47, 24), /* GPP_B */ 553}; 554 555static const struct intel_padgroup spth_community1_gpps[] = { 556 SPT_H_GPP(0, 48, 71, 48), /* GPP_C */ 557 SPT_H_GPP(1, 72, 95, 72), /* GPP_D */ 558 SPT_H_GPP(2, 96, 108, 96), /* GPP_E */ 559 SPT_H_GPP(3, 109, 132, 120), /* GPP_F */ 560 SPT_H_GPP(4, 133, 156, 144), /* GPP_G */ 561 SPT_H_GPP(5, 157, 180, 168), /* GPP_H */ 562}; 563 564static const struct intel_padgroup spth_community3_gpps[] = { 565 SPT_H_GPP(0, 181, 191, 192), /* GPP_I */ 566}; 567 568static const struct intel_community spth_communities[] = { 569 SPT_H_COMMUNITY(0, 0, 47, spth_community0_gpps), 570 SPT_H_COMMUNITY(1, 48, 180, spth_community1_gpps), 571 SPT_H_COMMUNITY(2, 181, 191, spth_community3_gpps), 572}; 573 574static const struct intel_pinctrl_soc_data spth_soc_data = { 575 .pins = spth_pins, 576 .npins = ARRAY_SIZE(spth_pins), 577 .groups = spth_groups, 578 .ngroups = ARRAY_SIZE(spth_groups), 579 .functions = spth_functions, 580 .nfunctions = ARRAY_SIZE(spth_functions), 581 .communities = spth_communities, 582 .ncommunities = ARRAY_SIZE(spth_communities), 583}; 584 585static const struct acpi_device_id spt_pinctrl_acpi_match[] = { 586 { "INT344B", (kernel_ulong_t)&sptlp_soc_data }, 587 { "INT3451", (kernel_ulong_t)&spth_soc_data }, 588 { "INT345D", (kernel_ulong_t)&spth_soc_data }, 589 { } 590}; 591MODULE_DEVICE_TABLE(acpi, spt_pinctrl_acpi_match); 592 593static INTEL_PINCTRL_PM_OPS(spt_pinctrl_pm_ops); 594 595static struct platform_driver spt_pinctrl_driver = { 596 .probe = intel_pinctrl_probe_by_hid, 597 .driver = { 598 .name = "sunrisepoint-pinctrl", 599 .acpi_match_table = spt_pinctrl_acpi_match, 600 .pm = &spt_pinctrl_pm_ops, 601 }, 602}; 603 604static int __init spt_pinctrl_init(void) 605{ 606 return platform_driver_register(&spt_pinctrl_driver); 607} 608subsys_initcall(spt_pinctrl_init); 609 610static void __exit spt_pinctrl_exit(void) 611{ 612 platform_driver_unregister(&spt_pinctrl_driver); 613} 614module_exit(spt_pinctrl_exit); 615 616MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); 617MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 618MODULE_DESCRIPTION("Intel Sunrisepoint PCH pinctrl/GPIO driver"); 619MODULE_LICENSE("GPL v2"); 620