1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Intel pinctrl/GPIO core driver. 4 * 5 * Copyright (C) 2015, Intel Corporation 6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 7 * Mika Westerberg <mika.westerberg@linux.intel.com> 8 */ 9 10#include <linux/acpi.h> 11#include <linux/gpio/driver.h> 12#include <linux/interrupt.h> 13#include <linux/log2.h> 14#include <linux/module.h> 15#include <linux/platform_device.h> 16#include <linux/property.h> 17#include <linux/time.h> 18 19#include <linux/pinctrl/pinctrl.h> 20#include <linux/pinctrl/pinmux.h> 21#include <linux/pinctrl/pinconf.h> 22#include <linux/pinctrl/pinconf-generic.h> 23 24#include "../core.h" 25#include "pinctrl-intel.h" 26 27/* Offset from regs */ 28#define REVID 0x000 29#define REVID_SHIFT 16 30#define REVID_MASK GENMASK(31, 16) 31 32#define PADBAR 0x00c 33 34#define PADOWN_BITS 4 35#define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) 36#define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p)) 37#define PADOWN_GPP(p) ((p) / 8) 38 39/* Offset from pad_regs */ 40#define PADCFG0 0x000 41#define PADCFG0_RXEVCFG_SHIFT 25 42#define PADCFG0_RXEVCFG_MASK GENMASK(26, 25) 43#define PADCFG0_RXEVCFG_LEVEL 0 44#define PADCFG0_RXEVCFG_EDGE 1 45#define PADCFG0_RXEVCFG_DISABLED 2 46#define PADCFG0_RXEVCFG_EDGE_BOTH 3 47#define PADCFG0_PREGFRXSEL BIT(24) 48#define PADCFG0_RXINV BIT(23) 49#define PADCFG0_GPIROUTIOXAPIC BIT(20) 50#define PADCFG0_GPIROUTSCI BIT(19) 51#define PADCFG0_GPIROUTSMI BIT(18) 52#define PADCFG0_GPIROUTNMI BIT(17) 53#define PADCFG0_PMODE_SHIFT 10 54#define PADCFG0_PMODE_MASK GENMASK(13, 10) 55#define PADCFG0_PMODE_GPIO 0 56#define PADCFG0_GPIORXDIS BIT(9) 57#define PADCFG0_GPIOTXDIS BIT(8) 58#define PADCFG0_GPIORXSTATE BIT(1) 59#define PADCFG0_GPIOTXSTATE BIT(0) 60 61#define PADCFG1 0x004 62#define PADCFG1_TERM_UP BIT(13) 63#define PADCFG1_TERM_SHIFT 10 64#define PADCFG1_TERM_MASK GENMASK(12, 10) 65#define PADCFG1_TERM_20K BIT(2) 66#define PADCFG1_TERM_5K BIT(1) 67#define PADCFG1_TERM_1K BIT(0) 68#define PADCFG1_TERM_833 (BIT(1) | BIT(0)) 69 70#define PADCFG2 0x008 71#define PADCFG2_DEBEN BIT(0) 72#define PADCFG2_DEBOUNCE_SHIFT 1 73#define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1) 74 75#define DEBOUNCE_PERIOD_NSEC 31250 76 77struct intel_pad_context { 78 u32 padcfg0; 79 u32 padcfg1; 80 u32 padcfg2; 81}; 82 83struct intel_community_context { 84 u32 *intmask; 85 u32 *hostown; 86}; 87 88#define pin_to_padno(c, p) ((p) - (c)->pin_base) 89#define padgroup_offset(g, p) ((p) - (g)->base) 90 91static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, 92 unsigned int pin) 93{ 94 struct intel_community *community; 95 int i; 96 97 for (i = 0; i < pctrl->ncommunities; i++) { 98 community = &pctrl->communities[i]; 99 if (pin >= community->pin_base && 100 pin < community->pin_base + community->npins) 101 return community; 102 } 103 104 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); 105 return NULL; 106} 107 108static const struct intel_padgroup * 109intel_community_get_padgroup(const struct intel_community *community, 110 unsigned int pin) 111{ 112 int i; 113 114 for (i = 0; i < community->ngpps; i++) { 115 const struct intel_padgroup *padgrp = &community->gpps[i]; 116 117 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size) 118 return padgrp; 119 } 120 121 return NULL; 122} 123 124static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, 125 unsigned int pin, unsigned int reg) 126{ 127 const struct intel_community *community; 128 unsigned int padno; 129 size_t nregs; 130 131 community = intel_get_community(pctrl, pin); 132 if (!community) 133 return NULL; 134 135 padno = pin_to_padno(community, pin); 136 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2; 137 138 if (reg >= nregs * 4) 139 return NULL; 140 141 return community->pad_regs + reg + padno * nregs * 4; 142} 143 144static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin) 145{ 146 const struct intel_community *community; 147 const struct intel_padgroup *padgrp; 148 unsigned int gpp, offset, gpp_offset; 149 void __iomem *padown; 150 151 community = intel_get_community(pctrl, pin); 152 if (!community) 153 return false; 154 if (!community->padown_offset) 155 return true; 156 157 padgrp = intel_community_get_padgroup(community, pin); 158 if (!padgrp) 159 return false; 160 161 gpp_offset = padgroup_offset(padgrp, pin); 162 gpp = PADOWN_GPP(gpp_offset); 163 offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4; 164 padown = community->regs + offset; 165 166 return !(readl(padown) & PADOWN_MASK(gpp_offset)); 167} 168 169static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin) 170{ 171 const struct intel_community *community; 172 const struct intel_padgroup *padgrp; 173 unsigned int offset, gpp_offset; 174 void __iomem *hostown; 175 176 community = intel_get_community(pctrl, pin); 177 if (!community) 178 return true; 179 if (!community->hostown_offset) 180 return false; 181 182 padgrp = intel_community_get_padgroup(community, pin); 183 if (!padgrp) 184 return true; 185 186 gpp_offset = padgroup_offset(padgrp, pin); 187 offset = community->hostown_offset + padgrp->reg_num * 4; 188 hostown = community->regs + offset; 189 190 return !(readl(hostown) & BIT(gpp_offset)); 191} 192 193/** 194 * enum - Locking variants of the pad configuration 195 * 196 * @PAD_UNLOCKED: pad is fully controlled by the configuration registers 197 * @PAD_LOCKED: pad configuration registers, except TX state, are locked 198 * @PAD_LOCKED_TX: pad configuration TX state is locked 199 * @PAD_LOCKED_FULL: pad configuration registers are locked completely 200 * 201 * Locking is considered as read-only mode for corresponding registers and 202 * their respective fields. That said, TX state bit is locked separately from 203 * the main locking scheme. 204 */ 205enum { 206 PAD_UNLOCKED = 0, 207 PAD_LOCKED = 1, 208 PAD_LOCKED_TX = 2, 209 PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX, 210}; 211 212static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin) 213{ 214 struct intel_community *community; 215 const struct intel_padgroup *padgrp; 216 unsigned int offset, gpp_offset; 217 u32 value; 218 int ret = PAD_UNLOCKED; 219 220 community = intel_get_community(pctrl, pin); 221 if (!community) 222 return PAD_LOCKED_FULL; 223 if (!community->padcfglock_offset) 224 return PAD_UNLOCKED; 225 226 padgrp = intel_community_get_padgroup(community, pin); 227 if (!padgrp) 228 return PAD_LOCKED_FULL; 229 230 gpp_offset = padgroup_offset(padgrp, pin); 231 232 /* 233 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, 234 * the pad is considered unlocked. Any other case means that it is 235 * either fully or partially locked. 236 */ 237 offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8; 238 value = readl(community->regs + offset); 239 if (value & BIT(gpp_offset)) 240 ret |= PAD_LOCKED; 241 242 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8; 243 value = readl(community->regs + offset); 244 if (value & BIT(gpp_offset)) 245 ret |= PAD_LOCKED_TX; 246 247 return ret; 248} 249 250static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin) 251{ 252 return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED; 253} 254 255static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin) 256{ 257 return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin); 258} 259 260static int intel_get_groups_count(struct pinctrl_dev *pctldev) 261{ 262 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 263 264 return pctrl->soc->ngroups; 265} 266 267static const char *intel_get_group_name(struct pinctrl_dev *pctldev, 268 unsigned int group) 269{ 270 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 271 272 return pctrl->soc->groups[group].name; 273} 274 275static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, 276 const unsigned int **pins, unsigned int *npins) 277{ 278 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 279 280 *pins = pctrl->soc->groups[group].pins; 281 *npins = pctrl->soc->groups[group].npins; 282 return 0; 283} 284 285static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 286 unsigned int pin) 287{ 288 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 289 void __iomem *padcfg; 290 u32 cfg0, cfg1, mode; 291 int locked; 292 bool acpi; 293 294 if (!intel_pad_owned_by_host(pctrl, pin)) { 295 seq_puts(s, "not available"); 296 return; 297 } 298 299 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 300 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 301 302 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 303 if (mode == PADCFG0_PMODE_GPIO) 304 seq_puts(s, "GPIO "); 305 else 306 seq_printf(s, "mode %d ", mode); 307 308 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); 309 310 /* Dump the additional PADCFG registers if available */ 311 padcfg = intel_get_padcfg(pctrl, pin, PADCFG2); 312 if (padcfg) 313 seq_printf(s, " 0x%08x", readl(padcfg)); 314 315 locked = intel_pad_locked(pctrl, pin); 316 acpi = intel_pad_acpi_mode(pctrl, pin); 317 318 if (locked || acpi) { 319 seq_puts(s, " ["); 320 if (locked) 321 seq_puts(s, "LOCKED"); 322 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX) 323 seq_puts(s, " tx"); 324 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL) 325 seq_puts(s, " full"); 326 327 if (locked && acpi) 328 seq_puts(s, ", "); 329 330 if (acpi) 331 seq_puts(s, "ACPI"); 332 seq_puts(s, "]"); 333 } 334} 335 336static const struct pinctrl_ops intel_pinctrl_ops = { 337 .get_groups_count = intel_get_groups_count, 338 .get_group_name = intel_get_group_name, 339 .get_group_pins = intel_get_group_pins, 340 .pin_dbg_show = intel_pin_dbg_show, 341}; 342 343static int intel_get_functions_count(struct pinctrl_dev *pctldev) 344{ 345 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 346 347 return pctrl->soc->nfunctions; 348} 349 350static const char *intel_get_function_name(struct pinctrl_dev *pctldev, 351 unsigned int function) 352{ 353 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 354 355 return pctrl->soc->functions[function].name; 356} 357 358static int intel_get_function_groups(struct pinctrl_dev *pctldev, 359 unsigned int function, 360 const char * const **groups, 361 unsigned int * const ngroups) 362{ 363 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 364 365 *groups = pctrl->soc->functions[function].groups; 366 *ngroups = pctrl->soc->functions[function].ngroups; 367 return 0; 368} 369 370static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, 371 unsigned int function, unsigned int group) 372{ 373 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 374 const struct intel_pingroup *grp = &pctrl->soc->groups[group]; 375 unsigned long flags; 376 int i; 377 378 raw_spin_lock_irqsave(&pctrl->lock, flags); 379 380 /* 381 * All pins in the groups needs to be accessible and writable 382 * before we can enable the mux for this group. 383 */ 384 for (i = 0; i < grp->npins; i++) { 385 if (!intel_pad_usable(pctrl, grp->pins[i])) { 386 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 387 return -EBUSY; 388 } 389 } 390 391 /* Now enable the mux setting for each pin in the group */ 392 for (i = 0; i < grp->npins; i++) { 393 void __iomem *padcfg0; 394 u32 value; 395 396 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0); 397 value = readl(padcfg0); 398 399 value &= ~PADCFG0_PMODE_MASK; 400 401 if (grp->modes) 402 value |= grp->modes[i] << PADCFG0_PMODE_SHIFT; 403 else 404 value |= grp->mode << PADCFG0_PMODE_SHIFT; 405 406 writel(value, padcfg0); 407 } 408 409 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 410 411 return 0; 412} 413 414static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input) 415{ 416 u32 value; 417 418 value = readl(padcfg0); 419 if (input) { 420 value &= ~PADCFG0_GPIORXDIS; 421 value |= PADCFG0_GPIOTXDIS; 422 } else { 423 value &= ~PADCFG0_GPIOTXDIS; 424 value |= PADCFG0_GPIORXDIS; 425 } 426 writel(value, padcfg0); 427} 428 429static int __intel_gpio_get_gpio_mode(u32 value) 430{ 431 return (value & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 432} 433 434static int intel_gpio_get_gpio_mode(void __iomem *padcfg0) 435{ 436 return __intel_gpio_get_gpio_mode(readl(padcfg0)); 437} 438 439static void intel_gpio_set_gpio_mode(void __iomem *padcfg0) 440{ 441 u32 value; 442 443 value = readl(padcfg0); 444 445 /* Put the pad into GPIO mode */ 446 value &= ~PADCFG0_PMODE_MASK; 447 value |= PADCFG0_PMODE_GPIO; 448 449 /* Disable TX buffer and enable RX (this will be input) */ 450 value &= ~PADCFG0_GPIORXDIS; 451 value |= PADCFG0_GPIOTXDIS; 452 453 /* Disable SCI/SMI/NMI generation */ 454 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI); 455 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI); 456 457 writel(value, padcfg0); 458} 459 460static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, 461 struct pinctrl_gpio_range *range, 462 unsigned int pin) 463{ 464 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 465 void __iomem *padcfg0; 466 unsigned long flags; 467 468 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 469 470 raw_spin_lock_irqsave(&pctrl->lock, flags); 471 472 if (!intel_pad_owned_by_host(pctrl, pin)) { 473 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 474 return -EBUSY; 475 } 476 477 if (!intel_pad_is_unlocked(pctrl, pin)) { 478 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 479 return 0; 480 } 481 482 /* 483 * If pin is already configured in GPIO mode, we assume that 484 * firmware provides correct settings. In such case we avoid 485 * potential glitches on the pin. Otherwise, for the pin in 486 * alternative mode, consumer has to supply respective flags. 487 */ 488 if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) { 489 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 490 return 0; 491 } 492 493 intel_gpio_set_gpio_mode(padcfg0); 494 495 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 496 497 return 0; 498} 499 500static int intel_gpio_set_direction(struct pinctrl_dev *pctldev, 501 struct pinctrl_gpio_range *range, 502 unsigned int pin, bool input) 503{ 504 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 505 void __iomem *padcfg0; 506 unsigned long flags; 507 508 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 509 510 raw_spin_lock_irqsave(&pctrl->lock, flags); 511 __intel_gpio_set_direction(padcfg0, input); 512 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 513 514 return 0; 515} 516 517static const struct pinmux_ops intel_pinmux_ops = { 518 .get_functions_count = intel_get_functions_count, 519 .get_function_name = intel_get_function_name, 520 .get_function_groups = intel_get_function_groups, 521 .set_mux = intel_pinmux_set_mux, 522 .gpio_request_enable = intel_gpio_request_enable, 523 .gpio_set_direction = intel_gpio_set_direction, 524}; 525 526static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin, 527 enum pin_config_param param, u32 *arg) 528{ 529 const struct intel_community *community; 530 void __iomem *padcfg1; 531 unsigned long flags; 532 u32 value, term; 533 534 community = intel_get_community(pctrl, pin); 535 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 536 537 raw_spin_lock_irqsave(&pctrl->lock, flags); 538 value = readl(padcfg1); 539 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 540 541 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT; 542 543 switch (param) { 544 case PIN_CONFIG_BIAS_DISABLE: 545 if (term) 546 return -EINVAL; 547 break; 548 549 case PIN_CONFIG_BIAS_PULL_UP: 550 if (!term || !(value & PADCFG1_TERM_UP)) 551 return -EINVAL; 552 553 switch (term) { 554 case PADCFG1_TERM_833: 555 *arg = 833; 556 break; 557 case PADCFG1_TERM_1K: 558 *arg = 1000; 559 break; 560 case PADCFG1_TERM_5K: 561 *arg = 5000; 562 break; 563 case PADCFG1_TERM_20K: 564 *arg = 20000; 565 break; 566 } 567 568 break; 569 570 case PIN_CONFIG_BIAS_PULL_DOWN: 571 if (!term || value & PADCFG1_TERM_UP) 572 return -EINVAL; 573 574 switch (term) { 575 case PADCFG1_TERM_833: 576 if (!(community->features & PINCTRL_FEATURE_1K_PD)) 577 return -EINVAL; 578 *arg = 833; 579 break; 580 case PADCFG1_TERM_1K: 581 if (!(community->features & PINCTRL_FEATURE_1K_PD)) 582 return -EINVAL; 583 *arg = 1000; 584 break; 585 case PADCFG1_TERM_5K: 586 *arg = 5000; 587 break; 588 case PADCFG1_TERM_20K: 589 *arg = 20000; 590 break; 591 } 592 593 break; 594 595 default: 596 return -EINVAL; 597 } 598 599 return 0; 600} 601 602static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin, 603 enum pin_config_param param, u32 *arg) 604{ 605 void __iomem *padcfg2; 606 unsigned long flags; 607 unsigned long v; 608 u32 value2; 609 610 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 611 if (!padcfg2) 612 return -ENOTSUPP; 613 614 raw_spin_lock_irqsave(&pctrl->lock, flags); 615 value2 = readl(padcfg2); 616 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 617 if (!(value2 & PADCFG2_DEBEN)) 618 return -EINVAL; 619 620 v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT; 621 *arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC; 622 623 return 0; 624} 625 626static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 627 unsigned long *config) 628{ 629 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 630 enum pin_config_param param = pinconf_to_config_param(*config); 631 u32 arg = 0; 632 int ret; 633 634 if (!intel_pad_owned_by_host(pctrl, pin)) 635 return -ENOTSUPP; 636 637 switch (param) { 638 case PIN_CONFIG_BIAS_DISABLE: 639 case PIN_CONFIG_BIAS_PULL_UP: 640 case PIN_CONFIG_BIAS_PULL_DOWN: 641 ret = intel_config_get_pull(pctrl, pin, param, &arg); 642 if (ret) 643 return ret; 644 break; 645 646 case PIN_CONFIG_INPUT_DEBOUNCE: 647 ret = intel_config_get_debounce(pctrl, pin, param, &arg); 648 if (ret) 649 return ret; 650 break; 651 652 default: 653 return -ENOTSUPP; 654 } 655 656 *config = pinconf_to_config_packed(param, arg); 657 return 0; 658} 659 660static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, 661 unsigned long config) 662{ 663 unsigned int param = pinconf_to_config_param(config); 664 unsigned int arg = pinconf_to_config_argument(config); 665 const struct intel_community *community; 666 void __iomem *padcfg1; 667 unsigned long flags; 668 int ret = 0; 669 u32 value; 670 671 community = intel_get_community(pctrl, pin); 672 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 673 674 raw_spin_lock_irqsave(&pctrl->lock, flags); 675 676 value = readl(padcfg1); 677 678 switch (param) { 679 case PIN_CONFIG_BIAS_DISABLE: 680 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP); 681 break; 682 683 case PIN_CONFIG_BIAS_PULL_UP: 684 value &= ~PADCFG1_TERM_MASK; 685 686 value |= PADCFG1_TERM_UP; 687 688 /* Set default strength value in case none is given */ 689 if (arg == 1) 690 arg = 5000; 691 692 switch (arg) { 693 case 20000: 694 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 695 break; 696 case 5000: 697 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 698 break; 699 case 1000: 700 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 701 break; 702 case 833: 703 value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT; 704 break; 705 default: 706 ret = -EINVAL; 707 } 708 709 break; 710 711 case PIN_CONFIG_BIAS_PULL_DOWN: 712 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK); 713 714 /* Set default strength value in case none is given */ 715 if (arg == 1) 716 arg = 5000; 717 718 switch (arg) { 719 case 20000: 720 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 721 break; 722 case 5000: 723 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 724 break; 725 case 1000: 726 if (!(community->features & PINCTRL_FEATURE_1K_PD)) { 727 ret = -EINVAL; 728 break; 729 } 730 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 731 break; 732 case 833: 733 if (!(community->features & PINCTRL_FEATURE_1K_PD)) { 734 ret = -EINVAL; 735 break; 736 } 737 value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT; 738 break; 739 default: 740 ret = -EINVAL; 741 } 742 743 break; 744 } 745 746 if (!ret) 747 writel(value, padcfg1); 748 749 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 750 751 return ret; 752} 753 754static int intel_config_set_debounce(struct intel_pinctrl *pctrl, 755 unsigned int pin, unsigned int debounce) 756{ 757 void __iomem *padcfg0, *padcfg2; 758 unsigned long flags; 759 u32 value0, value2; 760 761 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 762 if (!padcfg2) 763 return -ENOTSUPP; 764 765 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 766 767 raw_spin_lock_irqsave(&pctrl->lock, flags); 768 769 value0 = readl(padcfg0); 770 value2 = readl(padcfg2); 771 772 /* Disable glitch filter and debouncer */ 773 value0 &= ~PADCFG0_PREGFRXSEL; 774 value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK); 775 776 if (debounce) { 777 unsigned long v; 778 779 v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC); 780 if (v < 3 || v > 15) { 781 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 782 return -EINVAL; 783 } 784 785 /* Enable glitch filter and debouncer */ 786 value0 |= PADCFG0_PREGFRXSEL; 787 value2 |= v << PADCFG2_DEBOUNCE_SHIFT; 788 value2 |= PADCFG2_DEBEN; 789 } 790 791 writel(value0, padcfg0); 792 writel(value2, padcfg2); 793 794 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 795 796 return 0; 797} 798 799static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 800 unsigned long *configs, unsigned int nconfigs) 801{ 802 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 803 int i, ret; 804 805 if (!intel_pad_usable(pctrl, pin)) 806 return -ENOTSUPP; 807 808 for (i = 0; i < nconfigs; i++) { 809 switch (pinconf_to_config_param(configs[i])) { 810 case PIN_CONFIG_BIAS_DISABLE: 811 case PIN_CONFIG_BIAS_PULL_UP: 812 case PIN_CONFIG_BIAS_PULL_DOWN: 813 ret = intel_config_set_pull(pctrl, pin, configs[i]); 814 if (ret) 815 return ret; 816 break; 817 818 case PIN_CONFIG_INPUT_DEBOUNCE: 819 ret = intel_config_set_debounce(pctrl, pin, 820 pinconf_to_config_argument(configs[i])); 821 if (ret) 822 return ret; 823 break; 824 825 default: 826 return -ENOTSUPP; 827 } 828 } 829 830 return 0; 831} 832 833static const struct pinconf_ops intel_pinconf_ops = { 834 .is_generic = true, 835 .pin_config_get = intel_config_get, 836 .pin_config_set = intel_config_set, 837}; 838 839static const struct pinctrl_desc intel_pinctrl_desc = { 840 .pctlops = &intel_pinctrl_ops, 841 .pmxops = &intel_pinmux_ops, 842 .confops = &intel_pinconf_ops, 843 .owner = THIS_MODULE, 844}; 845 846/** 847 * intel_gpio_to_pin() - Translate from GPIO offset to pin number 848 * @pctrl: Pinctrl structure 849 * @offset: GPIO offset from gpiolib 850 * @community: Community is filled here if not %NULL 851 * @padgrp: Pad group is filled here if not %NULL 852 * 853 * When coming through gpiolib irqchip, the GPIO offset is not 854 * automatically translated to pinctrl pin number. This function can be 855 * used to find out the corresponding pinctrl pin. 856 */ 857static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset, 858 const struct intel_community **community, 859 const struct intel_padgroup **padgrp) 860{ 861 int i; 862 863 for (i = 0; i < pctrl->ncommunities; i++) { 864 const struct intel_community *comm = &pctrl->communities[i]; 865 int j; 866 867 for (j = 0; j < comm->ngpps; j++) { 868 const struct intel_padgroup *pgrp = &comm->gpps[j]; 869 870 if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) 871 continue; 872 873 if (offset >= pgrp->gpio_base && 874 offset < pgrp->gpio_base + pgrp->size) { 875 int pin; 876 877 pin = pgrp->base + offset - pgrp->gpio_base; 878 if (community) 879 *community = comm; 880 if (padgrp) 881 *padgrp = pgrp; 882 883 return pin; 884 } 885 } 886 } 887 888 return -EINVAL; 889} 890 891/** 892 * intel_pin_to_gpio() - Translate from pin number to GPIO offset 893 * @pctrl: Pinctrl structure 894 * @pin: pin number 895 * 896 * Translate the pin number of pinctrl to GPIO offset 897 */ 898static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin) 899{ 900 const struct intel_community *community; 901 const struct intel_padgroup *padgrp; 902 903 community = intel_get_community(pctrl, pin); 904 if (!community) 905 return -EINVAL; 906 907 padgrp = intel_community_get_padgroup(community, pin); 908 if (!padgrp) 909 return -EINVAL; 910 911 return pin - padgrp->base + padgrp->gpio_base; 912} 913 914static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset) 915{ 916 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 917 void __iomem *reg; 918 u32 padcfg0; 919 int pin; 920 921 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 922 if (pin < 0) 923 return -EINVAL; 924 925 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 926 if (!reg) 927 return -EINVAL; 928 929 padcfg0 = readl(reg); 930 if (!(padcfg0 & PADCFG0_GPIOTXDIS)) 931 return !!(padcfg0 & PADCFG0_GPIOTXSTATE); 932 933 return !!(padcfg0 & PADCFG0_GPIORXSTATE); 934} 935 936static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset, 937 int value) 938{ 939 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 940 unsigned long flags; 941 void __iomem *reg; 942 u32 padcfg0; 943 int pin; 944 945 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 946 if (pin < 0) 947 return; 948 949 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 950 if (!reg) 951 return; 952 953 raw_spin_lock_irqsave(&pctrl->lock, flags); 954 padcfg0 = readl(reg); 955 if (value) 956 padcfg0 |= PADCFG0_GPIOTXSTATE; 957 else 958 padcfg0 &= ~PADCFG0_GPIOTXSTATE; 959 writel(padcfg0, reg); 960 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 961} 962 963static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 964{ 965 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 966 unsigned long flags; 967 void __iomem *reg; 968 u32 padcfg0; 969 int pin; 970 971 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 972 if (pin < 0) 973 return -EINVAL; 974 975 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 976 if (!reg) 977 return -EINVAL; 978 979 raw_spin_lock_irqsave(&pctrl->lock, flags); 980 padcfg0 = readl(reg); 981 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 982 if (padcfg0 & PADCFG0_PMODE_MASK) 983 return -EINVAL; 984 985 if (padcfg0 & PADCFG0_GPIOTXDIS) 986 return GPIO_LINE_DIRECTION_IN; 987 988 return GPIO_LINE_DIRECTION_OUT; 989} 990 991static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 992{ 993 return pinctrl_gpio_direction_input(chip->base + offset); 994} 995 996static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 997 int value) 998{ 999 intel_gpio_set(chip, offset, value); 1000 return pinctrl_gpio_direction_output(chip->base + offset); 1001} 1002 1003static const struct gpio_chip intel_gpio_chip = { 1004 .owner = THIS_MODULE, 1005 .request = gpiochip_generic_request, 1006 .free = gpiochip_generic_free, 1007 .get_direction = intel_gpio_get_direction, 1008 .direction_input = intel_gpio_direction_input, 1009 .direction_output = intel_gpio_direction_output, 1010 .get = intel_gpio_get, 1011 .set = intel_gpio_set, 1012 .set_config = gpiochip_generic_config, 1013}; 1014 1015static void intel_gpio_irq_ack(struct irq_data *d) 1016{ 1017 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1018 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1019 const struct intel_community *community; 1020 const struct intel_padgroup *padgrp; 1021 int pin; 1022 1023 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); 1024 if (pin >= 0) { 1025 unsigned int gpp, gpp_offset, is_offset; 1026 1027 gpp = padgrp->reg_num; 1028 gpp_offset = padgroup_offset(padgrp, pin); 1029 is_offset = community->is_offset + gpp * 4; 1030 1031 raw_spin_lock(&pctrl->lock); 1032 writel(BIT(gpp_offset), community->regs + is_offset); 1033 raw_spin_unlock(&pctrl->lock); 1034 } 1035} 1036 1037static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask) 1038{ 1039 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1040 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1041 const struct intel_community *community; 1042 const struct intel_padgroup *padgrp; 1043 int pin; 1044 1045 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); 1046 if (pin >= 0) { 1047 unsigned int gpp, gpp_offset; 1048 unsigned long flags; 1049 void __iomem *reg, *is; 1050 u32 value; 1051 1052 gpp = padgrp->reg_num; 1053 gpp_offset = padgroup_offset(padgrp, pin); 1054 1055 reg = community->regs + community->ie_offset + gpp * 4; 1056 is = community->regs + community->is_offset + gpp * 4; 1057 1058 raw_spin_lock_irqsave(&pctrl->lock, flags); 1059 1060 /* Clear interrupt status first to avoid unexpected interrupt */ 1061 writel(BIT(gpp_offset), is); 1062 1063 value = readl(reg); 1064 if (mask) 1065 value &= ~BIT(gpp_offset); 1066 else 1067 value |= BIT(gpp_offset); 1068 writel(value, reg); 1069 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1070 } 1071} 1072 1073static void intel_gpio_irq_mask(struct irq_data *d) 1074{ 1075 intel_gpio_irq_mask_unmask(d, true); 1076} 1077 1078static void intel_gpio_irq_unmask(struct irq_data *d) 1079{ 1080 intel_gpio_irq_mask_unmask(d, false); 1081} 1082 1083static int intel_gpio_irq_type(struct irq_data *d, unsigned int type) 1084{ 1085 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1086 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1087 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 1088 unsigned long flags; 1089 void __iomem *reg; 1090 u32 value; 1091 1092 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 1093 if (!reg) 1094 return -EINVAL; 1095 1096 /* 1097 * If the pin is in ACPI mode it is still usable as a GPIO but it 1098 * cannot be used as IRQ because GPI_IS status bit will not be 1099 * updated by the host controller hardware. 1100 */ 1101 if (intel_pad_acpi_mode(pctrl, pin)) { 1102 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); 1103 return -EPERM; 1104 } 1105 1106 raw_spin_lock_irqsave(&pctrl->lock, flags); 1107 1108 intel_gpio_set_gpio_mode(reg); 1109 1110 value = readl(reg); 1111 1112 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV); 1113 1114 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 1115 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT; 1116 } else if (type & IRQ_TYPE_EDGE_FALLING) { 1117 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 1118 value |= PADCFG0_RXINV; 1119 } else if (type & IRQ_TYPE_EDGE_RISING) { 1120 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 1121 } else if (type & IRQ_TYPE_LEVEL_MASK) { 1122 if (type & IRQ_TYPE_LEVEL_LOW) 1123 value |= PADCFG0_RXINV; 1124 } else { 1125 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT; 1126 } 1127 1128 writel(value, reg); 1129 1130 if (type & IRQ_TYPE_EDGE_BOTH) 1131 irq_set_handler_locked(d, handle_edge_irq); 1132 else if (type & IRQ_TYPE_LEVEL_MASK) 1133 irq_set_handler_locked(d, handle_level_irq); 1134 1135 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1136 1137 return 0; 1138} 1139 1140static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) 1141{ 1142 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1143 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1144 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 1145 1146 if (on) 1147 enable_irq_wake(pctrl->irq); 1148 else 1149 disable_irq_wake(pctrl->irq); 1150 1151 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin); 1152 return 0; 1153} 1154 1155static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, 1156 const struct intel_community *community) 1157{ 1158 struct gpio_chip *gc = &pctrl->chip; 1159 unsigned int gpp; 1160 int ret = 0; 1161 1162 for (gpp = 0; gpp < community->ngpps; gpp++) { 1163 const struct intel_padgroup *padgrp = &community->gpps[gpp]; 1164 unsigned long pending, enabled, gpp_offset; 1165 unsigned long flags; 1166 1167 raw_spin_lock_irqsave(&pctrl->lock, flags); 1168 1169 pending = readl(community->regs + community->is_offset + 1170 padgrp->reg_num * 4); 1171 enabled = readl(community->regs + community->ie_offset + 1172 padgrp->reg_num * 4); 1173 1174 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1175 1176 /* Only interrupts that are enabled */ 1177 pending &= enabled; 1178 1179 for_each_set_bit(gpp_offset, &pending, padgrp->size) { 1180 unsigned int irq; 1181 1182 irq = irq_find_mapping(gc->irq.domain, 1183 padgrp->gpio_base + gpp_offset); 1184 generic_handle_irq(irq); 1185 } 1186 1187 ret += pending ? 1 : 0; 1188 } 1189 1190 return ret; 1191} 1192 1193static irqreturn_t intel_gpio_irq(int irq, void *data) 1194{ 1195 const struct intel_community *community; 1196 struct intel_pinctrl *pctrl = data; 1197 unsigned int i; 1198 int ret = 0; 1199 1200 /* Need to check all communities for pending interrupts */ 1201 for (i = 0; i < pctrl->ncommunities; i++) { 1202 community = &pctrl->communities[i]; 1203 ret += intel_gpio_community_irq_handler(pctrl, community); 1204 } 1205 1206 return IRQ_RETVAL(ret); 1207} 1208 1209static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) 1210{ 1211 int i; 1212 1213 for (i = 0; i < pctrl->ncommunities; i++) { 1214 const struct intel_community *community; 1215 void __iomem *base; 1216 unsigned int gpp; 1217 1218 community = &pctrl->communities[i]; 1219 base = community->regs; 1220 1221 for (gpp = 0; gpp < community->ngpps; gpp++) { 1222 /* Mask and clear all interrupts */ 1223 writel(0, base + community->ie_offset + gpp * 4); 1224 writel(0xffff, base + community->is_offset + gpp * 4); 1225 } 1226 } 1227} 1228 1229static int intel_gpio_irq_init_hw(struct gpio_chip *gc) 1230{ 1231 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1232 1233 /* 1234 * Make sure the interrupt lines are in a proper state before 1235 * further configuration. 1236 */ 1237 intel_gpio_irq_init(pctrl); 1238 1239 return 0; 1240} 1241 1242static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl, 1243 const struct intel_community *community) 1244{ 1245 int ret = 0, i; 1246 1247 for (i = 0; i < community->ngpps; i++) { 1248 const struct intel_padgroup *gpp = &community->gpps[i]; 1249 1250 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) 1251 continue; 1252 1253 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 1254 gpp->gpio_base, gpp->base, 1255 gpp->size); 1256 if (ret) 1257 return ret; 1258 } 1259 1260 return ret; 1261} 1262 1263static int intel_gpio_add_pin_ranges(struct gpio_chip *gc) 1264{ 1265 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1266 int ret, i; 1267 1268 for (i = 0; i < pctrl->ncommunities; i++) { 1269 struct intel_community *community = &pctrl->communities[i]; 1270 1271 ret = intel_gpio_add_community_ranges(pctrl, community); 1272 if (ret) { 1273 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 1274 return ret; 1275 } 1276 } 1277 1278 return 0; 1279} 1280 1281static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl) 1282{ 1283 const struct intel_community *community; 1284 unsigned int ngpio = 0; 1285 int i, j; 1286 1287 for (i = 0; i < pctrl->ncommunities; i++) { 1288 community = &pctrl->communities[i]; 1289 for (j = 0; j < community->ngpps; j++) { 1290 const struct intel_padgroup *gpp = &community->gpps[j]; 1291 1292 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) 1293 continue; 1294 1295 if (gpp->gpio_base + gpp->size > ngpio) 1296 ngpio = gpp->gpio_base + gpp->size; 1297 } 1298 } 1299 1300 return ngpio; 1301} 1302 1303static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) 1304{ 1305 int ret; 1306 struct gpio_irq_chip *girq; 1307 1308 pctrl->chip = intel_gpio_chip; 1309 1310 /* Setup GPIO chip */ 1311 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl); 1312 pctrl->chip.label = dev_name(pctrl->dev); 1313 pctrl->chip.parent = pctrl->dev; 1314 pctrl->chip.base = -1; 1315 pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges; 1316 pctrl->irq = irq; 1317 1318 /* Setup IRQ chip */ 1319 pctrl->irqchip.name = dev_name(pctrl->dev); 1320 pctrl->irqchip.irq_ack = intel_gpio_irq_ack; 1321 pctrl->irqchip.irq_mask = intel_gpio_irq_mask; 1322 pctrl->irqchip.irq_unmask = intel_gpio_irq_unmask; 1323 pctrl->irqchip.irq_set_type = intel_gpio_irq_type; 1324 pctrl->irqchip.irq_set_wake = intel_gpio_irq_wake; 1325 pctrl->irqchip.flags = IRQCHIP_MASK_ON_SUSPEND; 1326 1327 /* 1328 * On some platforms several GPIO controllers share the same interrupt 1329 * line. 1330 */ 1331 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, 1332 IRQF_SHARED | IRQF_NO_THREAD, 1333 dev_name(pctrl->dev), pctrl); 1334 if (ret) { 1335 dev_err(pctrl->dev, "failed to request interrupt\n"); 1336 return ret; 1337 } 1338 1339 girq = &pctrl->chip.irq; 1340 girq->chip = &pctrl->irqchip; 1341 /* This will let us handle the IRQ in the driver */ 1342 girq->parent_handler = NULL; 1343 girq->num_parents = 0; 1344 girq->default_type = IRQ_TYPE_NONE; 1345 girq->handler = handle_bad_irq; 1346 girq->init_hw = intel_gpio_irq_init_hw; 1347 1348 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); 1349 if (ret) { 1350 dev_err(pctrl->dev, "failed to register gpiochip\n"); 1351 return ret; 1352 } 1353 1354 return 0; 1355} 1356 1357static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl, 1358 struct intel_community *community) 1359{ 1360 struct intel_padgroup *gpps; 1361 unsigned int npins = community->npins; 1362 unsigned int padown_num = 0; 1363 size_t ngpps, i; 1364 1365 if (community->gpps) 1366 ngpps = community->ngpps; 1367 else 1368 ngpps = DIV_ROUND_UP(community->npins, community->gpp_size); 1369 1370 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); 1371 if (!gpps) 1372 return -ENOMEM; 1373 1374 for (i = 0; i < ngpps; i++) { 1375 if (community->gpps) { 1376 gpps[i] = community->gpps[i]; 1377 } else { 1378 unsigned int gpp_size = community->gpp_size; 1379 1380 gpps[i].reg_num = i; 1381 gpps[i].base = community->pin_base + i * gpp_size; 1382 gpps[i].size = min(gpp_size, npins); 1383 npins -= gpps[i].size; 1384 } 1385 1386 if (gpps[i].size > 32) 1387 return -EINVAL; 1388 1389 /* Special treatment for GPIO base */ 1390 switch (gpps[i].gpio_base) { 1391 case INTEL_GPIO_BASE_MATCH: 1392 gpps[i].gpio_base = gpps[i].base; 1393 break; 1394 case INTEL_GPIO_BASE_ZERO: 1395 gpps[i].gpio_base = 0; 1396 break; 1397 case INTEL_GPIO_BASE_NOMAP: 1398 default: 1399 break; 1400 } 1401 1402 gpps[i].padown_num = padown_num; 1403 1404 /* 1405 * In older hardware the number of padown registers per 1406 * group is fixed regardless of the group size. 1407 */ 1408 if (community->gpp_num_padown_regs) 1409 padown_num += community->gpp_num_padown_regs; 1410 else 1411 padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32); 1412 } 1413 1414 community->ngpps = ngpps; 1415 community->gpps = gpps; 1416 1417 return 0; 1418} 1419 1420static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) 1421{ 1422#ifdef CONFIG_PM_SLEEP 1423 const struct intel_pinctrl_soc_data *soc = pctrl->soc; 1424 struct intel_community_context *communities; 1425 struct intel_pad_context *pads; 1426 int i; 1427 1428 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); 1429 if (!pads) 1430 return -ENOMEM; 1431 1432 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, 1433 sizeof(*communities), GFP_KERNEL); 1434 if (!communities) 1435 return -ENOMEM; 1436 1437 1438 for (i = 0; i < pctrl->ncommunities; i++) { 1439 struct intel_community *community = &pctrl->communities[i]; 1440 u32 *intmask, *hostown; 1441 1442 intmask = devm_kcalloc(pctrl->dev, community->ngpps, 1443 sizeof(*intmask), GFP_KERNEL); 1444 if (!intmask) 1445 return -ENOMEM; 1446 1447 communities[i].intmask = intmask; 1448 1449 hostown = devm_kcalloc(pctrl->dev, community->ngpps, 1450 sizeof(*hostown), GFP_KERNEL); 1451 if (!hostown) 1452 return -ENOMEM; 1453 1454 communities[i].hostown = hostown; 1455 } 1456 1457 pctrl->context.pads = pads; 1458 pctrl->context.communities = communities; 1459#endif 1460 1461 return 0; 1462} 1463 1464static int intel_pinctrl_probe(struct platform_device *pdev, 1465 const struct intel_pinctrl_soc_data *soc_data) 1466{ 1467 struct intel_pinctrl *pctrl; 1468 int i, ret, irq; 1469 1470 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1471 if (!pctrl) 1472 return -ENOMEM; 1473 1474 pctrl->dev = &pdev->dev; 1475 pctrl->soc = soc_data; 1476 raw_spin_lock_init(&pctrl->lock); 1477 1478 /* 1479 * Make a copy of the communities which we can use to hold pointers 1480 * to the registers. 1481 */ 1482 pctrl->ncommunities = pctrl->soc->ncommunities; 1483 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities, 1484 sizeof(*pctrl->communities), GFP_KERNEL); 1485 if (!pctrl->communities) 1486 return -ENOMEM; 1487 1488 for (i = 0; i < pctrl->ncommunities; i++) { 1489 struct intel_community *community = &pctrl->communities[i]; 1490 void __iomem *regs; 1491 u32 padbar; 1492 1493 *community = pctrl->soc->communities[i]; 1494 1495 regs = devm_platform_ioremap_resource(pdev, community->barno); 1496 if (IS_ERR(regs)) 1497 return PTR_ERR(regs); 1498 1499 /* 1500 * Determine community features based on the revision if 1501 * not specified already. 1502 */ 1503 if (!community->features) { 1504 u32 rev; 1505 1506 rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT; 1507 if (rev >= 0x94) { 1508 community->features |= PINCTRL_FEATURE_DEBOUNCE; 1509 community->features |= PINCTRL_FEATURE_1K_PD; 1510 } 1511 } 1512 1513 /* Read offset of the pad configuration registers */ 1514 padbar = readl(regs + PADBAR); 1515 1516 community->regs = regs; 1517 community->pad_regs = regs + padbar; 1518 1519 ret = intel_pinctrl_add_padgroups(pctrl, community); 1520 if (ret) 1521 return ret; 1522 } 1523 1524 irq = platform_get_irq(pdev, 0); 1525 if (irq < 0) 1526 return irq; 1527 1528 ret = intel_pinctrl_pm_init(pctrl); 1529 if (ret) 1530 return ret; 1531 1532 pctrl->pctldesc = intel_pinctrl_desc; 1533 pctrl->pctldesc.name = dev_name(&pdev->dev); 1534 pctrl->pctldesc.pins = pctrl->soc->pins; 1535 pctrl->pctldesc.npins = pctrl->soc->npins; 1536 1537 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, 1538 pctrl); 1539 if (IS_ERR(pctrl->pctldev)) { 1540 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1541 return PTR_ERR(pctrl->pctldev); 1542 } 1543 1544 ret = intel_gpio_probe(pctrl, irq); 1545 if (ret) 1546 return ret; 1547 1548 platform_set_drvdata(pdev, pctrl); 1549 1550 return 0; 1551} 1552 1553int intel_pinctrl_probe_by_hid(struct platform_device *pdev) 1554{ 1555 const struct intel_pinctrl_soc_data *data; 1556 1557 data = device_get_match_data(&pdev->dev); 1558 if (!data) 1559 return -ENODATA; 1560 1561 return intel_pinctrl_probe(pdev, data); 1562} 1563EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid); 1564 1565int intel_pinctrl_probe_by_uid(struct platform_device *pdev) 1566{ 1567 const struct intel_pinctrl_soc_data *data; 1568 1569 data = intel_pinctrl_get_soc_data(pdev); 1570 if (IS_ERR(data)) 1571 return PTR_ERR(data); 1572 1573 return intel_pinctrl_probe(pdev, data); 1574} 1575EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid); 1576 1577const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev) 1578{ 1579 const struct intel_pinctrl_soc_data * const *table; 1580 const struct intel_pinctrl_soc_data *data = NULL; 1581 1582 table = device_get_match_data(&pdev->dev); 1583 if (table) { 1584 struct acpi_device *adev = ACPI_COMPANION(&pdev->dev); 1585 unsigned int i; 1586 1587 for (i = 0; table[i]; i++) { 1588 if (!strcmp(adev->pnp.unique_id, table[i]->uid)) { 1589 data = table[i]; 1590 break; 1591 } 1592 } 1593 } else { 1594 const struct platform_device_id *id; 1595 1596 id = platform_get_device_id(pdev); 1597 if (!id) 1598 return ERR_PTR(-ENODEV); 1599 1600 table = (const struct intel_pinctrl_soc_data * const *)id->driver_data; 1601 data = table[pdev->id]; 1602 } 1603 1604 return data ?: ERR_PTR(-ENODATA); 1605} 1606EXPORT_SYMBOL_GPL(intel_pinctrl_get_soc_data); 1607 1608#ifdef CONFIG_PM_SLEEP 1609static bool __intel_gpio_is_direct_irq(u32 value) 1610{ 1611 return (value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) && 1612 (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO); 1613} 1614 1615static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin) 1616{ 1617 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin); 1618 u32 value; 1619 1620 if (!pd || !intel_pad_usable(pctrl, pin)) 1621 return false; 1622 1623 /* 1624 * Only restore the pin if it is actually in use by the kernel (or 1625 * by userspace). It is possible that some pins are used by the 1626 * BIOS during resume and those are not always locked down so leave 1627 * them alone. 1628 */ 1629 if (pd->mux_owner || pd->gpio_owner || 1630 gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin))) 1631 return true; 1632 1633 /* 1634 * The firmware on some systems may configure GPIO pins to be 1635 * an interrupt source in so called "direct IRQ" mode. In such 1636 * cases the GPIO controller driver has no idea if those pins 1637 * are being used or not. At the same time, there is a known bug 1638 * in the firmwares that don't restore the pin settings correctly 1639 * after suspend, i.e. by an unknown reason the Rx value becomes 1640 * inverted. 1641 * 1642 * Hence, let's save and restore the pins that are configured 1643 * as GPIOs in the input mode with GPIROUTIOXAPIC bit set. 1644 * 1645 * See https://bugzilla.kernel.org/show_bug.cgi?id=214749. 1646 */ 1647 value = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 1648 if (__intel_gpio_is_direct_irq(value)) 1649 return true; 1650 1651 return false; 1652} 1653 1654int intel_pinctrl_suspend_noirq(struct device *dev) 1655{ 1656 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1657 struct intel_community_context *communities; 1658 struct intel_pad_context *pads; 1659 int i; 1660 1661 pads = pctrl->context.pads; 1662 for (i = 0; i < pctrl->soc->npins; i++) { 1663 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1664 void __iomem *padcfg; 1665 u32 val; 1666 1667 if (!intel_pinctrl_should_save(pctrl, desc->number)) 1668 continue; 1669 1670 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); 1671 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; 1672 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); 1673 pads[i].padcfg1 = val; 1674 1675 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); 1676 if (padcfg) 1677 pads[i].padcfg2 = readl(padcfg); 1678 } 1679 1680 communities = pctrl->context.communities; 1681 for (i = 0; i < pctrl->ncommunities; i++) { 1682 struct intel_community *community = &pctrl->communities[i]; 1683 void __iomem *base; 1684 unsigned int gpp; 1685 1686 base = community->regs + community->ie_offset; 1687 for (gpp = 0; gpp < community->ngpps; gpp++) 1688 communities[i].intmask[gpp] = readl(base + gpp * 4); 1689 1690 base = community->regs + community->hostown_offset; 1691 for (gpp = 0; gpp < community->ngpps; gpp++) 1692 communities[i].hostown[gpp] = readl(base + gpp * 4); 1693 } 1694 1695 return 0; 1696} 1697EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq); 1698 1699static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value) 1700{ 1701 u32 curr, updated; 1702 1703 curr = readl(reg); 1704 1705 updated = (curr & ~mask) | (value & mask); 1706 if (curr == updated) 1707 return false; 1708 1709 writel(updated, reg); 1710 return true; 1711} 1712 1713static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c, 1714 void __iomem *base, unsigned int gpp, u32 saved) 1715{ 1716 const struct intel_community *community = &pctrl->communities[c]; 1717 const struct intel_padgroup *padgrp = &community->gpps[gpp]; 1718 struct device *dev = pctrl->dev; 1719 const char *dummy; 1720 u32 requested = 0; 1721 unsigned int i; 1722 1723 if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) 1724 return; 1725 1726 for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy) 1727 requested |= BIT(i); 1728 1729 if (!intel_gpio_update_reg(base + gpp * 4, requested, saved)) 1730 return; 1731 1732 dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); 1733} 1734 1735static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c, 1736 void __iomem *base, unsigned int gpp, u32 saved) 1737{ 1738 struct device *dev = pctrl->dev; 1739 1740 if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved)) 1741 return; 1742 1743 dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); 1744} 1745 1746static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin, 1747 unsigned int reg, u32 saved) 1748{ 1749 u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0; 1750 unsigned int n = reg / sizeof(u32); 1751 struct device *dev = pctrl->dev; 1752 void __iomem *padcfg; 1753 1754 padcfg = intel_get_padcfg(pctrl, pin, reg); 1755 if (!padcfg) 1756 return; 1757 1758 if (!intel_gpio_update_reg(padcfg, ~mask, saved)) 1759 return; 1760 1761 dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg)); 1762} 1763 1764int intel_pinctrl_resume_noirq(struct device *dev) 1765{ 1766 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1767 const struct intel_community_context *communities; 1768 const struct intel_pad_context *pads; 1769 int i; 1770 1771 /* Mask all interrupts */ 1772 intel_gpio_irq_init(pctrl); 1773 1774 pads = pctrl->context.pads; 1775 for (i = 0; i < pctrl->soc->npins; i++) { 1776 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1777 1778 if (!(intel_pinctrl_should_save(pctrl, desc->number) || 1779 /* 1780 * If the firmware mangled the register contents too much, 1781 * check the saved value for the Direct IRQ mode. 1782 */ 1783 __intel_gpio_is_direct_irq(pads[i].padcfg0))) 1784 continue; 1785 1786 intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0); 1787 intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1); 1788 intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2); 1789 } 1790 1791 communities = pctrl->context.communities; 1792 for (i = 0; i < pctrl->ncommunities; i++) { 1793 struct intel_community *community = &pctrl->communities[i]; 1794 void __iomem *base; 1795 unsigned int gpp; 1796 1797 base = community->regs + community->ie_offset; 1798 for (gpp = 0; gpp < community->ngpps; gpp++) 1799 intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]); 1800 1801 base = community->regs + community->hostown_offset; 1802 for (gpp = 0; gpp < community->ngpps; gpp++) 1803 intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]); 1804 } 1805 1806 return 0; 1807} 1808EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq); 1809#endif 1810 1811MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); 1812MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1813MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver"); 1814MODULE_LICENSE("GPL v2"); 1815