1// SPDX-License-Identifier: GPL-2.0+ 2// 3// Core driver for the imx pin controller in imx1/21/27 4// 5// Copyright (C) 2013 Pengutronix 6// Author: Markus Pargmann <mpa@pengutronix.de> 7// 8// Based on pinctrl-imx.c: 9// Author: Dong Aisheng <dong.aisheng@linaro.org> 10// Copyright (C) 2012 Freescale Semiconductor, Inc. 11// Copyright (C) 2012 Linaro Ltd. 12 13#include <linux/bitops.h> 14#include <linux/err.h> 15#include <linux/init.h> 16#include <linux/io.h> 17#include <linux/of.h> 18#include <linux/of_device.h> 19#include <linux/pinctrl/machine.h> 20#include <linux/pinctrl/pinconf.h> 21#include <linux/pinctrl/pinctrl.h> 22#include <linux/pinctrl/pinmux.h> 23#include <linux/slab.h> 24 25#include "../core.h" 26#include "pinctrl-imx1.h" 27 28struct imx1_pinctrl { 29 struct device *dev; 30 struct pinctrl_dev *pctl; 31 void __iomem *base; 32 const struct imx1_pinctrl_soc_info *info; 33}; 34 35/* 36 * MX1 register offsets 37 */ 38 39#define MX1_DDIR 0x00 40#define MX1_OCR 0x04 41#define MX1_ICONFA 0x0c 42#define MX1_ICONFB 0x14 43#define MX1_GIUS 0x20 44#define MX1_GPR 0x38 45#define MX1_PUEN 0x40 46 47#define MX1_PORT_STRIDE 0x100 48 49 50/* 51 * MUX_ID format defines 52 */ 53#define MX1_MUX_FUNCTION(val) (BIT(0) & val) 54#define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1) 55#define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2) 56#define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4) 57#define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8) 58#define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10) 59 60 61/* 62 * IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX 63 * control registers are separated into function, output configuration, input 64 * configuration A, input configuration B, GPIO in use and data direction. 65 * 66 * Those controls that are represented by 1 bit have a direct mapping between 67 * bit position and pin id. If they are represented by 2 bit, the lower 16 pins 68 * are in the first register and the upper 16 pins in the second (next) 69 * register. pin_id is stored in bit (pin_id%16)*2 and the bit above. 70 */ 71 72/* 73 * Calculates the register offset from a pin_id 74 */ 75static void __iomem *imx1_mem(struct imx1_pinctrl *ipctl, unsigned int pin_id) 76{ 77 unsigned int port = pin_id / 32; 78 return ipctl->base + port * MX1_PORT_STRIDE; 79} 80 81/* 82 * Write to a register with 2 bits per pin. The function will automatically 83 * use the next register if the pin is managed in the second register. 84 */ 85static void imx1_write_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, 86 u32 value, u32 reg_offset) 87{ 88 void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; 89 int offset = (pin_id % 16) * 2; /* offset, regardless of register used */ 90 int mask = ~(0x3 << offset); /* Mask for 2 bits at offset */ 91 u32 old_val; 92 u32 new_val; 93 94 /* Use the next register if the pin's port pin number is >=16 */ 95 if (pin_id % 32 >= 16) 96 reg += 0x04; 97 98 dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n", 99 reg, offset, value); 100 101 /* Get current state of pins */ 102 old_val = readl(reg); 103 old_val &= mask; 104 105 new_val = value & 0x3; /* Make sure value is really 2 bit */ 106 new_val <<= offset; 107 new_val |= old_val;/* Set new state for pin_id */ 108 109 writel(new_val, reg); 110} 111 112static void imx1_write_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, 113 u32 value, u32 reg_offset) 114{ 115 void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; 116 int offset = pin_id % 32; 117 int mask = ~BIT_MASK(offset); 118 u32 old_val; 119 u32 new_val; 120 121 /* Get current state of pins */ 122 old_val = readl(reg); 123 old_val &= mask; 124 125 new_val = value & 0x1; /* Make sure value is really 1 bit */ 126 new_val <<= offset; 127 new_val |= old_val;/* Set new state for pin_id */ 128 129 writel(new_val, reg); 130} 131 132static int imx1_read_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, 133 u32 reg_offset) 134{ 135 void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; 136 int offset = (pin_id % 16) * 2; 137 138 /* Use the next register if the pin's port pin number is >=16 */ 139 if (pin_id % 32 >= 16) 140 reg += 0x04; 141 142 return (readl(reg) & (BIT(offset) | BIT(offset+1))) >> offset; 143} 144 145static int imx1_read_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id, 146 u32 reg_offset) 147{ 148 void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; 149 int offset = pin_id % 32; 150 151 return !!(readl(reg) & BIT(offset)); 152} 153 154static inline const struct imx1_pin_group *imx1_pinctrl_find_group_by_name( 155 const struct imx1_pinctrl_soc_info *info, 156 const char *name) 157{ 158 const struct imx1_pin_group *grp = NULL; 159 int i; 160 161 for (i = 0; i < info->ngroups; i++) { 162 if (!strcmp(info->groups[i].name, name)) { 163 grp = &info->groups[i]; 164 break; 165 } 166 } 167 168 return grp; 169} 170 171static int imx1_get_groups_count(struct pinctrl_dev *pctldev) 172{ 173 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 174 const struct imx1_pinctrl_soc_info *info = ipctl->info; 175 176 return info->ngroups; 177} 178 179static const char *imx1_get_group_name(struct pinctrl_dev *pctldev, 180 unsigned selector) 181{ 182 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 183 const struct imx1_pinctrl_soc_info *info = ipctl->info; 184 185 return info->groups[selector].name; 186} 187 188static int imx1_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 189 const unsigned int **pins, 190 unsigned *npins) 191{ 192 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 193 const struct imx1_pinctrl_soc_info *info = ipctl->info; 194 195 if (selector >= info->ngroups) 196 return -EINVAL; 197 198 *pins = info->groups[selector].pin_ids; 199 *npins = info->groups[selector].npins; 200 201 return 0; 202} 203 204static void imx1_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 205 unsigned offset) 206{ 207 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 208 209 seq_printf(s, "GPIO %d, function %d, direction %d, oconf %d, iconfa %d, iconfb %d", 210 imx1_read_bit(ipctl, offset, MX1_GIUS), 211 imx1_read_bit(ipctl, offset, MX1_GPR), 212 imx1_read_bit(ipctl, offset, MX1_DDIR), 213 imx1_read_2bit(ipctl, offset, MX1_OCR), 214 imx1_read_2bit(ipctl, offset, MX1_ICONFA), 215 imx1_read_2bit(ipctl, offset, MX1_ICONFB)); 216} 217 218static int imx1_dt_node_to_map(struct pinctrl_dev *pctldev, 219 struct device_node *np, 220 struct pinctrl_map **map, unsigned *num_maps) 221{ 222 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 223 const struct imx1_pinctrl_soc_info *info = ipctl->info; 224 const struct imx1_pin_group *grp; 225 struct pinctrl_map *new_map; 226 struct device_node *parent; 227 int map_num = 1; 228 int i, j; 229 230 /* 231 * first find the group of this node and check if we need create 232 * config maps for pins 233 */ 234 grp = imx1_pinctrl_find_group_by_name(info, np->name); 235 if (!grp) { 236 dev_err(info->dev, "unable to find group for node %pOFn\n", 237 np); 238 return -EINVAL; 239 } 240 241 for (i = 0; i < grp->npins; i++) 242 map_num++; 243 244 new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map), 245 GFP_KERNEL); 246 if (!new_map) 247 return -ENOMEM; 248 249 *map = new_map; 250 *num_maps = map_num; 251 252 /* create mux map */ 253 parent = of_get_parent(np); 254 if (!parent) { 255 kfree(new_map); 256 return -EINVAL; 257 } 258 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 259 new_map[0].data.mux.function = parent->name; 260 new_map[0].data.mux.group = np->name; 261 of_node_put(parent); 262 263 /* create config map */ 264 new_map++; 265 for (i = j = 0; i < grp->npins; i++) { 266 new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; 267 new_map[j].data.configs.group_or_pin = 268 pin_get_name(pctldev, grp->pins[i].pin_id); 269 new_map[j].data.configs.configs = &grp->pins[i].config; 270 new_map[j].data.configs.num_configs = 1; 271 j++; 272 } 273 274 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 275 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 276 277 return 0; 278} 279 280static void imx1_dt_free_map(struct pinctrl_dev *pctldev, 281 struct pinctrl_map *map, unsigned num_maps) 282{ 283 kfree(map); 284} 285 286static const struct pinctrl_ops imx1_pctrl_ops = { 287 .get_groups_count = imx1_get_groups_count, 288 .get_group_name = imx1_get_group_name, 289 .get_group_pins = imx1_get_group_pins, 290 .pin_dbg_show = imx1_pin_dbg_show, 291 .dt_node_to_map = imx1_dt_node_to_map, 292 .dt_free_map = imx1_dt_free_map, 293}; 294 295static int imx1_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 296 unsigned group) 297{ 298 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 299 const struct imx1_pinctrl_soc_info *info = ipctl->info; 300 const struct imx1_pin *pins; 301 unsigned int npins; 302 int i; 303 304 /* 305 * Configure the mux mode for each pin in the group for a specific 306 * function. 307 */ 308 pins = info->groups[group].pins; 309 npins = info->groups[group].npins; 310 311 WARN_ON(!pins || !npins); 312 313 dev_dbg(ipctl->dev, "enable function %s group %s\n", 314 info->functions[selector].name, info->groups[group].name); 315 316 for (i = 0; i < npins; i++) { 317 unsigned int mux = pins[i].mux_id; 318 unsigned int pin_id = pins[i].pin_id; 319 unsigned int afunction = MX1_MUX_FUNCTION(mux); 320 unsigned int gpio_in_use = MX1_MUX_GPIO(mux); 321 unsigned int direction = MX1_MUX_DIR(mux); 322 unsigned int gpio_oconf = MX1_MUX_OCONF(mux); 323 unsigned int gpio_iconfa = MX1_MUX_ICONFA(mux); 324 unsigned int gpio_iconfb = MX1_MUX_ICONFB(mux); 325 326 dev_dbg(pctldev->dev, "%s, pin 0x%x, function %d, gpio %d, direction %d, oconf %d, iconfa %d, iconfb %d\n", 327 __func__, pin_id, afunction, gpio_in_use, 328 direction, gpio_oconf, gpio_iconfa, 329 gpio_iconfb); 330 331 imx1_write_bit(ipctl, pin_id, gpio_in_use, MX1_GIUS); 332 imx1_write_bit(ipctl, pin_id, direction, MX1_DDIR); 333 334 if (gpio_in_use) { 335 imx1_write_2bit(ipctl, pin_id, gpio_oconf, MX1_OCR); 336 imx1_write_2bit(ipctl, pin_id, gpio_iconfa, 337 MX1_ICONFA); 338 imx1_write_2bit(ipctl, pin_id, gpio_iconfb, 339 MX1_ICONFB); 340 } else { 341 imx1_write_bit(ipctl, pin_id, afunction, MX1_GPR); 342 } 343 } 344 345 return 0; 346} 347 348static int imx1_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 349{ 350 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 351 const struct imx1_pinctrl_soc_info *info = ipctl->info; 352 353 return info->nfunctions; 354} 355 356static const char *imx1_pmx_get_func_name(struct pinctrl_dev *pctldev, 357 unsigned selector) 358{ 359 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 360 const struct imx1_pinctrl_soc_info *info = ipctl->info; 361 362 return info->functions[selector].name; 363} 364 365static int imx1_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, 366 const char * const **groups, 367 unsigned * const num_groups) 368{ 369 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 370 const struct imx1_pinctrl_soc_info *info = ipctl->info; 371 372 *groups = info->functions[selector].groups; 373 *num_groups = info->functions[selector].num_groups; 374 375 return 0; 376} 377 378static const struct pinmux_ops imx1_pmx_ops = { 379 .get_functions_count = imx1_pmx_get_funcs_count, 380 .get_function_name = imx1_pmx_get_func_name, 381 .get_function_groups = imx1_pmx_get_groups, 382 .set_mux = imx1_pmx_set, 383}; 384 385static int imx1_pinconf_get(struct pinctrl_dev *pctldev, 386 unsigned pin_id, unsigned long *config) 387{ 388 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 389 390 *config = imx1_read_bit(ipctl, pin_id, MX1_PUEN); 391 392 return 0; 393} 394 395static int imx1_pinconf_set(struct pinctrl_dev *pctldev, 396 unsigned pin_id, unsigned long *configs, 397 unsigned num_configs) 398{ 399 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 400 int i; 401 402 for (i = 0; i != num_configs; ++i) { 403 imx1_write_bit(ipctl, pin_id, configs[i] & 0x01, MX1_PUEN); 404 405 dev_dbg(ipctl->dev, "pinconf set pullup pin %s\n", 406 pin_desc_get(pctldev, pin_id)->name); 407 } 408 409 return 0; 410} 411 412static void imx1_pinconf_dbg_show(struct pinctrl_dev *pctldev, 413 struct seq_file *s, unsigned pin_id) 414{ 415 unsigned long config; 416 417 imx1_pinconf_get(pctldev, pin_id, &config); 418 seq_printf(s, "0x%lx", config); 419} 420 421static void imx1_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 422 struct seq_file *s, unsigned group) 423{ 424 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 425 const struct imx1_pinctrl_soc_info *info = ipctl->info; 426 struct imx1_pin_group *grp; 427 unsigned long config; 428 const char *name; 429 int i, ret; 430 431 if (group >= info->ngroups) 432 return; 433 434 seq_puts(s, "\n"); 435 grp = &info->groups[group]; 436 for (i = 0; i < grp->npins; i++) { 437 name = pin_get_name(pctldev, grp->pins[i].pin_id); 438 ret = imx1_pinconf_get(pctldev, grp->pins[i].pin_id, &config); 439 if (ret) 440 return; 441 seq_printf(s, "%s: 0x%lx", name, config); 442 } 443} 444 445static const struct pinconf_ops imx1_pinconf_ops = { 446 .pin_config_get = imx1_pinconf_get, 447 .pin_config_set = imx1_pinconf_set, 448 .pin_config_dbg_show = imx1_pinconf_dbg_show, 449 .pin_config_group_dbg_show = imx1_pinconf_group_dbg_show, 450}; 451 452static struct pinctrl_desc imx1_pinctrl_desc = { 453 .pctlops = &imx1_pctrl_ops, 454 .pmxops = &imx1_pmx_ops, 455 .confops = &imx1_pinconf_ops, 456 .owner = THIS_MODULE, 457}; 458 459static int imx1_pinctrl_parse_groups(struct device_node *np, 460 struct imx1_pin_group *grp, 461 struct imx1_pinctrl_soc_info *info, 462 u32 index) 463{ 464 int size; 465 const __be32 *list; 466 int i; 467 468 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np); 469 470 /* Initialise group */ 471 grp->name = np->name; 472 473 /* 474 * the binding format is fsl,pins = <PIN MUX_ID CONFIG> 475 */ 476 list = of_get_property(np, "fsl,pins", &size); 477 /* we do not check return since it's safe node passed down */ 478 if (!size || size % 12) { 479 dev_notice(info->dev, "Not a valid fsl,pins property (%pOFn)\n", 480 np); 481 return -EINVAL; 482 } 483 484 grp->npins = size / 12; 485 grp->pins = devm_kcalloc(info->dev, 486 grp->npins, sizeof(struct imx1_pin), GFP_KERNEL); 487 grp->pin_ids = devm_kcalloc(info->dev, 488 grp->npins, sizeof(unsigned int), GFP_KERNEL); 489 490 if (!grp->pins || !grp->pin_ids) 491 return -ENOMEM; 492 493 for (i = 0; i < grp->npins; i++) { 494 grp->pins[i].pin_id = be32_to_cpu(*list++); 495 grp->pins[i].mux_id = be32_to_cpu(*list++); 496 grp->pins[i].config = be32_to_cpu(*list++); 497 498 grp->pin_ids[i] = grp->pins[i].pin_id; 499 } 500 501 return 0; 502} 503 504static int imx1_pinctrl_parse_functions(struct device_node *np, 505 struct imx1_pinctrl_soc_info *info, 506 u32 index) 507{ 508 struct device_node *child; 509 struct imx1_pmx_func *func; 510 struct imx1_pin_group *grp; 511 int ret; 512 static u32 grp_index; 513 u32 i = 0; 514 515 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np); 516 517 func = &info->functions[index]; 518 519 /* Initialise function */ 520 func->name = np->name; 521 func->num_groups = of_get_child_count(np); 522 if (func->num_groups == 0) 523 return -EINVAL; 524 525 func->groups = devm_kcalloc(info->dev, 526 func->num_groups, sizeof(char *), GFP_KERNEL); 527 528 if (!func->groups) 529 return -ENOMEM; 530 531 for_each_child_of_node(np, child) { 532 func->groups[i] = child->name; 533 grp = &info->groups[grp_index++]; 534 ret = imx1_pinctrl_parse_groups(child, grp, info, i++); 535 if (ret == -ENOMEM) { 536 of_node_put(child); 537 return ret; 538 } 539 } 540 541 return 0; 542} 543 544static int imx1_pinctrl_parse_dt(struct platform_device *pdev, 545 struct imx1_pinctrl *pctl, struct imx1_pinctrl_soc_info *info) 546{ 547 struct device_node *np = pdev->dev.of_node; 548 struct device_node *child; 549 int ret; 550 u32 nfuncs = 0; 551 u32 ngroups = 0; 552 u32 ifunc = 0; 553 554 if (!np) 555 return -ENODEV; 556 557 for_each_child_of_node(np, child) { 558 ++nfuncs; 559 ngroups += of_get_child_count(child); 560 } 561 562 if (!nfuncs) { 563 dev_err(&pdev->dev, "No pin functions defined\n"); 564 return -EINVAL; 565 } 566 567 info->nfunctions = nfuncs; 568 info->functions = devm_kcalloc(&pdev->dev, 569 nfuncs, sizeof(struct imx1_pmx_func), GFP_KERNEL); 570 571 info->ngroups = ngroups; 572 info->groups = devm_kcalloc(&pdev->dev, 573 ngroups, sizeof(struct imx1_pin_group), GFP_KERNEL); 574 575 576 if (!info->functions || !info->groups) 577 return -ENOMEM; 578 579 for_each_child_of_node(np, child) { 580 ret = imx1_pinctrl_parse_functions(child, info, ifunc++); 581 if (ret == -ENOMEM) { 582 of_node_put(child); 583 return -ENOMEM; 584 } 585 } 586 587 return 0; 588} 589 590int imx1_pinctrl_core_probe(struct platform_device *pdev, 591 struct imx1_pinctrl_soc_info *info) 592{ 593 struct imx1_pinctrl *ipctl; 594 struct resource *res; 595 struct pinctrl_desc *pctl_desc; 596 int ret; 597 598 if (!info || !info->pins || !info->npins) { 599 dev_err(&pdev->dev, "wrong pinctrl info\n"); 600 return -EINVAL; 601 } 602 info->dev = &pdev->dev; 603 604 /* Create state holders etc for this driver */ 605 ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); 606 if (!ipctl) 607 return -ENOMEM; 608 609 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 610 if (!res) 611 return -ENOENT; 612 613 ipctl->base = devm_ioremap(&pdev->dev, res->start, 614 resource_size(res)); 615 if (!ipctl->base) 616 return -ENOMEM; 617 618 pctl_desc = &imx1_pinctrl_desc; 619 pctl_desc->name = dev_name(&pdev->dev); 620 pctl_desc->pins = info->pins; 621 pctl_desc->npins = info->npins; 622 623 ret = imx1_pinctrl_parse_dt(pdev, ipctl, info); 624 if (ret) { 625 dev_err(&pdev->dev, "fail to probe dt properties\n"); 626 return ret; 627 } 628 629 ipctl->info = info; 630 ipctl->dev = info->dev; 631 platform_set_drvdata(pdev, ipctl); 632 ipctl->pctl = devm_pinctrl_register(&pdev->dev, pctl_desc, ipctl); 633 if (IS_ERR(ipctl->pctl)) { 634 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); 635 return PTR_ERR(ipctl->pctl); 636 } 637 638 ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); 639 if (ret) { 640 dev_err(&pdev->dev, "Failed to populate subdevices\n"); 641 return ret; 642 } 643 644 dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); 645 646 return 0; 647} 648