1// SPDX-License-Identifier: GPL-2.0 2/** 3 * Wrapper driver for SERDES used in J721E 4 * 5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ 6 * Author: Kishon Vijay Abraham I <kishon@ti.com> 7 */ 8 9#include <dt-bindings/phy/phy.h> 10#include <linux/clk.h> 11#include <linux/clk-provider.h> 12#include <linux/gpio.h> 13#include <linux/gpio/consumer.h> 14#include <linux/io.h> 15#include <linux/module.h> 16#include <linux/mux/consumer.h> 17#include <linux/of_address.h> 18#include <linux/of_platform.h> 19#include <linux/platform_device.h> 20#include <linux/pm_runtime.h> 21#include <linux/regmap.h> 22#include <linux/reset-controller.h> 23 24#define WIZ_SERDES_CTRL 0x404 25#define WIZ_SERDES_TOP_CTRL 0x408 26#define WIZ_SERDES_RST 0x40c 27#define WIZ_SERDES_TYPEC 0x410 28#define WIZ_LANECTL(n) (0x480 + (0x40 * (n))) 29 30#define WIZ_MAX_LANES 4 31#define WIZ_MUX_NUM_CLOCKS 3 32#define WIZ_DIV_NUM_CLOCKS_16G 2 33#define WIZ_DIV_NUM_CLOCKS_10G 1 34 35#define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30) 36 37enum wiz_lane_standard_mode { 38 LANE_MODE_GEN1, 39 LANE_MODE_GEN2, 40 LANE_MODE_GEN3, 41 LANE_MODE_GEN4, 42}; 43 44enum wiz_refclk_mux_sel { 45 PLL0_REFCLK, 46 PLL1_REFCLK, 47 REFCLK_DIG, 48}; 49 50enum wiz_refclk_div_sel { 51 CMN_REFCLK_DIG_DIV, 52 CMN_REFCLK1_DIG_DIV, 53}; 54 55static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31); 56static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31); 57static const struct reg_field pll1_refclk_mux_sel = 58 REG_FIELD(WIZ_SERDES_RST, 29, 29); 59static const struct reg_field pll0_refclk_mux_sel = 60 REG_FIELD(WIZ_SERDES_RST, 28, 28); 61static const struct reg_field refclk_dig_sel_16g = 62 REG_FIELD(WIZ_SERDES_RST, 24, 25); 63static const struct reg_field refclk_dig_sel_10g = 64 REG_FIELD(WIZ_SERDES_RST, 24, 24); 65static const struct reg_field pma_cmn_refclk_int_mode = 66 REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29); 67static const struct reg_field pma_cmn_refclk_mode = 68 REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31); 69static const struct reg_field pma_cmn_refclk_dig_div = 70 REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27); 71static const struct reg_field pma_cmn_refclk1_dig_div = 72 REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25); 73 74static const struct reg_field p_enable[WIZ_MAX_LANES] = { 75 REG_FIELD(WIZ_LANECTL(0), 30, 31), 76 REG_FIELD(WIZ_LANECTL(1), 30, 31), 77 REG_FIELD(WIZ_LANECTL(2), 30, 31), 78 REG_FIELD(WIZ_LANECTL(3), 30, 31), 79}; 80 81enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 }; 82 83static const struct reg_field p_align[WIZ_MAX_LANES] = { 84 REG_FIELD(WIZ_LANECTL(0), 29, 29), 85 REG_FIELD(WIZ_LANECTL(1), 29, 29), 86 REG_FIELD(WIZ_LANECTL(2), 29, 29), 87 REG_FIELD(WIZ_LANECTL(3), 29, 29), 88}; 89 90static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = { 91 REG_FIELD(WIZ_LANECTL(0), 28, 28), 92 REG_FIELD(WIZ_LANECTL(1), 28, 28), 93 REG_FIELD(WIZ_LANECTL(2), 28, 28), 94 REG_FIELD(WIZ_LANECTL(3), 28, 28), 95}; 96 97static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = { 98 REG_FIELD(WIZ_LANECTL(0), 24, 25), 99 REG_FIELD(WIZ_LANECTL(1), 24, 25), 100 REG_FIELD(WIZ_LANECTL(2), 24, 25), 101 REG_FIELD(WIZ_LANECTL(3), 24, 25), 102}; 103 104static const struct reg_field typec_ln10_swap = 105 REG_FIELD(WIZ_SERDES_TYPEC, 30, 30); 106 107struct wiz_clk_mux { 108 struct clk_hw hw; 109 struct regmap_field *field; 110 u32 *table; 111 struct clk_init_data clk_data; 112}; 113 114#define to_wiz_clk_mux(_hw) container_of(_hw, struct wiz_clk_mux, hw) 115 116struct wiz_clk_divider { 117 struct clk_hw hw; 118 struct regmap_field *field; 119 const struct clk_div_table *table; 120 struct clk_init_data clk_data; 121}; 122 123#define to_wiz_clk_div(_hw) container_of(_hw, struct wiz_clk_divider, hw) 124 125struct wiz_clk_mux_sel { 126 struct regmap_field *field; 127 u32 table[4]; 128 const char *node_name; 129}; 130 131struct wiz_clk_div_sel { 132 struct regmap_field *field; 133 const struct clk_div_table *table; 134 const char *node_name; 135}; 136 137static struct wiz_clk_mux_sel clk_mux_sel_16g[] = { 138 { 139 /* 140 * Mux value to be configured for each of the input clocks 141 * in the order populated in device tree 142 */ 143 .table = { 1, 0 }, 144 .node_name = "pll0-refclk", 145 }, 146 { 147 .table = { 1, 0 }, 148 .node_name = "pll1-refclk", 149 }, 150 { 151 .table = { 1, 3, 0, 2 }, 152 .node_name = "refclk-dig", 153 }, 154}; 155 156static struct wiz_clk_mux_sel clk_mux_sel_10g[] = { 157 { 158 /* 159 * Mux value to be configured for each of the input clocks 160 * in the order populated in device tree 161 */ 162 .table = { 1, 0 }, 163 .node_name = "pll0-refclk", 164 }, 165 { 166 .table = { 1, 0 }, 167 .node_name = "pll1-refclk", 168 }, 169 { 170 .table = { 1, 0 }, 171 .node_name = "refclk-dig", 172 }, 173}; 174 175static const struct clk_div_table clk_div_table[] = { 176 { .val = 0, .div = 1, }, 177 { .val = 1, .div = 2, }, 178 { .val = 2, .div = 4, }, 179 { .val = 3, .div = 8, }, 180 { /* sentinel */ }, 181}; 182 183static struct wiz_clk_div_sel clk_div_sel[] = { 184 { 185 .table = clk_div_table, 186 .node_name = "cmn-refclk-dig-div", 187 }, 188 { 189 .table = clk_div_table, 190 .node_name = "cmn-refclk1-dig-div", 191 }, 192}; 193 194enum wiz_type { 195 J721E_WIZ_16G, 196 J721E_WIZ_10G, 197}; 198 199#define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */ 200#define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000 201 202struct wiz { 203 struct regmap *regmap; 204 enum wiz_type type; 205 struct wiz_clk_mux_sel *clk_mux_sel; 206 struct wiz_clk_div_sel *clk_div_sel; 207 unsigned int clk_div_sel_num; 208 struct regmap_field *por_en; 209 struct regmap_field *phy_reset_n; 210 struct regmap_field *p_enable[WIZ_MAX_LANES]; 211 struct regmap_field *p_align[WIZ_MAX_LANES]; 212 struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES]; 213 struct regmap_field *p_standard_mode[WIZ_MAX_LANES]; 214 struct regmap_field *pma_cmn_refclk_int_mode; 215 struct regmap_field *pma_cmn_refclk_mode; 216 struct regmap_field *pma_cmn_refclk_dig_div; 217 struct regmap_field *pma_cmn_refclk1_dig_div; 218 struct regmap_field *typec_ln10_swap; 219 220 struct device *dev; 221 u32 num_lanes; 222 struct platform_device *serdes_pdev; 223 struct reset_controller_dev wiz_phy_reset_dev; 224 struct gpio_desc *gpio_typec_dir; 225 int typec_dir_delay; 226 u32 lane_phy_type[WIZ_MAX_LANES]; 227}; 228 229static int wiz_reset(struct wiz *wiz) 230{ 231 int ret; 232 233 ret = regmap_field_write(wiz->por_en, 0x1); 234 if (ret) 235 return ret; 236 237 mdelay(1); 238 239 ret = regmap_field_write(wiz->por_en, 0x0); 240 if (ret) 241 return ret; 242 243 return 0; 244} 245 246static int wiz_mode_select(struct wiz *wiz) 247{ 248 u32 num_lanes = wiz->num_lanes; 249 enum wiz_lane_standard_mode mode; 250 int ret; 251 int i; 252 253 for (i = 0; i < num_lanes; i++) { 254 if (wiz->lane_phy_type[i] == PHY_TYPE_DP) 255 mode = LANE_MODE_GEN1; 256 else 257 mode = LANE_MODE_GEN4; 258 259 ret = regmap_field_write(wiz->p_standard_mode[i], mode); 260 if (ret) 261 return ret; 262 } 263 264 return 0; 265} 266 267static int wiz_init_raw_interface(struct wiz *wiz, bool enable) 268{ 269 u32 num_lanes = wiz->num_lanes; 270 int i; 271 int ret; 272 273 for (i = 0; i < num_lanes; i++) { 274 ret = regmap_field_write(wiz->p_align[i], enable); 275 if (ret) 276 return ret; 277 278 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable); 279 if (ret) 280 return ret; 281 } 282 283 return 0; 284} 285 286static int wiz_init(struct wiz *wiz) 287{ 288 struct device *dev = wiz->dev; 289 int ret; 290 291 ret = wiz_reset(wiz); 292 if (ret) { 293 dev_err(dev, "WIZ reset failed\n"); 294 return ret; 295 } 296 297 ret = wiz_mode_select(wiz); 298 if (ret) { 299 dev_err(dev, "WIZ mode select failed\n"); 300 return ret; 301 } 302 303 ret = wiz_init_raw_interface(wiz, true); 304 if (ret) { 305 dev_err(dev, "WIZ interface initialization failed\n"); 306 return ret; 307 } 308 309 return 0; 310} 311 312static int wiz_regfield_init(struct wiz *wiz) 313{ 314 struct wiz_clk_mux_sel *clk_mux_sel; 315 struct wiz_clk_div_sel *clk_div_sel; 316 struct regmap *regmap = wiz->regmap; 317 int num_lanes = wiz->num_lanes; 318 struct device *dev = wiz->dev; 319 int i; 320 321 wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en); 322 if (IS_ERR(wiz->por_en)) { 323 dev_err(dev, "POR_EN reg field init failed\n"); 324 return PTR_ERR(wiz->por_en); 325 } 326 327 wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap, 328 phy_reset_n); 329 if (IS_ERR(wiz->phy_reset_n)) { 330 dev_err(dev, "PHY_RESET_N reg field init failed\n"); 331 return PTR_ERR(wiz->phy_reset_n); 332 } 333 334 wiz->pma_cmn_refclk_int_mode = 335 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode); 336 if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) { 337 dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n"); 338 return PTR_ERR(wiz->pma_cmn_refclk_int_mode); 339 } 340 341 wiz->pma_cmn_refclk_mode = 342 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode); 343 if (IS_ERR(wiz->pma_cmn_refclk_mode)) { 344 dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n"); 345 return PTR_ERR(wiz->pma_cmn_refclk_mode); 346 } 347 348 clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK_DIG_DIV]; 349 clk_div_sel->field = devm_regmap_field_alloc(dev, regmap, 350 pma_cmn_refclk_dig_div); 351 if (IS_ERR(clk_div_sel->field)) { 352 dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n"); 353 return PTR_ERR(clk_div_sel->field); 354 } 355 356 if (wiz->type == J721E_WIZ_16G) { 357 clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK1_DIG_DIV]; 358 clk_div_sel->field = 359 devm_regmap_field_alloc(dev, regmap, 360 pma_cmn_refclk1_dig_div); 361 if (IS_ERR(clk_div_sel->field)) { 362 dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n"); 363 return PTR_ERR(clk_div_sel->field); 364 } 365 } 366 367 clk_mux_sel = &wiz->clk_mux_sel[PLL0_REFCLK]; 368 clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap, 369 pll0_refclk_mux_sel); 370 if (IS_ERR(clk_mux_sel->field)) { 371 dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n"); 372 return PTR_ERR(clk_mux_sel->field); 373 } 374 375 clk_mux_sel = &wiz->clk_mux_sel[PLL1_REFCLK]; 376 clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap, 377 pll1_refclk_mux_sel); 378 if (IS_ERR(clk_mux_sel->field)) { 379 dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n"); 380 return PTR_ERR(clk_mux_sel->field); 381 } 382 383 clk_mux_sel = &wiz->clk_mux_sel[REFCLK_DIG]; 384 if (wiz->type == J721E_WIZ_10G) 385 clk_mux_sel->field = 386 devm_regmap_field_alloc(dev, regmap, 387 refclk_dig_sel_10g); 388 else 389 clk_mux_sel->field = 390 devm_regmap_field_alloc(dev, regmap, 391 refclk_dig_sel_16g); 392 393 if (IS_ERR(clk_mux_sel->field)) { 394 dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n"); 395 return PTR_ERR(clk_mux_sel->field); 396 } 397 398 for (i = 0; i < num_lanes; i++) { 399 wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap, 400 p_enable[i]); 401 if (IS_ERR(wiz->p_enable[i])) { 402 dev_err(dev, "P%d_ENABLE reg field init failed\n", i); 403 return PTR_ERR(wiz->p_enable[i]); 404 } 405 406 wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap, 407 p_align[i]); 408 if (IS_ERR(wiz->p_align[i])) { 409 dev_err(dev, "P%d_ALIGN reg field init failed\n", i); 410 return PTR_ERR(wiz->p_align[i]); 411 } 412 413 wiz->p_raw_auto_start[i] = 414 devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]); 415 if (IS_ERR(wiz->p_raw_auto_start[i])) { 416 dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n", 417 i); 418 return PTR_ERR(wiz->p_raw_auto_start[i]); 419 } 420 421 wiz->p_standard_mode[i] = 422 devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]); 423 if (IS_ERR(wiz->p_standard_mode[i])) { 424 dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n", 425 i); 426 return PTR_ERR(wiz->p_standard_mode[i]); 427 } 428 } 429 430 wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap, 431 typec_ln10_swap); 432 if (IS_ERR(wiz->typec_ln10_swap)) { 433 dev_err(dev, "LN10_SWAP reg field init failed\n"); 434 return PTR_ERR(wiz->typec_ln10_swap); 435 } 436 437 return 0; 438} 439 440static u8 wiz_clk_mux_get_parent(struct clk_hw *hw) 441{ 442 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw); 443 struct regmap_field *field = mux->field; 444 unsigned int val; 445 446 regmap_field_read(field, &val); 447 return clk_mux_val_to_index(hw, mux->table, 0, val); 448} 449 450static int wiz_clk_mux_set_parent(struct clk_hw *hw, u8 index) 451{ 452 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw); 453 struct regmap_field *field = mux->field; 454 int val; 455 456 val = mux->table[index]; 457 return regmap_field_write(field, val); 458} 459 460static const struct clk_ops wiz_clk_mux_ops = { 461 .set_parent = wiz_clk_mux_set_parent, 462 .get_parent = wiz_clk_mux_get_parent, 463}; 464 465static int wiz_mux_clk_register(struct wiz *wiz, struct device_node *node, 466 struct regmap_field *field, u32 *table) 467{ 468 struct device *dev = wiz->dev; 469 struct clk_init_data *init; 470 const char **parent_names; 471 unsigned int num_parents; 472 struct wiz_clk_mux *mux; 473 char clk_name[100]; 474 struct clk *clk; 475 int ret; 476 477 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 478 if (!mux) 479 return -ENOMEM; 480 481 num_parents = of_clk_get_parent_count(node); 482 if (num_parents < 2) { 483 dev_err(dev, "SERDES clock must have parents\n"); 484 return -EINVAL; 485 } 486 487 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), 488 GFP_KERNEL); 489 if (!parent_names) 490 return -ENOMEM; 491 492 of_clk_parent_fill(node, parent_names, num_parents); 493 494 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 495 node->name); 496 497 init = &mux->clk_data; 498 499 init->ops = &wiz_clk_mux_ops; 500 init->flags = CLK_SET_RATE_NO_REPARENT; 501 init->parent_names = parent_names; 502 init->num_parents = num_parents; 503 init->name = clk_name; 504 505 mux->field = field; 506 mux->table = table; 507 mux->hw.init = init; 508 509 clk = devm_clk_register(dev, &mux->hw); 510 if (IS_ERR(clk)) 511 return PTR_ERR(clk); 512 513 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); 514 if (ret) 515 dev_err(dev, "Failed to add clock provider: %s\n", clk_name); 516 517 return ret; 518} 519 520static unsigned long wiz_clk_div_recalc_rate(struct clk_hw *hw, 521 unsigned long parent_rate) 522{ 523 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 524 struct regmap_field *field = div->field; 525 int val; 526 527 regmap_field_read(field, &val); 528 529 return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2); 530} 531 532static long wiz_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, 533 unsigned long *prate) 534{ 535 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 536 537 return divider_round_rate(hw, rate, prate, div->table, 2, 0x0); 538} 539 540static int wiz_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, 541 unsigned long parent_rate) 542{ 543 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 544 struct regmap_field *field = div->field; 545 int val; 546 547 val = divider_get_val(rate, parent_rate, div->table, 2, 0x0); 548 if (val < 0) 549 return val; 550 551 return regmap_field_write(field, val); 552} 553 554static const struct clk_ops wiz_clk_div_ops = { 555 .recalc_rate = wiz_clk_div_recalc_rate, 556 .round_rate = wiz_clk_div_round_rate, 557 .set_rate = wiz_clk_div_set_rate, 558}; 559 560static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node, 561 struct regmap_field *field, 562 const struct clk_div_table *table) 563{ 564 struct device *dev = wiz->dev; 565 struct wiz_clk_divider *div; 566 struct clk_init_data *init; 567 const char **parent_names; 568 char clk_name[100]; 569 struct clk *clk; 570 int ret; 571 572 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); 573 if (!div) 574 return -ENOMEM; 575 576 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 577 node->name); 578 579 parent_names = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL); 580 if (!parent_names) 581 return -ENOMEM; 582 583 of_clk_parent_fill(node, parent_names, 1); 584 585 init = &div->clk_data; 586 587 init->ops = &wiz_clk_div_ops; 588 init->flags = 0; 589 init->parent_names = parent_names; 590 init->num_parents = 1; 591 init->name = clk_name; 592 593 div->field = field; 594 div->table = table; 595 div->hw.init = init; 596 597 clk = devm_clk_register(dev, &div->hw); 598 if (IS_ERR(clk)) 599 return PTR_ERR(clk); 600 601 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); 602 if (ret) 603 dev_err(dev, "Failed to add clock provider: %s\n", clk_name); 604 605 return ret; 606} 607 608static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node) 609{ 610 struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 611 struct device_node *clk_node; 612 int i; 613 614 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { 615 clk_node = of_get_child_by_name(node, clk_mux_sel[i].node_name); 616 of_clk_del_provider(clk_node); 617 of_node_put(clk_node); 618 } 619 620 for (i = 0; i < wiz->clk_div_sel_num; i++) { 621 clk_node = of_get_child_by_name(node, clk_div_sel[i].node_name); 622 of_clk_del_provider(clk_node); 623 of_node_put(clk_node); 624 } 625} 626 627static int wiz_clock_init(struct wiz *wiz, struct device_node *node) 628{ 629 struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 630 struct device *dev = wiz->dev; 631 struct device_node *clk_node; 632 const char *node_name; 633 unsigned long rate; 634 struct clk *clk; 635 int ret; 636 int i; 637 638 clk = devm_clk_get(dev, "core_ref_clk"); 639 if (IS_ERR(clk)) { 640 dev_err(dev, "core_ref_clk clock not found\n"); 641 ret = PTR_ERR(clk); 642 return ret; 643 } 644 645 rate = clk_get_rate(clk); 646 if (rate >= 100000000) 647 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1); 648 else 649 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); 650 651 clk = devm_clk_get(dev, "ext_ref_clk"); 652 if (IS_ERR(clk)) { 653 dev_err(dev, "ext_ref_clk clock not found\n"); 654 ret = PTR_ERR(clk); 655 return ret; 656 } 657 658 rate = clk_get_rate(clk); 659 if (rate >= 100000000) 660 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0); 661 else 662 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2); 663 664 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { 665 node_name = clk_mux_sel[i].node_name; 666 clk_node = of_get_child_by_name(node, node_name); 667 if (!clk_node) { 668 dev_err(dev, "Unable to get %s node\n", node_name); 669 ret = -EINVAL; 670 goto err; 671 } 672 673 ret = wiz_mux_clk_register(wiz, clk_node, clk_mux_sel[i].field, 674 clk_mux_sel[i].table); 675 if (ret) { 676 dev_err(dev, "Failed to register %s clock\n", 677 node_name); 678 of_node_put(clk_node); 679 goto err; 680 } 681 682 of_node_put(clk_node); 683 } 684 685 for (i = 0; i < wiz->clk_div_sel_num; i++) { 686 node_name = clk_div_sel[i].node_name; 687 clk_node = of_get_child_by_name(node, node_name); 688 if (!clk_node) { 689 dev_err(dev, "Unable to get %s node\n", node_name); 690 ret = -EINVAL; 691 goto err; 692 } 693 694 ret = wiz_div_clk_register(wiz, clk_node, clk_div_sel[i].field, 695 clk_div_sel[i].table); 696 if (ret) { 697 dev_err(dev, "Failed to register %s clock\n", 698 node_name); 699 of_node_put(clk_node); 700 goto err; 701 } 702 703 of_node_put(clk_node); 704 } 705 706 return 0; 707err: 708 wiz_clock_cleanup(wiz, node); 709 710 return ret; 711} 712 713static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev, 714 unsigned long id) 715{ 716 struct device *dev = rcdev->dev; 717 struct wiz *wiz = dev_get_drvdata(dev); 718 int ret = 0; 719 720 if (id == 0) { 721 ret = regmap_field_write(wiz->phy_reset_n, false); 722 return ret; 723 } 724 725 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE); 726 return ret; 727} 728 729static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev, 730 unsigned long id) 731{ 732 struct device *dev = rcdev->dev; 733 struct wiz *wiz = dev_get_drvdata(dev); 734 int ret; 735 736 /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */ 737 if (id == 0 && wiz->gpio_typec_dir) { 738 if (wiz->typec_dir_delay) 739 msleep_interruptible(wiz->typec_dir_delay); 740 741 if (gpiod_get_value_cansleep(wiz->gpio_typec_dir)) 742 regmap_field_write(wiz->typec_ln10_swap, 1); 743 else 744 regmap_field_write(wiz->typec_ln10_swap, 0); 745 } 746 747 if (id == 0) { 748 ret = regmap_field_write(wiz->phy_reset_n, true); 749 return ret; 750 } 751 752 if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP) 753 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE); 754 else 755 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE); 756 757 return ret; 758} 759 760static const struct reset_control_ops wiz_phy_reset_ops = { 761 .assert = wiz_phy_reset_assert, 762 .deassert = wiz_phy_reset_deassert, 763}; 764 765static const struct regmap_config wiz_regmap_config = { 766 .reg_bits = 32, 767 .val_bits = 32, 768 .reg_stride = 4, 769 .fast_io = true, 770}; 771 772static const struct of_device_id wiz_id_table[] = { 773 { 774 .compatible = "ti,j721e-wiz-16g", .data = (void *)J721E_WIZ_16G 775 }, 776 { 777 .compatible = "ti,j721e-wiz-10g", .data = (void *)J721E_WIZ_10G 778 }, 779 {} 780}; 781MODULE_DEVICE_TABLE(of, wiz_id_table); 782 783static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz) 784{ 785 struct device_node *serdes, *subnode; 786 787 serdes = of_get_child_by_name(dev->of_node, "serdes"); 788 if (!serdes) { 789 dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__); 790 return -EINVAL; 791 } 792 793 for_each_child_of_node(serdes, subnode) { 794 u32 reg, num_lanes = 1, phy_type = PHY_NONE; 795 int ret, i; 796 797 ret = of_property_read_u32(subnode, "reg", ®); 798 if (ret) { 799 dev_err(dev, 800 "%s: Reading \"reg\" from \"%s\" failed: %d\n", 801 __func__, subnode->name, ret); 802 return ret; 803 } 804 of_property_read_u32(subnode, "cdns,num-lanes", &num_lanes); 805 of_property_read_u32(subnode, "cdns,phy-type", &phy_type); 806 807 dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__, 808 reg, reg + num_lanes - 1, phy_type); 809 810 for (i = reg; i < reg + num_lanes; i++) 811 wiz->lane_phy_type[i] = phy_type; 812 } 813 814 return 0; 815} 816 817static int wiz_probe(struct platform_device *pdev) 818{ 819 struct reset_controller_dev *phy_reset_dev; 820 struct device *dev = &pdev->dev; 821 struct device_node *node = dev->of_node; 822 struct platform_device *serdes_pdev; 823 struct device_node *child_node; 824 struct regmap *regmap; 825 struct resource res; 826 void __iomem *base; 827 struct wiz *wiz; 828 u32 num_lanes; 829 int ret; 830 831 wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL); 832 if (!wiz) 833 return -ENOMEM; 834 835 wiz->type = (enum wiz_type)of_device_get_match_data(dev); 836 837 child_node = of_get_child_by_name(node, "serdes"); 838 if (!child_node) { 839 dev_err(dev, "Failed to get SERDES child DT node\n"); 840 return -ENODEV; 841 } 842 843 ret = of_address_to_resource(child_node, 0, &res); 844 if (ret) { 845 dev_err(dev, "Failed to get memory resource\n"); 846 goto err_addr_to_resource; 847 } 848 849 base = devm_ioremap(dev, res.start, resource_size(&res)); 850 if (!base) { 851 ret = -ENOMEM; 852 goto err_addr_to_resource; 853 } 854 855 regmap = devm_regmap_init_mmio(dev, base, &wiz_regmap_config); 856 if (IS_ERR(regmap)) { 857 dev_err(dev, "Failed to initialize regmap\n"); 858 ret = PTR_ERR(regmap); 859 goto err_addr_to_resource; 860 } 861 862 ret = of_property_read_u32(node, "num-lanes", &num_lanes); 863 if (ret) { 864 dev_err(dev, "Failed to read num-lanes property\n"); 865 goto err_addr_to_resource; 866 } 867 868 if (num_lanes > WIZ_MAX_LANES) { 869 dev_err(dev, "Cannot support %d lanes\n", num_lanes); 870 ret = -ENODEV; 871 goto err_addr_to_resource; 872 } 873 874 wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir", 875 GPIOD_IN); 876 if (IS_ERR(wiz->gpio_typec_dir)) { 877 ret = PTR_ERR(wiz->gpio_typec_dir); 878 if (ret != -EPROBE_DEFER) 879 dev_err(dev, "Failed to request typec-dir gpio: %d\n", 880 ret); 881 goto err_addr_to_resource; 882 } 883 884 if (wiz->gpio_typec_dir) { 885 ret = of_property_read_u32(node, "typec-dir-debounce-ms", 886 &wiz->typec_dir_delay); 887 if (ret && ret != -EINVAL) { 888 dev_err(dev, "Invalid typec-dir-debounce property\n"); 889 goto err_addr_to_resource; 890 } 891 892 /* use min. debounce from Type-C spec if not provided in DT */ 893 if (ret == -EINVAL) 894 wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN; 895 896 if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN || 897 wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) { 898 ret = -EINVAL; 899 dev_err(dev, "Invalid typec-dir-debounce property\n"); 900 goto err_addr_to_resource; 901 } 902 } 903 904 ret = wiz_get_lane_phy_types(dev, wiz); 905 if (ret) 906 return ret; 907 908 wiz->dev = dev; 909 wiz->regmap = regmap; 910 wiz->num_lanes = num_lanes; 911 if (wiz->type == J721E_WIZ_10G) 912 wiz->clk_mux_sel = clk_mux_sel_10g; 913 else 914 wiz->clk_mux_sel = clk_mux_sel_16g; 915 916 wiz->clk_div_sel = clk_div_sel; 917 918 if (wiz->type == J721E_WIZ_10G) 919 wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G; 920 else 921 wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G; 922 923 platform_set_drvdata(pdev, wiz); 924 925 ret = wiz_regfield_init(wiz); 926 if (ret) { 927 dev_err(dev, "Failed to initialize regfields\n"); 928 goto err_addr_to_resource; 929 } 930 931 phy_reset_dev = &wiz->wiz_phy_reset_dev; 932 phy_reset_dev->dev = dev; 933 phy_reset_dev->ops = &wiz_phy_reset_ops, 934 phy_reset_dev->owner = THIS_MODULE, 935 phy_reset_dev->of_node = node; 936 /* Reset for each of the lane and one for the entire SERDES */ 937 phy_reset_dev->nr_resets = num_lanes + 1; 938 939 ret = devm_reset_controller_register(dev, phy_reset_dev); 940 if (ret < 0) { 941 dev_warn(dev, "Failed to register reset controller\n"); 942 goto err_addr_to_resource; 943 } 944 945 pm_runtime_enable(dev); 946 ret = pm_runtime_get_sync(dev); 947 if (ret < 0) { 948 dev_err(dev, "pm_runtime_get_sync failed\n"); 949 goto err_get_sync; 950 } 951 952 ret = wiz_clock_init(wiz, node); 953 if (ret < 0) { 954 dev_warn(dev, "Failed to initialize clocks\n"); 955 goto err_get_sync; 956 } 957 958 ret = wiz_init(wiz); 959 if (ret) { 960 dev_err(dev, "WIZ initialization failed\n"); 961 goto err_wiz_init; 962 } 963 964 serdes_pdev = of_platform_device_create(child_node, NULL, dev); 965 if (!serdes_pdev) { 966 dev_WARN(dev, "Unable to create SERDES platform device\n"); 967 ret = -ENOMEM; 968 goto err_wiz_init; 969 } 970 wiz->serdes_pdev = serdes_pdev; 971 972 of_node_put(child_node); 973 return 0; 974 975err_wiz_init: 976 wiz_clock_cleanup(wiz, node); 977 978err_get_sync: 979 pm_runtime_put(dev); 980 pm_runtime_disable(dev); 981 982err_addr_to_resource: 983 of_node_put(child_node); 984 985 return ret; 986} 987 988static int wiz_remove(struct platform_device *pdev) 989{ 990 struct device *dev = &pdev->dev; 991 struct device_node *node = dev->of_node; 992 struct platform_device *serdes_pdev; 993 struct wiz *wiz; 994 995 wiz = dev_get_drvdata(dev); 996 serdes_pdev = wiz->serdes_pdev; 997 998 of_platform_device_destroy(&serdes_pdev->dev, NULL); 999 wiz_clock_cleanup(wiz, node); 1000 pm_runtime_put(dev); 1001 pm_runtime_disable(dev); 1002 1003 return 0; 1004} 1005 1006static struct platform_driver wiz_driver = { 1007 .probe = wiz_probe, 1008 .remove = wiz_remove, 1009 .driver = { 1010 .name = "wiz", 1011 .of_match_table = wiz_id_table, 1012 }, 1013}; 1014module_platform_driver(wiz_driver); 1015 1016MODULE_AUTHOR("Texas Instruments Inc."); 1017MODULE_DESCRIPTION("TI J721E WIZ driver"); 1018MODULE_LICENSE("GPL v2"); 1019