1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/clk.h> 7#include <linux/clk-provider.h> 8#include <linux/delay.h> 9#include <linux/err.h> 10#include <linux/io.h> 11#include <linux/iopoll.h> 12#include <linux/kernel.h> 13#include <linux/module.h> 14#include <linux/of.h> 15#include <linux/of_device.h> 16#include <linux/of_address.h> 17#include <linux/phy/phy.h> 18#include <linux/platform_device.h> 19#include <linux/regulator/consumer.h> 20#include <linux/reset.h> 21#include <linux/slab.h> 22 23#include <dt-bindings/phy/phy.h> 24 25#include "phy-qcom-qmp.h" 26 27/* QPHY_SW_RESET bit */ 28#define SW_RESET BIT(0) 29/* QPHY_POWER_DOWN_CONTROL */ 30#define SW_PWRDN BIT(0) 31#define REFCLK_DRV_DSBL BIT(1) 32/* QPHY_START_CONTROL bits */ 33#define SERDES_START BIT(0) 34#define PCS_START BIT(1) 35#define PLL_READY_GATE_EN BIT(3) 36/* QPHY_PCS_STATUS bit */ 37#define PHYSTATUS BIT(6) 38/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ 39#define PCS_READY BIT(0) 40 41/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 42/* DP PHY soft reset */ 43#define SW_DPPHY_RESET BIT(0) 44/* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 45#define SW_DPPHY_RESET_MUX BIT(1) 46/* USB3 PHY soft reset */ 47#define SW_USB3PHY_RESET BIT(2) 48/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 49#define SW_USB3PHY_RESET_MUX BIT(3) 50 51/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 52#define USB3_MODE BIT(0) /* enables USB3 mode */ 53#define DP_MODE BIT(1) /* enables DP mode */ 54 55/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ 56#define ARCVR_DTCT_EN BIT(0) 57#define ALFPS_DTCT_EN BIT(1) 58#define ARCVR_DTCT_EVENT_SEL BIT(4) 59 60/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ 61#define IRQ_CLEAR BIT(0) 62 63/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ 64#define RCVR_DETECT BIT(0) 65 66/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ 67#define CLAMP_EN BIT(0) /* enables i/o clamp_n */ 68 69#define PHY_INIT_COMPLETE_TIMEOUT 10000 70#define POWER_DOWN_DELAY_US_MIN 10 71#define POWER_DOWN_DELAY_US_MAX 11 72 73#define MAX_PROP_NAME 32 74 75/* Define the assumed distance between lanes for underspecified device trees. */ 76#define QMP_PHY_LEGACY_LANE_STRIDE 0x400 77 78struct qmp_phy_init_tbl { 79 unsigned int offset; 80 unsigned int val; 81 /* 82 * register part of layout ? 83 * if yes, then offset gives index in the reg-layout 84 */ 85 bool in_layout; 86 /* 87 * mask of lanes for which this register is written 88 * for cases when second lane needs different values 89 */ 90 u8 lane_mask; 91}; 92 93#define QMP_PHY_INIT_CFG(o, v) \ 94 { \ 95 .offset = o, \ 96 .val = v, \ 97 .lane_mask = 0xff, \ 98 } 99 100#define QMP_PHY_INIT_CFG_L(o, v) \ 101 { \ 102 .offset = o, \ 103 .val = v, \ 104 .in_layout = true, \ 105 .lane_mask = 0xff, \ 106 } 107 108#define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 109 { \ 110 .offset = o, \ 111 .val = v, \ 112 .lane_mask = l, \ 113 } 114 115/* set of registers with offsets different per-PHY */ 116enum qphy_reg_layout { 117 /* Common block control registers */ 118 QPHY_COM_SW_RESET, 119 QPHY_COM_POWER_DOWN_CONTROL, 120 QPHY_COM_START_CONTROL, 121 QPHY_COM_PCS_READY_STATUS, 122 /* PCS registers */ 123 QPHY_PLL_LOCK_CHK_DLY_TIME, 124 QPHY_FLL_CNTRL1, 125 QPHY_FLL_CNTRL2, 126 QPHY_FLL_CNT_VAL_L, 127 QPHY_FLL_CNT_VAL_H_TOL, 128 QPHY_FLL_MAN_CODE, 129 QPHY_SW_RESET, 130 QPHY_START_CTRL, 131 QPHY_PCS_READY_STATUS, 132 QPHY_PCS_STATUS, 133 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 134 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 135 QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, 136 QPHY_PCS_POWER_DOWN_CONTROL, 137 /* Keep last to ensure regs_layout arrays are properly initialized */ 138 QPHY_LAYOUT_SIZE 139}; 140 141static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { 142 [QPHY_START_CTRL] = 0x00, 143 [QPHY_PCS_READY_STATUS] = 0x168, 144}; 145 146static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 147 [QPHY_COM_SW_RESET] = 0x400, 148 [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, 149 [QPHY_COM_START_CONTROL] = 0x408, 150 [QPHY_COM_PCS_READY_STATUS] = 0x448, 151 [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8, 152 [QPHY_FLL_CNTRL1] = 0xc4, 153 [QPHY_FLL_CNTRL2] = 0xc8, 154 [QPHY_FLL_CNT_VAL_L] = 0xcc, 155 [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0, 156 [QPHY_FLL_MAN_CODE] = 0xd4, 157 [QPHY_SW_RESET] = 0x00, 158 [QPHY_START_CTRL] = 0x08, 159 [QPHY_PCS_STATUS] = 0x174, 160}; 161 162static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 163 [QPHY_FLL_CNTRL1] = 0xc0, 164 [QPHY_FLL_CNTRL2] = 0xc4, 165 [QPHY_FLL_CNT_VAL_L] = 0xc8, 166 [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc, 167 [QPHY_FLL_MAN_CODE] = 0xd0, 168 [QPHY_SW_RESET] = 0x00, 169 [QPHY_START_CTRL] = 0x08, 170 [QPHY_PCS_STATUS] = 0x17c, 171 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4, 172 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8, 173 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178, 174}; 175 176static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 177 [QPHY_SW_RESET] = 0x00, 178 [QPHY_START_CTRL] = 0x08, 179 [QPHY_PCS_STATUS] = 0x174, 180 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8, 181 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc, 182 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170, 183}; 184 185static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 186 [QPHY_SW_RESET] = 0x00, 187 [QPHY_START_CTRL] = 0x08, 188 [QPHY_PCS_STATUS] = 0x174, 189}; 190 191static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 192 [QPHY_SW_RESET] = 0x00, 193 [QPHY_START_CTRL] = 0x08, 194 [QPHY_PCS_STATUS] = 0x2ac, 195}; 196 197static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 198 [QPHY_SW_RESET] = 0x00, 199 [QPHY_START_CTRL] = 0x44, 200 [QPHY_PCS_STATUS] = 0x14, 201 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 202 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308, 203 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314, 204}; 205 206static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = { 207 [QPHY_SW_RESET] = 0x00, 208 [QPHY_START_CTRL] = 0x44, 209 [QPHY_PCS_STATUS] = 0x14, 210 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 211 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608, 212 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614, 213}; 214 215static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { 216 [QPHY_START_CTRL] = 0x00, 217 [QPHY_PCS_READY_STATUS] = 0x160, 218}; 219 220static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { 221 [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START, 222 [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS, 223 [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET, 224}; 225 226static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = { 227 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a), 228 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 229 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 230 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 231 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 232 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 233 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 234 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 235 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 236 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), 237 /* PLL and Loop filter settings */ 238 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 239 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 240 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 241 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 242 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 243 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 244 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 245 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 246 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), 247 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), 248 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 249 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 250 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 251 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 252 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 253 /* SSC settings */ 254 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 255 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 256 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 257 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 258 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 259 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), 260 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), 261}; 262 263static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = { 264 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06), 265 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 266 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), 267 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), 268 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 269 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 270 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), 271 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 272 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0), 273}; 274 275static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = { 276 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 277 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), 278 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 279 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 280 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 281 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 282 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), 283 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 284 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 285 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 286 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 287 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 288 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 289 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 290 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 291 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 292 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 293 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 294 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 295 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 296 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), 297 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), 298 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), 299}; 300 301static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = { 302 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), 303 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 304 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 305 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 306 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42), 307 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 308 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 309 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), 310 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01), 311 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 312 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 313 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), 314 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09), 315 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 316 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 317 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 318 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 319 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 320 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a), 321 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a), 322 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 323 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), 324 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 325 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04), 326 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 327 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 328 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 329 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 330 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 331 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 332 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 333 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 334 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02), 335 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 336 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 337 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 338 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15), 339 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 340 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 341 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 342 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 343 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 344 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40), 345}; 346 347static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = { 348 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 349 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), 350}; 351 352static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = { 353 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 354 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01), 355 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00), 356 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 357 QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18), 358 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), 359 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04), 360 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 361 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 362 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19), 363}; 364 365static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = { 366 QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c), 367 QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00), 368 QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 369 370 QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05), 371 372 QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05), 373 QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02), 374 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00), 375 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3), 376 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e), 377}; 378 379static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { 380 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 381 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 382 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), 383 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 384 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 385 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 386 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 387 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 388 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 389 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 390 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 391 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 392 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 393 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 394 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 395 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 396 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 397 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), 398 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), 399 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), 400 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 401 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 402 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 403 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 404 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), 405 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 406 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), 407 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 408 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 409 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 410 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), 411 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 412 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 413 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 414 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 415 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 416 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 417 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 418 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 419 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 420 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 421 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 422}; 423 424static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { 425 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 426 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 427 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 428 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 429}; 430 431static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { 432 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 433 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), 434 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 435 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), 436 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 437 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 438 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 439 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 440 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 441 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), 442 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 443 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 444 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 445 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 446}; 447 448static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { 449 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 450 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 451 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 452 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 453 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 454 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 455 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 456 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 457 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), 458 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 459}; 460 461static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { 462 QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01), 463 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), 464 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), 465 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 466 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), 467 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 468 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 469 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05), 470 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), 471 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), 472 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), 473 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10), 474 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 475 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 476 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 477 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 478 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), 479 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54), 480 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), 481 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 482 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), 483 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), 484 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), 485 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 486 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 487 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 488 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 489 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 490 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), 491 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), 492 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), 493 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), 494 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 495 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), 496 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), 497 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), 498 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), 499 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), 500 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), 501 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), 502 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), 503 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), 504 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), 505 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), 506 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), 507 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), 508 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), 509}; 510 511static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = { 512 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 513 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), 514}; 515 516static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = { 517 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), 518 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), 519 QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), 520 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18), 521 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), 522 QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b), 523 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff), 524 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f), 525 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff), 526 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f), 527 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), 528}; 529 530static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = { 531 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), 532 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 533 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 534 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 535 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 536 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 537 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 538 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 539 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04), 540 /* PLL and Loop filter settings */ 541 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 542 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 543 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 544 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 545 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 546 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 547 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 548 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 549 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), 550 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), 551 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), 552 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 553 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 554 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 555 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 556 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 557 /* SSC settings */ 558 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 559 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 560 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 561 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 562 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 563 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), 564 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), 565}; 566 567static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = { 568 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 569 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 570 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), 571}; 572 573static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = { 574 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 575 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), 576 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 577 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), 578 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb), 579 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 580 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 581 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), 582 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18), 583 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 584}; 585 586static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = { 587 /* FLL settings */ 588 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03), 589 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02), 590 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09), 591 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42), 592 QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85), 593 594 /* Lock Det settings */ 595 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1), 596 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f), 597 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47), 598 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08), 599}; 600 601static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { 602 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 603 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 604 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), 605 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), 606 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), 607 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 608 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), 609 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), 610 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), 611 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), 612 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), 613 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), 614 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), 615 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 616 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), 617 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), 618 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 619 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), 620 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 621 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 622 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), 623 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), 624 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), 625 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 626 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), 627 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 628 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), 629 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 630 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 631 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), 632 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 633 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), 634 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), 635 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 636 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), 637 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), 638 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), 639 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 640 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 641 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 642}; 643 644static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { 645 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 646 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), 647 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), 648 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 649 QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36), 650 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), 651}; 652 653static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { 654 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 655 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 656 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), 657 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), 658 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 659 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 660 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), 661}; 662 663static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { 664 QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4), 665 QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0), 666 QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), 667 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), 668 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), 669 QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), 670 QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), 671 QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73), 672 QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99), 673 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15), 674 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe), 675 QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0), 676 QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3), 677}; 678 679static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { 680 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 681 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 682 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), 683 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 684 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 685 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 686 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 687 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 688 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 689 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 690 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 691 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 692 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 693 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 694 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 695 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 696 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 697 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 698 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 699 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 700 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 701 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 702 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 703 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 704 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 705 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 706 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 707 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 708 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 709 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 710 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 711 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 712 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 713 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 714 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 715 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 716 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 717 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 718 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 719 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 720 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 721 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 722}; 723 724static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { 725 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 726 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 727 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 728 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 729}; 730 731static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { 732 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 733 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), 734 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 735 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 736 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 737 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 738 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 739 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 740 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 741 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), 742 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 743 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), 744 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 745 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 746 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 747 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 748}; 749 750static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { 751 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 752 753 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 754 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 755 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 756 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 757 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 758 759 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 760 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 761 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 762 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 763 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 764 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 765 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 766 767 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), 768 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 769 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), 770 771 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), 772}; 773 774static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { 775 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), 776 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), 777 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), 778 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), 779 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 780}; 781 782static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { 783 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), 784 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), 785 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), 786 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), 787 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), 788 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), 789 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 790 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), 791 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), 792 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), 793 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), 794 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), 795 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), 796 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), 797 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), 798 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), 799 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), 800 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), 801 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), 802 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), 803 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), 804 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), 805 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), 806 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), 807 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), 808 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), 809 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), 810 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), 811 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), 812 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), 813 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 814 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 815 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), 816 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), 817 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), 818 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), 819 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), 820 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), 821 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), 822 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), 823 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), 824 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), 825 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), 826 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), 827 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), 828}; 829 830static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { 831 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), 832 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), 833 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), 834 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), 835 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), 836 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), 837 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), 838 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), 839 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), 840 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), 841 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), 842 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), 843 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), 844 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), 845 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), 846 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), 847 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), 848 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), 849 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), 850 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), 851 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), 852 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), 853 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), 854 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), 855 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), 856 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), 857 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), 858 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), 859 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), 860 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), 861 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), 862 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), 863 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), 864 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), 865 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), 866 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), 867 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), 868 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), 869 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), 870 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), 871 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), 872 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), 873 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), 874 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), 875 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), 876 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), 877 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), 878 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), 879 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), 880 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), 881 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), 882 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), 883 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), 884 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), 885 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), 886 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), 887}; 888 889static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = { 890}; 891 892static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { 893 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), 894 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), 895 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), 896 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), 897 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), 898 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), 899 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), 900}; 901 902static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { 903 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 904 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 905 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 906 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 907 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 908 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 909 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), 910 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 911 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 912 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 913 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 914 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 915 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 916 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 917 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 918 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 919 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 920 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 921 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 922 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 923 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 924 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 925 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 926 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 927 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 928 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 929 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 930 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 931 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 932 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 933 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 934 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 935 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 936 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 937 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 938 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 939}; 940 941static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { 942 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 943 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 944 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 945 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 946 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 947}; 948 949static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { 950 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 951 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), 952 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 953 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), 954 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 955 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 956 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), 957 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), 958 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 959 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 960 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 961 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 962 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 963 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 964 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), 965 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), 966 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), 967 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 968 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 969 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 970 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 971}; 972 973static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { 974 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), 975 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 976 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 977 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 978 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), 979 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), 980 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 981}; 982 983static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { 984 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), 985 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 986 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 987 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 988 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), 989 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), 990 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 991}; 992 993static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { 994 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 995 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), 996 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), 997 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), 998 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), 999 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), 1000 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 1001}; 1002 1003static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { 1004 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), 1005 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 1006 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 1007 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 1008 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), 1009 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), 1010 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), 1011}; 1012 1013static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { 1014 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), 1015 QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), 1016 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 1017 QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), 1018 QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), 1019 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), 1020 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), 1021 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1022 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), 1023 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), 1024 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), 1025 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), 1026 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), 1027 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 1028 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 1029}; 1030 1031static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { 1032 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 1033 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1034 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 1035 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 1036 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 1037 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1038 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 1039 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 1040 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 1041}; 1042 1043static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { 1044 /* FLL settings */ 1045 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 1046 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 1047 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 1048 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 1049 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 1050 1051 /* Lock Det settings */ 1052 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 1053 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 1054 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 1055 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 1056 1057 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 1058 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 1059 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 1060 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 1061 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 1062 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 1063 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 1064 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 1065 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 1066 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 1067 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 1068 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 1069 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 1070 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 1071 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 1072 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 1073 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 1074 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 1075 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 1076 1077 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 1078 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 1079 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 1080 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 1081 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1082 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1083 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 1084 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 1085 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 1086 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 1087 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 1088}; 1089 1090static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = { 1091 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 1092 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 1093 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 1094 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 1095 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 1096 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 1097 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 1098 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 1099 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 1100 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 1101 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 1102 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 1103 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 1104 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 1105 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 1106 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 1107 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1108 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1109 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 1110 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 1111 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 1112 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 1113 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 1114 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 1115 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 1116 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 1117 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 1118 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 1119 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 1120 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 1121 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 1122 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 1123 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 1124 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 1125 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 1126 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 1127}; 1128 1129static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = { 1130 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 1131 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 1132 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), 1133 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06), 1134 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 1135}; 1136 1137static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = { 1138 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c), 1139 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50), 1140 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 1141 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 1142 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 1143 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 1144 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 1145 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1146 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 1147 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), 1148 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 1149}; 1150 1151static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = { 1152 /* FLL settings */ 1153 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 1154 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 1155 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 1156 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 1157 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 1158 1159 /* Lock Det settings */ 1160 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 1161 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 1162 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 1163 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 1164 1165 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 1166 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 1167 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 1168 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5), 1169 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c), 1170 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64), 1171 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a), 1172 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 1173 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 1174 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 1175 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 1176 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 1177 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 1178 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 1179 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 1180 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 1181 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 1182 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 1183 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 1184 1185 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 1186 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 1187 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 1188 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 1189 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1190 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1191 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 1192 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 1193 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 1194 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 1195 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 1196 1197 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), 1198 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), 1199}; 1200 1201static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = { 1202 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 1203 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 1204 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 1205 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 1206 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 1207 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5), 1208 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 1209 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 1210 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 1211 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 1212 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), 1213 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 1214 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04), 1215 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05), 1216 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff), 1217 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00), 1218 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 1219 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 1220 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 1221 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 1222 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1223 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1224 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda), 1225 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 1226 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff), 1227 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c), 1228 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98), 1229 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06), 1230 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16), 1231 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36), 1232 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 1233 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00), 1234 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1), 1235 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00), 1236 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32), 1237 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f), 1238 1239 /* Rate B */ 1240 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), 1241}; 1242 1243static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = { 1244 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 1245 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04), 1246 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 1247}; 1248 1249static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = { 1250 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), 1251 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), 1252 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 1253 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 1254 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 1255 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b), 1256 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 1257 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 1258 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 1259 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), 1260 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), 1261 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04), 1262 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 1263 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81), 1264 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 1265 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 1266}; 1267 1268static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = { 1269 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e), 1270 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a), 1271 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02), 1272 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03), 1273 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43), 1274 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f), 1275 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a), 1276 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02), 1277}; 1278 1279static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = { 1280 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 1281 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 1282 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 1283 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06), 1284 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 1285 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 1286 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 1287 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 1288 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 1289 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 1290 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 1291 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 1292 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 1293 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 1294 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 1295 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1296 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1297 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 1298 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 1299 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 1300 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 1301 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 1302 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 1303 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 1304 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 1305 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 1306 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 1307 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 1308 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 1309 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80), 1310 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 1311 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 1312 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 1313 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 1314 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 1315 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 1316 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 1317 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 1318}; 1319 1320static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = { 1321 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 1322 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 1323 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 1324 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), 1325}; 1326 1327static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = { 1328 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 1329 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1330 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 1331 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 1332 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07), 1333 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1334 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43), 1335 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), 1336 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 1337 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), 1338 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), 1339 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), 1340 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), 1341 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), 1342 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), 1343 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03), 1344 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), 1345}; 1346 1347static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = { 1348 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 1349 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 1350 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 1351 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 1352 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 1353 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 1354 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 1355 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 1356 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 1357 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 1358 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 1359 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 1360 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 1361 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 1362 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 1363 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 1364 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 1365 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15), 1366 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 1367 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 1368 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 1369 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 1370 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d), 1371 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 1372 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 1373 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 1374 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 1375 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 1376 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 1377 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 1378 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1379 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1380 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 1381 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 1382 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a), 1383 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 1384 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 1385 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 1386}; 1387 1388static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = { 1389 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), 1390 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), 1391 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1392 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01), 1393 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1394 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1395 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00), 1396 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1397 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 1398 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1399 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1400 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1401 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff), 1402 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c), 1403 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), 1404 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1405 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98), 1406 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1407 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1408 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1409 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32), 1410 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f), 1411 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), 1412 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), 1413 1414 /* Rate B */ 1415 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), 1416}; 1417 1418static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = { 1419 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), 1420 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), 1421 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), 1422 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), 1423 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05), 1424 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), 1425}; 1426 1427static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = { 1428 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), 1429 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), 1430 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 1431 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), 1432 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), 1433 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 1434 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), 1435 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 1436 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), 1437 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 1438 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), 1439 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), 1440 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 1441 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 1442 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d), 1443 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 1444 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), 1445 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1446 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1447 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36), 1448 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36), 1449 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6), 1450 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b), 1451 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d), 1452 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0), 1453 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8), 1454 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 1455 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 1456 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 1457 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), 1458 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), 1459 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 1460 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 1461 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 1462 1463}; 1464 1465static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = { 1466 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), 1467 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), 1468 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 1469 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 1470 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), 1471 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), 1472 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 1473}; 1474 1475static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { 1476 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 1477 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 1478 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 1479 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1480 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1481 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 1482 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 1483 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 1484 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 1485 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1486 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1487 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1488 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1489 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1490 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1491 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 1492 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 1493 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 1494 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 1495 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 1496 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 1497 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 1498 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 1499 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 1500 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 1501 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 1502 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1503 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 1504 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 1505 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 1506 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 1507 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 1508 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 1509 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 1510 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 1511 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1512 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1513 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 1514 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 1515 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1516}; 1517 1518static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { 1519 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), 1520 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), 1521 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 1522 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 1523 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 1524}; 1525 1526static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { 1527 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 1528 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1529 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1530 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1531 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1532 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 1533 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 1534 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 1535 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 1536 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 1537 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 1538 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), 1539 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1540 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1541 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1542 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1543 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1544 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 1545 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 1546 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1547 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 1548 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), 1549 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), 1550 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 1551 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), 1552 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 1553 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 1554 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 1555 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 1556 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 1557 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 1558 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1559 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 1560 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 1561 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 1562 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 1563}; 1564 1565static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { 1566 /* Lock Det settings */ 1567 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1568 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 1569 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 1570 1571 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 1572 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 1573 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 1574 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1575 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1576 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 1577 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 1578 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 1579 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1580 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1581}; 1582 1583static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = { 1584 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 1585 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1586 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 1587 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 1588 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 1589 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 1590 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 1591 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1592 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1593 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1594 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1595 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1596 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 1597 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 1598 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 1599 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 1600 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 1601 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 1602 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 1603 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 1604 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 1605 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 1606 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 1607 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 1608 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 1609 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 1610 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1611 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1612 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1613 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 1614 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 1615 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 1616 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 1617 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 1618 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 1619 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 1620 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 1621 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1622 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1623 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1624}; 1625 1626static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = { 1627 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 1628 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95), 1629 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), 1630 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05), 1631}; 1632 1633static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = { 1634 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), 1635 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 1636 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37), 1637 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f), 1638 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef), 1639 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 1640 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 1641 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 1642 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 1643 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 1644 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 1645 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 1646 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 1647 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 1648 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 1649 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1650 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1651 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1652 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1653 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08), 1654 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 1655 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 1656 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 1657 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1658 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1659 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1660 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 1661 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1662 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1663 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 1664 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1665 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1666 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1667 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20), 1668 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), 1669 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 1670}; 1671 1672static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = { 1673 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1674 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 1675 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 1676 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 1677 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1678 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1679 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 1680 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), 1681 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1682 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f), 1683 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1684 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1685 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 1686 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 1687 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 1688 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 1689}; 1690 1691static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { 1692 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), 1693 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), 1694 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1695 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 1696 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 1697 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 1698 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), 1699 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), 1700}; 1701 1702static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { 1703 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 1704 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1705 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1706 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1707 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1708 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 1709 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 1710 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 1711 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 1712 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 1713 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 1714 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 1715 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1716 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1717 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1718 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1719 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1720 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 1721 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 1722 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1723 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), 1724 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), 1725 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), 1726 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), 1727 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), 1728 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 1729 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), 1730 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 1731 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 1732 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 1733 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 1734 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 1735 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 1736 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1737 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 1738 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 1739 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 1740 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 1741}; 1742 1743static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { 1744 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1745 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 1746 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 1747 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 1748 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 1749 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 1750 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 1751 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1752 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1753 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 1754 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 1755 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 1756 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1757 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1758}; 1759 1760static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = { 1761 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 1762 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 1763 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82), 1764 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), 1765 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1766 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 1767}; 1768 1769static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = { 1770 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), 1771 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff), 1772 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), 1773 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), 1774 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 1775 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 1776 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 1777 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 1778 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 1779 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 1780 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 1781 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 1782 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 1783 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 1784 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 1785 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1786 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1787 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1788 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1789 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a), 1790 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 1791 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 1792 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1793 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1794 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1795 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 1796 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1797 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1798 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 1799 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1800 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1801 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1802 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1803 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 1804 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 1805 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 1806}; 1807 1808static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = { 1809 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1810 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 1811 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 1812 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 1813 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1814 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1815 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 1816 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 1817 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), 1818 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1819 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 1820 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1821 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1822 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 1823 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 1824 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 1825}; 1826 1827/* struct qmp_phy_cfg - per-PHY initialization config */ 1828struct qmp_phy_cfg { 1829 /* phy-type - PCIE/UFS/USB */ 1830 unsigned int type; 1831 /* number of lanes provided by phy */ 1832 int nlanes; 1833 1834 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1835 const struct qmp_phy_init_tbl *serdes_tbl; 1836 int serdes_tbl_num; 1837 const struct qmp_phy_init_tbl *tx_tbl; 1838 int tx_tbl_num; 1839 const struct qmp_phy_init_tbl *rx_tbl; 1840 int rx_tbl_num; 1841 const struct qmp_phy_init_tbl *pcs_tbl; 1842 int pcs_tbl_num; 1843 const struct qmp_phy_init_tbl *pcs_misc_tbl; 1844 int pcs_misc_tbl_num; 1845 1846 /* Init sequence for DP PHY block link rates */ 1847 const struct qmp_phy_init_tbl *serdes_tbl_rbr; 1848 int serdes_tbl_rbr_num; 1849 const struct qmp_phy_init_tbl *serdes_tbl_hbr; 1850 int serdes_tbl_hbr_num; 1851 const struct qmp_phy_init_tbl *serdes_tbl_hbr2; 1852 int serdes_tbl_hbr2_num; 1853 const struct qmp_phy_init_tbl *serdes_tbl_hbr3; 1854 int serdes_tbl_hbr3_num; 1855 1856 /* clock ids to be requested */ 1857 const char * const *clk_list; 1858 int num_clks; 1859 /* resets to be requested */ 1860 const char * const *reset_list; 1861 int num_resets; 1862 /* regulators to be requested */ 1863 const char * const *vreg_list; 1864 int num_vregs; 1865 1866 /* array of registers with different offsets */ 1867 const unsigned int *regs; 1868 1869 unsigned int start_ctrl; 1870 unsigned int pwrdn_ctrl; 1871 unsigned int mask_com_pcs_ready; 1872 1873 /* true, if PHY has a separate PHY_COM control block */ 1874 bool has_phy_com_ctrl; 1875 /* true, if PHY has a reset for individual lanes */ 1876 bool has_lane_rst; 1877 /* true, if PHY needs delay after POWER_DOWN */ 1878 bool has_pwrdn_delay; 1879 /* power_down delay in usec */ 1880 int pwrdn_delay_min; 1881 int pwrdn_delay_max; 1882 1883 /* true, if PHY has a separate DP_COM control block */ 1884 bool has_phy_dp_com_ctrl; 1885 /* true, if PHY has secondary tx/rx lanes to be configured */ 1886 bool is_dual_lane_phy; 1887 1888 /* true, if PCS block has no separate SW_RESET register */ 1889 bool no_pcs_sw_reset; 1890}; 1891 1892struct qmp_phy_combo_cfg { 1893 const struct qmp_phy_cfg *usb_cfg; 1894 const struct qmp_phy_cfg *dp_cfg; 1895}; 1896 1897/** 1898 * struct qmp_phy - per-lane phy descriptor 1899 * 1900 * @phy: generic phy 1901 * @cfg: phy specific configuration 1902 * @serdes: iomapped memory space for phy's serdes (i.e. PLL) 1903 * @tx: iomapped memory space for lane's tx 1904 * @rx: iomapped memory space for lane's rx 1905 * @pcs: iomapped memory space for lane's pcs 1906 * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) 1907 * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) 1908 * @pcs_misc: iomapped memory space for lane's pcs_misc 1909 * @pipe_clk: pipe lock 1910 * @index: lane index 1911 * @qmp: QMP phy to which this lane belongs 1912 * @lane_rst: lane's reset controller 1913 * @mode: current PHY mode 1914 */ 1915struct qmp_phy { 1916 struct phy *phy; 1917 const struct qmp_phy_cfg *cfg; 1918 void __iomem *serdes; 1919 void __iomem *tx; 1920 void __iomem *rx; 1921 void __iomem *pcs; 1922 void __iomem *tx2; 1923 void __iomem *rx2; 1924 void __iomem *pcs_misc; 1925 struct clk *pipe_clk; 1926 unsigned int index; 1927 struct qcom_qmp *qmp; 1928 struct reset_control *lane_rst; 1929 enum phy_mode mode; 1930 unsigned int dp_aux_cfg; 1931 struct phy_configure_opts_dp dp_opts; 1932 struct qmp_phy_dp_clks *dp_clks; 1933}; 1934 1935struct qmp_phy_dp_clks { 1936 struct qmp_phy *qphy; 1937 struct clk_hw dp_link_hw; 1938 struct clk_hw dp_pixel_hw; 1939}; 1940 1941/** 1942 * struct qcom_qmp - structure holding QMP phy block attributes 1943 * 1944 * @dev: device 1945 * @dp_com: iomapped memory space for phy's dp_com control block 1946 * 1947 * @clks: array of clocks required by phy 1948 * @resets: array of resets required by phy 1949 * @vregs: regulator supplies bulk data 1950 * 1951 * @phys: array of per-lane phy descriptors 1952 * @phy_mutex: mutex lock for PHY common block initialization 1953 * @init_count: phy common block initialization count 1954 * @ufs_reset: optional UFS PHY reset handle 1955 */ 1956struct qcom_qmp { 1957 struct device *dev; 1958 void __iomem *dp_com; 1959 1960 struct clk_bulk_data *clks; 1961 struct reset_control **resets; 1962 struct regulator_bulk_data *vregs; 1963 1964 struct qmp_phy **phys; 1965 1966 struct mutex phy_mutex; 1967 int init_count; 1968 1969 struct reset_control *ufs_reset; 1970}; 1971 1972static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1973{ 1974 u32 reg; 1975 1976 reg = readl(base + offset); 1977 reg |= val; 1978 writel(reg, base + offset); 1979 1980 /* ensure that above write is through */ 1981 readl(base + offset); 1982} 1983 1984static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1985{ 1986 u32 reg; 1987 1988 reg = readl(base + offset); 1989 reg &= ~val; 1990 writel(reg, base + offset); 1991 1992 /* ensure that above write is through */ 1993 readl(base + offset); 1994} 1995 1996/* list of clocks required by phy */ 1997static const char * const msm8996_phy_clk_l[] = { 1998 "aux", "cfg_ahb", "ref", 1999}; 2000 2001static const char * const msm8996_ufs_phy_clk_l[] = { 2002 "ref", 2003}; 2004 2005static const char * const qmp_v3_phy_clk_l[] = { 2006 "aux", "cfg_ahb", "ref", "com_aux", 2007}; 2008 2009static const char * const sdm845_pciephy_clk_l[] = { 2010 "aux", "cfg_ahb", "ref", "refgen", 2011}; 2012 2013static const char * const qmp_v4_phy_clk_l[] = { 2014 "aux", "ref_clk_src", "ref", "com_aux", 2015}; 2016 2017/* the primary usb3 phy on sm8250 doesn't have a ref clock */ 2018static const char * const qmp_v4_sm8250_usbphy_clk_l[] = { 2019 "aux", "ref_clk_src", "com_aux" 2020}; 2021 2022static const char * const sdm845_ufs_phy_clk_l[] = { 2023 "ref", "ref_aux", 2024}; 2025 2026/* list of resets */ 2027static const char * const msm8996_pciephy_reset_l[] = { 2028 "phy", "common", "cfg", 2029}; 2030 2031static const char * const msm8996_usb3phy_reset_l[] = { 2032 "phy", "common", 2033}; 2034 2035static const char * const sc7180_usb3phy_reset_l[] = { 2036 "phy", 2037}; 2038 2039static const char * const sdm845_pciephy_reset_l[] = { 2040 "phy", 2041}; 2042 2043/* list of regulators */ 2044static const char * const qmp_phy_vreg_l[] = { 2045 "vdda-phy", "vdda-pll", 2046}; 2047 2048static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { 2049 .type = PHY_TYPE_USB3, 2050 .nlanes = 1, 2051 2052 .serdes_tbl = ipq8074_usb3_serdes_tbl, 2053 .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl), 2054 .tx_tbl = msm8996_usb3_tx_tbl, 2055 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), 2056 .rx_tbl = ipq8074_usb3_rx_tbl, 2057 .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl), 2058 .pcs_tbl = ipq8074_usb3_pcs_tbl, 2059 .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl), 2060 .clk_list = msm8996_phy_clk_l, 2061 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 2062 .reset_list = msm8996_usb3phy_reset_l, 2063 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2064 .vreg_list = qmp_phy_vreg_l, 2065 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2066 .regs = usb3phy_regs_layout, 2067 2068 .start_ctrl = SERDES_START | PCS_START, 2069 .pwrdn_ctrl = SW_PWRDN, 2070}; 2071 2072static const struct qmp_phy_cfg msm8996_pciephy_cfg = { 2073 .type = PHY_TYPE_PCIE, 2074 .nlanes = 3, 2075 2076 .serdes_tbl = msm8996_pcie_serdes_tbl, 2077 .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl), 2078 .tx_tbl = msm8996_pcie_tx_tbl, 2079 .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl), 2080 .rx_tbl = msm8996_pcie_rx_tbl, 2081 .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl), 2082 .pcs_tbl = msm8996_pcie_pcs_tbl, 2083 .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl), 2084 .clk_list = msm8996_phy_clk_l, 2085 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 2086 .reset_list = msm8996_pciephy_reset_l, 2087 .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l), 2088 .vreg_list = qmp_phy_vreg_l, 2089 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2090 .regs = pciephy_regs_layout, 2091 2092 .start_ctrl = PCS_START | PLL_READY_GATE_EN, 2093 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2094 .mask_com_pcs_ready = PCS_READY, 2095 2096 .has_phy_com_ctrl = true, 2097 .has_lane_rst = true, 2098 .has_pwrdn_delay = true, 2099 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 2100 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 2101}; 2102 2103static const struct qmp_phy_cfg msm8996_ufs_cfg = { 2104 .type = PHY_TYPE_UFS, 2105 .nlanes = 1, 2106 2107 .serdes_tbl = msm8996_ufs_serdes_tbl, 2108 .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl), 2109 .tx_tbl = msm8996_ufs_tx_tbl, 2110 .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl), 2111 .rx_tbl = msm8996_ufs_rx_tbl, 2112 .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl), 2113 2114 .clk_list = msm8996_ufs_phy_clk_l, 2115 .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l), 2116 2117 .vreg_list = qmp_phy_vreg_l, 2118 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2119 2120 .regs = msm8996_ufsphy_regs_layout, 2121 2122 .start_ctrl = SERDES_START, 2123 .pwrdn_ctrl = SW_PWRDN, 2124 2125 .no_pcs_sw_reset = true, 2126}; 2127 2128static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { 2129 .type = PHY_TYPE_USB3, 2130 .nlanes = 1, 2131 2132 .serdes_tbl = msm8996_usb3_serdes_tbl, 2133 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl), 2134 .tx_tbl = msm8996_usb3_tx_tbl, 2135 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), 2136 .rx_tbl = msm8996_usb3_rx_tbl, 2137 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl), 2138 .pcs_tbl = msm8996_usb3_pcs_tbl, 2139 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl), 2140 .clk_list = msm8996_phy_clk_l, 2141 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 2142 .reset_list = msm8996_usb3phy_reset_l, 2143 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2144 .vreg_list = qmp_phy_vreg_l, 2145 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2146 .regs = usb3phy_regs_layout, 2147 2148 .start_ctrl = SERDES_START | PCS_START, 2149 .pwrdn_ctrl = SW_PWRDN, 2150}; 2151 2152static const char * const ipq8074_pciephy_clk_l[] = { 2153 "aux", "cfg_ahb", 2154}; 2155/* list of resets */ 2156static const char * const ipq8074_pciephy_reset_l[] = { 2157 "phy", "common", 2158}; 2159 2160static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { 2161 .type = PHY_TYPE_PCIE, 2162 .nlanes = 1, 2163 2164 .serdes_tbl = ipq8074_pcie_serdes_tbl, 2165 .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), 2166 .tx_tbl = ipq8074_pcie_tx_tbl, 2167 .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), 2168 .rx_tbl = ipq8074_pcie_rx_tbl, 2169 .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), 2170 .pcs_tbl = ipq8074_pcie_pcs_tbl, 2171 .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), 2172 .clk_list = ipq8074_pciephy_clk_l, 2173 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 2174 .reset_list = ipq8074_pciephy_reset_l, 2175 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 2176 .vreg_list = NULL, 2177 .num_vregs = 0, 2178 .regs = pciephy_regs_layout, 2179 2180 .start_ctrl = SERDES_START | PCS_START, 2181 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2182 2183 .has_phy_com_ctrl = false, 2184 .has_lane_rst = false, 2185 .has_pwrdn_delay = true, 2186 .pwrdn_delay_min = 995, /* us */ 2187 .pwrdn_delay_max = 1005, /* us */ 2188}; 2189 2190static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { 2191 .type = PHY_TYPE_PCIE, 2192 .nlanes = 1, 2193 2194 .serdes_tbl = sdm845_qmp_pcie_serdes_tbl, 2195 .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), 2196 .tx_tbl = sdm845_qmp_pcie_tx_tbl, 2197 .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), 2198 .rx_tbl = sdm845_qmp_pcie_rx_tbl, 2199 .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), 2200 .pcs_tbl = sdm845_qmp_pcie_pcs_tbl, 2201 .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), 2202 .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl, 2203 .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), 2204 .clk_list = sdm845_pciephy_clk_l, 2205 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2206 .reset_list = sdm845_pciephy_reset_l, 2207 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2208 .vreg_list = qmp_phy_vreg_l, 2209 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2210 .regs = sdm845_qmp_pciephy_regs_layout, 2211 2212 .start_ctrl = PCS_START | SERDES_START, 2213 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2214 2215 .has_pwrdn_delay = true, 2216 .pwrdn_delay_min = 995, /* us */ 2217 .pwrdn_delay_max = 1005, /* us */ 2218}; 2219 2220static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { 2221 .type = PHY_TYPE_PCIE, 2222 .nlanes = 1, 2223 2224 .serdes_tbl = sdm845_qhp_pcie_serdes_tbl, 2225 .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), 2226 .tx_tbl = sdm845_qhp_pcie_tx_tbl, 2227 .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), 2228 .rx_tbl = sdm845_qhp_pcie_rx_tbl, 2229 .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), 2230 .pcs_tbl = sdm845_qhp_pcie_pcs_tbl, 2231 .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), 2232 .clk_list = sdm845_pciephy_clk_l, 2233 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2234 .reset_list = sdm845_pciephy_reset_l, 2235 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2236 .vreg_list = qmp_phy_vreg_l, 2237 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2238 .regs = sdm845_qhp_pciephy_regs_layout, 2239 2240 .start_ctrl = PCS_START | SERDES_START, 2241 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2242 2243 .has_pwrdn_delay = true, 2244 .pwrdn_delay_min = 995, /* us */ 2245 .pwrdn_delay_max = 1005, /* us */ 2246}; 2247 2248static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { 2249 .type = PHY_TYPE_USB3, 2250 .nlanes = 1, 2251 2252 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 2253 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 2254 .tx_tbl = qmp_v3_usb3_tx_tbl, 2255 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 2256 .rx_tbl = qmp_v3_usb3_rx_tbl, 2257 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 2258 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 2259 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 2260 .clk_list = qmp_v3_phy_clk_l, 2261 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 2262 .reset_list = msm8996_usb3phy_reset_l, 2263 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2264 .vreg_list = qmp_phy_vreg_l, 2265 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2266 .regs = qmp_v3_usb3phy_regs_layout, 2267 2268 .start_ctrl = SERDES_START | PCS_START, 2269 .pwrdn_ctrl = SW_PWRDN, 2270 2271 .has_pwrdn_delay = true, 2272 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 2273 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 2274 2275 .has_phy_dp_com_ctrl = true, 2276 .is_dual_lane_phy = true, 2277}; 2278 2279static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { 2280 .type = PHY_TYPE_USB3, 2281 .nlanes = 1, 2282 2283 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 2284 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 2285 .tx_tbl = qmp_v3_usb3_tx_tbl, 2286 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 2287 .rx_tbl = qmp_v3_usb3_rx_tbl, 2288 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 2289 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 2290 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 2291 .clk_list = qmp_v3_phy_clk_l, 2292 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 2293 .reset_list = sc7180_usb3phy_reset_l, 2294 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 2295 .vreg_list = qmp_phy_vreg_l, 2296 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2297 .regs = qmp_v3_usb3phy_regs_layout, 2298 2299 .start_ctrl = SERDES_START | PCS_START, 2300 .pwrdn_ctrl = SW_PWRDN, 2301 2302 .has_pwrdn_delay = true, 2303 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 2304 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 2305 2306 .has_phy_dp_com_ctrl = true, 2307 .is_dual_lane_phy = true, 2308}; 2309 2310static const struct qmp_phy_cfg sc7180_dpphy_cfg = { 2311 .type = PHY_TYPE_DP, 2312 .nlanes = 1, 2313 2314 .serdes_tbl = qmp_v3_dp_serdes_tbl, 2315 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 2316 .tx_tbl = qmp_v3_dp_tx_tbl, 2317 .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 2318 2319 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 2320 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 2321 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 2322 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 2323 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 2324 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 2325 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 2326 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 2327 2328 .clk_list = qmp_v3_phy_clk_l, 2329 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 2330 .reset_list = sc7180_usb3phy_reset_l, 2331 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 2332 .vreg_list = qmp_phy_vreg_l, 2333 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2334 .regs = qmp_v3_usb3phy_regs_layout, 2335 2336 .has_phy_dp_com_ctrl = true, 2337 .is_dual_lane_phy = true, 2338}; 2339 2340static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = { 2341 .usb_cfg = &sc7180_usb3phy_cfg, 2342 .dp_cfg = &sc7180_dpphy_cfg, 2343}; 2344 2345static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { 2346 .type = PHY_TYPE_USB3, 2347 .nlanes = 1, 2348 2349 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl, 2350 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl), 2351 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl, 2352 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl), 2353 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl, 2354 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl), 2355 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl, 2356 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl), 2357 .clk_list = qmp_v3_phy_clk_l, 2358 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 2359 .reset_list = msm8996_usb3phy_reset_l, 2360 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2361 .vreg_list = qmp_phy_vreg_l, 2362 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2363 .regs = qmp_v3_usb3phy_regs_layout, 2364 2365 .start_ctrl = SERDES_START | PCS_START, 2366 .pwrdn_ctrl = SW_PWRDN, 2367 2368 .has_pwrdn_delay = true, 2369 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 2370 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 2371}; 2372 2373static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { 2374 .type = PHY_TYPE_UFS, 2375 .nlanes = 2, 2376 2377 .serdes_tbl = sdm845_ufsphy_serdes_tbl, 2378 .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl), 2379 .tx_tbl = sdm845_ufsphy_tx_tbl, 2380 .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl), 2381 .rx_tbl = sdm845_ufsphy_rx_tbl, 2382 .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl), 2383 .pcs_tbl = sdm845_ufsphy_pcs_tbl, 2384 .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl), 2385 .clk_list = sdm845_ufs_phy_clk_l, 2386 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 2387 .vreg_list = qmp_phy_vreg_l, 2388 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2389 .regs = sdm845_ufsphy_regs_layout, 2390 2391 .start_ctrl = SERDES_START, 2392 .pwrdn_ctrl = SW_PWRDN, 2393 2394 .is_dual_lane_phy = true, 2395 .no_pcs_sw_reset = true, 2396}; 2397 2398static const struct qmp_phy_cfg msm8998_pciephy_cfg = { 2399 .type = PHY_TYPE_PCIE, 2400 .nlanes = 1, 2401 2402 .serdes_tbl = msm8998_pcie_serdes_tbl, 2403 .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), 2404 .tx_tbl = msm8998_pcie_tx_tbl, 2405 .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), 2406 .rx_tbl = msm8998_pcie_rx_tbl, 2407 .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), 2408 .pcs_tbl = msm8998_pcie_pcs_tbl, 2409 .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), 2410 .clk_list = msm8996_phy_clk_l, 2411 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 2412 .reset_list = ipq8074_pciephy_reset_l, 2413 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 2414 .vreg_list = qmp_phy_vreg_l, 2415 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2416 .regs = pciephy_regs_layout, 2417 2418 .start_ctrl = SERDES_START | PCS_START, 2419 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2420}; 2421 2422static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { 2423 .type = PHY_TYPE_USB3, 2424 .nlanes = 1, 2425 2426 .serdes_tbl = msm8998_usb3_serdes_tbl, 2427 .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl), 2428 .tx_tbl = msm8998_usb3_tx_tbl, 2429 .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl), 2430 .rx_tbl = msm8998_usb3_rx_tbl, 2431 .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl), 2432 .pcs_tbl = msm8998_usb3_pcs_tbl, 2433 .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl), 2434 .clk_list = msm8996_phy_clk_l, 2435 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 2436 .reset_list = msm8996_usb3phy_reset_l, 2437 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2438 .vreg_list = qmp_phy_vreg_l, 2439 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2440 .regs = qmp_v3_usb3phy_regs_layout, 2441 2442 .start_ctrl = SERDES_START | PCS_START, 2443 .pwrdn_ctrl = SW_PWRDN, 2444 2445 .is_dual_lane_phy = true, 2446}; 2447 2448static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { 2449 .type = PHY_TYPE_UFS, 2450 .nlanes = 2, 2451 2452 .serdes_tbl = sm8150_ufsphy_serdes_tbl, 2453 .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl), 2454 .tx_tbl = sm8150_ufsphy_tx_tbl, 2455 .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl), 2456 .rx_tbl = sm8150_ufsphy_rx_tbl, 2457 .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl), 2458 .pcs_tbl = sm8150_ufsphy_pcs_tbl, 2459 .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl), 2460 .clk_list = sdm845_ufs_phy_clk_l, 2461 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 2462 .vreg_list = qmp_phy_vreg_l, 2463 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2464 .regs = sm8150_ufsphy_regs_layout, 2465 2466 .start_ctrl = SERDES_START, 2467 .pwrdn_ctrl = SW_PWRDN, 2468 2469 .is_dual_lane_phy = true, 2470}; 2471 2472static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { 2473 .type = PHY_TYPE_USB3, 2474 .nlanes = 1, 2475 2476 .serdes_tbl = sm8150_usb3_serdes_tbl, 2477 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 2478 .tx_tbl = sm8150_usb3_tx_tbl, 2479 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), 2480 .rx_tbl = sm8150_usb3_rx_tbl, 2481 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), 2482 .pcs_tbl = sm8150_usb3_pcs_tbl, 2483 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), 2484 .clk_list = qmp_v4_phy_clk_l, 2485 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 2486 .reset_list = msm8996_usb3phy_reset_l, 2487 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2488 .vreg_list = qmp_phy_vreg_l, 2489 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2490 .regs = qmp_v4_usb3phy_regs_layout, 2491 2492 .start_ctrl = SERDES_START | PCS_START, 2493 .pwrdn_ctrl = SW_PWRDN, 2494 2495 .has_pwrdn_delay = true, 2496 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 2497 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 2498 2499 .has_phy_dp_com_ctrl = true, 2500 .is_dual_lane_phy = true, 2501}; 2502 2503static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { 2504 .type = PHY_TYPE_USB3, 2505 .nlanes = 1, 2506 2507 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 2508 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 2509 .tx_tbl = sm8150_usb3_uniphy_tx_tbl, 2510 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl), 2511 .rx_tbl = sm8150_usb3_uniphy_rx_tbl, 2512 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl), 2513 .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl, 2514 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl), 2515 .clk_list = qmp_v4_phy_clk_l, 2516 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 2517 .reset_list = msm8996_usb3phy_reset_l, 2518 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2519 .vreg_list = qmp_phy_vreg_l, 2520 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2521 .regs = qmp_v4_usb3_uniphy_regs_layout, 2522 2523 .start_ctrl = SERDES_START | PCS_START, 2524 .pwrdn_ctrl = SW_PWRDN, 2525 2526 .has_pwrdn_delay = true, 2527 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 2528 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 2529}; 2530 2531static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { 2532 .type = PHY_TYPE_USB3, 2533 .nlanes = 1, 2534 2535 .serdes_tbl = sm8150_usb3_serdes_tbl, 2536 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 2537 .tx_tbl = sm8250_usb3_tx_tbl, 2538 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), 2539 .rx_tbl = sm8250_usb3_rx_tbl, 2540 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), 2541 .pcs_tbl = sm8250_usb3_pcs_tbl, 2542 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), 2543 .clk_list = qmp_v4_sm8250_usbphy_clk_l, 2544 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), 2545 .reset_list = msm8996_usb3phy_reset_l, 2546 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2547 .vreg_list = qmp_phy_vreg_l, 2548 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2549 .regs = qmp_v4_usb3phy_regs_layout, 2550 2551 .start_ctrl = SERDES_START | PCS_START, 2552 .pwrdn_ctrl = SW_PWRDN, 2553 2554 .has_pwrdn_delay = true, 2555 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 2556 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 2557 2558 .has_phy_dp_com_ctrl = true, 2559 .is_dual_lane_phy = true, 2560}; 2561 2562static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { 2563 .type = PHY_TYPE_USB3, 2564 .nlanes = 1, 2565 2566 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 2567 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 2568 .tx_tbl = sm8250_usb3_uniphy_tx_tbl, 2569 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl), 2570 .rx_tbl = sm8250_usb3_uniphy_rx_tbl, 2571 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl), 2572 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, 2573 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), 2574 .clk_list = qmp_v4_phy_clk_l, 2575 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 2576 .reset_list = msm8996_usb3phy_reset_l, 2577 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2578 .vreg_list = qmp_phy_vreg_l, 2579 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2580 .regs = qmp_v4_usb3_uniphy_regs_layout, 2581 2582 .start_ctrl = SERDES_START | PCS_START, 2583 .pwrdn_ctrl = SW_PWRDN, 2584 2585 .has_pwrdn_delay = true, 2586 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 2587 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 2588}; 2589 2590static void qcom_qmp_phy_configure_lane(void __iomem *base, 2591 const unsigned int *regs, 2592 const struct qmp_phy_init_tbl tbl[], 2593 int num, 2594 u8 lane_mask) 2595{ 2596 int i; 2597 const struct qmp_phy_init_tbl *t = tbl; 2598 2599 if (!t) 2600 return; 2601 2602 for (i = 0; i < num; i++, t++) { 2603 if (!(t->lane_mask & lane_mask)) 2604 continue; 2605 2606 if (t->in_layout) 2607 writel(t->val, base + regs[t->offset]); 2608 else 2609 writel(t->val, base + t->offset); 2610 } 2611} 2612 2613static void qcom_qmp_phy_configure(void __iomem *base, 2614 const unsigned int *regs, 2615 const struct qmp_phy_init_tbl tbl[], 2616 int num) 2617{ 2618 qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff); 2619} 2620 2621static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy) 2622{ 2623 struct qcom_qmp *qmp = qphy->qmp; 2624 const struct qmp_phy_cfg *cfg = qphy->cfg; 2625 void __iomem *serdes = qphy->serdes; 2626 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 2627 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 2628 int serdes_tbl_num = cfg->serdes_tbl_num; 2629 int ret; 2630 2631 qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); 2632 2633 if (cfg->type == PHY_TYPE_DP) { 2634 switch (dp_opts->link_rate) { 2635 case 1620: 2636 qcom_qmp_phy_configure(serdes, cfg->regs, 2637 cfg->serdes_tbl_rbr, 2638 cfg->serdes_tbl_rbr_num); 2639 break; 2640 case 2700: 2641 qcom_qmp_phy_configure(serdes, cfg->regs, 2642 cfg->serdes_tbl_hbr, 2643 cfg->serdes_tbl_hbr_num); 2644 break; 2645 case 5400: 2646 qcom_qmp_phy_configure(serdes, cfg->regs, 2647 cfg->serdes_tbl_hbr2, 2648 cfg->serdes_tbl_hbr2_num); 2649 break; 2650 case 8100: 2651 qcom_qmp_phy_configure(serdes, cfg->regs, 2652 cfg->serdes_tbl_hbr3, 2653 cfg->serdes_tbl_hbr3_num); 2654 break; 2655 default: 2656 /* Other link rates aren't supported */ 2657 return -EINVAL; 2658 } 2659 } 2660 2661 2662 if (cfg->has_phy_com_ctrl) { 2663 void __iomem *status; 2664 unsigned int mask, val; 2665 2666 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); 2667 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], 2668 SERDES_START | PCS_START); 2669 2670 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; 2671 mask = cfg->mask_com_pcs_ready; 2672 2673 ret = readl_poll_timeout(status, val, (val & mask), 10, 2674 PHY_INIT_COMPLETE_TIMEOUT); 2675 if (ret) { 2676 dev_err(qmp->dev, 2677 "phy common block init timed-out\n"); 2678 return ret; 2679 } 2680 } 2681 2682 return 0; 2683} 2684 2685static void qcom_qmp_phy_dp_aux_init(struct qmp_phy *qphy) 2686{ 2687 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2688 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 2689 qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); 2690 2691 /* Turn on BIAS current for PHY/PLL */ 2692 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | 2693 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, 2694 qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); 2695 2696 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); 2697 2698 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2699 DP_PHY_PD_CTL_LANE_0_1_PWRDN | 2700 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | 2701 DP_PHY_PD_CTL_DP_CLAMP_EN, 2702 qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); 2703 2704 writel(QSERDES_V3_COM_BIAS_EN | 2705 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | 2706 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | 2707 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, 2708 qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); 2709 2710 writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG0); 2711 writel(0x13, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1); 2712 writel(0x24, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2); 2713 writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG3); 2714 writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG4); 2715 writel(0x26, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG5); 2716 writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG6); 2717 writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG7); 2718 writel(0xbb, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG8); 2719 writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG9); 2720 qphy->dp_aux_cfg = 0; 2721 2722 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 2723 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 2724 PHY_AUX_REQ_ERR_MASK, 2725 qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); 2726} 2727 2728static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { 2729 { 0x00, 0x0c, 0x14, 0x19 }, 2730 { 0x00, 0x0b, 0x12, 0xff }, 2731 { 0x00, 0x0b, 0xff, 0xff }, 2732 { 0x04, 0xff, 0xff, 0xff } 2733}; 2734 2735static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { 2736 { 0x08, 0x0f, 0x16, 0x1f }, 2737 { 0x11, 0x1e, 0x1f, 0xff }, 2738 { 0x19, 0x1f, 0xff, 0xff }, 2739 { 0x1f, 0xff, 0xff, 0xff } 2740}; 2741 2742static void qcom_qmp_phy_configure_dp_tx(struct qmp_phy *qphy) 2743{ 2744 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 2745 unsigned int v_level = 0, p_level = 0; 2746 u32 bias_en, drvr_en; 2747 u8 voltage_swing_cfg, pre_emphasis_cfg; 2748 int i; 2749 2750 for (i = 0; i < dp_opts->lanes; i++) { 2751 v_level = max(v_level, dp_opts->voltage[i]); 2752 p_level = max(p_level, dp_opts->pre[i]); 2753 } 2754 2755 if (dp_opts->lanes == 1) { 2756 bias_en = 0x3e; 2757 drvr_en = 0x13; 2758 } else { 2759 bias_en = 0x3f; 2760 drvr_en = 0x10; 2761 } 2762 2763 voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level]; 2764 pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level]; 2765 2766 /* TODO: Move check to config check */ 2767 if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) 2768 return; 2769 2770 /* Enable MUX to use Cursor values from these registers */ 2771 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; 2772 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; 2773 2774 writel(voltage_swing_cfg, qphy->tx + QSERDES_V3_TX_TX_DRV_LVL); 2775 writel(pre_emphasis_cfg, qphy->tx + QSERDES_V3_TX_TX_EMP_POST1_LVL); 2776 writel(voltage_swing_cfg, qphy->tx2 + QSERDES_V3_TX_TX_DRV_LVL); 2777 writel(pre_emphasis_cfg, qphy->tx2 + QSERDES_V3_TX_TX_EMP_POST1_LVL); 2778 2779 writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); 2780 writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 2781 writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); 2782 writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 2783} 2784 2785static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) 2786{ 2787 const struct phy_configure_opts_dp *dp_opts = &opts->dp; 2788 struct qmp_phy *qphy = phy_get_drvdata(phy); 2789 2790 memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); 2791 if (qphy->dp_opts.set_voltages) { 2792 qcom_qmp_phy_configure_dp_tx(qphy); 2793 qphy->dp_opts.set_voltages = 0; 2794 } 2795 2796 return 0; 2797} 2798 2799static int qcom_qmp_phy_configure_dp_phy(struct qmp_phy *qphy) 2800{ 2801 const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; 2802 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 2803 u32 val, phy_vco_div, status; 2804 unsigned long pixel_freq; 2805 2806 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2807 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; 2808 2809 /* 2810 * TODO: Assume orientation is CC1 for now and two lanes, need to 2811 * use type-c connector to understand orientation and lanes. 2812 * 2813 * Otherwise val changes to be like below if this code understood 2814 * the orientation of the type-c cable. 2815 * 2816 * if (lane_cnt == 4 || orientation == ORIENTATION_CC2) 2817 * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; 2818 * if (lane_cnt == 4 || orientation == ORIENTATION_CC1) 2819 * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; 2820 * if (orientation == ORIENTATION_CC2) 2821 * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); 2822 */ 2823 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; 2824 writel(val, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); 2825 2826 writel(0x5c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); 2827 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); 2828 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); 2829 2830 switch (dp_opts->link_rate) { 2831 case 1620: 2832 phy_vco_div = 0x1; 2833 pixel_freq = 1620000000UL / 2; 2834 break; 2835 case 2700: 2836 phy_vco_div = 0x1; 2837 pixel_freq = 2700000000UL / 2; 2838 break; 2839 case 5400: 2840 phy_vco_div = 0x2; 2841 pixel_freq = 5400000000UL / 4; 2842 break; 2843 case 8100: 2844 phy_vco_div = 0x0; 2845 pixel_freq = 8100000000UL / 6; 2846 break; 2847 default: 2848 /* Other link rates aren't supported */ 2849 return -EINVAL; 2850 } 2851 writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV); 2852 2853 clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); 2854 clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); 2855 2856 writel(0x04, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2); 2857 writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG); 2858 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_CFG); 2859 writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG); 2860 writel(0x09, qphy->pcs + QSERDES_V3_DP_PHY_CFG); 2861 2862 writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL); 2863 2864 if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS, 2865 status, 2866 ((status & BIT(0)) > 0), 2867 500, 2868 10000)) 2869 return -ETIMEDOUT; 2870 2871 writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG); 2872 2873 if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, 2874 status, 2875 ((status & BIT(1)) > 0), 2876 500, 2877 10000)) 2878 return -ETIMEDOUT; 2879 2880 writel(0x18, qphy->pcs + QSERDES_V3_DP_PHY_CFG); 2881 udelay(2000); 2882 writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG); 2883 2884 return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, 2885 status, 2886 ((status & BIT(1)) > 0), 2887 500, 2888 10000); 2889} 2890 2891/* 2892 * We need to calibrate the aux setting here as many times 2893 * as the caller tries 2894 */ 2895static int qcom_qmp_dp_phy_calibrate(struct phy *phy) 2896{ 2897 struct qmp_phy *qphy = phy_get_drvdata(phy); 2898 const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; 2899 u8 val; 2900 2901 qphy->dp_aux_cfg++; 2902 qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 2903 val = cfg1_settings[qphy->dp_aux_cfg]; 2904 2905 writel(val, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1); 2906 2907 return 0; 2908} 2909 2910static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) 2911{ 2912 struct qcom_qmp *qmp = qphy->qmp; 2913 const struct qmp_phy_cfg *cfg = qphy->cfg; 2914 void __iomem *serdes = qphy->serdes; 2915 void __iomem *pcs = qphy->pcs; 2916 void __iomem *dp_com = qmp->dp_com; 2917 int ret, i; 2918 2919 mutex_lock(&qmp->phy_mutex); 2920 if (qmp->init_count++) { 2921 mutex_unlock(&qmp->phy_mutex); 2922 return 0; 2923 } 2924 2925 /* turn on regulator supplies */ 2926 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 2927 if (ret) { 2928 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 2929 goto err_reg_enable; 2930 } 2931 2932 for (i = 0; i < cfg->num_resets; i++) { 2933 ret = reset_control_assert(qmp->resets[i]); 2934 if (ret) { 2935 dev_err(qmp->dev, "%s reset assert failed\n", 2936 cfg->reset_list[i]); 2937 goto err_rst_assert; 2938 } 2939 } 2940 2941 for (i = cfg->num_resets - 1; i >= 0; i--) { 2942 ret = reset_control_deassert(qmp->resets[i]); 2943 if (ret) { 2944 dev_err(qmp->dev, "%s reset deassert failed\n", 2945 qphy->cfg->reset_list[i]); 2946 goto err_rst; 2947 } 2948 } 2949 2950 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 2951 if (ret) { 2952 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret); 2953 goto err_rst; 2954 } 2955 2956 if (cfg->has_phy_dp_com_ctrl) { 2957 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, 2958 SW_PWRDN); 2959 /* override hardware control for reset of qmp phy */ 2960 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2961 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2962 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2963 2964 /* Default type-c orientation, i.e CC1 */ 2965 qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); 2966 2967 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, 2968 USB3_MODE | DP_MODE); 2969 2970 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 2971 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2972 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2973 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2974 2975 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 2976 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 2977 } 2978 2979 if (cfg->has_phy_com_ctrl) { 2980 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], 2981 SW_PWRDN); 2982 } else { 2983 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) 2984 qphy_setbits(pcs, 2985 cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2986 cfg->pwrdn_ctrl); 2987 else 2988 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, 2989 cfg->pwrdn_ctrl); 2990 } 2991 2992 mutex_unlock(&qmp->phy_mutex); 2993 2994 return 0; 2995 2996err_rst: 2997 while (++i < cfg->num_resets) 2998 reset_control_assert(qmp->resets[i]); 2999err_rst_assert: 3000 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 3001err_reg_enable: 3002 mutex_unlock(&qmp->phy_mutex); 3003 3004 return ret; 3005} 3006 3007static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy) 3008{ 3009 struct qcom_qmp *qmp = qphy->qmp; 3010 const struct qmp_phy_cfg *cfg = qphy->cfg; 3011 void __iomem *serdes = qphy->serdes; 3012 int i = cfg->num_resets; 3013 3014 mutex_lock(&qmp->phy_mutex); 3015 if (--qmp->init_count) { 3016 mutex_unlock(&qmp->phy_mutex); 3017 return 0; 3018 } 3019 3020 reset_control_assert(qmp->ufs_reset); 3021 if (cfg->has_phy_com_ctrl) { 3022 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], 3023 SERDES_START | PCS_START); 3024 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], 3025 SW_RESET); 3026 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], 3027 SW_PWRDN); 3028 } 3029 3030 while (--i >= 0) 3031 reset_control_assert(qmp->resets[i]); 3032 3033 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 3034 3035 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 3036 3037 mutex_unlock(&qmp->phy_mutex); 3038 3039 return 0; 3040} 3041 3042static int qcom_qmp_phy_init(struct phy *phy) 3043{ 3044 struct qmp_phy *qphy = phy_get_drvdata(phy); 3045 struct qcom_qmp *qmp = qphy->qmp; 3046 const struct qmp_phy_cfg *cfg = qphy->cfg; 3047 int ret; 3048 dev_vdbg(qmp->dev, "Initializing QMP phy\n"); 3049 3050 if (cfg->no_pcs_sw_reset) { 3051 /* 3052 * Get UFS reset, which is delayed until now to avoid a 3053 * circular dependency where UFS needs its PHY, but the PHY 3054 * needs this UFS reset. 3055 */ 3056 if (!qmp->ufs_reset) { 3057 qmp->ufs_reset = 3058 devm_reset_control_get_exclusive(qmp->dev, 3059 "ufsphy"); 3060 3061 if (IS_ERR(qmp->ufs_reset)) { 3062 ret = PTR_ERR(qmp->ufs_reset); 3063 dev_err(qmp->dev, 3064 "failed to get UFS reset: %d\n", 3065 ret); 3066 3067 qmp->ufs_reset = NULL; 3068 return ret; 3069 } 3070 } 3071 3072 ret = reset_control_assert(qmp->ufs_reset); 3073 if (ret) 3074 return ret; 3075 } 3076 3077 ret = qcom_qmp_phy_com_init(qphy); 3078 if (ret) 3079 return ret; 3080 3081 if (cfg->type == PHY_TYPE_DP) 3082 qcom_qmp_phy_dp_aux_init(qphy); 3083 3084 return 0; 3085} 3086 3087static int qcom_qmp_phy_power_on(struct phy *phy) 3088{ 3089 struct qmp_phy *qphy = phy_get_drvdata(phy); 3090 struct qcom_qmp *qmp = qphy->qmp; 3091 const struct qmp_phy_cfg *cfg = qphy->cfg; 3092 void __iomem *tx = qphy->tx; 3093 void __iomem *rx = qphy->rx; 3094 void __iomem *pcs = qphy->pcs; 3095 void __iomem *pcs_misc = qphy->pcs_misc; 3096 void __iomem *status; 3097 unsigned int mask, val, ready; 3098 int ret; 3099 3100 qcom_qmp_phy_serdes_init(qphy); 3101 3102 if (cfg->has_lane_rst) { 3103 ret = reset_control_deassert(qphy->lane_rst); 3104 if (ret) { 3105 dev_err(qmp->dev, "lane%d reset deassert failed\n", 3106 qphy->index); 3107 goto err_lane_rst; 3108 } 3109 } 3110 3111 ret = clk_prepare_enable(qphy->pipe_clk); 3112 if (ret) { 3113 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 3114 goto err_clk_enable; 3115 } 3116 3117 /* Tx, Rx, and PCS configurations */ 3118 qcom_qmp_phy_configure_lane(tx, cfg->regs, 3119 cfg->tx_tbl, cfg->tx_tbl_num, 1); 3120 /* Configuration for other LANE for USB-DP combo PHY */ 3121 if (cfg->is_dual_lane_phy) 3122 qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs, 3123 cfg->tx_tbl, cfg->tx_tbl_num, 2); 3124 3125 /* Configure special DP tx tunings */ 3126 if (cfg->type == PHY_TYPE_DP) 3127 qcom_qmp_phy_configure_dp_tx(qphy); 3128 3129 qcom_qmp_phy_configure_lane(rx, cfg->regs, 3130 cfg->rx_tbl, cfg->rx_tbl_num, 1); 3131 3132 if (cfg->is_dual_lane_phy) 3133 qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs, 3134 cfg->rx_tbl, cfg->rx_tbl_num, 2); 3135 3136 /* Configure link rate, swing, etc. */ 3137 if (cfg->type == PHY_TYPE_DP) 3138 qcom_qmp_phy_configure_dp_phy(qphy); 3139 else 3140 qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); 3141 3142 ret = reset_control_deassert(qmp->ufs_reset); 3143 if (ret) 3144 goto err_pcs_ready; 3145 3146 qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, 3147 cfg->pcs_misc_tbl_num); 3148 3149 /* 3150 * Pull out PHY from POWER DOWN state. 3151 * This is active low enable signal to power-down PHY. 3152 */ 3153 if(cfg->type == PHY_TYPE_PCIE) 3154 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); 3155 3156 if (cfg->has_pwrdn_delay) 3157 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 3158 3159 if (cfg->type != PHY_TYPE_DP) { 3160 /* Pull PHY out of reset state */ 3161 if (!cfg->no_pcs_sw_reset) 3162 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 3163 /* start SerDes and Phy-Coding-Sublayer */ 3164 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 3165 3166 if (cfg->type == PHY_TYPE_UFS) { 3167 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; 3168 mask = PCS_READY; 3169 ready = PCS_READY; 3170 } else { 3171 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 3172 mask = PHYSTATUS; 3173 ready = 0; 3174 } 3175 3176 ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, 3177 PHY_INIT_COMPLETE_TIMEOUT); 3178 if (ret) { 3179 dev_err(qmp->dev, "phy initialization timed-out\n"); 3180 goto err_pcs_ready; 3181 } 3182 } 3183 return 0; 3184 3185err_pcs_ready: 3186 clk_disable_unprepare(qphy->pipe_clk); 3187err_clk_enable: 3188 if (cfg->has_lane_rst) 3189 reset_control_assert(qphy->lane_rst); 3190err_lane_rst: 3191 return ret; 3192} 3193 3194static int qcom_qmp_phy_power_off(struct phy *phy) 3195{ 3196 struct qmp_phy *qphy = phy_get_drvdata(phy); 3197 const struct qmp_phy_cfg *cfg = qphy->cfg; 3198 3199 clk_disable_unprepare(qphy->pipe_clk); 3200 3201 if (cfg->type == PHY_TYPE_DP) { 3202 /* Assert DP PHY power down */ 3203 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); 3204 } else { 3205 /* PHY reset */ 3206 if (!cfg->no_pcs_sw_reset) 3207 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 3208 3209 /* stop SerDes and Phy-Coding-Sublayer */ 3210 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 3211 3212 /* Put PHY into POWER DOWN state: active low */ 3213 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { 3214 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 3215 cfg->pwrdn_ctrl); 3216 } else { 3217 qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, 3218 cfg->pwrdn_ctrl); 3219 } 3220 } 3221 3222 return 0; 3223} 3224 3225static int qcom_qmp_phy_exit(struct phy *phy) 3226{ 3227 struct qmp_phy *qphy = phy_get_drvdata(phy); 3228 const struct qmp_phy_cfg *cfg = qphy->cfg; 3229 3230 if (cfg->has_lane_rst) 3231 reset_control_assert(qphy->lane_rst); 3232 3233 qcom_qmp_phy_com_exit(qphy); 3234 3235 return 0; 3236} 3237 3238static int qcom_qmp_phy_enable(struct phy *phy) 3239{ 3240 int ret; 3241 3242 ret = qcom_qmp_phy_init(phy); 3243 if (ret) 3244 return ret; 3245 3246 ret = qcom_qmp_phy_power_on(phy); 3247 if (ret) 3248 qcom_qmp_phy_exit(phy); 3249 3250 return ret; 3251} 3252 3253static int qcom_qmp_phy_disable(struct phy *phy) 3254{ 3255 int ret; 3256 3257 ret = qcom_qmp_phy_power_off(phy); 3258 if (ret) 3259 return ret; 3260 return qcom_qmp_phy_exit(phy); 3261} 3262 3263static int qcom_qmp_phy_set_mode(struct phy *phy, 3264 enum phy_mode mode, int submode) 3265{ 3266 struct qmp_phy *qphy = phy_get_drvdata(phy); 3267 3268 qphy->mode = mode; 3269 3270 return 0; 3271} 3272 3273static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy) 3274{ 3275 const struct qmp_phy_cfg *cfg = qphy->cfg; 3276 void __iomem *pcs = qphy->pcs; 3277 void __iomem *pcs_misc = qphy->pcs_misc; 3278 u32 intr_mask; 3279 3280 if (qphy->mode == PHY_MODE_USB_HOST_SS || 3281 qphy->mode == PHY_MODE_USB_DEVICE_SS) 3282 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 3283 else 3284 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 3285 3286 /* Clear any pending interrupts status */ 3287 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 3288 /* Writing 1 followed by 0 clears the interrupt */ 3289 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 3290 3291 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 3292 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 3293 3294 /* Enable required PHY autonomous mode interrupts */ 3295 qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 3296 3297 /* Enable i/o clamp_n for autonomous mode */ 3298 if (pcs_misc) 3299 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 3300} 3301 3302static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy) 3303{ 3304 const struct qmp_phy_cfg *cfg = qphy->cfg; 3305 void __iomem *pcs = qphy->pcs; 3306 void __iomem *pcs_misc = qphy->pcs_misc; 3307 3308 /* Disable i/o clamp_n on resume for normal mode */ 3309 if (pcs_misc) 3310 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 3311 3312 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 3313 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 3314 3315 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 3316 /* Writing 1 followed by 0 clears the interrupt */ 3317 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 3318} 3319 3320static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) 3321{ 3322 struct qcom_qmp *qmp = dev_get_drvdata(dev); 3323 struct qmp_phy *qphy = qmp->phys[0]; 3324 const struct qmp_phy_cfg *cfg = qphy->cfg; 3325 3326 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); 3327 3328 /* Supported only for USB3 PHY and luckily USB3 is the first phy */ 3329 if (cfg->type != PHY_TYPE_USB3) 3330 return 0; 3331 3332 if (!qmp->init_count) { 3333 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 3334 return 0; 3335 } 3336 3337 qcom_qmp_phy_enable_autonomous_mode(qphy); 3338 3339 clk_disable_unprepare(qphy->pipe_clk); 3340 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 3341 3342 return 0; 3343} 3344 3345static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) 3346{ 3347 struct qcom_qmp *qmp = dev_get_drvdata(dev); 3348 struct qmp_phy *qphy = qmp->phys[0]; 3349 const struct qmp_phy_cfg *cfg = qphy->cfg; 3350 int ret = 0; 3351 3352 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); 3353 3354 /* Supported only for USB3 PHY and luckily USB3 is the first phy */ 3355 if (cfg->type != PHY_TYPE_USB3) 3356 return 0; 3357 3358 if (!qmp->init_count) { 3359 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 3360 return 0; 3361 } 3362 3363 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 3364 if (ret) { 3365 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret); 3366 return ret; 3367 } 3368 3369 ret = clk_prepare_enable(qphy->pipe_clk); 3370 if (ret) { 3371 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 3372 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 3373 return ret; 3374 } 3375 3376 qcom_qmp_phy_disable_autonomous_mode(qphy); 3377 3378 return 0; 3379} 3380 3381static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) 3382{ 3383 struct qcom_qmp *qmp = dev_get_drvdata(dev); 3384 int num = cfg->num_vregs; 3385 int i; 3386 3387 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 3388 if (!qmp->vregs) 3389 return -ENOMEM; 3390 3391 for (i = 0; i < num; i++) 3392 qmp->vregs[i].supply = cfg->vreg_list[i]; 3393 3394 return devm_regulator_bulk_get(dev, num, qmp->vregs); 3395} 3396 3397static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) 3398{ 3399 struct qcom_qmp *qmp = dev_get_drvdata(dev); 3400 int i; 3401 3402 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 3403 sizeof(*qmp->resets), GFP_KERNEL); 3404 if (!qmp->resets) 3405 return -ENOMEM; 3406 3407 for (i = 0; i < cfg->num_resets; i++) { 3408 struct reset_control *rst; 3409 const char *name = cfg->reset_list[i]; 3410 3411 rst = devm_reset_control_get(dev, name); 3412 if (IS_ERR(rst)) { 3413 dev_err(dev, "failed to get %s reset\n", name); 3414 return PTR_ERR(rst); 3415 } 3416 qmp->resets[i] = rst; 3417 } 3418 3419 return 0; 3420} 3421 3422static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) 3423{ 3424 struct qcom_qmp *qmp = dev_get_drvdata(dev); 3425 int num = cfg->num_clks; 3426 int i; 3427 3428 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 3429 if (!qmp->clks) 3430 return -ENOMEM; 3431 3432 for (i = 0; i < num; i++) 3433 qmp->clks[i].id = cfg->clk_list[i]; 3434 3435 return devm_clk_bulk_get(dev, num, qmp->clks); 3436} 3437 3438static void phy_clk_release_provider(void *res) 3439{ 3440 of_clk_del_provider(res); 3441} 3442 3443/* 3444 * Register a fixed rate pipe clock. 3445 * 3446 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 3447 * controls it. The <s>_pipe_clk coming out of the GCC is requested 3448 * by the PHY driver for its operations. 3449 * We register the <s>_pipe_clksrc here. The gcc driver takes care 3450 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 3451 * Below picture shows this relationship. 3452 * 3453 * +---------------+ 3454 * | PHY block |<<---------------------------------------+ 3455 * | | | 3456 * | +-------+ | +-----+ | 3457 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 3458 * clk | +-------+ | +-----+ 3459 * +---------------+ 3460 */ 3461static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) 3462{ 3463 struct clk_fixed_rate *fixed; 3464 struct clk_init_data init = { }; 3465 int ret; 3466 3467 ret = of_property_read_string(np, "clock-output-names", &init.name); 3468 if (ret) { 3469 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 3470 return ret; 3471 } 3472 3473 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); 3474 if (!fixed) 3475 return -ENOMEM; 3476 3477 init.ops = &clk_fixed_rate_ops; 3478 3479 /* controllers using QMP phys use 125MHz pipe clock interface */ 3480 fixed->fixed_rate = 125000000; 3481 fixed->hw.init = &init; 3482 3483 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 3484 if (ret) 3485 return ret; 3486 3487 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 3488 if (ret) 3489 return ret; 3490 3491 /* 3492 * Roll a devm action because the clock provider is the child node, but 3493 * the child node is not actually a device. 3494 */ 3495 ret = devm_add_action(qmp->dev, phy_clk_release_provider, np); 3496 if (ret) 3497 phy_clk_release_provider(np); 3498 3499 return ret; 3500} 3501 3502/* 3503 * Display Port PLL driver block diagram for branch clocks 3504 * 3505 * +------------------------------+ 3506 * | DP_VCO_CLK | 3507 * | | 3508 * | +-------------------+ | 3509 * | | (DP PLL/VCO) | | 3510 * | +---------+---------+ | 3511 * | v | 3512 * | +----------+-----------+ | 3513 * | | hsclk_divsel_clk_src | | 3514 * | +----------+-----------+ | 3515 * +------------------------------+ 3516 * | 3517 * +---------<---------v------------>----------+ 3518 * | | 3519 * +--------v----------------+ | 3520 * | dp_phy_pll_link_clk | | 3521 * | link_clk | | 3522 * +--------+----------------+ | 3523 * | | 3524 * | | 3525 * v v 3526 * Input to DISPCC block | 3527 * for link clk, crypto clk | 3528 * and interface clock | 3529 * | 3530 * | 3531 * +--------<------------+-----------------+---<---+ 3532 * | | | 3533 * +----v---------+ +--------v-----+ +--------v------+ 3534 * | vco_divided | | vco_divided | | vco_divided | 3535 * | _clk_src | | _clk_src | | _clk_src | 3536 * | | | | | | 3537 * |divsel_six | | divsel_two | | divsel_four | 3538 * +-------+------+ +-----+--------+ +--------+------+ 3539 * | | | 3540 * v---->----------v-------------<------v 3541 * | 3542 * +----------+-----------------+ 3543 * | dp_phy_pll_vco_div_clk | 3544 * +---------+------------------+ 3545 * | 3546 * v 3547 * Input to DISPCC block 3548 * for DP pixel clock 3549 * 3550 */ 3551static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, 3552 struct clk_rate_request *req) 3553{ 3554 switch (req->rate) { 3555 case 1620000000UL / 2: 3556 case 2700000000UL / 2: 3557 /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ 3558 return 0; 3559 default: 3560 return -EINVAL; 3561 } 3562} 3563 3564static unsigned long 3565qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 3566{ 3567 const struct qmp_phy_dp_clks *dp_clks; 3568 const struct qmp_phy *qphy; 3569 const struct phy_configure_opts_dp *dp_opts; 3570 3571 dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw); 3572 qphy = dp_clks->qphy; 3573 dp_opts = &qphy->dp_opts; 3574 3575 switch (dp_opts->link_rate) { 3576 case 1620: 3577 return 1620000000UL / 2; 3578 case 2700: 3579 return 2700000000UL / 2; 3580 case 5400: 3581 return 5400000000UL / 4; 3582 case 8100: 3583 return 8100000000UL / 6; 3584 default: 3585 return 0; 3586 } 3587} 3588 3589static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = { 3590 .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate, 3591 .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate, 3592}; 3593 3594static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw, 3595 struct clk_rate_request *req) 3596{ 3597 switch (req->rate) { 3598 case 162000000: 3599 case 270000000: 3600 case 540000000: 3601 case 810000000: 3602 return 0; 3603 default: 3604 return -EINVAL; 3605 } 3606} 3607 3608static unsigned long 3609qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 3610{ 3611 const struct qmp_phy_dp_clks *dp_clks; 3612 const struct qmp_phy *qphy; 3613 const struct phy_configure_opts_dp *dp_opts; 3614 3615 dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw); 3616 qphy = dp_clks->qphy; 3617 dp_opts = &qphy->dp_opts; 3618 3619 switch (dp_opts->link_rate) { 3620 case 1620: 3621 case 2700: 3622 case 5400: 3623 case 8100: 3624 return dp_opts->link_rate * 100000; 3625 default: 3626 return 0; 3627 } 3628} 3629 3630static const struct clk_ops qcom_qmp_dp_link_clk_ops = { 3631 .determine_rate = qcom_qmp_dp_link_clk_determine_rate, 3632 .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate, 3633}; 3634 3635static struct clk_hw * 3636qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) 3637{ 3638 struct qmp_phy_dp_clks *dp_clks = data; 3639 unsigned int idx = clkspec->args[0]; 3640 3641 if (idx >= 2) { 3642 pr_err("%s: invalid index %u\n", __func__, idx); 3643 return ERR_PTR(-EINVAL); 3644 } 3645 3646 if (idx == 0) 3647 return &dp_clks->dp_link_hw; 3648 3649 return &dp_clks->dp_pixel_hw; 3650} 3651 3652static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, 3653 struct device_node *np) 3654{ 3655 struct clk_init_data init = { }; 3656 struct qmp_phy_dp_clks *dp_clks; 3657 int ret; 3658 3659 dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL); 3660 if (!dp_clks) 3661 return -ENOMEM; 3662 3663 dp_clks->qphy = qphy; 3664 qphy->dp_clks = dp_clks; 3665 3666 init.ops = &qcom_qmp_dp_link_clk_ops; 3667 init.name = "qmp_dp_phy_pll_link_clk"; 3668 dp_clks->dp_link_hw.init = &init; 3669 ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw); 3670 if (ret) 3671 return ret; 3672 3673 init.ops = &qcom_qmp_dp_pixel_clk_ops; 3674 init.name = "qmp_dp_phy_pll_vco_div_clk"; 3675 dp_clks->dp_pixel_hw.init = &init; 3676 ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw); 3677 if (ret) 3678 return ret; 3679 3680 ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks); 3681 if (ret) 3682 return ret; 3683 3684 /* 3685 * Roll a devm action because the clock provider is the child node, but 3686 * the child node is not actually a device. 3687 */ 3688 ret = devm_add_action(qmp->dev, phy_clk_release_provider, np); 3689 if (ret) 3690 phy_clk_release_provider(np); 3691 3692 return ret; 3693} 3694 3695static const struct phy_ops qcom_qmp_phy_gen_ops = { 3696 .init = qcom_qmp_phy_enable, 3697 .exit = qcom_qmp_phy_disable, 3698 .set_mode = qcom_qmp_phy_set_mode, 3699 .owner = THIS_MODULE, 3700}; 3701 3702static const struct phy_ops qcom_qmp_phy_dp_ops = { 3703 .init = qcom_qmp_phy_init, 3704 .configure = qcom_qmp_dp_phy_configure, 3705 .power_on = qcom_qmp_phy_power_on, 3706 .calibrate = qcom_qmp_dp_phy_calibrate, 3707 .power_off = qcom_qmp_phy_power_off, 3708 .exit = qcom_qmp_phy_exit, 3709 .set_mode = qcom_qmp_phy_set_mode, 3710 .owner = THIS_MODULE, 3711}; 3712 3713static const struct phy_ops qcom_qmp_pcie_ufs_ops = { 3714 .power_on = qcom_qmp_phy_enable, 3715 .power_off = qcom_qmp_phy_disable, 3716 .set_mode = qcom_qmp_phy_set_mode, 3717 .owner = THIS_MODULE, 3718}; 3719 3720static void qcom_qmp_reset_control_put(void *data) 3721{ 3722 reset_control_put(data); 3723} 3724 3725static 3726int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, 3727 void __iomem *serdes, const struct qmp_phy_cfg *cfg) 3728{ 3729 struct qcom_qmp *qmp = dev_get_drvdata(dev); 3730 struct phy *generic_phy; 3731 struct qmp_phy *qphy; 3732 const struct phy_ops *ops; 3733 char prop_name[MAX_PROP_NAME]; 3734 int ret; 3735 3736 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 3737 if (!qphy) 3738 return -ENOMEM; 3739 3740 qphy->cfg = cfg; 3741 qphy->serdes = serdes; 3742 /* 3743 * Get memory resources for each phy lane: 3744 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 3745 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 3746 * For single lane PHYs: pcs_misc (optional) -> 3. 3747 */ 3748 qphy->tx = of_iomap(np, 0); 3749 if (!qphy->tx) 3750 return -ENOMEM; 3751 3752 qphy->rx = of_iomap(np, 1); 3753 if (!qphy->rx) 3754 return -ENOMEM; 3755 3756 qphy->pcs = of_iomap(np, 2); 3757 if (!qphy->pcs) 3758 return -ENOMEM; 3759 3760 /* 3761 * If this is a dual-lane PHY, then there should be registers for the 3762 * second lane. Some old device trees did not specify this, so fall 3763 * back to old legacy behavior of assuming they can be reached at an 3764 * offset from the first lane. 3765 */ 3766 if (cfg->is_dual_lane_phy) { 3767 qphy->tx2 = of_iomap(np, 3); 3768 qphy->rx2 = of_iomap(np, 4); 3769 if (!qphy->tx2 || !qphy->rx2) { 3770 dev_warn(dev, 3771 "Underspecified device tree, falling back to legacy register regions\n"); 3772 3773 /* In the old version, pcs_misc is at index 3. */ 3774 qphy->pcs_misc = qphy->tx2; 3775 qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; 3776 qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; 3777 3778 } else { 3779 qphy->pcs_misc = of_iomap(np, 5); 3780 } 3781 3782 } else { 3783 qphy->pcs_misc = of_iomap(np, 3); 3784 } 3785 3786 if (!qphy->pcs_misc) 3787 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 3788 3789 /* 3790 * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3 3791 * based phys, so they essentially have pipe clock. So, 3792 * we return error in case phy is USB3 or PIPE type. 3793 * Otherwise, we initialize pipe clock to NULL for 3794 * all phys that don't need this. 3795 */ 3796 snprintf(prop_name, sizeof(prop_name), "pipe%d", id); 3797 qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); 3798 if (IS_ERR(qphy->pipe_clk)) { 3799 if (cfg->type == PHY_TYPE_PCIE || 3800 cfg->type == PHY_TYPE_USB3) { 3801 ret = PTR_ERR(qphy->pipe_clk); 3802 if (ret != -EPROBE_DEFER) 3803 dev_err(dev, 3804 "failed to get lane%d pipe_clk, %d\n", 3805 id, ret); 3806 return ret; 3807 } 3808 qphy->pipe_clk = NULL; 3809 } 3810 3811 /* Get lane reset, if any */ 3812 if (cfg->has_lane_rst) { 3813 snprintf(prop_name, sizeof(prop_name), "lane%d", id); 3814 qphy->lane_rst = of_reset_control_get(np, prop_name); 3815 if (IS_ERR(qphy->lane_rst)) { 3816 dev_err(dev, "failed to get lane%d reset\n", id); 3817 return PTR_ERR(qphy->lane_rst); 3818 } 3819 ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put, 3820 qphy->lane_rst); 3821 if (ret) 3822 return ret; 3823 } 3824 3825 if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE) 3826 ops = &qcom_qmp_pcie_ufs_ops; 3827 else if (cfg->type == PHY_TYPE_DP) 3828 ops = &qcom_qmp_phy_dp_ops; 3829 else 3830 ops = &qcom_qmp_phy_gen_ops; 3831 3832 generic_phy = devm_phy_create(dev, np, ops); 3833 if (IS_ERR(generic_phy)) { 3834 ret = PTR_ERR(generic_phy); 3835 dev_err(dev, "failed to create qphy %d\n", ret); 3836 return ret; 3837 } 3838 3839 qphy->phy = generic_phy; 3840 qphy->index = id; 3841 qphy->qmp = qmp; 3842 qmp->phys[id] = qphy; 3843 phy_set_drvdata(generic_phy, qphy); 3844 3845 return 0; 3846} 3847 3848static const struct of_device_id qcom_qmp_phy_of_match_table[] = { 3849 { 3850 .compatible = "qcom,ipq8074-qmp-usb3-phy", 3851 .data = &ipq8074_usb3phy_cfg, 3852 }, { 3853 .compatible = "qcom,msm8996-qmp-pcie-phy", 3854 .data = &msm8996_pciephy_cfg, 3855 }, { 3856 .compatible = "qcom,msm8996-qmp-ufs-phy", 3857 .data = &msm8996_ufs_cfg, 3858 }, { 3859 .compatible = "qcom,msm8996-qmp-usb3-phy", 3860 .data = &msm8996_usb3phy_cfg, 3861 }, { 3862 .compatible = "qcom,msm8998-qmp-pcie-phy", 3863 .data = &msm8998_pciephy_cfg, 3864 }, { 3865 .compatible = "qcom,msm8998-qmp-ufs-phy", 3866 .data = &sdm845_ufsphy_cfg, 3867 }, { 3868 .compatible = "qcom,ipq8074-qmp-pcie-phy", 3869 .data = &ipq8074_pciephy_cfg, 3870 }, { 3871 .compatible = "qcom,sc7180-qmp-usb3-phy", 3872 .data = &sc7180_usb3phy_cfg, 3873 }, { 3874 .compatible = "qcom,sc7180-qmp-usb3-dp-phy", 3875 /* It's a combo phy */ 3876 }, { 3877 .compatible = "qcom,sdm845-qhp-pcie-phy", 3878 .data = &sdm845_qhp_pciephy_cfg, 3879 }, { 3880 .compatible = "qcom,sdm845-qmp-pcie-phy", 3881 .data = &sdm845_qmp_pciephy_cfg, 3882 }, { 3883 .compatible = "qcom,sdm845-qmp-usb3-phy", 3884 .data = &qmp_v3_usb3phy_cfg, 3885 }, { 3886 .compatible = "qcom,sdm845-qmp-usb3-uni-phy", 3887 .data = &qmp_v3_usb3_uniphy_cfg, 3888 }, { 3889 .compatible = "qcom,sdm845-qmp-ufs-phy", 3890 .data = &sdm845_ufsphy_cfg, 3891 }, { 3892 .compatible = "qcom,msm8998-qmp-usb3-phy", 3893 .data = &msm8998_usb3phy_cfg, 3894 }, { 3895 .compatible = "qcom,sm8150-qmp-ufs-phy", 3896 .data = &sm8150_ufsphy_cfg, 3897 }, { 3898 .compatible = "qcom,sm8250-qmp-ufs-phy", 3899 .data = &sm8150_ufsphy_cfg, 3900 }, { 3901 .compatible = "qcom,sm8150-qmp-usb3-phy", 3902 .data = &sm8150_usb3phy_cfg, 3903 }, { 3904 .compatible = "qcom,sm8150-qmp-usb3-uni-phy", 3905 .data = &sm8150_usb3_uniphy_cfg, 3906 }, { 3907 .compatible = "qcom,sm8250-qmp-usb3-phy", 3908 .data = &sm8250_usb3phy_cfg, 3909 }, { 3910 .compatible = "qcom,sm8250-qmp-usb3-uni-phy", 3911 .data = &sm8250_usb3_uniphy_cfg, 3912 }, 3913 { }, 3914}; 3915MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table); 3916 3917static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = { 3918 { 3919 .compatible = "qcom,sc7180-qmp-usb3-dp-phy", 3920 .data = &sc7180_usb3dpphy_cfg, 3921 }, 3922 { } 3923}; 3924 3925static const struct dev_pm_ops qcom_qmp_phy_pm_ops = { 3926 SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend, 3927 qcom_qmp_phy_runtime_resume, NULL) 3928}; 3929 3930static int qcom_qmp_phy_probe(struct platform_device *pdev) 3931{ 3932 struct qcom_qmp *qmp; 3933 struct device *dev = &pdev->dev; 3934 struct device_node *child; 3935 struct phy_provider *phy_provider; 3936 void __iomem *serdes; 3937 void __iomem *usb_serdes; 3938 void __iomem *dp_serdes = NULL; 3939 const struct qmp_phy_combo_cfg *combo_cfg = NULL; 3940 const struct qmp_phy_cfg *cfg = NULL; 3941 const struct qmp_phy_cfg *usb_cfg = NULL; 3942 const struct qmp_phy_cfg *dp_cfg = NULL; 3943 int num, id, expected_phys; 3944 int ret; 3945 3946 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 3947 if (!qmp) 3948 return -ENOMEM; 3949 3950 qmp->dev = dev; 3951 dev_set_drvdata(dev, qmp); 3952 3953 /* Get the specific init parameters of QMP phy */ 3954 cfg = of_device_get_match_data(dev); 3955 if (!cfg) { 3956 const struct of_device_id *match; 3957 3958 match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev); 3959 if (!match) 3960 return -EINVAL; 3961 3962 combo_cfg = match->data; 3963 if (!combo_cfg) 3964 return -EINVAL; 3965 3966 usb_cfg = combo_cfg->usb_cfg; 3967 cfg = usb_cfg; /* Setup clks and regulators */ 3968 } 3969 3970 /* per PHY serdes; usually located at base address */ 3971 usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0); 3972 if (IS_ERR(serdes)) 3973 return PTR_ERR(serdes); 3974 3975 /* per PHY dp_com; if PHY has dp_com control block */ 3976 if (combo_cfg || cfg->has_phy_dp_com_ctrl) { 3977 qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); 3978 if (IS_ERR(qmp->dp_com)) 3979 return PTR_ERR(qmp->dp_com); 3980 } 3981 3982 if (combo_cfg) { 3983 /* Only two serdes for combo PHY */ 3984 dp_serdes = devm_platform_ioremap_resource(pdev, 2); 3985 if (IS_ERR(dp_serdes)) 3986 return PTR_ERR(dp_serdes); 3987 3988 dp_cfg = combo_cfg->dp_cfg; 3989 expected_phys = 2; 3990 } else { 3991 expected_phys = cfg->nlanes; 3992 } 3993 3994 mutex_init(&qmp->phy_mutex); 3995 3996 ret = qcom_qmp_phy_clk_init(dev, cfg); 3997 if (ret) 3998 return ret; 3999 4000 ret = qcom_qmp_phy_reset_init(dev, cfg); 4001 if (ret) 4002 return ret; 4003 4004 ret = qcom_qmp_phy_vreg_init(dev, cfg); 4005 if (ret) { 4006 if (ret != -EPROBE_DEFER) 4007 dev_err(dev, "failed to get regulator supplies: %d\n", 4008 ret); 4009 return ret; 4010 } 4011 4012 num = of_get_available_child_count(dev->of_node); 4013 /* do we have a rogue child node ? */ 4014 if (num > expected_phys) 4015 return -EINVAL; 4016 4017 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); 4018 if (!qmp->phys) 4019 return -ENOMEM; 4020 4021 pm_runtime_set_active(dev); 4022 pm_runtime_enable(dev); 4023 /* 4024 * Prevent runtime pm from being ON by default. Users can enable 4025 * it using power/control in sysfs. 4026 */ 4027 pm_runtime_forbid(dev); 4028 4029 id = 0; 4030 for_each_available_child_of_node(dev->of_node, child) { 4031 if (of_node_name_eq(child, "dp-phy")) { 4032 cfg = dp_cfg; 4033 serdes = dp_serdes; 4034 } else if (of_node_name_eq(child, "usb3-phy")) { 4035 cfg = usb_cfg; 4036 serdes = usb_serdes; 4037 } 4038 4039 /* Create per-lane phy */ 4040 ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg); 4041 if (ret) { 4042 dev_err(dev, "failed to create lane%d phy, %d\n", 4043 id, ret); 4044 goto err_node_put; 4045 } 4046 4047 /* 4048 * Register the pipe clock provided by phy. 4049 * See function description to see details of this pipe clock. 4050 */ 4051 if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) { 4052 ret = phy_pipe_clk_register(qmp, child); 4053 if (ret) { 4054 dev_err(qmp->dev, 4055 "failed to register pipe clock source\n"); 4056 goto err_node_put; 4057 } 4058 } else if (cfg->type == PHY_TYPE_DP) { 4059 ret = phy_dp_clks_register(qmp, qmp->phys[id], child); 4060 if (ret) { 4061 dev_err(qmp->dev, 4062 "failed to register DP clock source\n"); 4063 goto err_node_put; 4064 } 4065 } 4066 id++; 4067 } 4068 4069 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 4070 if (!IS_ERR(phy_provider)) 4071 dev_info(dev, "Registered Qcom-QMP phy\n"); 4072 else 4073 pm_runtime_disable(dev); 4074 4075 return PTR_ERR_OR_ZERO(phy_provider); 4076 4077err_node_put: 4078 pm_runtime_disable(dev); 4079 of_node_put(child); 4080 return ret; 4081} 4082 4083static struct platform_driver qcom_qmp_phy_driver = { 4084 .probe = qcom_qmp_phy_probe, 4085 .driver = { 4086 .name = "qcom-qmp-phy", 4087 .pm = &qcom_qmp_phy_pm_ops, 4088 .of_match_table = qcom_qmp_phy_of_match_table, 4089 }, 4090}; 4091 4092module_platform_driver(qcom_qmp_phy_driver); 4093 4094MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 4095MODULE_DESCRIPTION("Qualcomm QMP PHY driver"); 4096MODULE_LICENSE("GPL v2"); 4097