1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Chunhui Dai <chunhui.dai@mediatek.com>
5 */
6
7#ifndef _MTK_HDMI_PHY_H
8#define _MTK_HDMI_PHY_H
9#include <linux/clk.h>
10#include <linux/clk-provider.h>
11#include <linux/delay.h>
12#include <linux/io.h>
13#include <linux/mfd/syscon.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/phy/phy.h>
17#include <linux/platform_device.h>
18#include <linux/types.h>
19
20struct mtk_hdmi_phy;
21
22struct mtk_hdmi_phy_conf {
23	unsigned long flags;
24	bool pll_default_off;
25	const struct clk_ops *hdmi_phy_clk_ops;
26	void (*hdmi_phy_enable_tmds)(struct mtk_hdmi_phy *hdmi_phy);
27	void (*hdmi_phy_disable_tmds)(struct mtk_hdmi_phy *hdmi_phy);
28};
29
30struct mtk_hdmi_phy {
31	void __iomem *regs;
32	struct device *dev;
33	struct mtk_hdmi_phy_conf *conf;
34	struct clk *pll;
35	struct clk_hw pll_hw;
36	unsigned long pll_rate;
37	unsigned char drv_imp_clk;
38	unsigned char drv_imp_d2;
39	unsigned char drv_imp_d1;
40	unsigned char drv_imp_d0;
41	unsigned int ibias;
42	unsigned int ibias_up;
43};
44
45void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
46			     u32 bits);
47void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
48			   u32 bits);
49void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
50		       u32 val, u32 mask);
51struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw);
52
53extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
54extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf;
55
56#endif /* _MTK_HDMI_PHY_H */
57