1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Cadence Sierra PHY Driver 4 * 5 * Copyright (c) 2018 Cadence Design Systems 6 * Author: Alan Douglas <adouglas@cadence.com> 7 * 8 */ 9#include <linux/clk.h> 10#include <linux/delay.h> 11#include <linux/err.h> 12#include <linux/io.h> 13#include <linux/module.h> 14#include <linux/phy/phy.h> 15#include <linux/platform_device.h> 16#include <linux/pm_runtime.h> 17#include <linux/regmap.h> 18#include <linux/reset.h> 19#include <linux/slab.h> 20#include <linux/of.h> 21#include <linux/of_platform.h> 22#include <dt-bindings/phy/phy.h> 23 24/* PHY register offsets */ 25#define SIERRA_COMMON_CDB_OFFSET 0x0 26#define SIERRA_MACRO_ID_REG 0x0 27#define SIERRA_CMN_PLLLC_MODE_PREG 0x48 28#define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49 29#define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A 30#define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG 0x4B 31#define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F 32#define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50 33#define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62 34 35#define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 36 ((0x4000 << (block_offset)) + \ 37 (((ln) << 9) << (reg_offset))) 38 39#define SIERRA_DET_STANDEC_A_PREG 0x000 40#define SIERRA_DET_STANDEC_B_PREG 0x001 41#define SIERRA_DET_STANDEC_C_PREG 0x002 42#define SIERRA_DET_STANDEC_D_PREG 0x003 43#define SIERRA_DET_STANDEC_E_PREG 0x004 44#define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG 0x008 45#define SIERRA_PSM_A0IN_TMR_PREG 0x009 46#define SIERRA_PSM_DIAG_PREG 0x015 47#define SIERRA_PSC_TX_A0_PREG 0x028 48#define SIERRA_PSC_TX_A1_PREG 0x029 49#define SIERRA_PSC_TX_A2_PREG 0x02A 50#define SIERRA_PSC_TX_A3_PREG 0x02B 51#define SIERRA_PSC_RX_A0_PREG 0x030 52#define SIERRA_PSC_RX_A1_PREG 0x031 53#define SIERRA_PSC_RX_A2_PREG 0x032 54#define SIERRA_PSC_RX_A3_PREG 0x033 55#define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A 56#define SIERRA_PLLCTRL_GEN_D_PREG 0x03E 57#define SIERRA_PLLCTRL_CPGAIN_MODE_PREG 0x03F 58#define SIERRA_PLLCTRL_STATUS_PREG 0x044 59#define SIERRA_CLKPATH_BIASTRIM_PREG 0x04B 60#define SIERRA_DFE_BIASTRIM_PREG 0x04C 61#define SIERRA_DRVCTRL_ATTEN_PREG 0x06A 62#define SIERRA_CLKPATHCTRL_TMR_PREG 0x081 63#define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG 0x085 64#define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG 0x086 65#define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG 0x087 66#define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG 0x088 67#define SIERRA_CREQ_CCLKDET_MODE01_PREG 0x08E 68#define SIERRA_RX_CTLE_MAINTENANCE_PREG 0x091 69#define SIERRA_CREQ_FSMCLK_SEL_PREG 0x092 70#define SIERRA_CREQ_EQ_CTRL_PREG 0x093 71#define SIERRA_CREQ_SPARE_PREG 0x096 72#define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG 0x097 73#define SIERRA_CTLELUT_CTRL_PREG 0x098 74#define SIERRA_DFE_ECMP_RATESEL_PREG 0x0C0 75#define SIERRA_DFE_SMP_RATESEL_PREG 0x0C1 76#define SIERRA_DEQ_PHALIGN_CTRL 0x0C4 77#define SIERRA_DEQ_CONCUR_CTRL1_PREG 0x0C8 78#define SIERRA_DEQ_CONCUR_CTRL2_PREG 0x0C9 79#define SIERRA_DEQ_EPIPWR_CTRL2_PREG 0x0CD 80#define SIERRA_DEQ_FAST_MAINT_CYCLES_PREG 0x0CE 81#define SIERRA_DEQ_ERRCMP_CTRL_PREG 0x0D0 82#define SIERRA_DEQ_OFFSET_CTRL_PREG 0x0D8 83#define SIERRA_DEQ_GAIN_CTRL_PREG 0x0E0 84#define SIERRA_DEQ_VGATUNE_CTRL_PREG 0x0E1 85#define SIERRA_DEQ_GLUT0 0x0E8 86#define SIERRA_DEQ_GLUT1 0x0E9 87#define SIERRA_DEQ_GLUT2 0x0EA 88#define SIERRA_DEQ_GLUT3 0x0EB 89#define SIERRA_DEQ_GLUT4 0x0EC 90#define SIERRA_DEQ_GLUT5 0x0ED 91#define SIERRA_DEQ_GLUT6 0x0EE 92#define SIERRA_DEQ_GLUT7 0x0EF 93#define SIERRA_DEQ_GLUT8 0x0F0 94#define SIERRA_DEQ_GLUT9 0x0F1 95#define SIERRA_DEQ_GLUT10 0x0F2 96#define SIERRA_DEQ_GLUT11 0x0F3 97#define SIERRA_DEQ_GLUT12 0x0F4 98#define SIERRA_DEQ_GLUT13 0x0F5 99#define SIERRA_DEQ_GLUT14 0x0F6 100#define SIERRA_DEQ_GLUT15 0x0F7 101#define SIERRA_DEQ_GLUT16 0x0F8 102#define SIERRA_DEQ_ALUT0 0x108 103#define SIERRA_DEQ_ALUT1 0x109 104#define SIERRA_DEQ_ALUT2 0x10A 105#define SIERRA_DEQ_ALUT3 0x10B 106#define SIERRA_DEQ_ALUT4 0x10C 107#define SIERRA_DEQ_ALUT5 0x10D 108#define SIERRA_DEQ_ALUT6 0x10E 109#define SIERRA_DEQ_ALUT7 0x10F 110#define SIERRA_DEQ_ALUT8 0x110 111#define SIERRA_DEQ_ALUT9 0x111 112#define SIERRA_DEQ_ALUT10 0x112 113#define SIERRA_DEQ_ALUT11 0x113 114#define SIERRA_DEQ_ALUT12 0x114 115#define SIERRA_DEQ_ALUT13 0x115 116#define SIERRA_DEQ_DFETAP_CTRL_PREG 0x128 117#define SIERRA_DFE_EN_1010_IGNORE_PREG 0x134 118#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 119#define SIERRA_DEQ_TAU_CTRL2_PREG 0x151 120#define SIERRA_DEQ_PICTRL_PREG 0x161 121#define SIERRA_CPICAL_TMRVAL_MODE1_PREG 0x170 122#define SIERRA_CPICAL_TMRVAL_MODE0_PREG 0x171 123#define SIERRA_CPICAL_PICNT_MODE1_PREG 0x174 124#define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C 125#define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG 0x183 126#define SIERRA_LFPSDET_SUPPORT_PREG 0x188 127#define SIERRA_LFPSFILT_NS_PREG 0x18A 128#define SIERRA_LFPSFILT_RD_PREG 0x18B 129#define SIERRA_LFPSFILT_MP_PREG 0x18C 130#define SIERRA_SIGDET_SUPPORT_PREG 0x190 131#define SIERRA_SDFILT_H2L_A_PREG 0x191 132#define SIERRA_SDFILT_L2H_PREG 0x193 133#define SIERRA_RXBUFFER_CTLECTRL_PREG 0x19E 134#define SIERRA_RXBUFFER_RCDFECTRL_PREG 0x19F 135#define SIERRA_RXBUFFER_DFECTRL_PREG 0x1A0 136#define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG 0x14F 137#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 138 139#define SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset) \ 140 (0xc000 << (block_offset)) 141#define SIERRA_PHY_PLL_CFG 0xe 142 143#define SIERRA_MACRO_ID 0x00007364 144#define SIERRA_MAX_LANES 16 145#define PLL_LOCK_TIME 100000 146 147static const struct reg_field macro_id_type = 148 REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15); 149static const struct reg_field phy_pll_cfg_1 = 150 REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1); 151static const struct reg_field pllctrl_lock = 152 REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0); 153 154struct cdns_sierra_inst { 155 struct phy *phy; 156 u32 phy_type; 157 u32 num_lanes; 158 u32 mlane; 159 struct reset_control *lnk_rst; 160}; 161 162struct cdns_reg_pairs { 163 u16 val; 164 u32 off; 165}; 166 167struct cdns_sierra_data { 168 u32 id_value; 169 u8 block_offset_shift; 170 u8 reg_offset_shift; 171 u32 pcie_cmn_regs; 172 u32 pcie_ln_regs; 173 u32 usb_cmn_regs; 174 u32 usb_ln_regs; 175 const struct cdns_reg_pairs *pcie_cmn_vals; 176 const struct cdns_reg_pairs *pcie_ln_vals; 177 const struct cdns_reg_pairs *usb_cmn_vals; 178 const struct cdns_reg_pairs *usb_ln_vals; 179}; 180 181struct cdns_regmap_cdb_context { 182 struct device *dev; 183 void __iomem *base; 184 u8 reg_offset_shift; 185}; 186 187struct cdns_sierra_phy { 188 struct device *dev; 189 struct regmap *regmap; 190 struct cdns_sierra_data *init_data; 191 struct cdns_sierra_inst phys[SIERRA_MAX_LANES]; 192 struct reset_control *phy_rst; 193 struct reset_control *apb_rst; 194 struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES]; 195 struct regmap *regmap_phy_config_ctrl; 196 struct regmap *regmap_common_cdb; 197 struct regmap_field *macro_id_type; 198 struct regmap_field *phy_pll_cfg_1; 199 struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; 200 struct clk *clk; 201 struct clk *cmn_refclk_dig_div; 202 struct clk *cmn_refclk1_dig_div; 203 int nsubnodes; 204 u32 num_lanes; 205 bool autoconf; 206}; 207 208static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val) 209{ 210 struct cdns_regmap_cdb_context *ctx = context; 211 u32 offset = reg << ctx->reg_offset_shift; 212 213 writew(val, ctx->base + offset); 214 215 return 0; 216} 217 218static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val) 219{ 220 struct cdns_regmap_cdb_context *ctx = context; 221 u32 offset = reg << ctx->reg_offset_shift; 222 223 *val = readw(ctx->base + offset); 224 return 0; 225} 226 227#define SIERRA_LANE_CDB_REGMAP_CONF(n) \ 228{ \ 229 .name = "sierra_lane" n "_cdb", \ 230 .reg_stride = 1, \ 231 .fast_io = true, \ 232 .reg_write = cdns_regmap_write, \ 233 .reg_read = cdns_regmap_read, \ 234} 235 236static const struct regmap_config cdns_sierra_lane_cdb_config[] = { 237 SIERRA_LANE_CDB_REGMAP_CONF("0"), 238 SIERRA_LANE_CDB_REGMAP_CONF("1"), 239 SIERRA_LANE_CDB_REGMAP_CONF("2"), 240 SIERRA_LANE_CDB_REGMAP_CONF("3"), 241 SIERRA_LANE_CDB_REGMAP_CONF("4"), 242 SIERRA_LANE_CDB_REGMAP_CONF("5"), 243 SIERRA_LANE_CDB_REGMAP_CONF("6"), 244 SIERRA_LANE_CDB_REGMAP_CONF("7"), 245 SIERRA_LANE_CDB_REGMAP_CONF("8"), 246 SIERRA_LANE_CDB_REGMAP_CONF("9"), 247 SIERRA_LANE_CDB_REGMAP_CONF("10"), 248 SIERRA_LANE_CDB_REGMAP_CONF("11"), 249 SIERRA_LANE_CDB_REGMAP_CONF("12"), 250 SIERRA_LANE_CDB_REGMAP_CONF("13"), 251 SIERRA_LANE_CDB_REGMAP_CONF("14"), 252 SIERRA_LANE_CDB_REGMAP_CONF("15"), 253}; 254 255static const struct regmap_config cdns_sierra_common_cdb_config = { 256 .name = "sierra_common_cdb", 257 .reg_stride = 1, 258 .fast_io = true, 259 .reg_write = cdns_regmap_write, 260 .reg_read = cdns_regmap_read, 261}; 262 263static const struct regmap_config cdns_sierra_phy_config_ctrl_config = { 264 .name = "sierra_phy_config_ctrl", 265 .reg_stride = 1, 266 .fast_io = true, 267 .reg_write = cdns_regmap_write, 268 .reg_read = cdns_regmap_read, 269}; 270 271static int cdns_sierra_phy_init(struct phy *gphy) 272{ 273 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 274 struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent); 275 struct regmap *regmap; 276 int i, j; 277 const struct cdns_reg_pairs *cmn_vals, *ln_vals; 278 u32 num_cmn_regs, num_ln_regs; 279 280 /* Initialise the PHY registers, unless auto configured */ 281 if (phy->autoconf) 282 return 0; 283 284 clk_set_rate(phy->cmn_refclk_dig_div, 25000000); 285 clk_set_rate(phy->cmn_refclk1_dig_div, 25000000); 286 if (ins->phy_type == PHY_TYPE_PCIE) { 287 num_cmn_regs = phy->init_data->pcie_cmn_regs; 288 num_ln_regs = phy->init_data->pcie_ln_regs; 289 cmn_vals = phy->init_data->pcie_cmn_vals; 290 ln_vals = phy->init_data->pcie_ln_vals; 291 } else if (ins->phy_type == PHY_TYPE_USB3) { 292 num_cmn_regs = phy->init_data->usb_cmn_regs; 293 num_ln_regs = phy->init_data->usb_ln_regs; 294 cmn_vals = phy->init_data->usb_cmn_vals; 295 ln_vals = phy->init_data->usb_ln_vals; 296 } else { 297 return -EINVAL; 298 } 299 300 regmap = phy->regmap_common_cdb; 301 for (j = 0; j < num_cmn_regs ; j++) 302 regmap_write(regmap, cmn_vals[j].off, cmn_vals[j].val); 303 304 for (i = 0; i < ins->num_lanes; i++) { 305 for (j = 0; j < num_ln_regs ; j++) { 306 regmap = phy->regmap_lane_cdb[i + ins->mlane]; 307 regmap_write(regmap, ln_vals[j].off, ln_vals[j].val); 308 } 309 } 310 311 return 0; 312} 313 314static int cdns_sierra_phy_on(struct phy *gphy) 315{ 316 struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent); 317 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 318 struct device *dev = sp->dev; 319 u32 val; 320 int ret; 321 322 ret = reset_control_deassert(sp->phy_rst); 323 if (ret) { 324 dev_err(dev, "Failed to take the PHY out of reset\n"); 325 return ret; 326 } 327 328 /* Take the PHY lane group out of reset */ 329 ret = reset_control_deassert(ins->lnk_rst); 330 if (ret) { 331 dev_err(dev, "Failed to take the PHY lane out of reset\n"); 332 return ret; 333 } 334 335 ret = regmap_field_read_poll_timeout(sp->pllctrl_lock[ins->mlane], 336 val, val, 1000, PLL_LOCK_TIME); 337 if (ret < 0) 338 dev_err(dev, "PLL lock of lane failed\n"); 339 340 return ret; 341} 342 343static int cdns_sierra_phy_off(struct phy *gphy) 344{ 345 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 346 347 return reset_control_assert(ins->lnk_rst); 348} 349 350static int cdns_sierra_phy_reset(struct phy *gphy) 351{ 352 struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent); 353 354 reset_control_assert(sp->phy_rst); 355 reset_control_deassert(sp->phy_rst); 356 return 0; 357}; 358 359static const struct phy_ops ops = { 360 .init = cdns_sierra_phy_init, 361 .power_on = cdns_sierra_phy_on, 362 .power_off = cdns_sierra_phy_off, 363 .reset = cdns_sierra_phy_reset, 364 .owner = THIS_MODULE, 365}; 366 367static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst, 368 struct device_node *child) 369{ 370 if (of_property_read_u32(child, "reg", &inst->mlane)) 371 return -EINVAL; 372 373 if (of_property_read_u32(child, "cdns,num-lanes", &inst->num_lanes)) 374 return -EINVAL; 375 376 if (of_property_read_u32(child, "cdns,phy-type", &inst->phy_type)) 377 return -EINVAL; 378 379 return 0; 380} 381 382static const struct of_device_id cdns_sierra_id_table[]; 383 384static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base, 385 u32 block_offset, u8 reg_offset_shift, 386 const struct regmap_config *config) 387{ 388 struct cdns_regmap_cdb_context *ctx; 389 390 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 391 if (!ctx) 392 return ERR_PTR(-ENOMEM); 393 394 ctx->dev = dev; 395 ctx->base = base + block_offset; 396 ctx->reg_offset_shift = reg_offset_shift; 397 398 return devm_regmap_init(dev, NULL, ctx, config); 399} 400 401static int cdns_regfield_init(struct cdns_sierra_phy *sp) 402{ 403 struct device *dev = sp->dev; 404 struct regmap_field *field; 405 struct regmap *regmap; 406 int i; 407 408 regmap = sp->regmap_common_cdb; 409 field = devm_regmap_field_alloc(dev, regmap, macro_id_type); 410 if (IS_ERR(field)) { 411 dev_err(dev, "MACRO_ID_TYPE reg field init failed\n"); 412 return PTR_ERR(field); 413 } 414 sp->macro_id_type = field; 415 416 regmap = sp->regmap_phy_config_ctrl; 417 field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1); 418 if (IS_ERR(field)) { 419 dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n"); 420 return PTR_ERR(field); 421 } 422 sp->phy_pll_cfg_1 = field; 423 424 for (i = 0; i < SIERRA_MAX_LANES; i++) { 425 regmap = sp->regmap_lane_cdb[i]; 426 field = devm_regmap_field_alloc(dev, regmap, pllctrl_lock); 427 if (IS_ERR(field)) { 428 dev_err(dev, "P%d_ENABLE reg field init failed\n", i); 429 return PTR_ERR(field); 430 } 431 sp->pllctrl_lock[i] = field; 432 } 433 434 return 0; 435} 436 437static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp, 438 void __iomem *base, u8 block_offset_shift, 439 u8 reg_offset_shift) 440{ 441 struct device *dev = sp->dev; 442 struct regmap *regmap; 443 u32 block_offset; 444 int i; 445 446 for (i = 0; i < SIERRA_MAX_LANES; i++) { 447 block_offset = SIERRA_LANE_CDB_OFFSET(i, block_offset_shift, 448 reg_offset_shift); 449 regmap = cdns_regmap_init(dev, base, block_offset, 450 reg_offset_shift, 451 &cdns_sierra_lane_cdb_config[i]); 452 if (IS_ERR(regmap)) { 453 dev_err(dev, "Failed to init lane CDB regmap\n"); 454 return PTR_ERR(regmap); 455 } 456 sp->regmap_lane_cdb[i] = regmap; 457 } 458 459 regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET, 460 reg_offset_shift, 461 &cdns_sierra_common_cdb_config); 462 if (IS_ERR(regmap)) { 463 dev_err(dev, "Failed to init common CDB regmap\n"); 464 return PTR_ERR(regmap); 465 } 466 sp->regmap_common_cdb = regmap; 467 468 block_offset = SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset_shift); 469 regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift, 470 &cdns_sierra_phy_config_ctrl_config); 471 if (IS_ERR(regmap)) { 472 dev_err(dev, "Failed to init PHY config and control regmap\n"); 473 return PTR_ERR(regmap); 474 } 475 sp->regmap_phy_config_ctrl = regmap; 476 477 return 0; 478} 479 480static int cdns_sierra_phy_probe(struct platform_device *pdev) 481{ 482 struct cdns_sierra_phy *sp; 483 struct phy_provider *phy_provider; 484 struct device *dev = &pdev->dev; 485 const struct of_device_id *match; 486 struct cdns_sierra_data *data; 487 unsigned int id_value; 488 struct resource *res; 489 int i, ret, node = 0; 490 void __iomem *base; 491 struct clk *clk; 492 struct device_node *dn = dev->of_node, *child; 493 494 if (of_get_child_count(dn) == 0) 495 return -ENODEV; 496 497 /* Get init data for this PHY */ 498 match = of_match_device(cdns_sierra_id_table, dev); 499 if (!match) 500 return -EINVAL; 501 502 data = (struct cdns_sierra_data *)match->data; 503 504 sp = devm_kzalloc(dev, sizeof(*sp), GFP_KERNEL); 505 if (!sp) 506 return -ENOMEM; 507 dev_set_drvdata(dev, sp); 508 sp->dev = dev; 509 sp->init_data = data; 510 511 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 512 base = devm_ioremap_resource(dev, res); 513 if (IS_ERR(base)) { 514 dev_err(dev, "missing \"reg\"\n"); 515 return PTR_ERR(base); 516 } 517 518 ret = cdns_regmap_init_blocks(sp, base, data->block_offset_shift, 519 data->reg_offset_shift); 520 if (ret) 521 return ret; 522 523 ret = cdns_regfield_init(sp); 524 if (ret) 525 return ret; 526 527 platform_set_drvdata(pdev, sp); 528 529 sp->clk = devm_clk_get_optional(dev, "phy_clk"); 530 if (IS_ERR(sp->clk)) { 531 dev_err(dev, "failed to get clock phy_clk\n"); 532 return PTR_ERR(sp->clk); 533 } 534 535 sp->phy_rst = devm_reset_control_get(dev, "sierra_reset"); 536 if (IS_ERR(sp->phy_rst)) { 537 dev_err(dev, "failed to get reset\n"); 538 return PTR_ERR(sp->phy_rst); 539 } 540 541 sp->apb_rst = devm_reset_control_get_optional(dev, "sierra_apb"); 542 if (IS_ERR(sp->apb_rst)) { 543 dev_err(dev, "failed to get apb reset\n"); 544 return PTR_ERR(sp->apb_rst); 545 } 546 547 clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div"); 548 if (IS_ERR(clk)) { 549 dev_err(dev, "cmn_refclk_dig_div clock not found\n"); 550 ret = PTR_ERR(clk); 551 return ret; 552 } 553 sp->cmn_refclk_dig_div = clk; 554 555 clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div"); 556 if (IS_ERR(clk)) { 557 dev_err(dev, "cmn_refclk1_dig_div clock not found\n"); 558 ret = PTR_ERR(clk); 559 return ret; 560 } 561 sp->cmn_refclk1_dig_div = clk; 562 563 ret = clk_prepare_enable(sp->clk); 564 if (ret) 565 return ret; 566 567 /* Enable APB */ 568 reset_control_deassert(sp->apb_rst); 569 570 /* Check that PHY is present */ 571 regmap_field_read(sp->macro_id_type, &id_value); 572 if (sp->init_data->id_value != id_value) { 573 ret = -EINVAL; 574 goto clk_disable; 575 } 576 577 sp->autoconf = of_property_read_bool(dn, "cdns,autoconf"); 578 579 for_each_available_child_of_node(dn, child) { 580 struct phy *gphy; 581 582 sp->phys[node].lnk_rst = 583 of_reset_control_array_get_exclusive(child); 584 585 if (IS_ERR(sp->phys[node].lnk_rst)) { 586 dev_err(dev, "failed to get reset %s\n", 587 child->full_name); 588 ret = PTR_ERR(sp->phys[node].lnk_rst); 589 goto put_child2; 590 } 591 592 if (!sp->autoconf) { 593 ret = cdns_sierra_get_optional(&sp->phys[node], child); 594 if (ret) { 595 dev_err(dev, "missing property in node %s\n", 596 child->name); 597 goto put_child; 598 } 599 } 600 601 sp->num_lanes += sp->phys[node].num_lanes; 602 603 gphy = devm_phy_create(dev, child, &ops); 604 605 if (IS_ERR(gphy)) { 606 ret = PTR_ERR(gphy); 607 goto put_child; 608 } 609 sp->phys[node].phy = gphy; 610 phy_set_drvdata(gphy, &sp->phys[node]); 611 612 node++; 613 } 614 sp->nsubnodes = node; 615 616 if (sp->num_lanes > SIERRA_MAX_LANES) { 617 ret = -EINVAL; 618 dev_err(dev, "Invalid lane configuration\n"); 619 goto put_child2; 620 } 621 622 /* If more than one subnode, configure the PHY as multilink */ 623 if (!sp->autoconf && sp->nsubnodes > 1) 624 regmap_field_write(sp->phy_pll_cfg_1, 0x1); 625 626 pm_runtime_enable(dev); 627 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 628 return PTR_ERR_OR_ZERO(phy_provider); 629 630put_child: 631 node++; 632put_child2: 633 for (i = 0; i < node; i++) 634 reset_control_put(sp->phys[i].lnk_rst); 635 of_node_put(child); 636clk_disable: 637 clk_disable_unprepare(sp->clk); 638 reset_control_assert(sp->apb_rst); 639 return ret; 640} 641 642static int cdns_sierra_phy_remove(struct platform_device *pdev) 643{ 644 struct cdns_sierra_phy *phy = platform_get_drvdata(pdev); 645 int i; 646 647 reset_control_assert(phy->phy_rst); 648 reset_control_assert(phy->apb_rst); 649 pm_runtime_disable(&pdev->dev); 650 651 /* 652 * The device level resets will be put automatically. 653 * Need to put the subnode resets here though. 654 */ 655 for (i = 0; i < phy->nsubnodes; i++) { 656 reset_control_assert(phy->phys[i].lnk_rst); 657 reset_control_put(phy->phys[i].lnk_rst); 658 } 659 return 0; 660} 661 662/* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */ 663static const struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = { 664 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 665 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 666 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 667 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 668 {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} 669}; 670 671/* refclk100MHz_32b_PCIe_ln_ext_ssc */ 672static const struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = { 673 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 674 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 675 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 676 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 677 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 678 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 679 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG} 680}; 681 682/* refclk100MHz_20b_USB_cmn_pll_ext_ssc */ 683static const struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = { 684 {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 685 {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 686 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 687 {0x0000, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} 688}; 689 690/* refclk100MHz_20b_USB_ln_ext_ssc */ 691static const struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = { 692 {0xFE0A, SIERRA_DET_STANDEC_A_PREG}, 693 {0x000F, SIERRA_DET_STANDEC_B_PREG}, 694 {0x55A5, SIERRA_DET_STANDEC_C_PREG}, 695 {0x69ad, SIERRA_DET_STANDEC_D_PREG}, 696 {0x0241, SIERRA_DET_STANDEC_E_PREG}, 697 {0x0110, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG}, 698 {0x0014, SIERRA_PSM_A0IN_TMR_PREG}, 699 {0xCF00, SIERRA_PSM_DIAG_PREG}, 700 {0x001F, SIERRA_PSC_TX_A0_PREG}, 701 {0x0007, SIERRA_PSC_TX_A1_PREG}, 702 {0x0003, SIERRA_PSC_TX_A2_PREG}, 703 {0x0003, SIERRA_PSC_TX_A3_PREG}, 704 {0x0FFF, SIERRA_PSC_RX_A0_PREG}, 705 {0x0003, SIERRA_PSC_RX_A1_PREG}, 706 {0x0003, SIERRA_PSC_RX_A2_PREG}, 707 {0x0001, SIERRA_PSC_RX_A3_PREG}, 708 {0x0001, SIERRA_PLLCTRL_SUBRATE_PREG}, 709 {0x0406, SIERRA_PLLCTRL_GEN_D_PREG}, 710 {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG}, 711 {0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG}, 712 {0x2512, SIERRA_DFE_BIASTRIM_PREG}, 713 {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, 714 {0x823E, SIERRA_CLKPATHCTRL_TMR_PREG}, 715 {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 716 {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 717 {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG}, 718 {0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 719 {0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG}, 720 {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, 721 {0x0000, SIERRA_CREQ_SPARE_PREG}, 722 {0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 723 {0x8452, SIERRA_CTLELUT_CTRL_PREG}, 724 {0x4121, SIERRA_DFE_ECMP_RATESEL_PREG}, 725 {0x4121, SIERRA_DFE_SMP_RATESEL_PREG}, 726 {0x0003, SIERRA_DEQ_PHALIGN_CTRL}, 727 {0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG}, 728 {0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 729 {0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 730 {0x0048, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 731 {0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 732 {0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG}, 733 {0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG}, 734 {0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG}, 735 {0x0014, SIERRA_DEQ_GLUT0}, 736 {0x0014, SIERRA_DEQ_GLUT1}, 737 {0x0014, SIERRA_DEQ_GLUT2}, 738 {0x0014, SIERRA_DEQ_GLUT3}, 739 {0x0014, SIERRA_DEQ_GLUT4}, 740 {0x0014, SIERRA_DEQ_GLUT5}, 741 {0x0014, SIERRA_DEQ_GLUT6}, 742 {0x0014, SIERRA_DEQ_GLUT7}, 743 {0x0014, SIERRA_DEQ_GLUT8}, 744 {0x0014, SIERRA_DEQ_GLUT9}, 745 {0x0014, SIERRA_DEQ_GLUT10}, 746 {0x0014, SIERRA_DEQ_GLUT11}, 747 {0x0014, SIERRA_DEQ_GLUT12}, 748 {0x0014, SIERRA_DEQ_GLUT13}, 749 {0x0014, SIERRA_DEQ_GLUT14}, 750 {0x0014, SIERRA_DEQ_GLUT15}, 751 {0x0014, SIERRA_DEQ_GLUT16}, 752 {0x0BAE, SIERRA_DEQ_ALUT0}, 753 {0x0AEB, SIERRA_DEQ_ALUT1}, 754 {0x0A28, SIERRA_DEQ_ALUT2}, 755 {0x0965, SIERRA_DEQ_ALUT3}, 756 {0x08A2, SIERRA_DEQ_ALUT4}, 757 {0x07DF, SIERRA_DEQ_ALUT5}, 758 {0x071C, SIERRA_DEQ_ALUT6}, 759 {0x0659, SIERRA_DEQ_ALUT7}, 760 {0x0596, SIERRA_DEQ_ALUT8}, 761 {0x0514, SIERRA_DEQ_ALUT9}, 762 {0x0492, SIERRA_DEQ_ALUT10}, 763 {0x0410, SIERRA_DEQ_ALUT11}, 764 {0x038E, SIERRA_DEQ_ALUT12}, 765 {0x030C, SIERRA_DEQ_ALUT13}, 766 {0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG}, 767 {0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG}, 768 {0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG}, 769 {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 770 {0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG}, 771 {0x0033, SIERRA_DEQ_PICTRL_PREG}, 772 {0x0400, SIERRA_CPICAL_TMRVAL_MODE1_PREG}, 773 {0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG}, 774 {0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG}, 775 {0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG}, 776 {0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG}, 777 {0x0005, SIERRA_LFPSDET_SUPPORT_PREG}, 778 {0x000F, SIERRA_LFPSFILT_NS_PREG}, 779 {0x0009, SIERRA_LFPSFILT_RD_PREG}, 780 {0x0001, SIERRA_LFPSFILT_MP_PREG}, 781 {0x6013, SIERRA_SIGDET_SUPPORT_PREG}, 782 {0x8013, SIERRA_SDFILT_H2L_A_PREG}, 783 {0x8009, SIERRA_SDFILT_L2H_PREG}, 784 {0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG}, 785 {0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 786 {0x4243, SIERRA_RXBUFFER_DFECTRL_PREG} 787}; 788 789static const struct cdns_sierra_data cdns_map_sierra = { 790 SIERRA_MACRO_ID, 791 0x2, 792 0x2, 793 ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc), 794 ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc), 795 ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc), 796 ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc), 797 cdns_pcie_cmn_regs_ext_ssc, 798 cdns_pcie_ln_regs_ext_ssc, 799 cdns_usb_cmn_regs_ext_ssc, 800 cdns_usb_ln_regs_ext_ssc, 801}; 802 803static const struct cdns_sierra_data cdns_ti_map_sierra = { 804 SIERRA_MACRO_ID, 805 0x0, 806 0x1, 807 ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc), 808 ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc), 809 ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc), 810 ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc), 811 cdns_pcie_cmn_regs_ext_ssc, 812 cdns_pcie_ln_regs_ext_ssc, 813 cdns_usb_cmn_regs_ext_ssc, 814 cdns_usb_ln_regs_ext_ssc, 815}; 816 817static const struct of_device_id cdns_sierra_id_table[] = { 818 { 819 .compatible = "cdns,sierra-phy-t0", 820 .data = &cdns_map_sierra, 821 }, 822 { 823 .compatible = "ti,sierra-phy-t0", 824 .data = &cdns_ti_map_sierra, 825 }, 826 {} 827}; 828MODULE_DEVICE_TABLE(of, cdns_sierra_id_table); 829 830static struct platform_driver cdns_sierra_driver = { 831 .probe = cdns_sierra_phy_probe, 832 .remove = cdns_sierra_phy_remove, 833 .driver = { 834 .name = "cdns-sierra-phy", 835 .of_match_table = cdns_sierra_id_table, 836 }, 837}; 838module_platform_driver(cdns_sierra_driver); 839 840MODULE_ALIAS("platform:cdns_sierra"); 841MODULE_AUTHOR("Cadence Design Systems"); 842MODULE_DESCRIPTION("CDNS sierra phy driver"); 843MODULE_LICENSE("GPL v2"); 844