18c2ecf20Sopenharmony_ci/* 28c2ecf20Sopenharmony_ci * Copyright (C) 2016 Broadcom 38c2ecf20Sopenharmony_ci * 48c2ecf20Sopenharmony_ci * This program is free software; you can redistribute it and/or 58c2ecf20Sopenharmony_ci * modify it under the terms of the GNU General Public License as 68c2ecf20Sopenharmony_ci * published by the Free Software Foundation version 2. 78c2ecf20Sopenharmony_ci * 88c2ecf20Sopenharmony_ci * This program is distributed "as is" WITHOUT ANY WARRANTY of any 98c2ecf20Sopenharmony_ci * kind, whether express or implied; without even the implied warranty 108c2ecf20Sopenharmony_ci * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 118c2ecf20Sopenharmony_ci * GNU General Public License for more details. 128c2ecf20Sopenharmony_ci */ 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci#include <linux/device.h> 158c2ecf20Sopenharmony_ci#include <linux/module.h> 168c2ecf20Sopenharmony_ci#include <linux/of_mdio.h> 178c2ecf20Sopenharmony_ci#include <linux/mdio.h> 188c2ecf20Sopenharmony_ci#include <linux/phy.h> 198c2ecf20Sopenharmony_ci#include <linux/phy/phy.h> 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ci#define BLK_ADDR_REG_OFFSET 0x1f 228c2ecf20Sopenharmony_ci#define PLL_AFE1_100MHZ_BLK 0x2100 238c2ecf20Sopenharmony_ci#define PLL_CLK_AMP_OFFSET 0x03 248c2ecf20Sopenharmony_ci#define PLL_CLK_AMP_2P05V 0x2b18 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_cistatic int ns2_pci_phy_init(struct phy *p) 278c2ecf20Sopenharmony_ci{ 288c2ecf20Sopenharmony_ci struct mdio_device *mdiodev = phy_get_drvdata(p); 298c2ecf20Sopenharmony_ci int rc; 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ci /* select the AFE 100MHz block page */ 328c2ecf20Sopenharmony_ci rc = mdiobus_write(mdiodev->bus, mdiodev->addr, 338c2ecf20Sopenharmony_ci BLK_ADDR_REG_OFFSET, PLL_AFE1_100MHZ_BLK); 348c2ecf20Sopenharmony_ci if (rc) 358c2ecf20Sopenharmony_ci goto err; 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_ci /* set the 100 MHz reference clock amplitude to 2.05 v */ 388c2ecf20Sopenharmony_ci rc = mdiobus_write(mdiodev->bus, mdiodev->addr, 398c2ecf20Sopenharmony_ci PLL_CLK_AMP_OFFSET, PLL_CLK_AMP_2P05V); 408c2ecf20Sopenharmony_ci if (rc) 418c2ecf20Sopenharmony_ci goto err; 428c2ecf20Sopenharmony_ci 438c2ecf20Sopenharmony_ci return 0; 448c2ecf20Sopenharmony_ci 458c2ecf20Sopenharmony_cierr: 468c2ecf20Sopenharmony_ci dev_err(&mdiodev->dev, "Error %d writing to phy\n", rc); 478c2ecf20Sopenharmony_ci return rc; 488c2ecf20Sopenharmony_ci} 498c2ecf20Sopenharmony_ci 508c2ecf20Sopenharmony_cistatic const struct phy_ops ns2_pci_phy_ops = { 518c2ecf20Sopenharmony_ci .init = ns2_pci_phy_init, 528c2ecf20Sopenharmony_ci .owner = THIS_MODULE, 538c2ecf20Sopenharmony_ci}; 548c2ecf20Sopenharmony_ci 558c2ecf20Sopenharmony_cistatic int ns2_pci_phy_probe(struct mdio_device *mdiodev) 568c2ecf20Sopenharmony_ci{ 578c2ecf20Sopenharmony_ci struct device *dev = &mdiodev->dev; 588c2ecf20Sopenharmony_ci struct phy_provider *provider; 598c2ecf20Sopenharmony_ci struct phy *phy; 608c2ecf20Sopenharmony_ci 618c2ecf20Sopenharmony_ci phy = devm_phy_create(dev, dev->of_node, &ns2_pci_phy_ops); 628c2ecf20Sopenharmony_ci if (IS_ERR(phy)) { 638c2ecf20Sopenharmony_ci dev_err(dev, "failed to create Phy\n"); 648c2ecf20Sopenharmony_ci return PTR_ERR(phy); 658c2ecf20Sopenharmony_ci } 668c2ecf20Sopenharmony_ci 678c2ecf20Sopenharmony_ci phy_set_drvdata(phy, mdiodev); 688c2ecf20Sopenharmony_ci 698c2ecf20Sopenharmony_ci provider = devm_of_phy_provider_register(&phy->dev, 708c2ecf20Sopenharmony_ci of_phy_simple_xlate); 718c2ecf20Sopenharmony_ci if (IS_ERR(provider)) { 728c2ecf20Sopenharmony_ci dev_err(dev, "failed to register Phy provider\n"); 738c2ecf20Sopenharmony_ci return PTR_ERR(provider); 748c2ecf20Sopenharmony_ci } 758c2ecf20Sopenharmony_ci 768c2ecf20Sopenharmony_ci dev_info(dev, "%s PHY registered\n", dev_name(dev)); 778c2ecf20Sopenharmony_ci 788c2ecf20Sopenharmony_ci return 0; 798c2ecf20Sopenharmony_ci} 808c2ecf20Sopenharmony_ci 818c2ecf20Sopenharmony_cistatic const struct of_device_id ns2_pci_phy_of_match[] = { 828c2ecf20Sopenharmony_ci { .compatible = "brcm,ns2-pcie-phy", }, 838c2ecf20Sopenharmony_ci { /* sentinel */ }, 848c2ecf20Sopenharmony_ci}; 858c2ecf20Sopenharmony_ciMODULE_DEVICE_TABLE(of, ns2_pci_phy_of_match); 868c2ecf20Sopenharmony_ci 878c2ecf20Sopenharmony_cistatic struct mdio_driver ns2_pci_phy_driver = { 888c2ecf20Sopenharmony_ci .mdiodrv = { 898c2ecf20Sopenharmony_ci .driver = { 908c2ecf20Sopenharmony_ci .name = "phy-bcm-ns2-pci", 918c2ecf20Sopenharmony_ci .of_match_table = ns2_pci_phy_of_match, 928c2ecf20Sopenharmony_ci }, 938c2ecf20Sopenharmony_ci }, 948c2ecf20Sopenharmony_ci .probe = ns2_pci_phy_probe, 958c2ecf20Sopenharmony_ci}; 968c2ecf20Sopenharmony_cimdio_module_driver(ns2_pci_phy_driver); 978c2ecf20Sopenharmony_ci 988c2ecf20Sopenharmony_ciMODULE_AUTHOR("Broadcom"); 998c2ecf20Sopenharmony_ciMODULE_DESCRIPTION("Broadcom Northstar2 PCI Phy driver"); 1008c2ecf20Sopenharmony_ciMODULE_LICENSE("GPL v2"); 1018c2ecf20Sopenharmony_ciMODULE_ALIAS("platform:phy-bcm-ns2-pci"); 102