18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Amlogic AXG PCIE PHY driver 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright (C) 2020 Remi Pommarel <repk@triplefau.lt> 68c2ecf20Sopenharmony_ci */ 78c2ecf20Sopenharmony_ci#include <linux/module.h> 88c2ecf20Sopenharmony_ci#include <linux/phy/phy.h> 98c2ecf20Sopenharmony_ci#include <linux/regmap.h> 108c2ecf20Sopenharmony_ci#include <linux/reset.h> 118c2ecf20Sopenharmony_ci#include <linux/platform_device.h> 128c2ecf20Sopenharmony_ci#include <linux/bitfield.h> 138c2ecf20Sopenharmony_ci#include <dt-bindings/phy/phy.h> 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ci#define MESON_PCIE_REG0 0x00 168c2ecf20Sopenharmony_ci#define MESON_PCIE_COMMON_CLK BIT(4) 178c2ecf20Sopenharmony_ci#define MESON_PCIE_PORT_SEL GENMASK(3, 2) 188c2ecf20Sopenharmony_ci#define MESON_PCIE_CLK BIT(1) 198c2ecf20Sopenharmony_ci#define MESON_PCIE_POWERDOWN BIT(0) 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ci#define MESON_PCIE_TWO_X1 FIELD_PREP(MESON_PCIE_PORT_SEL, 0x3) 228c2ecf20Sopenharmony_ci#define MESON_PCIE_COMMON_REF_CLK FIELD_PREP(MESON_PCIE_COMMON_CLK, 0x1) 238c2ecf20Sopenharmony_ci#define MESON_PCIE_PHY_INIT (MESON_PCIE_TWO_X1 | \ 248c2ecf20Sopenharmony_ci MESON_PCIE_COMMON_REF_CLK) 258c2ecf20Sopenharmony_ci#define MESON_PCIE_RESET_DELAY 500 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_cistruct phy_axg_pcie_priv { 288c2ecf20Sopenharmony_ci struct phy *phy; 298c2ecf20Sopenharmony_ci struct phy *analog; 308c2ecf20Sopenharmony_ci struct regmap *regmap; 318c2ecf20Sopenharmony_ci struct reset_control *reset; 328c2ecf20Sopenharmony_ci}; 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_cistatic const struct regmap_config phy_axg_pcie_regmap_conf = { 358c2ecf20Sopenharmony_ci .reg_bits = 8, 368c2ecf20Sopenharmony_ci .val_bits = 32, 378c2ecf20Sopenharmony_ci .reg_stride = 4, 388c2ecf20Sopenharmony_ci .max_register = MESON_PCIE_REG0, 398c2ecf20Sopenharmony_ci}; 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_cistatic int phy_axg_pcie_power_on(struct phy *phy) 428c2ecf20Sopenharmony_ci{ 438c2ecf20Sopenharmony_ci struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy); 448c2ecf20Sopenharmony_ci int ret; 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ci ret = phy_power_on(priv->analog); 478c2ecf20Sopenharmony_ci if (ret != 0) 488c2ecf20Sopenharmony_ci return ret; 498c2ecf20Sopenharmony_ci 508c2ecf20Sopenharmony_ci regmap_update_bits(priv->regmap, MESON_PCIE_REG0, 518c2ecf20Sopenharmony_ci MESON_PCIE_POWERDOWN, 0); 528c2ecf20Sopenharmony_ci return 0; 538c2ecf20Sopenharmony_ci} 548c2ecf20Sopenharmony_ci 558c2ecf20Sopenharmony_cistatic int phy_axg_pcie_power_off(struct phy *phy) 568c2ecf20Sopenharmony_ci{ 578c2ecf20Sopenharmony_ci struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy); 588c2ecf20Sopenharmony_ci int ret; 598c2ecf20Sopenharmony_ci 608c2ecf20Sopenharmony_ci ret = phy_power_off(priv->analog); 618c2ecf20Sopenharmony_ci if (ret != 0) 628c2ecf20Sopenharmony_ci return ret; 638c2ecf20Sopenharmony_ci 648c2ecf20Sopenharmony_ci regmap_update_bits(priv->regmap, MESON_PCIE_REG0, 658c2ecf20Sopenharmony_ci MESON_PCIE_POWERDOWN, 1); 668c2ecf20Sopenharmony_ci return 0; 678c2ecf20Sopenharmony_ci} 688c2ecf20Sopenharmony_ci 698c2ecf20Sopenharmony_cistatic int phy_axg_pcie_init(struct phy *phy) 708c2ecf20Sopenharmony_ci{ 718c2ecf20Sopenharmony_ci struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy); 728c2ecf20Sopenharmony_ci int ret; 738c2ecf20Sopenharmony_ci 748c2ecf20Sopenharmony_ci ret = phy_init(priv->analog); 758c2ecf20Sopenharmony_ci if (ret != 0) 768c2ecf20Sopenharmony_ci return ret; 778c2ecf20Sopenharmony_ci 788c2ecf20Sopenharmony_ci regmap_write(priv->regmap, MESON_PCIE_REG0, MESON_PCIE_PHY_INIT); 798c2ecf20Sopenharmony_ci return reset_control_reset(priv->reset); 808c2ecf20Sopenharmony_ci} 818c2ecf20Sopenharmony_ci 828c2ecf20Sopenharmony_cistatic int phy_axg_pcie_exit(struct phy *phy) 838c2ecf20Sopenharmony_ci{ 848c2ecf20Sopenharmony_ci struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy); 858c2ecf20Sopenharmony_ci int ret; 868c2ecf20Sopenharmony_ci 878c2ecf20Sopenharmony_ci ret = phy_exit(priv->analog); 888c2ecf20Sopenharmony_ci if (ret != 0) 898c2ecf20Sopenharmony_ci return ret; 908c2ecf20Sopenharmony_ci 918c2ecf20Sopenharmony_ci return reset_control_reset(priv->reset); 928c2ecf20Sopenharmony_ci} 938c2ecf20Sopenharmony_ci 948c2ecf20Sopenharmony_cistatic int phy_axg_pcie_reset(struct phy *phy) 958c2ecf20Sopenharmony_ci{ 968c2ecf20Sopenharmony_ci struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy); 978c2ecf20Sopenharmony_ci int ret = 0; 988c2ecf20Sopenharmony_ci 998c2ecf20Sopenharmony_ci ret = phy_reset(priv->analog); 1008c2ecf20Sopenharmony_ci if (ret != 0) 1018c2ecf20Sopenharmony_ci goto out; 1028c2ecf20Sopenharmony_ci 1038c2ecf20Sopenharmony_ci ret = reset_control_assert(priv->reset); 1048c2ecf20Sopenharmony_ci if (ret != 0) 1058c2ecf20Sopenharmony_ci goto out; 1068c2ecf20Sopenharmony_ci udelay(MESON_PCIE_RESET_DELAY); 1078c2ecf20Sopenharmony_ci 1088c2ecf20Sopenharmony_ci ret = reset_control_deassert(priv->reset); 1098c2ecf20Sopenharmony_ci if (ret != 0) 1108c2ecf20Sopenharmony_ci goto out; 1118c2ecf20Sopenharmony_ci udelay(MESON_PCIE_RESET_DELAY); 1128c2ecf20Sopenharmony_ci 1138c2ecf20Sopenharmony_ciout: 1148c2ecf20Sopenharmony_ci return ret; 1158c2ecf20Sopenharmony_ci} 1168c2ecf20Sopenharmony_ci 1178c2ecf20Sopenharmony_cistatic const struct phy_ops phy_axg_pcie_ops = { 1188c2ecf20Sopenharmony_ci .init = phy_axg_pcie_init, 1198c2ecf20Sopenharmony_ci .exit = phy_axg_pcie_exit, 1208c2ecf20Sopenharmony_ci .power_on = phy_axg_pcie_power_on, 1218c2ecf20Sopenharmony_ci .power_off = phy_axg_pcie_power_off, 1228c2ecf20Sopenharmony_ci .reset = phy_axg_pcie_reset, 1238c2ecf20Sopenharmony_ci .owner = THIS_MODULE, 1248c2ecf20Sopenharmony_ci}; 1258c2ecf20Sopenharmony_ci 1268c2ecf20Sopenharmony_cistatic int phy_axg_pcie_probe(struct platform_device *pdev) 1278c2ecf20Sopenharmony_ci{ 1288c2ecf20Sopenharmony_ci struct phy_provider *pphy; 1298c2ecf20Sopenharmony_ci struct device *dev = &pdev->dev; 1308c2ecf20Sopenharmony_ci struct phy_axg_pcie_priv *priv; 1318c2ecf20Sopenharmony_ci struct device_node *np = dev->of_node; 1328c2ecf20Sopenharmony_ci struct resource *res; 1338c2ecf20Sopenharmony_ci void __iomem *base; 1348c2ecf20Sopenharmony_ci int ret; 1358c2ecf20Sopenharmony_ci 1368c2ecf20Sopenharmony_ci priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL); 1378c2ecf20Sopenharmony_ci if (!priv) 1388c2ecf20Sopenharmony_ci return -ENOMEM; 1398c2ecf20Sopenharmony_ci 1408c2ecf20Sopenharmony_ci priv->phy = devm_phy_create(dev, np, &phy_axg_pcie_ops); 1418c2ecf20Sopenharmony_ci if (IS_ERR(priv->phy)) { 1428c2ecf20Sopenharmony_ci ret = PTR_ERR(priv->phy); 1438c2ecf20Sopenharmony_ci if (ret != -EPROBE_DEFER) 1448c2ecf20Sopenharmony_ci dev_err(dev, "failed to create PHY\n"); 1458c2ecf20Sopenharmony_ci return ret; 1468c2ecf20Sopenharmony_ci } 1478c2ecf20Sopenharmony_ci 1488c2ecf20Sopenharmony_ci res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1498c2ecf20Sopenharmony_ci base = devm_ioremap_resource(dev, res); 1508c2ecf20Sopenharmony_ci if (IS_ERR(base)) 1518c2ecf20Sopenharmony_ci return PTR_ERR(base); 1528c2ecf20Sopenharmony_ci 1538c2ecf20Sopenharmony_ci priv->regmap = devm_regmap_init_mmio(dev, base, 1548c2ecf20Sopenharmony_ci &phy_axg_pcie_regmap_conf); 1558c2ecf20Sopenharmony_ci if (IS_ERR(priv->regmap)) 1568c2ecf20Sopenharmony_ci return PTR_ERR(priv->regmap); 1578c2ecf20Sopenharmony_ci 1588c2ecf20Sopenharmony_ci priv->reset = devm_reset_control_array_get(dev, false, false); 1598c2ecf20Sopenharmony_ci if (IS_ERR(priv->reset)) 1608c2ecf20Sopenharmony_ci return PTR_ERR(priv->reset); 1618c2ecf20Sopenharmony_ci 1628c2ecf20Sopenharmony_ci priv->analog = devm_phy_get(dev, "analog"); 1638c2ecf20Sopenharmony_ci if (IS_ERR(priv->analog)) 1648c2ecf20Sopenharmony_ci return PTR_ERR(priv->analog); 1658c2ecf20Sopenharmony_ci 1668c2ecf20Sopenharmony_ci phy_set_drvdata(priv->phy, priv); 1678c2ecf20Sopenharmony_ci dev_set_drvdata(dev, priv); 1688c2ecf20Sopenharmony_ci pphy = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1698c2ecf20Sopenharmony_ci 1708c2ecf20Sopenharmony_ci return PTR_ERR_OR_ZERO(pphy); 1718c2ecf20Sopenharmony_ci} 1728c2ecf20Sopenharmony_ci 1738c2ecf20Sopenharmony_cistatic const struct of_device_id phy_axg_pcie_of_match[] = { 1748c2ecf20Sopenharmony_ci { 1758c2ecf20Sopenharmony_ci .compatible = "amlogic,axg-pcie-phy", 1768c2ecf20Sopenharmony_ci }, 1778c2ecf20Sopenharmony_ci { }, 1788c2ecf20Sopenharmony_ci}; 1798c2ecf20Sopenharmony_ciMODULE_DEVICE_TABLE(of, phy_axg_pcie_of_match); 1808c2ecf20Sopenharmony_ci 1818c2ecf20Sopenharmony_cistatic struct platform_driver phy_axg_pcie_driver = { 1828c2ecf20Sopenharmony_ci .probe = phy_axg_pcie_probe, 1838c2ecf20Sopenharmony_ci .driver = { 1848c2ecf20Sopenharmony_ci .name = "phy-axg-pcie", 1858c2ecf20Sopenharmony_ci .of_match_table = phy_axg_pcie_of_match, 1868c2ecf20Sopenharmony_ci }, 1878c2ecf20Sopenharmony_ci}; 1888c2ecf20Sopenharmony_cimodule_platform_driver(phy_axg_pcie_driver); 1898c2ecf20Sopenharmony_ci 1908c2ecf20Sopenharmony_ciMODULE_AUTHOR("Remi Pommarel <repk@triplefau.lt>"); 1918c2ecf20Sopenharmony_ciMODULE_DESCRIPTION("Amlogic AXG PCIE PHY driver"); 1928c2ecf20Sopenharmony_ciMODULE_LICENSE("GPL v2"); 193