18c2ecf20Sopenharmony_ci# SPDX-License-Identifier: GPL-2.0-only 28c2ecf20Sopenharmony_ci# 38c2ecf20Sopenharmony_ci# Performance Monitor Drivers 48c2ecf20Sopenharmony_ci# 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_cimenu "Performance monitor support" 78c2ecf20Sopenharmony_ci depends on PERF_EVENTS 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ciconfig ARM_CCI_PMU 108c2ecf20Sopenharmony_ci tristate "ARM CCI PMU driver" 118c2ecf20Sopenharmony_ci depends on (ARM && CPU_V7) || ARM64 128c2ecf20Sopenharmony_ci select ARM_CCI 138c2ecf20Sopenharmony_ci help 148c2ecf20Sopenharmony_ci Support for PMU events monitoring on the ARM CCI (Cache Coherent 158c2ecf20Sopenharmony_ci Interconnect) family of products. 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ci If compiled as a module, it will be called arm-cci. 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ciconfig ARM_CCI400_PMU 208c2ecf20Sopenharmony_ci bool "support CCI-400" 218c2ecf20Sopenharmony_ci default y 228c2ecf20Sopenharmony_ci depends on ARM_CCI_PMU 238c2ecf20Sopenharmony_ci select ARM_CCI400_COMMON 248c2ecf20Sopenharmony_ci help 258c2ecf20Sopenharmony_ci CCI-400 provides 4 independent event counters counting events related 268c2ecf20Sopenharmony_ci to the connected slave/master interfaces, plus a cycle counter. 278c2ecf20Sopenharmony_ci 288c2ecf20Sopenharmony_ciconfig ARM_CCI5xx_PMU 298c2ecf20Sopenharmony_ci bool "support CCI-500/CCI-550" 308c2ecf20Sopenharmony_ci default y 318c2ecf20Sopenharmony_ci depends on ARM_CCI_PMU 328c2ecf20Sopenharmony_ci help 338c2ecf20Sopenharmony_ci CCI-500/CCI-550 both provide 8 independent event counters, which can 348c2ecf20Sopenharmony_ci count events pertaining to the slave/master interfaces as well as the 358c2ecf20Sopenharmony_ci internal events to the CCI. 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_ciconfig ARM_CCN 388c2ecf20Sopenharmony_ci tristate "ARM CCN driver support" 398c2ecf20Sopenharmony_ci depends on ARM || ARM64 408c2ecf20Sopenharmony_ci help 418c2ecf20Sopenharmony_ci PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) 428c2ecf20Sopenharmony_ci interconnect. 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_ciconfig ARM_CMN 458c2ecf20Sopenharmony_ci tristate "Arm CMN-600 PMU support" 468c2ecf20Sopenharmony_ci depends on ARM64 || (COMPILE_TEST && 64BIT) 478c2ecf20Sopenharmony_ci help 488c2ecf20Sopenharmony_ci Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh 498c2ecf20Sopenharmony_ci Network interconnect. 508c2ecf20Sopenharmony_ci 518c2ecf20Sopenharmony_ciconfig ARM_PMU 528c2ecf20Sopenharmony_ci depends on ARM || ARM64 538c2ecf20Sopenharmony_ci bool "ARM PMU framework" 548c2ecf20Sopenharmony_ci default y 558c2ecf20Sopenharmony_ci help 568c2ecf20Sopenharmony_ci Say y if you want to use CPU performance monitors on ARM-based 578c2ecf20Sopenharmony_ci systems. 588c2ecf20Sopenharmony_ci 598c2ecf20Sopenharmony_ciconfig ARM_PMU_ACPI 608c2ecf20Sopenharmony_ci depends on ARM_PMU && ACPI 618c2ecf20Sopenharmony_ci def_bool y 628c2ecf20Sopenharmony_ci 638c2ecf20Sopenharmony_ciconfig ARM_SMMU_V3_PMU 648c2ecf20Sopenharmony_ci tristate "ARM SMMUv3 Performance Monitors Extension" 658c2ecf20Sopenharmony_ci depends on ARM64 && ACPI && ARM_SMMU_V3 668c2ecf20Sopenharmony_ci help 678c2ecf20Sopenharmony_ci Provides support for the ARM SMMUv3 Performance Monitor Counter 688c2ecf20Sopenharmony_ci Groups (PMCG), which provide monitoring of transactions passing 698c2ecf20Sopenharmony_ci through the SMMU and allow the resulting information to be filtered 708c2ecf20Sopenharmony_ci based on the Stream ID of the corresponding master. 718c2ecf20Sopenharmony_ci 728c2ecf20Sopenharmony_ciconfig ARM_DSU_PMU 738c2ecf20Sopenharmony_ci tristate "ARM DynamIQ Shared Unit (DSU) PMU" 748c2ecf20Sopenharmony_ci depends on ARM64 758c2ecf20Sopenharmony_ci help 768c2ecf20Sopenharmony_ci Provides support for performance monitor unit in ARM DynamIQ Shared 778c2ecf20Sopenharmony_ci Unit (DSU). The DSU integrates one or more cores with an L3 memory 788c2ecf20Sopenharmony_ci system, control logic. The PMU allows counting various events related 798c2ecf20Sopenharmony_ci to DSU. 808c2ecf20Sopenharmony_ci 818c2ecf20Sopenharmony_ciconfig FSL_IMX8_DDR_PMU 828c2ecf20Sopenharmony_ci tristate "Freescale i.MX8 DDR perf monitor" 838c2ecf20Sopenharmony_ci depends on ARCH_MXC 848c2ecf20Sopenharmony_ci help 858c2ecf20Sopenharmony_ci Provides support for the DDR performance monitor in i.MX8, which 868c2ecf20Sopenharmony_ci can give information about memory throughput and other related 878c2ecf20Sopenharmony_ci events. 888c2ecf20Sopenharmony_ci 898c2ecf20Sopenharmony_ciconfig QCOM_L2_PMU 908c2ecf20Sopenharmony_ci bool "Qualcomm Technologies L2-cache PMU" 918c2ecf20Sopenharmony_ci depends on ARCH_QCOM && ARM64 && ACPI 928c2ecf20Sopenharmony_ci select QCOM_KRYO_L2_ACCESSORS 938c2ecf20Sopenharmony_ci help 948c2ecf20Sopenharmony_ci Provides support for the L2 cache performance monitor unit (PMU) 958c2ecf20Sopenharmony_ci in Qualcomm Technologies processors. 968c2ecf20Sopenharmony_ci Adds the L2 cache PMU into the perf events subsystem for 978c2ecf20Sopenharmony_ci monitoring L2 cache events. 988c2ecf20Sopenharmony_ci 998c2ecf20Sopenharmony_ciconfig QCOM_L3_PMU 1008c2ecf20Sopenharmony_ci bool "Qualcomm Technologies L3-cache PMU" 1018c2ecf20Sopenharmony_ci depends on ARCH_QCOM && ARM64 && ACPI 1028c2ecf20Sopenharmony_ci select QCOM_IRQ_COMBINER 1038c2ecf20Sopenharmony_ci help 1048c2ecf20Sopenharmony_ci Provides support for the L3 cache performance monitor unit (PMU) 1058c2ecf20Sopenharmony_ci in Qualcomm Technologies processors. 1068c2ecf20Sopenharmony_ci Adds the L3 cache PMU into the perf events subsystem for 1078c2ecf20Sopenharmony_ci monitoring L3 cache events. 1088c2ecf20Sopenharmony_ci 1098c2ecf20Sopenharmony_ciconfig THUNDERX2_PMU 1108c2ecf20Sopenharmony_ci tristate "Cavium ThunderX2 SoC PMU UNCORE" 1118c2ecf20Sopenharmony_ci depends on ARCH_THUNDER2 && ARM64 && ACPI && NUMA 1128c2ecf20Sopenharmony_ci default m 1138c2ecf20Sopenharmony_ci help 1148c2ecf20Sopenharmony_ci Provides support for ThunderX2 UNCORE events. 1158c2ecf20Sopenharmony_ci The SoC has PMU support in its L3 cache controller (L3C) and 1168c2ecf20Sopenharmony_ci in the DDR4 Memory Controller (DMC). 1178c2ecf20Sopenharmony_ci 1188c2ecf20Sopenharmony_ciconfig XGENE_PMU 1198c2ecf20Sopenharmony_ci depends on ARCH_XGENE 1208c2ecf20Sopenharmony_ci bool "APM X-Gene SoC PMU" 1218c2ecf20Sopenharmony_ci default n 1228c2ecf20Sopenharmony_ci help 1238c2ecf20Sopenharmony_ci Say y if you want to use APM X-Gene SoC performance monitors. 1248c2ecf20Sopenharmony_ci 1258c2ecf20Sopenharmony_ciconfig ARM_SPE_PMU 1268c2ecf20Sopenharmony_ci tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" 1278c2ecf20Sopenharmony_ci depends on ARM64 1288c2ecf20Sopenharmony_ci help 1298c2ecf20Sopenharmony_ci Enable perf support for the ARMv8.2 Statistical Profiling 1308c2ecf20Sopenharmony_ci Extension, which provides periodic sampling of operations in 1318c2ecf20Sopenharmony_ci the CPU pipeline and reports this via the perf AUX interface. 1328c2ecf20Sopenharmony_ci 1338c2ecf20Sopenharmony_cisource "drivers/perf/hisilicon/Kconfig" 1348c2ecf20Sopenharmony_ci 1358c2ecf20Sopenharmony_ciendmenu 136