1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Support routines for initializing a PCI subsystem
4 *
5 * Extruded from code written by
6 *      Dave Rusling (david.rusling@reo.mts.dec.com)
7 *      David Mosberger (davidm@cs.arizona.edu)
8 *	David Miller (davem@redhat.com)
9 *
10 * Fixed for multiple PCI buses, 1999 Andrea Arcangeli <andrea@suse.de>
11 *
12 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
13 *	     Resource sorting
14 */
15
16#include <linux/kernel.h>
17#include <linux/export.h>
18#include <linux/pci.h>
19#include <linux/errno.h>
20#include <linux/ioport.h>
21#include <linux/cache.h>
22#include <linux/slab.h>
23#include "pci.h"
24
25static void pci_std_update_resource(struct pci_dev *dev, int resno)
26{
27	struct pci_bus_region region;
28	bool disable;
29	u16 cmd;
30	u32 new, check, mask;
31	int reg;
32	struct resource *res = dev->resource + resno;
33
34	/* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
35	if (dev->is_virtfn)
36		return;
37
38	/*
39	 * Ignore resources for unimplemented BARs and unused resource slots
40	 * for 64 bit BARs.
41	 */
42	if (!res->flags)
43		return;
44
45	if (res->flags & IORESOURCE_UNSET)
46		return;
47
48	/*
49	 * Ignore non-moveable resources.  This might be legacy resources for
50	 * which no functional BAR register exists or another important
51	 * system resource we shouldn't move around.
52	 */
53	if (res->flags & IORESOURCE_PCI_FIXED)
54		return;
55
56	pcibios_resource_to_bus(dev->bus, &region, res);
57	new = region.start;
58
59	if (res->flags & IORESOURCE_IO) {
60		mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
61		new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK;
62	} else if (resno == PCI_ROM_RESOURCE) {
63		mask = PCI_ROM_ADDRESS_MASK;
64	} else {
65		mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
66		new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;
67	}
68
69	if (resno < PCI_ROM_RESOURCE) {
70		reg = PCI_BASE_ADDRESS_0 + 4 * resno;
71	} else if (resno == PCI_ROM_RESOURCE) {
72
73		/*
74		 * Apparently some Matrox devices have ROM BARs that read
75		 * as zero when disabled, so don't update ROM BARs unless
76		 * they're enabled.  See
77		 * https://lore.kernel.org/r/43147B3D.1030309@vc.cvut.cz/
78		 */
79		if (!(res->flags & IORESOURCE_ROM_ENABLE))
80			return;
81
82		reg = dev->rom_base_reg;
83		new |= PCI_ROM_ADDRESS_ENABLE;
84	} else
85		return;
86
87	/*
88	 * We can't update a 64-bit BAR atomically, so when possible,
89	 * disable decoding so that a half-updated BAR won't conflict
90	 * with another device.
91	 */
92	disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
93	if (disable) {
94		pci_read_config_word(dev, PCI_COMMAND, &cmd);
95		pci_write_config_word(dev, PCI_COMMAND,
96				      cmd & ~PCI_COMMAND_MEMORY);
97	}
98
99	pci_write_config_dword(dev, reg, new);
100	pci_read_config_dword(dev, reg, &check);
101
102	if ((new ^ check) & mask) {
103		pci_err(dev, "BAR %d: error updating (%#08x != %#08x)\n",
104			resno, new, check);
105	}
106
107	if (res->flags & IORESOURCE_MEM_64) {
108		new = region.start >> 16 >> 16;
109		pci_write_config_dword(dev, reg + 4, new);
110		pci_read_config_dword(dev, reg + 4, &check);
111		if (check != new) {
112			pci_err(dev, "BAR %d: error updating (high %#08x != %#08x)\n",
113				resno, new, check);
114		}
115	}
116
117	if (disable)
118		pci_write_config_word(dev, PCI_COMMAND, cmd);
119}
120
121void pci_update_resource(struct pci_dev *dev, int resno)
122{
123	if (resno <= PCI_ROM_RESOURCE)
124		pci_std_update_resource(dev, resno);
125#ifdef CONFIG_PCI_IOV
126	else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
127		pci_iov_update_resource(dev, resno);
128#endif
129}
130
131int pci_claim_resource(struct pci_dev *dev, int resource)
132{
133	struct resource *res = &dev->resource[resource];
134	struct resource *root, *conflict;
135
136	if (res->flags & IORESOURCE_UNSET) {
137		pci_info(dev, "can't claim BAR %d %pR: no address assigned\n",
138			 resource, res);
139		return -EINVAL;
140	}
141
142	/*
143	 * If we have a shadow copy in RAM, the PCI device doesn't respond
144	 * to the shadow range, so we don't need to claim it, and upstream
145	 * bridges don't need to route the range to the device.
146	 */
147	if (res->flags & IORESOURCE_ROM_SHADOW)
148		return 0;
149
150	root = pci_find_parent_resource(dev, res);
151	if (!root) {
152		pci_info(dev, "can't claim BAR %d %pR: no compatible bridge window\n",
153			 resource, res);
154		res->flags |= IORESOURCE_UNSET;
155		return -EINVAL;
156	}
157
158	conflict = request_resource_conflict(root, res);
159	if (conflict) {
160		pci_info(dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
161			 resource, res, conflict->name, conflict);
162		res->flags |= IORESOURCE_UNSET;
163		return -EBUSY;
164	}
165
166	return 0;
167}
168EXPORT_SYMBOL(pci_claim_resource);
169
170void pci_disable_bridge_window(struct pci_dev *dev)
171{
172	/* MMIO Base/Limit */
173	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
174
175	/* Prefetchable MMIO Base/Limit */
176	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
177	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
178	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
179}
180
181/*
182 * Generic function that returns a value indicating that the device's
183 * original BIOS BAR address was not saved and so is not available for
184 * reinstatement.
185 *
186 * Can be over-ridden by architecture specific code that implements
187 * reinstatement functionality rather than leaving it disabled when
188 * normal allocation attempts fail.
189 */
190resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
191{
192	return 0;
193}
194
195static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
196		int resno, resource_size_t size)
197{
198	struct resource *root, *conflict;
199	resource_size_t fw_addr, start, end;
200
201	fw_addr = pcibios_retrieve_fw_addr(dev, resno);
202	if (!fw_addr)
203		return -ENOMEM;
204
205	start = res->start;
206	end = res->end;
207	res->start = fw_addr;
208	res->end = res->start + size - 1;
209	res->flags &= ~IORESOURCE_UNSET;
210
211	root = pci_find_parent_resource(dev, res);
212	if (!root) {
213		/*
214		 * If dev is behind a bridge, accesses will only reach it
215		 * if res is inside the relevant bridge window.
216		 */
217		if (pci_upstream_bridge(dev))
218			return -ENXIO;
219
220		/*
221		 * On the root bus, assume the host bridge will forward
222		 * everything.
223		 */
224		if (res->flags & IORESOURCE_IO)
225			root = &ioport_resource;
226		else
227			root = &iomem_resource;
228	}
229
230	pci_info(dev, "BAR %d: trying firmware assignment %pR\n",
231		 resno, res);
232	conflict = request_resource_conflict(root, res);
233	if (conflict) {
234		pci_info(dev, "BAR %d: %pR conflicts with %s %pR\n",
235			 resno, res, conflict->name, conflict);
236		res->start = start;
237		res->end = end;
238		res->flags |= IORESOURCE_UNSET;
239		return -EBUSY;
240	}
241	return 0;
242}
243
244/*
245 * We don't have to worry about legacy ISA devices, so nothing to do here.
246 * This is marked as __weak because multiple architectures define it; it should
247 * eventually go away.
248 */
249resource_size_t __weak pcibios_align_resource(void *data,
250					      const struct resource *res,
251					      resource_size_t size,
252					      resource_size_t align)
253{
254       return res->start;
255}
256
257static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
258		int resno, resource_size_t size, resource_size_t align)
259{
260	struct resource *res = dev->resource + resno;
261	resource_size_t min;
262	int ret;
263
264	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
265
266	/*
267	 * First, try exact prefetching match.  Even if a 64-bit
268	 * prefetchable bridge window is below 4GB, we can't put a 32-bit
269	 * prefetchable resource in it because pbus_size_mem() assumes a
270	 * 64-bit window will contain no 32-bit resources.  If we assign
271	 * things differently than they were sized, not everything will fit.
272	 */
273	ret = pci_bus_alloc_resource(bus, res, size, align, min,
274				     IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
275				     pcibios_align_resource, dev);
276	if (ret == 0)
277		return 0;
278
279	/*
280	 * If the prefetchable window is only 32 bits wide, we can put
281	 * 64-bit prefetchable resources in it.
282	 */
283	if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
284	     (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
285		ret = pci_bus_alloc_resource(bus, res, size, align, min,
286					     IORESOURCE_PREFETCH,
287					     pcibios_align_resource, dev);
288		if (ret == 0)
289			return 0;
290	}
291
292	/*
293	 * If we didn't find a better match, we can put any memory resource
294	 * in a non-prefetchable window.  If this resource is 32 bits and
295	 * non-prefetchable, the first call already tried the only possibility
296	 * so we don't need to try again.
297	 */
298	if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
299		ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
300					     pcibios_align_resource, dev);
301
302	return ret;
303}
304
305static int _pci_assign_resource(struct pci_dev *dev, int resno,
306				resource_size_t size, resource_size_t min_align)
307{
308	struct pci_bus *bus;
309	int ret;
310
311	bus = dev->bus;
312	while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
313		if (!bus->parent || !bus->self->transparent)
314			break;
315		bus = bus->parent;
316	}
317
318	return ret;
319}
320
321int pci_assign_resource(struct pci_dev *dev, int resno)
322{
323	struct resource *res = dev->resource + resno;
324	resource_size_t align, size;
325	int ret;
326
327	if (res->flags & IORESOURCE_PCI_FIXED)
328		return 0;
329
330	res->flags |= IORESOURCE_UNSET;
331	align = pci_resource_alignment(dev, res);
332	if (!align) {
333		pci_info(dev, "BAR %d: can't assign %pR (bogus alignment)\n",
334			 resno, res);
335		return -EINVAL;
336	}
337
338	size = resource_size(res);
339	ret = _pci_assign_resource(dev, resno, size, align);
340
341	/*
342	 * If we failed to assign anything, let's try the address
343	 * where firmware left it.  That at least has a chance of
344	 * working, which is better than just leaving it disabled.
345	 */
346	if (ret < 0) {
347		pci_info(dev, "BAR %d: no space for %pR\n", resno, res);
348		ret = pci_revert_fw_address(res, dev, resno, size);
349	}
350
351	if (ret < 0) {
352		pci_info(dev, "BAR %d: failed to assign %pR\n", resno, res);
353		return ret;
354	}
355
356	res->flags &= ~IORESOURCE_UNSET;
357	res->flags &= ~IORESOURCE_STARTALIGN;
358	pci_info(dev, "BAR %d: assigned %pR\n", resno, res);
359	if (resno < PCI_BRIDGE_RESOURCES)
360		pci_update_resource(dev, resno);
361
362	return 0;
363}
364EXPORT_SYMBOL(pci_assign_resource);
365
366int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
367			resource_size_t min_align)
368{
369	struct resource *res = dev->resource + resno;
370	unsigned long flags;
371	resource_size_t new_size;
372	int ret;
373
374	if (res->flags & IORESOURCE_PCI_FIXED)
375		return 0;
376
377	flags = res->flags;
378	res->flags |= IORESOURCE_UNSET;
379	if (!res->parent) {
380		pci_info(dev, "BAR %d: can't reassign an unassigned resource %pR\n",
381			 resno, res);
382		return -EINVAL;
383	}
384
385	/* already aligned with min_align */
386	new_size = resource_size(res) + addsize;
387	ret = _pci_assign_resource(dev, resno, new_size, min_align);
388	if (ret) {
389		res->flags = flags;
390		pci_info(dev, "BAR %d: %pR (failed to expand by %#llx)\n",
391			 resno, res, (unsigned long long) addsize);
392		return ret;
393	}
394
395	res->flags &= ~IORESOURCE_UNSET;
396	res->flags &= ~IORESOURCE_STARTALIGN;
397	pci_info(dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
398		 resno, res, (unsigned long long) addsize);
399	if (resno < PCI_BRIDGE_RESOURCES)
400		pci_update_resource(dev, resno);
401
402	return 0;
403}
404
405void pci_release_resource(struct pci_dev *dev, int resno)
406{
407	struct resource *res = dev->resource + resno;
408
409	pci_info(dev, "BAR %d: releasing %pR\n", resno, res);
410
411	if (!res->parent)
412		return;
413
414	release_resource(res);
415	res->end = resource_size(res) - 1;
416	res->start = 0;
417	res->flags |= IORESOURCE_UNSET;
418}
419EXPORT_SYMBOL(pci_release_resource);
420
421int pci_resize_resource(struct pci_dev *dev, int resno, int size)
422{
423	struct resource *res = dev->resource + resno;
424	struct pci_host_bridge *host;
425	int old, ret;
426	u32 sizes;
427	u16 cmd;
428
429	/* Check if we must preserve the firmware's resource assignment */
430	host = pci_find_host_bridge(dev->bus);
431	if (host->preserve_config)
432		return -ENOTSUPP;
433
434	/* Make sure the resource isn't assigned before resizing it. */
435	if (!(res->flags & IORESOURCE_UNSET))
436		return -EBUSY;
437
438	pci_read_config_word(dev, PCI_COMMAND, &cmd);
439	if (cmd & PCI_COMMAND_MEMORY)
440		return -EBUSY;
441
442	sizes = pci_rebar_get_possible_sizes(dev, resno);
443	if (!sizes)
444		return -ENOTSUPP;
445
446	if (!(sizes & BIT(size)))
447		return -EINVAL;
448
449	old = pci_rebar_get_current_size(dev, resno);
450	if (old < 0)
451		return old;
452
453	ret = pci_rebar_set_size(dev, resno, size);
454	if (ret)
455		return ret;
456
457	res->end = res->start + pci_rebar_size_to_bytes(size) - 1;
458
459	/* Check if the new config works by trying to assign everything. */
460	if (dev->bus->self) {
461		ret = pci_reassign_bridge_resources(dev->bus->self, res->flags);
462		if (ret)
463			goto error_resize;
464	}
465	return 0;
466
467error_resize:
468	pci_rebar_set_size(dev, resno, old);
469	res->end = res->start + pci_rebar_size_to_bytes(old) - 1;
470	return ret;
471}
472EXPORT_SYMBOL(pci_resize_resource);
473
474int pci_enable_resources(struct pci_dev *dev, int mask)
475{
476	u16 cmd, old_cmd;
477	int i;
478	struct resource *r;
479
480	pci_read_config_word(dev, PCI_COMMAND, &cmd);
481	old_cmd = cmd;
482
483	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
484		if (!(mask & (1 << i)))
485			continue;
486
487		r = &dev->resource[i];
488
489		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
490			continue;
491		if ((i == PCI_ROM_RESOURCE) &&
492				(!(r->flags & IORESOURCE_ROM_ENABLE)))
493			continue;
494
495		if (r->flags & IORESOURCE_UNSET) {
496			pci_err(dev, "can't enable device: BAR %d %pR not assigned\n",
497				i, r);
498			return -EINVAL;
499		}
500
501		if (!r->parent) {
502			pci_err(dev, "can't enable device: BAR %d %pR not claimed\n",
503				i, r);
504			return -EINVAL;
505		}
506
507		if (r->flags & IORESOURCE_IO)
508			cmd |= PCI_COMMAND_IO;
509		if (r->flags & IORESOURCE_MEM)
510			cmd |= PCI_COMMAND_MEMORY;
511	}
512
513	if (cmd != old_cmd) {
514		pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
515		pci_write_config_word(dev, PCI_COMMAND, cmd);
516	}
517	return 0;
518}
519