1// SPDX-License-Identifier: GPL-2.0 2/* 3 * This file contains work-arounds for many known PCI hardware bugs. 4 * Devices present only on certain architectures (host bridges et cetera) 5 * should be handled in arch-specific code. 6 * 7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 8 * 9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 10 * 11 * Init/reset quirks for USB host controllers should be in the USB quirks 12 * file, where their drivers can use them. 13 */ 14 15#include <linux/types.h> 16#include <linux/kernel.h> 17#include <linux/export.h> 18#include <linux/pci.h> 19#include <linux/init.h> 20#include <linux/delay.h> 21#include <linux/acpi.h> 22#include <linux/dmi.h> 23#include <linux/ioport.h> 24#include <linux/sched.h> 25#include <linux/ktime.h> 26#include <linux/mm.h> 27#include <linux/nvme.h> 28#include <linux/platform_data/x86/apple.h> 29#include <linux/pm_runtime.h> 30#include <linux/suspend.h> 31#include <linux/switchtec.h> 32#include <linux/vgaarb.h> 33#include <asm/dma.h> /* isa_dma_bridge_buggy */ 34#include "pci.h" 35 36static ktime_t fixup_debug_start(struct pci_dev *dev, 37 void (*fn)(struct pci_dev *dev)) 38{ 39 if (initcall_debug) 40 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current)); 41 42 return ktime_get(); 43} 44 45static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, 46 void (*fn)(struct pci_dev *dev)) 47{ 48 ktime_t delta, rettime; 49 unsigned long long duration; 50 51 rettime = ktime_get(); 52 delta = ktime_sub(rettime, calltime); 53 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 54 if (initcall_debug || duration > 10000) 55 pci_info(dev, "%pS took %lld usecs\n", fn, duration); 56} 57 58static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 59 struct pci_fixup *end) 60{ 61 ktime_t calltime; 62 63 for (; f < end; f++) 64 if ((f->class == (u32) (dev->class >> f->class_shift) || 65 f->class == (u32) PCI_ANY_ID) && 66 (f->vendor == dev->vendor || 67 f->vendor == (u16) PCI_ANY_ID) && 68 (f->device == dev->device || 69 f->device == (u16) PCI_ANY_ID)) { 70 void (*hook)(struct pci_dev *dev); 71#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 72 hook = offset_to_ptr(&f->hook_offset); 73#else 74 hook = f->hook; 75#endif 76 calltime = fixup_debug_start(dev, hook); 77 hook(dev); 78 fixup_debug_report(dev, calltime, hook); 79 } 80} 81 82extern struct pci_fixup __start_pci_fixups_early[]; 83extern struct pci_fixup __end_pci_fixups_early[]; 84extern struct pci_fixup __start_pci_fixups_header[]; 85extern struct pci_fixup __end_pci_fixups_header[]; 86extern struct pci_fixup __start_pci_fixups_final[]; 87extern struct pci_fixup __end_pci_fixups_final[]; 88extern struct pci_fixup __start_pci_fixups_enable[]; 89extern struct pci_fixup __end_pci_fixups_enable[]; 90extern struct pci_fixup __start_pci_fixups_resume[]; 91extern struct pci_fixup __end_pci_fixups_resume[]; 92extern struct pci_fixup __start_pci_fixups_resume_early[]; 93extern struct pci_fixup __end_pci_fixups_resume_early[]; 94extern struct pci_fixup __start_pci_fixups_suspend[]; 95extern struct pci_fixup __end_pci_fixups_suspend[]; 96extern struct pci_fixup __start_pci_fixups_suspend_late[]; 97extern struct pci_fixup __end_pci_fixups_suspend_late[]; 98 99static bool pci_apply_fixup_final_quirks; 100 101void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 102{ 103 struct pci_fixup *start, *end; 104 105 switch (pass) { 106 case pci_fixup_early: 107 start = __start_pci_fixups_early; 108 end = __end_pci_fixups_early; 109 break; 110 111 case pci_fixup_header: 112 start = __start_pci_fixups_header; 113 end = __end_pci_fixups_header; 114 break; 115 116 case pci_fixup_final: 117 if (!pci_apply_fixup_final_quirks) 118 return; 119 start = __start_pci_fixups_final; 120 end = __end_pci_fixups_final; 121 break; 122 123 case pci_fixup_enable: 124 start = __start_pci_fixups_enable; 125 end = __end_pci_fixups_enable; 126 break; 127 128 case pci_fixup_resume: 129 start = __start_pci_fixups_resume; 130 end = __end_pci_fixups_resume; 131 break; 132 133 case pci_fixup_resume_early: 134 start = __start_pci_fixups_resume_early; 135 end = __end_pci_fixups_resume_early; 136 break; 137 138 case pci_fixup_suspend: 139 start = __start_pci_fixups_suspend; 140 end = __end_pci_fixups_suspend; 141 break; 142 143 case pci_fixup_suspend_late: 144 start = __start_pci_fixups_suspend_late; 145 end = __end_pci_fixups_suspend_late; 146 break; 147 148 default: 149 /* stupid compiler warning, you would think with an enum... */ 150 return; 151 } 152 pci_do_fixups(dev, start, end); 153} 154EXPORT_SYMBOL(pci_fixup_device); 155 156static int __init pci_apply_final_quirks(void) 157{ 158 struct pci_dev *dev = NULL; 159 u8 cls = 0; 160 u8 tmp; 161 162 if (pci_cache_line_size) 163 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2); 164 165 pci_apply_fixup_final_quirks = true; 166 for_each_pci_dev(dev) { 167 pci_fixup_device(pci_fixup_final, dev); 168 /* 169 * If arch hasn't set it explicitly yet, use the CLS 170 * value shared by all PCI devices. If there's a 171 * mismatch, fall back to the default value. 172 */ 173 if (!pci_cache_line_size) { 174 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 175 if (!cls) 176 cls = tmp; 177 if (!tmp || cls == tmp) 178 continue; 179 180 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n", 181 cls << 2, tmp << 2, 182 pci_dfl_cache_line_size << 2); 183 pci_cache_line_size = pci_dfl_cache_line_size; 184 } 185 } 186 187 if (!pci_cache_line_size) { 188 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2, 189 pci_dfl_cache_line_size << 2); 190 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 191 } 192 193 return 0; 194} 195fs_initcall_sync(pci_apply_final_quirks); 196 197/* 198 * Decoding should be disabled for a PCI device during BAR sizing to avoid 199 * conflict. But doing so may cause problems on host bridge and perhaps other 200 * key system devices. For devices that need to have mmio decoding always-on, 201 * we need to set the dev->mmio_always_on bit. 202 */ 203static void quirk_mmio_always_on(struct pci_dev *dev) 204{ 205 dev->mmio_always_on = 1; 206} 207DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 208 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 209 210static void aspeed_fixup_vgaarb(struct pci_dev *pdev) 211{ 212 struct pci_dev *bridge; 213 struct pci_bus *bus; 214 struct pci_dev *vdevp = NULL; 215 u16 config; 216 217 bus = pdev->bus; 218 bridge = bus->self; 219 220 /* Is VGA routed to us? */ 221 if (bridge && (pci_is_bridge(bridge))) { 222 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, &config); 223 224 /* Yes, this bridge is PCI bridge-to-bridge spec compliant, 225 * just return! 226 */ 227 if (config & PCI_BRIDGE_CTL_VGA) 228 return; 229 230 dev_warn(&pdev->dev, "VGA bridge control is not enabled\n"); 231 } 232 233 /* Just return if the system already have a default device */ 234 if (vga_default_device()) 235 return; 236 237 /* No default vga device */ 238 while ((vdevp = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, vdevp))) { 239 if (vdevp->vendor != 0x1a03) { 240 /* Have other vga devcie in the system, do nothing */ 241 dev_info(&pdev->dev, "Another boot vga device: 0x%x:0x%x\n", 242 vdevp->vendor, vdevp->device); 243 return; 244 } 245 } 246 247 vga_set_default_device(pdev); 248 249 dev_info(&pdev->dev, "Boot vga device set as 0x%x:0x%x\n", 250 pdev->vendor, pdev->device); 251} 252DECLARE_PCI_FIXUP_CLASS_FINAL(0x1a03, 0x2000, PCI_CLASS_DISPLAY_VGA, 8, aspeed_fixup_vgaarb); 253 254/* 255 * The Mellanox Tavor device gives false positive parity errors. Mark this 256 * device with a broken_parity_status to allow PCI scanning code to "skip" 257 * this now blacklisted device. 258 */ 259static void quirk_mellanox_tavor(struct pci_dev *dev) 260{ 261 dev->broken_parity_status = 1; /* This device gives false positives */ 262} 263DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor); 264DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor); 265 266/* 267 * Deal with broken BIOSes that neglect to enable passive release, 268 * which can cause problems in combination with the 82441FX/PPro MTRRs 269 */ 270static void quirk_passive_release(struct pci_dev *dev) 271{ 272 struct pci_dev *d = NULL; 273 unsigned char dlc; 274 275 /* 276 * We have to make sure a particular bit is set in the PIIX3 277 * ISA bridge, so we have to go out and find it. 278 */ 279 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 280 pci_read_config_byte(d, 0x82, &dlc); 281 if (!(dlc & 1<<1)) { 282 pci_info(d, "PIIX3: Enabling Passive Release\n"); 283 dlc |= 1<<1; 284 pci_write_config_byte(d, 0x82, dlc); 285 } 286 } 287} 288DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 289DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 290 291/* 292 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a 293 * workaround but VIA don't answer queries. If you happen to have good 294 * contacts at VIA ask them for me please -- Alan 295 * 296 * This appears to be BIOS not version dependent. So presumably there is a 297 * chipset level fix. 298 */ 299static void quirk_isa_dma_hangs(struct pci_dev *dev) 300{ 301 if (!isa_dma_bridge_buggy) { 302 isa_dma_bridge_buggy = 1; 303 pci_info(dev, "Activating ISA DMA hang workarounds\n"); 304 } 305} 306/* 307 * It's not totally clear which chipsets are the problematic ones. We know 308 * 82C586 and 82C596 variants are affected. 309 */ 310DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 311DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 312DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 313DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 314DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 315DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 316DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 317 318/* 319 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear 320 * for some HT machines to use C4 w/o hanging. 321 */ 322static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 323{ 324 u32 pmbase; 325 u16 pm1a; 326 327 pci_read_config_dword(dev, 0x40, &pmbase); 328 pmbase = pmbase & 0xff80; 329 pm1a = inw(pmbase); 330 331 if (pm1a & 0x10) { 332 pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); 333 outw(0x10, pmbase); 334 } 335} 336DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 337 338/* Chipsets where PCI->PCI transfers vanish or hang */ 339static void quirk_nopcipci(struct pci_dev *dev) 340{ 341 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 342 pci_info(dev, "Disabling direct PCI/PCI transfers\n"); 343 pci_pci_problems |= PCIPCI_FAIL; 344 } 345} 346DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 347DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 348 349static void quirk_nopciamd(struct pci_dev *dev) 350{ 351 u8 rev; 352 pci_read_config_byte(dev, 0x08, &rev); 353 if (rev == 0x13) { 354 /* Erratum 24 */ 355 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 356 pci_pci_problems |= PCIAGP_FAIL; 357 } 358} 359DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 360 361/* Triton requires workarounds to be used by the drivers */ 362static void quirk_triton(struct pci_dev *dev) 363{ 364 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 365 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 366 pci_pci_problems |= PCIPCI_TRITON; 367 } 368} 369DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 370DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 371DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 372DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 373 374/* 375 * VIA Apollo KT133 needs PCI latency patch 376 * Made according to a Windows driver-based patch by George E. Breese; 377 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 378 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on 379 * which Mr Breese based his work. 380 * 381 * Updated based on further information from the site and also on 382 * information provided by VIA 383 */ 384static void quirk_vialatency(struct pci_dev *dev) 385{ 386 struct pci_dev *p; 387 u8 busarb; 388 389 /* 390 * Ok, we have a potential problem chipset here. Now see if we have 391 * a buggy southbridge. 392 */ 393 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 394 if (p != NULL) { 395 396 /* 397 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; 398 * thanks Dan Hollis. 399 * Check for buggy part revisions 400 */ 401 if (p->revision < 0x40 || p->revision > 0x42) 402 goto exit; 403 } else { 404 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 405 if (p == NULL) /* No problem parts */ 406 goto exit; 407 408 /* Check for buggy part revisions */ 409 if (p->revision < 0x10 || p->revision > 0x12) 410 goto exit; 411 } 412 413 /* 414 * Ok we have the problem. Now set the PCI master grant to occur 415 * every master grant. The apparent bug is that under high PCI load 416 * (quite common in Linux of course) you can get data loss when the 417 * CPU is held off the bus for 3 bus master requests. This happens 418 * to include the IDE controllers.... 419 * 420 * VIA only apply this fix when an SB Live! is present but under 421 * both Linux and Windows this isn't enough, and we have seen 422 * corruption without SB Live! but with things like 3 UDMA IDE 423 * controllers. So we ignore that bit of the VIA recommendation.. 424 */ 425 pci_read_config_byte(dev, 0x76, &busarb); 426 427 /* 428 * Set bit 4 and bit 5 of byte 76 to 0x01 429 * "Master priority rotation on every PCI master grant" 430 */ 431 busarb &= ~(1<<5); 432 busarb |= (1<<4); 433 pci_write_config_byte(dev, 0x76, busarb); 434 pci_info(dev, "Applying VIA southbridge workaround\n"); 435exit: 436 pci_dev_put(p); 437} 438DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 439DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 440DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 441/* Must restore this on a resume from RAM */ 442DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 443DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 444DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 445 446/* VIA Apollo VP3 needs ETBF on BT848/878 */ 447static void quirk_viaetbf(struct pci_dev *dev) 448{ 449 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 450 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 451 pci_pci_problems |= PCIPCI_VIAETBF; 452 } 453} 454DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 455 456static void quirk_vsfx(struct pci_dev *dev) 457{ 458 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 459 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 460 pci_pci_problems |= PCIPCI_VSFX; 461 } 462} 463DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 464 465/* 466 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP 467 * space. Latency must be set to 0xA and Triton workaround applied too. 468 * [Info kindly provided by ALi] 469 */ 470static void quirk_alimagik(struct pci_dev *dev) 471{ 472 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 473 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 474 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 475 } 476} 477DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 478DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 479 480/* Natoma has some interesting boundary conditions with Zoran stuff at least */ 481static void quirk_natoma(struct pci_dev *dev) 482{ 483 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 484 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 485 pci_pci_problems |= PCIPCI_NATOMA; 486 } 487} 488DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 489DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 490DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 491DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 492DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 493DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 494 495/* 496 * This chip can cause PCI parity errors if config register 0xA0 is read 497 * while DMAs are occurring. 498 */ 499static void quirk_citrine(struct pci_dev *dev) 500{ 501 dev->cfg_size = 0xA0; 502} 503DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 504 505/* 506 * This chip can cause bus lockups if config addresses above 0x600 507 * are read or written. 508 */ 509static void quirk_nfp6000(struct pci_dev *dev) 510{ 511 dev->cfg_size = 0x600; 512} 513DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000); 514DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000); 515DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000); 516DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000); 517 518/* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ 519static void quirk_extend_bar_to_page(struct pci_dev *dev) 520{ 521 int i; 522 523 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 524 struct resource *r = &dev->resource[i]; 525 526 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { 527 r->end = PAGE_SIZE - 1; 528 r->start = 0; 529 r->flags |= IORESOURCE_UNSET; 530 pci_info(dev, "expanded BAR %d to page size: %pR\n", 531 i, r); 532 } 533 } 534} 535DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 536 537/* 538 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 539 * If it's needed, re-allocate the region. 540 */ 541static void quirk_s3_64M(struct pci_dev *dev) 542{ 543 struct resource *r = &dev->resource[0]; 544 545 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 546 r->flags |= IORESOURCE_UNSET; 547 r->start = 0; 548 r->end = 0x3ffffff; 549 } 550} 551DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 552DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 553 554static void quirk_io(struct pci_dev *dev, int pos, unsigned size, 555 const char *name) 556{ 557 u32 region; 558 struct pci_bus_region bus_region; 559 struct resource *res = dev->resource + pos; 560 561 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); 562 563 if (!region) 564 return; 565 566 res->name = pci_name(dev); 567 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; 568 res->flags |= 569 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); 570 region &= ~(size - 1); 571 572 /* Convert from PCI bus to resource space */ 573 bus_region.start = region; 574 bus_region.end = region + size - 1; 575 pcibios_bus_to_resource(dev->bus, res, &bus_region); 576 577 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", 578 name, PCI_BASE_ADDRESS_0 + (pos << 2), res); 579} 580 581/* 582 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 583 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 584 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 585 * (which conflicts w/ BAR1's memory range). 586 * 587 * CS553x's ISA PCI BARs may also be read-only (ref: 588 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). 589 */ 590static void quirk_cs5536_vsa(struct pci_dev *dev) 591{ 592 static char *name = "CS5536 ISA bridge"; 593 594 if (pci_resource_len(dev, 0) != 8) { 595 quirk_io(dev, 0, 8, name); /* SMB */ 596 quirk_io(dev, 1, 256, name); /* GPIO */ 597 quirk_io(dev, 2, 64, name); /* MFGPT */ 598 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n", 599 name); 600 } 601} 602DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 603 604static void quirk_io_region(struct pci_dev *dev, int port, 605 unsigned size, int nr, const char *name) 606{ 607 u16 region; 608 struct pci_bus_region bus_region; 609 struct resource *res = dev->resource + nr; 610 611 pci_read_config_word(dev, port, ®ion); 612 region &= ~(size - 1); 613 614 if (!region) 615 return; 616 617 res->name = pci_name(dev); 618 res->flags = IORESOURCE_IO; 619 620 /* Convert from PCI bus to resource space */ 621 bus_region.start = region; 622 bus_region.end = region + size - 1; 623 pcibios_bus_to_resource(dev->bus, res, &bus_region); 624 625 if (!pci_claim_resource(dev, nr)) 626 pci_info(dev, "quirk: %pR claimed by %s\n", res, name); 627} 628 629/* 630 * ATI Northbridge setups MCE the processor if you even read somewhere 631 * between 0x3b0->0x3bb or read 0x3d3 632 */ 633static void quirk_ati_exploding_mce(struct pci_dev *dev) 634{ 635 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 636 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 637 request_region(0x3b0, 0x0C, "RadeonIGP"); 638 request_region(0x3d3, 0x01, "RadeonIGP"); 639} 640DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 641 642/* 643 * In the AMD NL platform, this device ([1022:7912]) has a class code of 644 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 645 * claim it. The same applies on the VanGogh platform device ([1022:163a]). 646 * 647 * But the dwc3 driver is a more specific driver for this device, and we'd 648 * prefer to use it instead of xhci. To prevent xhci from claiming the 649 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 650 * defines as "USB device (not host controller)". The dwc3 driver can then 651 * claim it based on its Vendor and Device ID. 652 */ 653static void quirk_amd_dwc_class(struct pci_dev *pdev) 654{ 655 u32 class = pdev->class; 656 657 if (class != PCI_CLASS_SERIAL_USB_DEVICE) { 658 /* Use "USB Device (not host controller)" class */ 659 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 660 pci_info(pdev, 661 "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 662 class, pdev->class); 663 } 664} 665DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, 666 quirk_amd_dwc_class); 667DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VANGOGH_USB, 668 quirk_amd_dwc_class); 669 670/* 671 * Synopsys USB 3.x host HAPS platform has a class code of 672 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these 673 * devices should use dwc3-haps driver. Change these devices' class code to 674 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming 675 * them. 676 */ 677static void quirk_synopsys_haps(struct pci_dev *pdev) 678{ 679 u32 class = pdev->class; 680 681 switch (pdev->device) { 682 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3: 683 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI: 684 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31: 685 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 686 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 687 class, pdev->class); 688 break; 689 } 690} 691DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID, 692 PCI_CLASS_SERIAL_USB_XHCI, 0, 693 quirk_synopsys_haps); 694 695/* 696 * Let's make the southbridge information explicit instead of having to 697 * worry about people probing the ACPI areas, for example.. (Yes, it 698 * happens, and if you read the wrong ACPI register it will put the machine 699 * to sleep with no way of waking it up again. Bummer). 700 * 701 * ALI M7101: Two IO regions pointed to by words at 702 * 0xE0 (64 bytes of ACPI registers) 703 * 0xE2 (32 bytes of SMB registers) 704 */ 705static void quirk_ali7101_acpi(struct pci_dev *dev) 706{ 707 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 708 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 709} 710DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 711 712static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 713{ 714 u32 devres; 715 u32 mask, size, base; 716 717 pci_read_config_dword(dev, port, &devres); 718 if ((devres & enable) != enable) 719 return; 720 mask = (devres >> 16) & 15; 721 base = devres & 0xffff; 722 size = 16; 723 for (;;) { 724 unsigned bit = size >> 1; 725 if ((bit & mask) == bit) 726 break; 727 size = bit; 728 } 729 /* 730 * For now we only print it out. Eventually we'll want to 731 * reserve it (at least if it's in the 0x1000+ range), but 732 * let's get enough confirmation reports first. 733 */ 734 base &= -size; 735 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); 736} 737 738static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 739{ 740 u32 devres; 741 u32 mask, size, base; 742 743 pci_read_config_dword(dev, port, &devres); 744 if ((devres & enable) != enable) 745 return; 746 base = devres & 0xffff0000; 747 mask = (devres & 0x3f) << 16; 748 size = 128 << 16; 749 for (;;) { 750 unsigned bit = size >> 1; 751 if ((bit & mask) == bit) 752 break; 753 size = bit; 754 } 755 756 /* 757 * For now we only print it out. Eventually we'll want to 758 * reserve it, but let's get enough confirmation reports first. 759 */ 760 base &= -size; 761 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); 762} 763 764/* 765 * PIIX4 ACPI: Two IO regions pointed to by longwords at 766 * 0x40 (64 bytes of ACPI registers) 767 * 0x90 (16 bytes of SMB registers) 768 * and a few strange programmable PIIX4 device resources. 769 */ 770static void quirk_piix4_acpi(struct pci_dev *dev) 771{ 772 u32 res_a; 773 774 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 775 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 776 777 /* Device resource A has enables for some of the other ones */ 778 pci_read_config_dword(dev, 0x5c, &res_a); 779 780 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 781 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 782 783 /* Device resource D is just bitfields for static resources */ 784 785 /* Device 12 enabled? */ 786 if (res_a & (1 << 29)) { 787 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 788 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 789 } 790 /* Device 13 enabled? */ 791 if (res_a & (1 << 30)) { 792 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 793 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 794 } 795 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 796 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 797} 798DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 799DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 800 801#define ICH_PMBASE 0x40 802#define ICH_ACPI_CNTL 0x44 803#define ICH4_ACPI_EN 0x10 804#define ICH6_ACPI_EN 0x80 805#define ICH4_GPIOBASE 0x58 806#define ICH4_GPIO_CNTL 0x5c 807#define ICH4_GPIO_EN 0x10 808#define ICH6_GPIOBASE 0x48 809#define ICH6_GPIO_CNTL 0x4c 810#define ICH6_GPIO_EN 0x10 811 812/* 813 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 814 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 815 * 0x58 (64 bytes of GPIO I/O space) 816 */ 817static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 818{ 819 u8 enable; 820 821 /* 822 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 823 * with low legacy (and fixed) ports. We don't know the decoding 824 * priority and can't tell whether the legacy device or the one created 825 * here is really at that address. This happens on boards with broken 826 * BIOSes. 827 */ 828 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 829 if (enable & ICH4_ACPI_EN) 830 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 831 "ICH4 ACPI/GPIO/TCO"); 832 833 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 834 if (enable & ICH4_GPIO_EN) 835 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 836 "ICH4 GPIO"); 837} 838DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 839DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 840DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 841DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 842DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 843DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 844DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 845DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 846DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 847DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 848 849static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 850{ 851 u8 enable; 852 853 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 854 if (enable & ICH6_ACPI_EN) 855 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 856 "ICH6 ACPI/GPIO/TCO"); 857 858 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 859 if (enable & ICH6_GPIO_EN) 860 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 861 "ICH6 GPIO"); 862} 863 864static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, 865 const char *name, int dynsize) 866{ 867 u32 val; 868 u32 size, base; 869 870 pci_read_config_dword(dev, reg, &val); 871 872 /* Enabled? */ 873 if (!(val & 1)) 874 return; 875 base = val & 0xfffc; 876 if (dynsize) { 877 /* 878 * This is not correct. It is 16, 32 or 64 bytes depending on 879 * register D31:F0:ADh bits 5:4. 880 * 881 * But this gets us at least _part_ of it. 882 */ 883 size = 16; 884 } else { 885 size = 128; 886 } 887 base &= ~(size-1); 888 889 /* 890 * Just print it out for now. We should reserve it after more 891 * debugging. 892 */ 893 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 894} 895 896static void quirk_ich6_lpc(struct pci_dev *dev) 897{ 898 /* Shared ACPI/GPIO decode with all ICH6+ */ 899 ich6_lpc_acpi_gpio(dev); 900 901 /* ICH6-specific generic IO decode */ 902 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 903 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 904} 905DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 906DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 907 908static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, 909 const char *name) 910{ 911 u32 val; 912 u32 mask, base; 913 914 pci_read_config_dword(dev, reg, &val); 915 916 /* Enabled? */ 917 if (!(val & 1)) 918 return; 919 920 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ 921 base = val & 0xfffc; 922 mask = (val >> 16) & 0xfc; 923 mask |= 3; 924 925 /* 926 * Just print it out for now. We should reserve it after more 927 * debugging. 928 */ 929 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 930} 931 932/* ICH7-10 has the same common LPC generic IO decode registers */ 933static void quirk_ich7_lpc(struct pci_dev *dev) 934{ 935 /* We share the common ACPI/GPIO decode with ICH6 */ 936 ich6_lpc_acpi_gpio(dev); 937 938 /* And have 4 ICH7+ generic decodes */ 939 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 940 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 941 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 942 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 943} 944DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 945DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 946DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 947DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 948DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 949DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 950DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 951DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 952DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 953DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 954DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 955DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 956DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 957 958/* 959 * VIA ACPI: One IO region pointed to by longword at 960 * 0x48 or 0x20 (256 bytes of ACPI registers) 961 */ 962static void quirk_vt82c586_acpi(struct pci_dev *dev) 963{ 964 if (dev->revision & 0x10) 965 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, 966 "vt82c586 ACPI"); 967} 968DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 969 970/* 971 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 972 * 0x48 (256 bytes of ACPI registers) 973 * 0x70 (128 bytes of hardware monitoring register) 974 * 0x90 (16 bytes of SMB registers) 975 */ 976static void quirk_vt82c686_acpi(struct pci_dev *dev) 977{ 978 quirk_vt82c586_acpi(dev); 979 980 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, 981 "vt82c686 HW-mon"); 982 983 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); 984} 985DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 986 987/* 988 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 989 * 0x88 (128 bytes of power management registers) 990 * 0xd0 (16 bytes of SMB registers) 991 */ 992static void quirk_vt8235_acpi(struct pci_dev *dev) 993{ 994 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 995 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); 996} 997DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 998 999/* 1000 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast 1001 * back-to-back: Disable fast back-to-back on the secondary bus segment 1002 */ 1003static void quirk_xio2000a(struct pci_dev *dev) 1004{ 1005 struct pci_dev *pdev; 1006 u16 command; 1007 1008 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 1009 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 1010 pci_read_config_word(pdev, PCI_COMMAND, &command); 1011 if (command & PCI_COMMAND_FAST_BACK) 1012 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 1013 } 1014} 1015DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 1016 quirk_xio2000a); 1017 1018#ifdef CONFIG_X86_IO_APIC 1019 1020#include <asm/io_apic.h> 1021 1022/* 1023 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 1024 * devices to the external APIC. 1025 * 1026 * TODO: When we have device-specific interrupt routers, this code will go 1027 * away from quirks. 1028 */ 1029static void quirk_via_ioapic(struct pci_dev *dev) 1030{ 1031 u8 tmp; 1032 1033 if (nr_ioapics < 1) 1034 tmp = 0; /* nothing routed to external APIC */ 1035 else 1036 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 1037 1038 pci_info(dev, "%sbling VIA external APIC routing\n", 1039 tmp == 0 ? "Disa" : "Ena"); 1040 1041 /* Offset 0x58: External APIC IRQ output control */ 1042 pci_write_config_byte(dev, 0x58, tmp); 1043} 1044DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 1045DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 1046 1047/* 1048 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 1049 * This leads to doubled level interrupt rates. 1050 * Set this bit to get rid of cycle wastage. 1051 * Otherwise uncritical. 1052 */ 1053static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 1054{ 1055 u8 misc_control2; 1056#define BYPASS_APIC_DEASSERT 8 1057 1058 pci_read_config_byte(dev, 0x5B, &misc_control2); 1059 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 1060 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 1061 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 1062 } 1063} 1064DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1065DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1066 1067/* 1068 * The AMD IO-APIC can hang the box when an APIC IRQ is masked. 1069 * We check all revs >= B0 (yet not in the pre production!) as the bug 1070 * is currently marked NoFix 1071 * 1072 * We have multiple reports of hangs with this chipset that went away with 1073 * noapic specified. For the moment we assume it's the erratum. We may be wrong 1074 * of course. However the advice is demonstrably good even if so. 1075 */ 1076static void quirk_amd_ioapic(struct pci_dev *dev) 1077{ 1078 if (dev->revision >= 0x02) { 1079 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 1080 pci_warn(dev, " : booting with the \"noapic\" option\n"); 1081 } 1082} 1083DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 1084#endif /* CONFIG_X86_IO_APIC */ 1085 1086#if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS) 1087 1088static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) 1089{ 1090 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ 1091 if (dev->subsystem_device == 0xa118) 1092 dev->sriov->link = dev->devfn; 1093} 1094DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link); 1095#endif 1096 1097/* 1098 * Some settings of MMRBC can lead to data corruption so block changes. 1099 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 1100 */ 1101static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 1102{ 1103 if (dev->subordinate && dev->revision <= 0x12) { 1104 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 1105 dev->revision); 1106 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 1107 } 1108} 1109DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 1110 1111/* 1112 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up 1113 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register 1114 * at all. Therefore it seems like setting the pci_dev's IRQ to the value 1115 * of the ACPI SCI interrupt is only done for convenience. 1116 * -jgarzik 1117 */ 1118static void quirk_via_acpi(struct pci_dev *d) 1119{ 1120 u8 irq; 1121 1122 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ 1123 pci_read_config_byte(d, 0x42, &irq); 1124 irq &= 0xf; 1125 if (irq && (irq != 2)) 1126 d->irq = irq; 1127} 1128DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 1129DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 1130 1131/* VIA bridges which have VLink */ 1132static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 1133 1134static void quirk_via_bridge(struct pci_dev *dev) 1135{ 1136 /* See what bridge we have and find the device ranges */ 1137 switch (dev->device) { 1138 case PCI_DEVICE_ID_VIA_82C686: 1139 /* 1140 * The VT82C686 is special; it attaches to PCI and can have 1141 * any device number. All its subdevices are functions of 1142 * that single device. 1143 */ 1144 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 1145 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 1146 break; 1147 case PCI_DEVICE_ID_VIA_8237: 1148 case PCI_DEVICE_ID_VIA_8237A: 1149 via_vlink_dev_lo = 15; 1150 break; 1151 case PCI_DEVICE_ID_VIA_8235: 1152 via_vlink_dev_lo = 16; 1153 break; 1154 case PCI_DEVICE_ID_VIA_8231: 1155 case PCI_DEVICE_ID_VIA_8233_0: 1156 case PCI_DEVICE_ID_VIA_8233A: 1157 case PCI_DEVICE_ID_VIA_8233C_0: 1158 via_vlink_dev_lo = 17; 1159 break; 1160 } 1161} 1162DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 1163DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 1164DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 1165DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 1166DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 1167DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 1168DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 1169DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 1170 1171/* 1172 * quirk_via_vlink - VIA VLink IRQ number update 1173 * @dev: PCI device 1174 * 1175 * If the device we are dealing with is on a PIC IRQ we need to ensure that 1176 * the IRQ line register which usually is not relevant for PCI cards, is 1177 * actually written so that interrupts get sent to the right place. 1178 * 1179 * We only do this on systems where a VIA south bridge was detected, and 1180 * only for VIA devices on the motherboard (see quirk_via_bridge above). 1181 */ 1182static void quirk_via_vlink(struct pci_dev *dev) 1183{ 1184 u8 irq, new_irq; 1185 1186 /* Check if we have VLink at all */ 1187 if (via_vlink_dev_lo == -1) 1188 return; 1189 1190 new_irq = dev->irq; 1191 1192 /* Don't quirk interrupts outside the legacy IRQ range */ 1193 if (!new_irq || new_irq > 15) 1194 return; 1195 1196 /* Internal device ? */ 1197 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 1198 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 1199 return; 1200 1201 /* 1202 * This is an internal VLink device on a PIC interrupt. The BIOS 1203 * ought to have set this but may not have, so we redo it. 1204 */ 1205 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1206 if (new_irq != irq) { 1207 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", 1208 irq, new_irq); 1209 udelay(15); /* unknown if delay really needed */ 1210 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 1211 } 1212} 1213DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 1214 1215/* 1216 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID 1217 * of VT82C597 for backward compatibility. We need to switch it off to be 1218 * able to recognize the real type of the chip. 1219 */ 1220static void quirk_vt82c598_id(struct pci_dev *dev) 1221{ 1222 pci_write_config_byte(dev, 0xfc, 0); 1223 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 1224} 1225DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 1226 1227/* 1228 * CardBus controllers have a legacy base address that enables them to 1229 * respond as i82365 pcmcia controllers. We don't want them to do this 1230 * even if the Linux CardBus driver is not loaded, because the Linux i82365 1231 * driver does not (and should not) handle CardBus. 1232 */ 1233static void quirk_cardbus_legacy(struct pci_dev *dev) 1234{ 1235 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 1236} 1237DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1238 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1239DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 1240 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1241 1242/* 1243 * Following the PCI ordering rules is optional on the AMD762. I'm not sure 1244 * what the designers were smoking but let's not inhale... 1245 * 1246 * To be fair to AMD, it follows the spec by default, it's BIOS people who 1247 * turn it off! 1248 */ 1249static void quirk_amd_ordering(struct pci_dev *dev) 1250{ 1251 u32 pcic; 1252 pci_read_config_dword(dev, 0x4C, &pcic); 1253 if ((pcic & 6) != 6) { 1254 pcic |= 6; 1255 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 1256 pci_write_config_dword(dev, 0x4C, pcic); 1257 pci_read_config_dword(dev, 0x84, &pcic); 1258 pcic |= (1 << 23); /* Required in this mode */ 1259 pci_write_config_dword(dev, 0x84, pcic); 1260 } 1261} 1262DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1263DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1264 1265/* 1266 * DreamWorks-provided workaround for Dunord I-3000 problem 1267 * 1268 * This card decodes and responds to addresses not apparently assigned to 1269 * it. We force a larger allocation to ensure that nothing gets put too 1270 * close to it. 1271 */ 1272static void quirk_dunord(struct pci_dev *dev) 1273{ 1274 struct resource *r = &dev->resource[1]; 1275 1276 r->flags |= IORESOURCE_UNSET; 1277 r->start = 0; 1278 r->end = 0xffffff; 1279} 1280DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1281 1282/* 1283 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive 1284 * decoding (transparent), and does indicate this in the ProgIf. 1285 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01. 1286 */ 1287static void quirk_transparent_bridge(struct pci_dev *dev) 1288{ 1289 dev->transparent = 1; 1290} 1291DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1292DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1293 1294/* 1295 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce 1296 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets 1297 * found at http://www.national.com/analog for info on what these bits do. 1298 * <christer@weinigel.se> 1299 */ 1300static void quirk_mediagx_master(struct pci_dev *dev) 1301{ 1302 u8 reg; 1303 1304 pci_read_config_byte(dev, 0x41, ®); 1305 if (reg & 2) { 1306 reg &= ~2; 1307 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 1308 reg); 1309 pci_write_config_byte(dev, 0x41, reg); 1310 } 1311} 1312DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1313DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1314 1315/* 1316 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but 1317 * in the odd case it is not the results are corruption hence the presence 1318 * of a Linux check. 1319 */ 1320static void quirk_disable_pxb(struct pci_dev *pdev) 1321{ 1322 u16 config; 1323 1324 if (pdev->revision != 0x04) /* Only C0 requires this */ 1325 return; 1326 pci_read_config_word(pdev, 0x40, &config); 1327 if (config & (1<<6)) { 1328 config &= ~(1<<6); 1329 pci_write_config_word(pdev, 0x40, config); 1330 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1331 } 1332} 1333DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1334DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1335 1336static void quirk_amd_ide_mode(struct pci_dev *pdev) 1337{ 1338 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1339 u8 tmp; 1340 1341 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1342 if (tmp == 0x01) { 1343 pci_read_config_byte(pdev, 0x40, &tmp); 1344 pci_write_config_byte(pdev, 0x40, tmp|1); 1345 pci_write_config_byte(pdev, 0x9, 1); 1346 pci_write_config_byte(pdev, 0xa, 6); 1347 pci_write_config_byte(pdev, 0x40, tmp); 1348 1349 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1350 pci_info(pdev, "set SATA to AHCI mode\n"); 1351 } 1352} 1353DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1354DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1355DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1356DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1357DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1358DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1359DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1360DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1361 1362/* Serverworks CSB5 IDE does not fully support native mode */ 1363static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1364{ 1365 u8 prog; 1366 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1367 if (prog & 5) { 1368 prog &= ~5; 1369 pdev->class &= ~5; 1370 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1371 /* PCI layer will sort out resources */ 1372 } 1373} 1374DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1375 1376/* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */ 1377static void quirk_ide_samemode(struct pci_dev *pdev) 1378{ 1379 u8 prog; 1380 1381 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1382 1383 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1384 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n"); 1385 prog &= ~5; 1386 pdev->class &= ~5; 1387 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1388 } 1389} 1390DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1391 1392/* Some ATA devices break if put into D3 */ 1393static void quirk_no_ata_d3(struct pci_dev *pdev) 1394{ 1395 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1396} 1397/* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1398DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1399 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1400DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1401 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1402/* ALi loses some register settings that we cannot then restore */ 1403DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1404 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1405/* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1406 occur when mode detecting */ 1407DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1408 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1409 1410/* 1411 * This was originally an Alpha-specific thing, but it really fits here. 1412 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1413 */ 1414static void quirk_eisa_bridge(struct pci_dev *dev) 1415{ 1416 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1417} 1418DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1419 1420/* 1421 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1422 * is not activated. The myth is that Asus said that they do not want the 1423 * users to be irritated by just another PCI Device in the Win98 device 1424 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1425 * package 2.7.0 for details) 1426 * 1427 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1428 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1429 * becomes necessary to do this tweak in two steps -- the chosen trigger 1430 * is either the Host bridge (preferred) or on-board VGA controller. 1431 * 1432 * Note that we used to unhide the SMBus that way on Toshiba laptops 1433 * (Satellite A40 and Tecra M2) but then found that the thermal management 1434 * was done by SMM code, which could cause unsynchronized concurrent 1435 * accesses to the SMBus registers, with potentially bad effects. Thus you 1436 * should be very careful when adding new entries: if SMM is accessing the 1437 * Intel SMBus, this is a very good reason to leave it hidden. 1438 * 1439 * Likewise, many recent laptops use ACPI for thermal management. If the 1440 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1441 * natively, and keeping the SMBus hidden is the right thing to do. If you 1442 * are about to add an entry in the table below, please first disassemble 1443 * the DSDT and double-check that there is no code accessing the SMBus. 1444 */ 1445static int asus_hides_smbus; 1446 1447static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1448{ 1449 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1450 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1451 switch (dev->subsystem_device) { 1452 case 0x8025: /* P4B-LX */ 1453 case 0x8070: /* P4B */ 1454 case 0x8088: /* P4B533 */ 1455 case 0x1626: /* L3C notebook */ 1456 asus_hides_smbus = 1; 1457 } 1458 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1459 switch (dev->subsystem_device) { 1460 case 0x80b1: /* P4GE-V */ 1461 case 0x80b2: /* P4PE */ 1462 case 0x8093: /* P4B533-V */ 1463 asus_hides_smbus = 1; 1464 } 1465 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1466 switch (dev->subsystem_device) { 1467 case 0x8030: /* P4T533 */ 1468 asus_hides_smbus = 1; 1469 } 1470 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1471 switch (dev->subsystem_device) { 1472 case 0x8070: /* P4G8X Deluxe */ 1473 asus_hides_smbus = 1; 1474 } 1475 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1476 switch (dev->subsystem_device) { 1477 case 0x80c9: /* PU-DLS */ 1478 asus_hides_smbus = 1; 1479 } 1480 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1481 switch (dev->subsystem_device) { 1482 case 0x1751: /* M2N notebook */ 1483 case 0x1821: /* M5N notebook */ 1484 case 0x1897: /* A6L notebook */ 1485 asus_hides_smbus = 1; 1486 } 1487 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1488 switch (dev->subsystem_device) { 1489 case 0x184b: /* W1N notebook */ 1490 case 0x186a: /* M6Ne notebook */ 1491 asus_hides_smbus = 1; 1492 } 1493 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1494 switch (dev->subsystem_device) { 1495 case 0x80f2: /* P4P800-X */ 1496 asus_hides_smbus = 1; 1497 } 1498 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1499 switch (dev->subsystem_device) { 1500 case 0x1882: /* M6V notebook */ 1501 case 0x1977: /* A6VA notebook */ 1502 asus_hides_smbus = 1; 1503 } 1504 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1505 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1506 switch (dev->subsystem_device) { 1507 case 0x088C: /* HP Compaq nc8000 */ 1508 case 0x0890: /* HP Compaq nc6000 */ 1509 asus_hides_smbus = 1; 1510 } 1511 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1512 switch (dev->subsystem_device) { 1513 case 0x12bc: /* HP D330L */ 1514 case 0x12bd: /* HP D530 */ 1515 case 0x006a: /* HP Compaq nx9500 */ 1516 asus_hides_smbus = 1; 1517 } 1518 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1519 switch (dev->subsystem_device) { 1520 case 0x12bf: /* HP xw4100 */ 1521 asus_hides_smbus = 1; 1522 } 1523 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1524 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1525 switch (dev->subsystem_device) { 1526 case 0xC00C: /* Samsung P35 notebook */ 1527 asus_hides_smbus = 1; 1528 } 1529 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1530 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1531 switch (dev->subsystem_device) { 1532 case 0x0058: /* Compaq Evo N620c */ 1533 asus_hides_smbus = 1; 1534 } 1535 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1536 switch (dev->subsystem_device) { 1537 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1538 /* Motherboard doesn't have Host bridge 1539 * subvendor/subdevice IDs, therefore checking 1540 * its on-board VGA controller */ 1541 asus_hides_smbus = 1; 1542 } 1543 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1544 switch (dev->subsystem_device) { 1545 case 0x00b8: /* Compaq Evo D510 CMT */ 1546 case 0x00b9: /* Compaq Evo D510 SFF */ 1547 case 0x00ba: /* Compaq Evo D510 USDT */ 1548 /* Motherboard doesn't have Host bridge 1549 * subvendor/subdevice IDs and on-board VGA 1550 * controller is disabled if an AGP card is 1551 * inserted, therefore checking USB UHCI 1552 * Controller #1 */ 1553 asus_hides_smbus = 1; 1554 } 1555 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1556 switch (dev->subsystem_device) { 1557 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1558 /* Motherboard doesn't have host bridge 1559 * subvendor/subdevice IDs, therefore checking 1560 * its on-board VGA controller */ 1561 asus_hides_smbus = 1; 1562 } 1563 } 1564} 1565DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1566DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1567DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1568DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1569DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1570DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1571DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1572DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1573DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1574DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1575 1576DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1577DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1578DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1579 1580static void asus_hides_smbus_lpc(struct pci_dev *dev) 1581{ 1582 u16 val; 1583 1584 if (likely(!asus_hides_smbus)) 1585 return; 1586 1587 pci_read_config_word(dev, 0xF2, &val); 1588 if (val & 0x8) { 1589 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1590 pci_read_config_word(dev, 0xF2, &val); 1591 if (val & 0x8) 1592 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1593 val); 1594 else 1595 pci_info(dev, "Enabled i801 SMBus device\n"); 1596 } 1597} 1598DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1599DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1600DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1601DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1602DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1603DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1604DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1605DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1606DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1607DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1608DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1609DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1610DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1611DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1612 1613/* It appears we just have one such device. If not, we have a warning */ 1614static void __iomem *asus_rcba_base; 1615static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1616{ 1617 u32 rcba; 1618 1619 if (likely(!asus_hides_smbus)) 1620 return; 1621 WARN_ON(asus_rcba_base); 1622 1623 pci_read_config_dword(dev, 0xF0, &rcba); 1624 /* use bits 31:14, 16 kB aligned */ 1625 asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000); 1626 if (asus_rcba_base == NULL) 1627 return; 1628} 1629 1630static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1631{ 1632 u32 val; 1633 1634 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1635 return; 1636 1637 /* read the Function Disable register, dword mode only */ 1638 val = readl(asus_rcba_base + 0x3418); 1639 1640 /* enable the SMBus device */ 1641 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); 1642} 1643 1644static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1645{ 1646 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1647 return; 1648 1649 iounmap(asus_rcba_base); 1650 asus_rcba_base = NULL; 1651 pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); 1652} 1653 1654static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1655{ 1656 asus_hides_smbus_lpc_ich6_suspend(dev); 1657 asus_hides_smbus_lpc_ich6_resume_early(dev); 1658 asus_hides_smbus_lpc_ich6_resume(dev); 1659} 1660DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1661DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1662DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1663DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1664 1665/* SiS 96x south bridge: BIOS typically hides SMBus device... */ 1666static void quirk_sis_96x_smbus(struct pci_dev *dev) 1667{ 1668 u8 val = 0; 1669 pci_read_config_byte(dev, 0x77, &val); 1670 if (val & 0x10) { 1671 pci_info(dev, "Enabling SiS 96x SMBus\n"); 1672 pci_write_config_byte(dev, 0x77, val & ~0x10); 1673 } 1674} 1675DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1676DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1677DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1678DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1679DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1680DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1681DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1682DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1683 1684/* 1685 * ... This is further complicated by the fact that some SiS96x south 1686 * bridges pretend to be 85C503/5513 instead. In that case see if we 1687 * spotted a compatible north bridge to make sure. 1688 * (pci_find_device() doesn't work yet) 1689 * 1690 * We can also enable the sis96x bit in the discovery register.. 1691 */ 1692#define SIS_DETECT_REGISTER 0x40 1693 1694static void quirk_sis_503(struct pci_dev *dev) 1695{ 1696 u8 reg; 1697 u16 devid; 1698 1699 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1700 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1701 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1702 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1703 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1704 return; 1705 } 1706 1707 /* 1708 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case 1709 * it has already been processed. (Depends on link order, which is 1710 * apparently not guaranteed) 1711 */ 1712 dev->device = devid; 1713 quirk_sis_96x_smbus(dev); 1714} 1715DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1716DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1717 1718/* 1719 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1720 * and MC97 modem controller are disabled when a second PCI soundcard is 1721 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1722 * -- bjd 1723 */ 1724static void asus_hides_ac97_lpc(struct pci_dev *dev) 1725{ 1726 u8 val; 1727 int asus_hides_ac97 = 0; 1728 1729 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1730 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1731 asus_hides_ac97 = 1; 1732 } 1733 1734 if (!asus_hides_ac97) 1735 return; 1736 1737 pci_read_config_byte(dev, 0x50, &val); 1738 if (val & 0xc0) { 1739 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1740 pci_read_config_byte(dev, 0x50, &val); 1741 if (val & 0xc0) 1742 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1743 val); 1744 else 1745 pci_info(dev, "Enabled onboard AC97/MC97 devices\n"); 1746 } 1747} 1748DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1749DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1750 1751#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1752 1753/* 1754 * If we are using libata we can drive this chip properly but must do this 1755 * early on to make the additional device appear during the PCI scanning. 1756 */ 1757static void quirk_jmicron_ata(struct pci_dev *pdev) 1758{ 1759 u32 conf1, conf5, class; 1760 u8 hdr; 1761 1762 /* Only poke fn 0 */ 1763 if (PCI_FUNC(pdev->devfn)) 1764 return; 1765 1766 pci_read_config_dword(pdev, 0x40, &conf1); 1767 pci_read_config_dword(pdev, 0x80, &conf5); 1768 1769 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1770 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1771 1772 switch (pdev->device) { 1773 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1774 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1775 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1776 /* The controller should be in single function ahci mode */ 1777 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1778 break; 1779 1780 case PCI_DEVICE_ID_JMICRON_JMB365: 1781 case PCI_DEVICE_ID_JMICRON_JMB366: 1782 /* Redirect IDE second PATA port to the right spot */ 1783 conf5 |= (1 << 24); 1784 fallthrough; 1785 case PCI_DEVICE_ID_JMICRON_JMB361: 1786 case PCI_DEVICE_ID_JMICRON_JMB363: 1787 case PCI_DEVICE_ID_JMICRON_JMB369: 1788 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1789 /* Set the class codes correctly and then direct IDE 0 */ 1790 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1791 break; 1792 1793 case PCI_DEVICE_ID_JMICRON_JMB368: 1794 /* The controller should be in single function IDE mode */ 1795 conf1 |= 0x00C00000; /* Set 22, 23 */ 1796 break; 1797 } 1798 1799 pci_write_config_dword(pdev, 0x40, conf1); 1800 pci_write_config_dword(pdev, 0x80, conf5); 1801 1802 /* Update pdev accordingly */ 1803 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1804 pdev->hdr_type = hdr & 0x7f; 1805 pdev->multifunction = !!(hdr & 0x80); 1806 1807 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1808 pdev->class = class >> 8; 1809} 1810DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1811DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1812DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1813DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1814DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1815DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1816DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1817DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1818DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1819DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1820DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1821DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1822DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1823DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1824DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1825DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1826DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1827DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1828 1829#endif 1830 1831static void quirk_jmicron_async_suspend(struct pci_dev *dev) 1832{ 1833 if (dev->multifunction) { 1834 device_disable_async_suspend(&dev->dev); 1835 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); 1836 } 1837} 1838DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); 1839DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); 1840DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); 1841DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); 1842 1843#ifdef CONFIG_X86_IO_APIC 1844static void quirk_alder_ioapic(struct pci_dev *pdev) 1845{ 1846 int i; 1847 1848 if ((pdev->class >> 8) != 0xff00) 1849 return; 1850 1851 /* 1852 * The first BAR is the location of the IO-APIC... we must 1853 * not touch this (and it's already covered by the fixmap), so 1854 * forcibly insert it into the resource tree. 1855 */ 1856 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1857 insert_resource(&iomem_resource, &pdev->resource[0]); 1858 1859 /* 1860 * The next five BARs all seem to be rubbish, so just clean 1861 * them out. 1862 */ 1863 for (i = 1; i < PCI_STD_NUM_BARS; i++) 1864 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1865} 1866DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1867#endif 1868 1869static void quirk_no_msi(struct pci_dev *dev) 1870{ 1871 pci_info(dev, "avoiding MSI to work around a hardware defect\n"); 1872 dev->no_msi = 1; 1873} 1874DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi); 1875DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi); 1876DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi); 1877DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi); 1878DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi); 1879DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi); 1880 1881static void quirk_pcie_mch(struct pci_dev *pdev) 1882{ 1883 pdev->no_msi = 1; 1884} 1885DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1886DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1887DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1888 1889DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch); 1890 1891/* 1892 * It's possible for the MSI to get corrupted if SHPC and ACPI are used 1893 * together on certain PXH-based systems. 1894 */ 1895static void quirk_pcie_pxh(struct pci_dev *dev) 1896{ 1897 dev->no_msi = 1; 1898 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); 1899} 1900DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1901DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1902DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1903DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1904DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1905 1906/* 1907 * Some Intel PCI Express chipsets have trouble with downstream device 1908 * power management. 1909 */ 1910static void quirk_intel_pcie_pm(struct pci_dev *dev) 1911{ 1912 pci_pm_d3hot_delay = 120; 1913 dev->no_d1d2 = 1; 1914} 1915DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 1916DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 1917DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 1918DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 1919DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 1920DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 1921DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 1922DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 1923DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 1924DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 1925DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 1926DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 1927DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 1928DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 1929DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 1930DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 1931DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 1932DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 1933DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 1934DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1935DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1936 1937static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay) 1938{ 1939 if (dev->d3hot_delay >= delay) 1940 return; 1941 1942 dev->d3hot_delay = delay; 1943 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", 1944 dev->d3hot_delay); 1945} 1946 1947static void quirk_radeon_pm(struct pci_dev *dev) 1948{ 1949 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 1950 dev->subsystem_device == 0x00e2) 1951 quirk_d3hot_delay(dev, 20); 1952} 1953DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); 1954 1955/* 1956 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle. 1957 * https://bugzilla.kernel.org/show_bug.cgi?id=205587 1958 * 1959 * The kernel attempts to transition these devices to D3cold, but that seems 1960 * to be ineffective on the platforms in question; the PCI device appears to 1961 * remain on in D3hot state. The D3hot-to-D0 transition then requires an 1962 * extended delay in order to succeed. 1963 */ 1964static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev) 1965{ 1966 quirk_d3hot_delay(dev, 20); 1967} 1968DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot); 1969DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot); 1970DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot); 1971 1972#ifdef CONFIG_X86_IO_APIC 1973static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) 1974{ 1975 noioapicreroute = 1; 1976 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); 1977 1978 return 0; 1979} 1980 1981static const struct dmi_system_id boot_interrupt_dmi_table[] = { 1982 /* 1983 * Systems to exclude from boot interrupt reroute quirks 1984 */ 1985 { 1986 .callback = dmi_disable_ioapicreroute, 1987 .ident = "ASUSTek Computer INC. M2N-LR", 1988 .matches = { 1989 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."), 1990 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"), 1991 }, 1992 }, 1993 {} 1994}; 1995 1996/* 1997 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 1998 * remap the original interrupt in the Linux kernel to the boot interrupt, so 1999 * that a PCI device's interrupt handler is installed on the boot interrupt 2000 * line instead. 2001 */ 2002static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 2003{ 2004 dmi_check_system(boot_interrupt_dmi_table); 2005 if (noioapicquirk || noioapicreroute) 2006 return; 2007 2008 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 2009 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n", 2010 dev->vendor, dev->device); 2011} 2012DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 2013DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 2014DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 2015DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 2016DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 2017DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 2018DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 2019DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 2020DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 2021DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 2022DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 2023DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 2024DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 2025DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 2026DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 2027DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 2028 2029/* 2030 * On some chipsets we can disable the generation of legacy INTx boot 2031 * interrupts. 2032 */ 2033 2034/* 2035 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no 2036 * 300641-004US, section 5.7.3. 2037 * 2038 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003. 2039 * Core IO on Xeon E5 v2, see Intel order no 329188-003. 2040 * Core IO on Xeon E7 v2, see Intel order no 329595-002. 2041 * Core IO on Xeon E5 v3, see Intel order no 330784-003. 2042 * Core IO on Xeon E7 v3, see Intel order no 332315-001US. 2043 * Core IO on Xeon E5 v4, see Intel order no 333810-002US. 2044 * Core IO on Xeon E7 v4, see Intel order no 332315-001US. 2045 * Core IO on Xeon D-1500, see Intel order no 332051-001. 2046 * Core IO on Xeon Scalable, see Intel order no 610950. 2047 */ 2048#define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */ 2049#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 2050 2051#define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */ 2052#define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25) 2053 2054static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 2055{ 2056 u16 pci_config_word; 2057 u32 pci_config_dword; 2058 2059 if (noioapicquirk) 2060 return; 2061 2062 switch (dev->device) { 2063 case PCI_DEVICE_ID_INTEL_ESB_10: 2064 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2065 &pci_config_word); 2066 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 2067 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2068 pci_config_word); 2069 break; 2070 case 0x3c28: /* Xeon E5 1600/2600/4600 */ 2071 case 0x0e28: /* Xeon E5/E7 V2 */ 2072 case 0x2f28: /* Xeon E5/E7 V3,V4 */ 2073 case 0x6f28: /* Xeon D-1500 */ 2074 case 0x2034: /* Xeon Scalable Family */ 2075 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2076 &pci_config_dword); 2077 pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH; 2078 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2079 pci_config_dword); 2080 break; 2081 default: 2082 return; 2083 } 2084 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2085 dev->vendor, dev->device); 2086} 2087/* 2088 * Device 29 Func 5 Device IDs of IO-APIC 2089 * containing ABAR—APIC1 Alternate Base Address Register 2090 */ 2091DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2092 quirk_disable_intel_boot_interrupt); 2093DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2094 quirk_disable_intel_boot_interrupt); 2095 2096/* 2097 * Device 5 Func 0 Device IDs of Core IO modules/hubs 2098 * containing Coherent Interface Protocol Interrupt Control 2099 * 2100 * Device IDs obtained from volume 2 datasheets of commented 2101 * families above. 2102 */ 2103DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28, 2104 quirk_disable_intel_boot_interrupt); 2105DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28, 2106 quirk_disable_intel_boot_interrupt); 2107DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28, 2108 quirk_disable_intel_boot_interrupt); 2109DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28, 2110 quirk_disable_intel_boot_interrupt); 2111DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034, 2112 quirk_disable_intel_boot_interrupt); 2113DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28, 2114 quirk_disable_intel_boot_interrupt); 2115DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28, 2116 quirk_disable_intel_boot_interrupt); 2117DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28, 2118 quirk_disable_intel_boot_interrupt); 2119DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28, 2120 quirk_disable_intel_boot_interrupt); 2121DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034, 2122 quirk_disable_intel_boot_interrupt); 2123 2124/* Disable boot interrupts on HT-1000 */ 2125#define BC_HT1000_FEATURE_REG 0x64 2126#define BC_HT1000_PIC_REGS_ENABLE (1<<0) 2127#define BC_HT1000_MAP_IDX 0xC00 2128#define BC_HT1000_MAP_DATA 0xC01 2129 2130static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 2131{ 2132 u32 pci_config_dword; 2133 u8 irq; 2134 2135 if (noioapicquirk) 2136 return; 2137 2138 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 2139 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 2140 BC_HT1000_PIC_REGS_ENABLE); 2141 2142 for (irq = 0x10; irq < 0x10 + 32; irq++) { 2143 outb(irq, BC_HT1000_MAP_IDX); 2144 outb(0x00, BC_HT1000_MAP_DATA); 2145 } 2146 2147 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 2148 2149 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2150 dev->vendor, dev->device); 2151} 2152DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2153DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2154 2155/* Disable boot interrupts on AMD and ATI chipsets */ 2156 2157/* 2158 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 2159 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 2160 * (due to an erratum). 2161 */ 2162#define AMD_813X_MISC 0x40 2163#define AMD_813X_NOIOAMODE (1<<0) 2164#define AMD_813X_REV_B1 0x12 2165#define AMD_813X_REV_B2 0x13 2166 2167static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 2168{ 2169 u32 pci_config_dword; 2170 2171 if (noioapicquirk) 2172 return; 2173 if ((dev->revision == AMD_813X_REV_B1) || 2174 (dev->revision == AMD_813X_REV_B2)) 2175 return; 2176 2177 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 2178 pci_config_dword &= ~AMD_813X_NOIOAMODE; 2179 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 2180 2181 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2182 dev->vendor, dev->device); 2183} 2184DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2185DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2186DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2187DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2188 2189#define AMD_8111_PCI_IRQ_ROUTING 0x56 2190 2191static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 2192{ 2193 u16 pci_config_word; 2194 2195 if (noioapicquirk) 2196 return; 2197 2198 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 2199 if (!pci_config_word) { 2200 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n", 2201 dev->vendor, dev->device); 2202 return; 2203 } 2204 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 2205 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2206 dev->vendor, dev->device); 2207} 2208DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2209DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2210#endif /* CONFIG_X86_IO_APIC */ 2211 2212/* 2213 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 2214 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 2215 * Re-allocate the region if needed... 2216 */ 2217static void quirk_tc86c001_ide(struct pci_dev *dev) 2218{ 2219 struct resource *r = &dev->resource[0]; 2220 2221 if (r->start & 0x8) { 2222 r->flags |= IORESOURCE_UNSET; 2223 r->start = 0; 2224 r->end = 0xf; 2225 } 2226} 2227DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 2228 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 2229 quirk_tc86c001_ide); 2230 2231/* 2232 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the 2233 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 2234 * being read correctly if bit 7 of the base address is set. 2235 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 2236 * Re-allocate the regions to a 256-byte boundary if necessary. 2237 */ 2238static void quirk_plx_pci9050(struct pci_dev *dev) 2239{ 2240 unsigned int bar; 2241 2242 /* Fixed in revision 2 (PCI 9052). */ 2243 if (dev->revision >= 2) 2244 return; 2245 for (bar = 0; bar <= 1; bar++) 2246 if (pci_resource_len(dev, bar) == 0x80 && 2247 (pci_resource_start(dev, bar) & 0x80)) { 2248 struct resource *r = &dev->resource[bar]; 2249 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 2250 bar); 2251 r->flags |= IORESOURCE_UNSET; 2252 r->start = 0; 2253 r->end = 0xff; 2254 } 2255} 2256DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 2257 quirk_plx_pci9050); 2258/* 2259 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) 2260 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, 2261 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, 2262 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. 2263 * 2264 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" 2265 * driver. 2266 */ 2267DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); 2268DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); 2269 2270static void quirk_netmos(struct pci_dev *dev) 2271{ 2272 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 2273 unsigned int num_serial = dev->subsystem_device & 0xf; 2274 2275 /* 2276 * These Netmos parts are multiport serial devices with optional 2277 * parallel ports. Even when parallel ports are present, they 2278 * are identified as class SERIAL, which means the serial driver 2279 * will claim them. To prevent this, mark them as class OTHER. 2280 * These combo devices should be claimed by parport_serial. 2281 * 2282 * The subdevice ID is of the form 0x00PS, where <P> is the number 2283 * of parallel ports and <S> is the number of serial ports. 2284 */ 2285 switch (dev->device) { 2286 case PCI_DEVICE_ID_NETMOS_9835: 2287 /* Well, this rule doesn't hold for the following 9835 device */ 2288 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 2289 dev->subsystem_device == 0x0299) 2290 return; 2291 fallthrough; 2292 case PCI_DEVICE_ID_NETMOS_9735: 2293 case PCI_DEVICE_ID_NETMOS_9745: 2294 case PCI_DEVICE_ID_NETMOS_9845: 2295 case PCI_DEVICE_ID_NETMOS_9855: 2296 if (num_parallel) { 2297 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 2298 dev->device, num_parallel, num_serial); 2299 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 2300 (dev->class & 0xff); 2301 } 2302 } 2303} 2304DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 2305 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 2306 2307static void quirk_e100_interrupt(struct pci_dev *dev) 2308{ 2309 u16 command, pmcsr; 2310 u8 __iomem *csr; 2311 u8 cmd_hi; 2312 2313 switch (dev->device) { 2314 /* PCI IDs taken from drivers/net/e100.c */ 2315 case 0x1029: 2316 case 0x1030 ... 0x1034: 2317 case 0x1038 ... 0x103E: 2318 case 0x1050 ... 0x1057: 2319 case 0x1059: 2320 case 0x1064 ... 0x106B: 2321 case 0x1091 ... 0x1095: 2322 case 0x1209: 2323 case 0x1229: 2324 case 0x2449: 2325 case 0x2459: 2326 case 0x245D: 2327 case 0x27DC: 2328 break; 2329 default: 2330 return; 2331 } 2332 2333 /* 2334 * Some firmware hands off the e100 with interrupts enabled, 2335 * which can cause a flood of interrupts if packets are 2336 * received before the driver attaches to the device. So 2337 * disable all e100 interrupts here. The driver will 2338 * re-enable them when it's ready. 2339 */ 2340 pci_read_config_word(dev, PCI_COMMAND, &command); 2341 2342 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 2343 return; 2344 2345 /* 2346 * Check that the device is in the D0 power state. If it's not, 2347 * there is no point to look any further. 2348 */ 2349 if (dev->pm_cap) { 2350 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 2351 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 2352 return; 2353 } 2354 2355 /* Convert from PCI bus to resource space. */ 2356 csr = ioremap(pci_resource_start(dev, 0), 8); 2357 if (!csr) { 2358 pci_warn(dev, "Can't map e100 registers\n"); 2359 return; 2360 } 2361 2362 cmd_hi = readb(csr + 3); 2363 if (cmd_hi == 0) { 2364 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n"); 2365 writeb(1, csr + 3); 2366 } 2367 2368 iounmap(csr); 2369} 2370DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 2371 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 2372 2373/* 2374 * The 82575 and 82598 may experience data corruption issues when transitioning 2375 * out of L0S. To prevent this we need to disable L0S on the PCIe link. 2376 */ 2377static void quirk_disable_aspm_l0s(struct pci_dev *dev) 2378{ 2379 pci_info(dev, "Disabling L0s\n"); 2380 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 2381} 2382DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 2383DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 2384DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 2385DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 2386DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 2387DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 2388DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 2389DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 2390DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 2391DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 2392DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 2393DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 2394DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 2395DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 2396 2397static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev) 2398{ 2399 pci_info(dev, "Disabling ASPM L0s/L1\n"); 2400 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); 2401} 2402 2403/* 2404 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the 2405 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected; 2406 * disable both L0s and L1 for now to be safe. 2407 */ 2408DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1); 2409 2410/* 2411 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain 2412 * Link bit cleared after starting the link retrain process to allow this 2413 * process to finish. 2414 * 2415 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the 2416 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf. 2417 */ 2418static void quirk_enable_clear_retrain_link(struct pci_dev *dev) 2419{ 2420 dev->clear_retrain_link = 1; 2421 pci_info(dev, "Enable PCIe Retrain Link quirk\n"); 2422} 2423DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe110, quirk_enable_clear_retrain_link); 2424DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe111, quirk_enable_clear_retrain_link); 2425DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe130, quirk_enable_clear_retrain_link); 2426 2427static void fixup_rev1_53c810(struct pci_dev *dev) 2428{ 2429 u32 class = dev->class; 2430 2431 /* 2432 * rev 1 ncr53c810 chips don't set the class at all which means 2433 * they don't get their resources remapped. Fix that here. 2434 */ 2435 if (class) 2436 return; 2437 2438 dev->class = PCI_CLASS_STORAGE_SCSI << 8; 2439 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", 2440 class, dev->class); 2441} 2442DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 2443 2444/* Enable 1k I/O space granularity on the Intel P64H2 */ 2445static void quirk_p64h2_1k_io(struct pci_dev *dev) 2446{ 2447 u16 en1k; 2448 2449 pci_read_config_word(dev, 0x40, &en1k); 2450 2451 if (en1k & 0x200) { 2452 pci_info(dev, "Enable I/O Space to 1KB granularity\n"); 2453 dev->io_window_1k = 1; 2454 } 2455} 2456DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2457 2458/* 2459 * Under some circumstances, AER is not linked with extended capabilities. 2460 * Force it to be linked by setting the corresponding control bit in the 2461 * config space. 2462 */ 2463static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2464{ 2465 uint8_t b; 2466 2467 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2468 if (!(b & 0x20)) { 2469 pci_write_config_byte(dev, 0xf41, b | 0x20); 2470 pci_info(dev, "Linking AER extended capability\n"); 2471 } 2472 } 2473} 2474DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2475 quirk_nvidia_ck804_pcie_aer_ext_cap); 2476DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2477 quirk_nvidia_ck804_pcie_aer_ext_cap); 2478 2479static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2480{ 2481 /* 2482 * Disable PCI Bus Parking and PCI Master read caching on CX700 2483 * which causes unspecified timing errors with a VT6212L on the PCI 2484 * bus leading to USB2.0 packet loss. 2485 * 2486 * This quirk is only enabled if a second (on the external PCI bus) 2487 * VT6212L is found -- the CX700 core itself also contains a USB 2488 * host controller with the same PCI ID as the VT6212L. 2489 */ 2490 2491 /* Count VT6212L instances */ 2492 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2493 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2494 uint8_t b; 2495 2496 /* 2497 * p should contain the first (internal) VT6212L -- see if we have 2498 * an external one by searching again. 2499 */ 2500 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2501 if (!p) 2502 return; 2503 pci_dev_put(p); 2504 2505 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2506 if (b & 0x40) { 2507 /* Turn off PCI Bus Parking */ 2508 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2509 2510 pci_info(dev, "Disabling VIA CX700 PCI parking\n"); 2511 } 2512 } 2513 2514 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2515 if (b != 0) { 2516 /* Turn off PCI Master read caching */ 2517 pci_write_config_byte(dev, 0x72, 0x0); 2518 2519 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2520 pci_write_config_byte(dev, 0x75, 0x1); 2521 2522 /* Disable "Read FIFO Timer" */ 2523 pci_write_config_byte(dev, 0x77, 0x0); 2524 2525 pci_info(dev, "Disabling VIA CX700 PCI caching\n"); 2526 } 2527 } 2528} 2529DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2530 2531static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2532{ 2533 u32 rev; 2534 2535 pci_read_config_dword(dev, 0xf4, &rev); 2536 2537 /* Only CAP the MRRS if the device is a 5719 A0 */ 2538 if (rev == 0x05719000) { 2539 int readrq = pcie_get_readrq(dev); 2540 if (readrq > 2048) 2541 pcie_set_readrq(dev, 2048); 2542 } 2543} 2544DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2545 PCI_DEVICE_ID_TIGON3_5719, 2546 quirk_brcm_5719_limit_mrrs); 2547 2548/* 2549 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to 2550 * hide device 6 which configures the overflow device access containing the 2551 * DRBs - this is where we expose device 6. 2552 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2553 */ 2554static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2555{ 2556 u8 reg; 2557 2558 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2559 pci_info(dev, "Enabling MCH 'Overflow' Device\n"); 2560 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2561 } 2562} 2563DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2564 quirk_unhide_mch_dev6); 2565DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2566 quirk_unhide_mch_dev6); 2567 2568#ifdef CONFIG_PCI_MSI 2569/* 2570 * Some chipsets do not support MSI. We cannot easily rely on setting 2571 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some 2572 * other buses controlled by the chipset even if Linux is not aware of it. 2573 * Instead of setting the flag on all buses in the machine, simply disable 2574 * MSI globally. 2575 */ 2576static void quirk_disable_all_msi(struct pci_dev *dev) 2577{ 2578 pci_no_msi(); 2579 pci_warn(dev, "MSI quirk detected; MSI disabled\n"); 2580} 2581DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2582DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2583DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2584DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2585DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2586DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2587DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2588DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); 2589 2590/* Disable MSI on chipsets that are known to not support it */ 2591static void quirk_disable_msi(struct pci_dev *dev) 2592{ 2593 if (dev->subordinate) { 2594 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2595 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2596 } 2597} 2598DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2599DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2600DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2601 2602/* 2603 * The APC bridge device in AMD 780 family northbridges has some random 2604 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2605 * we use the possible vendor/device IDs of the host bridge for the 2606 * declared quirk, and search for the APC bridge by slot number. 2607 */ 2608static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2609{ 2610 struct pci_dev *apc_bridge; 2611 2612 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2613 if (apc_bridge) { 2614 if (apc_bridge->device == 0x9602) 2615 quirk_disable_msi(apc_bridge); 2616 pci_dev_put(apc_bridge); 2617 } 2618} 2619DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2620DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2621 2622/* 2623 * Go through the list of HyperTransport capabilities and return 1 if a HT 2624 * MSI capability is found and enabled. 2625 */ 2626static int msi_ht_cap_enabled(struct pci_dev *dev) 2627{ 2628 int pos, ttl = PCI_FIND_CAP_TTL; 2629 2630 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2631 while (pos && ttl--) { 2632 u8 flags; 2633 2634 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2635 &flags) == 0) { 2636 pci_info(dev, "Found %s HT MSI Mapping\n", 2637 flags & HT_MSI_FLAGS_ENABLE ? 2638 "enabled" : "disabled"); 2639 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2640 } 2641 2642 pos = pci_find_next_ht_capability(dev, pos, 2643 HT_CAPTYPE_MSI_MAPPING); 2644 } 2645 return 0; 2646} 2647 2648/* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */ 2649static void quirk_msi_ht_cap(struct pci_dev *dev) 2650{ 2651 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 2652 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2653 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2654 } 2655} 2656DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2657 quirk_msi_ht_cap); 2658 2659/* 2660 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported 2661 * if the MSI capability is set in any of these mappings. 2662 */ 2663static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2664{ 2665 struct pci_dev *pdev; 2666 2667 if (!dev->subordinate) 2668 return; 2669 2670 /* 2671 * Check HT MSI cap on this chipset and the root one. A single one 2672 * having MSI is enough to be sure that MSI is supported. 2673 */ 2674 pdev = pci_get_slot(dev->bus, 0); 2675 if (!pdev) 2676 return; 2677 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { 2678 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2679 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2680 } 2681 pci_dev_put(pdev); 2682} 2683DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2684 quirk_nvidia_ck804_msi_ht_cap); 2685 2686/* Force enable MSI mapping capability on HT bridges */ 2687static void ht_enable_msi_mapping(struct pci_dev *dev) 2688{ 2689 int pos, ttl = PCI_FIND_CAP_TTL; 2690 2691 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2692 while (pos && ttl--) { 2693 u8 flags; 2694 2695 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2696 &flags) == 0) { 2697 pci_info(dev, "Enabling HT MSI Mapping\n"); 2698 2699 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2700 flags | HT_MSI_FLAGS_ENABLE); 2701 } 2702 pos = pci_find_next_ht_capability(dev, pos, 2703 HT_CAPTYPE_MSI_MAPPING); 2704 } 2705} 2706DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2707 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2708 ht_enable_msi_mapping); 2709DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2710 ht_enable_msi_mapping); 2711 2712/* 2713 * The P5N32-SLI motherboards from Asus have a problem with MSI 2714 * for the MCP55 NIC. It is not yet determined whether the MSI problem 2715 * also affects other devices. As for now, turn off MSI for this device. 2716 */ 2717static void nvenet_msi_disable(struct pci_dev *dev) 2718{ 2719 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2720 2721 if (board_name && 2722 (strstr(board_name, "P5N32-SLI PREMIUM") || 2723 strstr(board_name, "P5N32-E SLI"))) { 2724 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); 2725 dev->no_msi = 1; 2726 } 2727} 2728DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2729 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2730 nvenet_msi_disable); 2731 2732/* 2733 * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled, 2734 * then the device can't use INTx interrupts. Tegra's PCIe root ports don't 2735 * generate MSI interrupts for PME and AER events instead only INTx interrupts 2736 * are generated. Though Tegra's PCIe root ports can generate MSI interrupts 2737 * for other events, since PCIe specificiation doesn't support using a mix of 2738 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port 2739 * service drivers registering their respective ISRs for MSIs. 2740 */ 2741static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev) 2742{ 2743 dev->no_msi = 1; 2744} 2745DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0, 2746 PCI_CLASS_BRIDGE_PCI, 8, 2747 pci_quirk_nvidia_tegra_disable_rp_msi); 2748DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1, 2749 PCI_CLASS_BRIDGE_PCI, 8, 2750 pci_quirk_nvidia_tegra_disable_rp_msi); 2751DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2, 2752 PCI_CLASS_BRIDGE_PCI, 8, 2753 pci_quirk_nvidia_tegra_disable_rp_msi); 2754DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, 2755 PCI_CLASS_BRIDGE_PCI, 8, 2756 pci_quirk_nvidia_tegra_disable_rp_msi); 2757DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, 2758 PCI_CLASS_BRIDGE_PCI, 8, 2759 pci_quirk_nvidia_tegra_disable_rp_msi); 2760DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, 2761 PCI_CLASS_BRIDGE_PCI, 8, 2762 pci_quirk_nvidia_tegra_disable_rp_msi); 2763DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, 2764 PCI_CLASS_BRIDGE_PCI, 8, 2765 pci_quirk_nvidia_tegra_disable_rp_msi); 2766DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12, 2767 PCI_CLASS_BRIDGE_PCI, 8, 2768 pci_quirk_nvidia_tegra_disable_rp_msi); 2769DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13, 2770 PCI_CLASS_BRIDGE_PCI, 8, 2771 pci_quirk_nvidia_tegra_disable_rp_msi); 2772DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae, 2773 PCI_CLASS_BRIDGE_PCI, 8, 2774 pci_quirk_nvidia_tegra_disable_rp_msi); 2775DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf, 2776 PCI_CLASS_BRIDGE_PCI, 8, 2777 pci_quirk_nvidia_tegra_disable_rp_msi); 2778DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5, 2779 PCI_CLASS_BRIDGE_PCI, 8, 2780 pci_quirk_nvidia_tegra_disable_rp_msi); 2781DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6, 2782 PCI_CLASS_BRIDGE_PCI, 8, 2783 pci_quirk_nvidia_tegra_disable_rp_msi); 2784 2785/* 2786 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2787 * config register. This register controls the routing of legacy 2788 * interrupts from devices that route through the MCP55. If this register 2789 * is misprogrammed, interrupts are only sent to the BSP, unlike 2790 * conventional systems where the IRQ is broadcast to all online CPUs. Not 2791 * having this register set properly prevents kdump from booting up 2792 * properly, so let's make sure that we have it set correctly. 2793 * Note that this is an undocumented register. 2794 */ 2795static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2796{ 2797 u32 cfg; 2798 2799 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2800 return; 2801 2802 pci_read_config_dword(dev, 0x74, &cfg); 2803 2804 if (cfg & ((1 << 2) | (1 << 15))) { 2805 pr_info("Rewriting IRQ routing register on MCP55\n"); 2806 cfg &= ~((1 << 2) | (1 << 15)); 2807 pci_write_config_dword(dev, 0x74, cfg); 2808 } 2809} 2810DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2811 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2812 nvbridge_check_legacy_irq_routing); 2813DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2814 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2815 nvbridge_check_legacy_irq_routing); 2816 2817static int ht_check_msi_mapping(struct pci_dev *dev) 2818{ 2819 int pos, ttl = PCI_FIND_CAP_TTL; 2820 int found = 0; 2821 2822 /* Check if there is HT MSI cap or enabled on this device */ 2823 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2824 while (pos && ttl--) { 2825 u8 flags; 2826 2827 if (found < 1) 2828 found = 1; 2829 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2830 &flags) == 0) { 2831 if (flags & HT_MSI_FLAGS_ENABLE) { 2832 if (found < 2) { 2833 found = 2; 2834 break; 2835 } 2836 } 2837 } 2838 pos = pci_find_next_ht_capability(dev, pos, 2839 HT_CAPTYPE_MSI_MAPPING); 2840 } 2841 2842 return found; 2843} 2844 2845static int host_bridge_with_leaf(struct pci_dev *host_bridge) 2846{ 2847 struct pci_dev *dev; 2848 int pos; 2849 int i, dev_no; 2850 int found = 0; 2851 2852 dev_no = host_bridge->devfn >> 3; 2853 for (i = dev_no + 1; i < 0x20; i++) { 2854 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2855 if (!dev) 2856 continue; 2857 2858 /* found next host bridge? */ 2859 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2860 if (pos != 0) { 2861 pci_dev_put(dev); 2862 break; 2863 } 2864 2865 if (ht_check_msi_mapping(dev)) { 2866 found = 1; 2867 pci_dev_put(dev); 2868 break; 2869 } 2870 pci_dev_put(dev); 2871 } 2872 2873 return found; 2874} 2875 2876#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 2877#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 2878 2879static int is_end_of_ht_chain(struct pci_dev *dev) 2880{ 2881 int pos, ctrl_off; 2882 int end = 0; 2883 u16 flags, ctrl; 2884 2885 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2886 2887 if (!pos) 2888 goto out; 2889 2890 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 2891 2892 ctrl_off = ((flags >> 10) & 1) ? 2893 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 2894 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 2895 2896 if (ctrl & (1 << 6)) 2897 end = 1; 2898 2899out: 2900 return end; 2901} 2902 2903static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 2904{ 2905 struct pci_dev *host_bridge; 2906 int pos; 2907 int i, dev_no; 2908 int found = 0; 2909 2910 dev_no = dev->devfn >> 3; 2911 for (i = dev_no; i >= 0; i--) { 2912 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 2913 if (!host_bridge) 2914 continue; 2915 2916 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2917 if (pos != 0) { 2918 found = 1; 2919 break; 2920 } 2921 pci_dev_put(host_bridge); 2922 } 2923 2924 if (!found) 2925 return; 2926 2927 /* don't enable end_device/host_bridge with leaf directly here */ 2928 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 2929 host_bridge_with_leaf(host_bridge)) 2930 goto out; 2931 2932 /* root did that ! */ 2933 if (msi_ht_cap_enabled(host_bridge)) 2934 goto out; 2935 2936 ht_enable_msi_mapping(dev); 2937 2938out: 2939 pci_dev_put(host_bridge); 2940} 2941 2942static void ht_disable_msi_mapping(struct pci_dev *dev) 2943{ 2944 int pos, ttl = PCI_FIND_CAP_TTL; 2945 2946 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2947 while (pos && ttl--) { 2948 u8 flags; 2949 2950 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2951 &flags) == 0) { 2952 pci_info(dev, "Disabling HT MSI Mapping\n"); 2953 2954 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2955 flags & ~HT_MSI_FLAGS_ENABLE); 2956 } 2957 pos = pci_find_next_ht_capability(dev, pos, 2958 HT_CAPTYPE_MSI_MAPPING); 2959 } 2960} 2961 2962static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 2963{ 2964 struct pci_dev *host_bridge; 2965 int pos; 2966 int found; 2967 2968 if (!pci_msi_enabled()) 2969 return; 2970 2971 /* check if there is HT MSI cap or enabled on this device */ 2972 found = ht_check_msi_mapping(dev); 2973 2974 /* no HT MSI CAP */ 2975 if (found == 0) 2976 return; 2977 2978 /* 2979 * HT MSI mapping should be disabled on devices that are below 2980 * a non-Hypertransport host bridge. Locate the host bridge... 2981 */ 2982 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, 2983 PCI_DEVFN(0, 0)); 2984 if (host_bridge == NULL) { 2985 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 2986 return; 2987 } 2988 2989 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2990 if (pos != 0) { 2991 /* Host bridge is to HT */ 2992 if (found == 1) { 2993 /* it is not enabled, try to enable it */ 2994 if (all) 2995 ht_enable_msi_mapping(dev); 2996 else 2997 nv_ht_enable_msi_mapping(dev); 2998 } 2999 goto out; 3000 } 3001 3002 /* HT MSI is not enabled */ 3003 if (found == 1) 3004 goto out; 3005 3006 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 3007 ht_disable_msi_mapping(dev); 3008 3009out: 3010 pci_dev_put(host_bridge); 3011} 3012 3013static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 3014{ 3015 return __nv_msi_ht_cap_quirk(dev, 1); 3016} 3017DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 3018DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 3019 3020static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 3021{ 3022 return __nv_msi_ht_cap_quirk(dev, 0); 3023} 3024DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 3025DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 3026 3027static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 3028{ 3029 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3030} 3031 3032static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 3033{ 3034 struct pci_dev *p; 3035 3036 /* 3037 * SB700 MSI issue will be fixed at HW level from revision A21; 3038 * we need check PCI REVISION ID of SMBus controller to get SB700 3039 * revision. 3040 */ 3041 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 3042 NULL); 3043 if (!p) 3044 return; 3045 3046 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 3047 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3048 pci_dev_put(p); 3049} 3050 3051static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 3052{ 3053 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 3054 if (dev->revision < 0x18) { 3055 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n"); 3056 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3057 } 3058} 3059DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3060 PCI_DEVICE_ID_TIGON3_5780, 3061 quirk_msi_intx_disable_bug); 3062DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3063 PCI_DEVICE_ID_TIGON3_5780S, 3064 quirk_msi_intx_disable_bug); 3065DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3066 PCI_DEVICE_ID_TIGON3_5714, 3067 quirk_msi_intx_disable_bug); 3068DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3069 PCI_DEVICE_ID_TIGON3_5714S, 3070 quirk_msi_intx_disable_bug); 3071DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3072 PCI_DEVICE_ID_TIGON3_5715, 3073 quirk_msi_intx_disable_bug); 3074DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3075 PCI_DEVICE_ID_TIGON3_5715S, 3076 quirk_msi_intx_disable_bug); 3077 3078DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 3079 quirk_msi_intx_disable_ati_bug); 3080DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 3081 quirk_msi_intx_disable_ati_bug); 3082DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 3083 quirk_msi_intx_disable_ati_bug); 3084DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 3085 quirk_msi_intx_disable_ati_bug); 3086DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 3087 quirk_msi_intx_disable_ati_bug); 3088 3089DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 3090 quirk_msi_intx_disable_bug); 3091DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 3092 quirk_msi_intx_disable_bug); 3093DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 3094 quirk_msi_intx_disable_bug); 3095 3096DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, 3097 quirk_msi_intx_disable_bug); 3098DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, 3099 quirk_msi_intx_disable_bug); 3100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, 3101 quirk_msi_intx_disable_bug); 3102DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, 3103 quirk_msi_intx_disable_bug); 3104DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, 3105 quirk_msi_intx_disable_bug); 3106DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, 3107 quirk_msi_intx_disable_bug); 3108DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, 3109 quirk_msi_intx_disable_qca_bug); 3110DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, 3111 quirk_msi_intx_disable_qca_bug); 3112DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, 3113 quirk_msi_intx_disable_qca_bug); 3114DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, 3115 quirk_msi_intx_disable_qca_bug); 3116DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, 3117 quirk_msi_intx_disable_qca_bug); 3118 3119/* 3120 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it 3121 * should be disabled on platforms where the device (mistakenly) advertises it. 3122 * 3123 * Notice that this quirk also disables MSI (which may work, but hasn't been 3124 * tested), since currently there is no standard way to disable only MSI-X. 3125 * 3126 * The 0031 device id is reused for other non Root Port device types, 3127 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class. 3128 */ 3129static void quirk_al_msi_disable(struct pci_dev *dev) 3130{ 3131 dev->no_msi = 1; 3132 pci_warn(dev, "Disabling MSI/MSI-X\n"); 3133} 3134DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, 3135 PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable); 3136#endif /* CONFIG_PCI_MSI */ 3137 3138/* 3139 * Allow manual resource allocation for PCI hotplug bridges via 3140 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI 3141 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to 3142 * allocate resources when hotplug device is inserted and PCI bus is 3143 * rescanned. 3144 */ 3145static void quirk_hotplug_bridge(struct pci_dev *dev) 3146{ 3147 dev->is_hotplug_bridge = 1; 3148} 3149DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 3150 3151/* 3152 * This is a quirk for the Ricoh MMC controller found as a part of some 3153 * multifunction chips. 3154 * 3155 * This is very similar and based on the ricoh_mmc driver written by 3156 * Philip Langdale. Thank you for these magic sequences. 3157 * 3158 * These chips implement the four main memory card controllers (SD, MMC, 3159 * MS, xD) and one or both of CardBus or FireWire. 3160 * 3161 * It happens that they implement SD and MMC support as separate 3162 * controllers (and PCI functions). The Linux SDHCI driver supports MMC 3163 * cards but the chip detects MMC cards in hardware and directs them to the 3164 * MMC controller - so the SDHCI driver never sees them. 3165 * 3166 * To get around this, we must disable the useless MMC controller. At that 3167 * point, the SDHCI controller will start seeing them. It seems to be the 3168 * case that the relevant PCI registers to deactivate the MMC controller 3169 * live on PCI function 0, which might be the CardBus controller or the 3170 * FireWire controller, depending on the particular chip in question 3171 * 3172 * This has to be done early, because as soon as we disable the MMC controller 3173 * other PCI functions shift up one level, e.g. function #2 becomes function 3174 * #1, and this will confuse the PCI core. 3175 */ 3176#ifdef CONFIG_MMC_RICOH_MMC 3177static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 3178{ 3179 u8 write_enable; 3180 u8 write_target; 3181 u8 disable; 3182 3183 /* 3184 * Disable via CardBus interface 3185 * 3186 * This must be done via function #0 3187 */ 3188 if (PCI_FUNC(dev->devfn)) 3189 return; 3190 3191 pci_read_config_byte(dev, 0xB7, &disable); 3192 if (disable & 0x02) 3193 return; 3194 3195 pci_read_config_byte(dev, 0x8E, &write_enable); 3196 pci_write_config_byte(dev, 0x8E, 0xAA); 3197 pci_read_config_byte(dev, 0x8D, &write_target); 3198 pci_write_config_byte(dev, 0x8D, 0xB7); 3199 pci_write_config_byte(dev, 0xB7, disable | 0x02); 3200 pci_write_config_byte(dev, 0x8E, write_enable); 3201 pci_write_config_byte(dev, 0x8D, write_target); 3202 3203 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n"); 3204 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3205} 3206DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3207DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3208 3209static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 3210{ 3211 u8 write_enable; 3212 u8 disable; 3213 3214 /* 3215 * Disable via FireWire interface 3216 * 3217 * This must be done via function #0 3218 */ 3219 if (PCI_FUNC(dev->devfn)) 3220 return; 3221 /* 3222 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 3223 * certain types of SD/MMC cards. Lowering the SD base clock 3224 * frequency from 200Mhz to 50Mhz fixes this issue. 3225 * 3226 * 0x150 - SD2.0 mode enable for changing base clock 3227 * frequency to 50Mhz 3228 * 0xe1 - Base clock frequency 3229 * 0x32 - 50Mhz new clock frequency 3230 * 0xf9 - Key register for 0x150 3231 * 0xfc - key register for 0xe1 3232 */ 3233 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 3234 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 3235 pci_write_config_byte(dev, 0xf9, 0xfc); 3236 pci_write_config_byte(dev, 0x150, 0x10); 3237 pci_write_config_byte(dev, 0xf9, 0x00); 3238 pci_write_config_byte(dev, 0xfc, 0x01); 3239 pci_write_config_byte(dev, 0xe1, 0x32); 3240 pci_write_config_byte(dev, 0xfc, 0x00); 3241 3242 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n"); 3243 } 3244 3245 pci_read_config_byte(dev, 0xCB, &disable); 3246 3247 if (disable & 0x02) 3248 return; 3249 3250 pci_read_config_byte(dev, 0xCA, &write_enable); 3251 pci_write_config_byte(dev, 0xCA, 0x57); 3252 pci_write_config_byte(dev, 0xCB, disable | 0x02); 3253 pci_write_config_byte(dev, 0xCA, write_enable); 3254 3255 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n"); 3256 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3257 3258} 3259DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3260DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3261DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3262DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3263DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3264DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3265#endif /*CONFIG_MMC_RICOH_MMC*/ 3266 3267#ifdef CONFIG_DMAR_TABLE 3268#define VTUNCERRMSK_REG 0x1ac 3269#define VTD_MSK_SPEC_ERRORS (1 << 31) 3270/* 3271 * This is a quirk for masking VT-d spec-defined errors to platform error 3272 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets 3273 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 3274 * on the RAS config settings of the platform) when a VT-d fault happens. 3275 * The resulting SMI caused the system to hang. 3276 * 3277 * VT-d spec-related errors are already handled by the VT-d OS code, so no 3278 * need to report the same error through other channels. 3279 */ 3280static void vtd_mask_spec_errors(struct pci_dev *dev) 3281{ 3282 u32 word; 3283 3284 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 3285 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 3286} 3287DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 3288DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 3289#endif 3290 3291static void fixup_ti816x_class(struct pci_dev *dev) 3292{ 3293 u32 class = dev->class; 3294 3295 /* TI 816x devices do not have class code set when in PCIe boot mode */ 3296 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; 3297 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", 3298 class, dev->class); 3299} 3300DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 3301 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); 3302 3303/* 3304 * Some PCIe devices do not work reliably with the claimed maximum 3305 * payload size supported. 3306 */ 3307static void fixup_mpss_256(struct pci_dev *dev) 3308{ 3309 dev->pcie_mpss = 1; /* 256 bytes */ 3310} 3311DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3312 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 3313DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3314 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 3315DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3316 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 3317DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256); 3318 3319/* 3320 * Intel 5000 and 5100 Memory controllers have an erratum with read completion 3321 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 3322 * Since there is no way of knowing what the PCIe MPS on each fabric will be 3323 * until all of the devices are discovered and buses walked, read completion 3324 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 3325 * it is possible to hotplug a device with MPS of 256B. 3326 */ 3327static void quirk_intel_mc_errata(struct pci_dev *dev) 3328{ 3329 int err; 3330 u16 rcc; 3331 3332 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 3333 pcie_bus_config == PCIE_BUS_DEFAULT) 3334 return; 3335 3336 /* 3337 * Intel erratum specifies bits to change but does not say what 3338 * they are. Keeping them magical until such time as the registers 3339 * and values can be explained. 3340 */ 3341 err = pci_read_config_word(dev, 0x48, &rcc); 3342 if (err) { 3343 pci_err(dev, "Error attempting to read the read completion coalescing register\n"); 3344 return; 3345 } 3346 3347 if (!(rcc & (1 << 10))) 3348 return; 3349 3350 rcc &= ~(1 << 10); 3351 3352 err = pci_write_config_word(dev, 0x48, rcc); 3353 if (err) { 3354 pci_err(dev, "Error attempting to write the read completion coalescing register\n"); 3355 return; 3356 } 3357 3358 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n"); 3359} 3360/* Intel 5000 series memory controllers and ports 2-7 */ 3361DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 3362DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 3363DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 3364DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 3365DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 3366DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 3367DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 3368DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 3369DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 3370DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 3371DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 3372DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 3373DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 3374DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 3375/* Intel 5100 series memory controllers and ports 2-7 */ 3376DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 3377DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 3378DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 3379DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 3380DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 3381DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 3382DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 3383DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 3384DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 3385DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 3386DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 3387 3388/* 3389 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. 3390 * To work around this, query the size it should be configured to by the 3391 * device and modify the resource end to correspond to this new size. 3392 */ 3393static void quirk_intel_ntb(struct pci_dev *dev) 3394{ 3395 int rc; 3396 u8 val; 3397 3398 rc = pci_read_config_byte(dev, 0x00D0, &val); 3399 if (rc) 3400 return; 3401 3402 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; 3403 3404 rc = pci_read_config_byte(dev, 0x00D1, &val); 3405 if (rc) 3406 return; 3407 3408 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; 3409} 3410DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 3411DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 3412 3413/* 3414 * Some BIOS implementations leave the Intel GPU interrupts enabled, even 3415 * though no one is handling them (e.g., if the i915 driver is never 3416 * loaded). Additionally the interrupt destination is not set up properly 3417 * and the interrupt ends up -somewhere-. 3418 * 3419 * These spurious interrupts are "sticky" and the kernel disables the 3420 * (shared) interrupt line after 100,000+ generated interrupts. 3421 * 3422 * Fix it by disabling the still enabled interrupts. This resolves crashes 3423 * often seen on monitor unplug. 3424 */ 3425#define I915_DEIER_REG 0x4400c 3426static void disable_igfx_irq(struct pci_dev *dev) 3427{ 3428 void __iomem *regs = pci_iomap(dev, 0, 0); 3429 if (regs == NULL) { 3430 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); 3431 return; 3432 } 3433 3434 /* Check if any interrupt line is still enabled */ 3435 if (readl(regs + I915_DEIER_REG) != 0) { 3436 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 3437 3438 writel(0, regs + I915_DEIER_REG); 3439 } 3440 3441 pci_iounmap(dev, regs); 3442} 3443DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq); 3444DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq); 3445DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq); 3446DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 3447DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq); 3448DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 3449DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); 3450 3451/* 3452 * PCI devices which are on Intel chips can skip the 10ms delay 3453 * before entering D3 mode. 3454 */ 3455static void quirk_remove_d3hot_delay(struct pci_dev *dev) 3456{ 3457 dev->d3hot_delay = 0; 3458} 3459/* C600 Series devices do not need 10ms d3hot_delay */ 3460DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay); 3461DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay); 3462DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay); 3463/* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */ 3464DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay); 3465DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay); 3466DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay); 3467DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay); 3468DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay); 3469DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay); 3470DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay); 3471DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay); 3472DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay); 3473DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay); 3474DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay); 3475/* Intel Cherrytrail devices do not need 10ms d3hot_delay */ 3476DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay); 3477DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay); 3478DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay); 3479DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay); 3480DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay); 3481DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay); 3482DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay); 3483DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay); 3484DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay); 3485 3486/* 3487 * Some devices may pass our check in pci_intx_mask_supported() if 3488 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly 3489 * support this feature. 3490 */ 3491static void quirk_broken_intx_masking(struct pci_dev *dev) 3492{ 3493 dev->broken_intx_masking = 1; 3494} 3495DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030, 3496 quirk_broken_intx_masking); 3497DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 3498 quirk_broken_intx_masking); 3499DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */ 3500 quirk_broken_intx_masking); 3501 3502/* 3503 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 3504 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC 3505 * 3506 * RTL8110SC - Fails under PCI device assignment using DisINTx masking. 3507 */ 3508DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169, 3509 quirk_broken_intx_masking); 3510 3511/* 3512 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, 3513 * DisINTx can be set but the interrupt status bit is non-functional. 3514 */ 3515DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking); 3516DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking); 3517DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking); 3518DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking); 3519DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking); 3520DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking); 3521DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking); 3522DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking); 3523DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking); 3524DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking); 3525DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking); 3526DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking); 3527DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking); 3528DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking); 3529DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking); 3530DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking); 3531 3532static u16 mellanox_broken_intx_devs[] = { 3533 PCI_DEVICE_ID_MELLANOX_HERMON_SDR, 3534 PCI_DEVICE_ID_MELLANOX_HERMON_DDR, 3535 PCI_DEVICE_ID_MELLANOX_HERMON_QDR, 3536 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2, 3537 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2, 3538 PCI_DEVICE_ID_MELLANOX_HERMON_EN, 3539 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2, 3540 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN, 3541 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2, 3542 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2, 3543 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2, 3544 PCI_DEVICE_ID_MELLANOX_CONNECTX2, 3545 PCI_DEVICE_ID_MELLANOX_CONNECTX3, 3546 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO, 3547}; 3548 3549#define CONNECTX_4_CURR_MAX_MINOR 99 3550#define CONNECTX_4_INTX_SUPPORT_MINOR 14 3551 3552/* 3553 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts. 3554 * If so, don't mark it as broken. 3555 * FW minor > 99 means older FW version format and no INTx masking support. 3556 * FW minor < 14 means new FW version format and no INTx masking support. 3557 */ 3558static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) 3559{ 3560 __be32 __iomem *fw_ver; 3561 u16 fw_major; 3562 u16 fw_minor; 3563 u16 fw_subminor; 3564 u32 fw_maj_min; 3565 u32 fw_sub_min; 3566 int i; 3567 3568 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { 3569 if (pdev->device == mellanox_broken_intx_devs[i]) { 3570 pdev->broken_intx_masking = 1; 3571 return; 3572 } 3573 } 3574 3575 /* 3576 * Getting here means Connect-IB cards and up. Connect-IB has no INTx 3577 * support so shouldn't be checked further 3578 */ 3579 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) 3580 return; 3581 3582 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && 3583 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) 3584 return; 3585 3586 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ 3587 if (pci_enable_device_mem(pdev)) { 3588 pci_warn(pdev, "Can't enable device memory\n"); 3589 return; 3590 } 3591 3592 fw_ver = ioremap(pci_resource_start(pdev, 0), 4); 3593 if (!fw_ver) { 3594 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); 3595 goto out; 3596 } 3597 3598 /* Reading from resource space should be 32b aligned */ 3599 fw_maj_min = ioread32be(fw_ver); 3600 fw_sub_min = ioread32be(fw_ver + 1); 3601 fw_major = fw_maj_min & 0xffff; 3602 fw_minor = fw_maj_min >> 16; 3603 fw_subminor = fw_sub_min & 0xffff; 3604 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || 3605 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { 3606 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", 3607 fw_major, fw_minor, fw_subminor, pdev->device == 3608 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); 3609 pdev->broken_intx_masking = 1; 3610 } 3611 3612 iounmap(fw_ver); 3613 3614out: 3615 pci_disable_device(pdev); 3616} 3617DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, 3618 mellanox_check_broken_intx_masking); 3619 3620static void quirk_no_bus_reset(struct pci_dev *dev) 3621{ 3622 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; 3623} 3624 3625/* 3626 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be 3627 * prevented for those affected devices. 3628 */ 3629static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) 3630{ 3631 if ((dev->device & 0xffc0) == 0x2340) 3632 quirk_no_bus_reset(dev); 3633} 3634DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 3635 quirk_nvidia_no_bus_reset); 3636 3637/* 3638 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. 3639 * The device will throw a Link Down error on AER-capable systems and 3640 * regardless of AER, config space of the device is never accessible again 3641 * and typically causes the system to hang or reset when access is attempted. 3642 * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/ 3643 */ 3644DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); 3645DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); 3646DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); 3647DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); 3648DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset); 3649DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset); 3650 3651/* 3652 * Root port on some Cavium CN8xxx chips do not successfully complete a bus 3653 * reset when used with certain child devices. After the reset, config 3654 * accesses to the child may fail. 3655 */ 3656DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); 3657 3658/* 3659 * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS 3660 * automatically disables LTSSM when Secondary Bus Reset is received and 3661 * the device stops working. Prevent bus reset for these devices. With 3662 * this change, the device can be assigned to VMs with VFIO, but it will 3663 * leak state between VMs. Reference 3664 * https://e2e.ti.com/support/processors/f/791/t/954382 3665 */ 3666DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset); 3667 3668static void quirk_no_pm_reset(struct pci_dev *dev) 3669{ 3670 /* 3671 * We can't do a bus reset on root bus devices, but an ineffective 3672 * PM reset may be better than nothing. 3673 */ 3674 if (!pci_is_root_bus(dev->bus)) 3675 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; 3676} 3677 3678/* 3679 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition 3680 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems 3681 * to have no effect on the device: it retains the framebuffer contents and 3682 * monitor sync. Advertising this support makes other layers, like VFIO, 3683 * assume pci_reset_function() is viable for this device. Mark it as 3684 * unavailable to skip it when testing reset methods. 3685 */ 3686DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 3687 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); 3688 3689/* 3690 * Spectrum-{1,2,3,4} devices report that a D3hot->D0 transition causes a reset 3691 * (i.e., they advertise NoSoftRst-). However, this transition does not have 3692 * any effect on the device: It continues to be operational and network ports 3693 * remain up. Advertising this support makes it seem as if a PM reset is viable 3694 * for these devices. Mark it as unavailable to skip it when testing reset 3695 * methods. 3696 */ 3697DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcb84, quirk_no_pm_reset); 3698DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf6c, quirk_no_pm_reset); 3699DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf70, quirk_no_pm_reset); 3700DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf80, quirk_no_pm_reset); 3701 3702/* 3703 * Thunderbolt controllers with broken MSI hotplug signaling: 3704 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part 3705 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge). 3706 */ 3707static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev) 3708{ 3709 if (pdev->is_hotplug_bridge && 3710 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || 3711 pdev->revision <= 1)) 3712 pdev->no_msi = 1; 3713} 3714DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3715 quirk_thunderbolt_hotplug_msi); 3716DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE, 3717 quirk_thunderbolt_hotplug_msi); 3718DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK, 3719 quirk_thunderbolt_hotplug_msi); 3720DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3721 quirk_thunderbolt_hotplug_msi); 3722DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE, 3723 quirk_thunderbolt_hotplug_msi); 3724 3725#ifdef CONFIG_ACPI 3726/* 3727 * Apple: Shutdown Cactus Ridge Thunderbolt controller. 3728 * 3729 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be 3730 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3731 * be present after resume if a device was plugged in before suspend. 3732 * 3733 * The Thunderbolt controller consists of a PCIe switch with downstream 3734 * bridges leading to the NHI and to the tunnel PCI bridges. 3735 * 3736 * This quirk cuts power to the whole chip. Therefore we have to apply it 3737 * during suspend_noirq of the upstream bridge. 3738 * 3739 * Power is automagically restored before resume. No action is needed. 3740 */ 3741static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) 3742{ 3743 acpi_handle bridge, SXIO, SXFP, SXLV; 3744 3745 if (!x86_apple_machine) 3746 return; 3747 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) 3748 return; 3749 3750 /* 3751 * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller. 3752 * We don't know how to turn it back on again, but firmware does, 3753 * so we can only use SXIO/SXFP/SXLF if we're suspending via 3754 * firmware. 3755 */ 3756 if (!pm_suspend_via_firmware()) 3757 return; 3758 3759 bridge = ACPI_HANDLE(&dev->dev); 3760 if (!bridge) 3761 return; 3762 3763 /* 3764 * SXIO and SXLV are present only on machines requiring this quirk. 3765 * Thunderbolt bridges in external devices might have the same 3766 * device ID as those on the host, but they will not have the 3767 * associated ACPI methods. This implicitly checks that we are at 3768 * the right bridge. 3769 */ 3770 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3771 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3772 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3773 return; 3774 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n"); 3775 3776 /* magic sequence */ 3777 acpi_execute_simple_method(SXIO, NULL, 1); 3778 acpi_execute_simple_method(SXFP, NULL, 0); 3779 msleep(300); 3780 acpi_execute_simple_method(SXLV, NULL, 0); 3781 acpi_execute_simple_method(SXIO, NULL, 0); 3782 acpi_execute_simple_method(SXLV, NULL, 0); 3783} 3784DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 3785 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3786 quirk_apple_poweroff_thunderbolt); 3787#endif 3788 3789/* 3790 * Following are device-specific reset methods which can be used to 3791 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3792 * not available. 3793 */ 3794static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) 3795{ 3796 /* 3797 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3798 * 3799 * The 82599 supports FLR on VFs, but FLR support is reported only 3800 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). 3801 * Thus we must call pcie_flr() directly without first checking if it is 3802 * supported. 3803 */ 3804 if (!probe) 3805 pcie_flr(dev); 3806 return 0; 3807} 3808 3809#define SOUTH_CHICKEN2 0xc2004 3810#define PCH_PP_STATUS 0xc7200 3811#define PCH_PP_CONTROL 0xc7204 3812#define MSG_CTL 0x45010 3813#define NSDE_PWR_STATE 0xd0100 3814#define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ 3815 3816static int reset_ivb_igd(struct pci_dev *dev, int probe) 3817{ 3818 void __iomem *mmio_base; 3819 unsigned long timeout; 3820 u32 val; 3821 3822 if (probe) 3823 return 0; 3824 3825 mmio_base = pci_iomap(dev, 0, 0); 3826 if (!mmio_base) 3827 return -ENOMEM; 3828 3829 iowrite32(0x00000002, mmio_base + MSG_CTL); 3830 3831 /* 3832 * Clobbering SOUTH_CHICKEN2 register is fine only if the next 3833 * driver loaded sets the right bits. However, this's a reset and 3834 * the bits have been set by i915 previously, so we clobber 3835 * SOUTH_CHICKEN2 register directly here. 3836 */ 3837 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); 3838 3839 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; 3840 iowrite32(val, mmio_base + PCH_PP_CONTROL); 3841 3842 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); 3843 do { 3844 val = ioread32(mmio_base + PCH_PP_STATUS); 3845 if ((val & 0xb0000000) == 0) 3846 goto reset_complete; 3847 msleep(10); 3848 } while (time_before(jiffies, timeout)); 3849 pci_warn(dev, "timeout during reset\n"); 3850 3851reset_complete: 3852 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 3853 3854 pci_iounmap(dev, mmio_base); 3855 return 0; 3856} 3857 3858/* Device-specific reset method for Chelsio T4-based adapters */ 3859static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) 3860{ 3861 u16 old_command; 3862 u16 msix_flags; 3863 3864 /* 3865 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating 3866 * that we have no device-specific reset method. 3867 */ 3868 if ((dev->device & 0xf000) != 0x4000) 3869 return -ENOTTY; 3870 3871 /* 3872 * If this is the "probe" phase, return 0 indicating that we can 3873 * reset this device. 3874 */ 3875 if (probe) 3876 return 0; 3877 3878 /* 3879 * T4 can wedge if there are DMAs in flight within the chip and Bus 3880 * Master has been disabled. We need to have it on till the Function 3881 * Level Reset completes. (BUS_MASTER is disabled in 3882 * pci_reset_function()). 3883 */ 3884 pci_read_config_word(dev, PCI_COMMAND, &old_command); 3885 pci_write_config_word(dev, PCI_COMMAND, 3886 old_command | PCI_COMMAND_MASTER); 3887 3888 /* 3889 * Perform the actual device function reset, saving and restoring 3890 * configuration information around the reset. 3891 */ 3892 pci_save_state(dev); 3893 3894 /* 3895 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts 3896 * are disabled when an MSI-X interrupt message needs to be delivered. 3897 * So we briefly re-enable MSI-X interrupts for the duration of the 3898 * FLR. The pci_restore_state() below will restore the original 3899 * MSI-X state. 3900 */ 3901 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); 3902 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) 3903 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, 3904 msix_flags | 3905 PCI_MSIX_FLAGS_ENABLE | 3906 PCI_MSIX_FLAGS_MASKALL); 3907 3908 pcie_flr(dev); 3909 3910 /* 3911 * Restore the configuration information (BAR values, etc.) including 3912 * the original PCI Configuration Space Command word, and return 3913 * success. 3914 */ 3915 pci_restore_state(dev); 3916 pci_write_config_word(dev, PCI_COMMAND, old_command); 3917 return 0; 3918} 3919 3920#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 3921#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 3922#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 3923 3924/* 3925 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after 3926 * FLR where config space reads from the device return -1. We seem to be 3927 * able to avoid this condition if we disable the NVMe controller prior to 3928 * FLR. This quirk is generic for any NVMe class device requiring similar 3929 * assistance to quiesce the device prior to FLR. 3930 * 3931 * NVMe specification: https://nvmexpress.org/resources/specifications/ 3932 * Revision 1.0e: 3933 * Chapter 2: Required and optional PCI config registers 3934 * Chapter 3: NVMe control registers 3935 * Chapter 7.3: Reset behavior 3936 */ 3937static int nvme_disable_and_flr(struct pci_dev *dev, int probe) 3938{ 3939 void __iomem *bar; 3940 u16 cmd; 3941 u32 cfg; 3942 3943 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || 3944 !pcie_has_flr(dev) || !pci_resource_start(dev, 0)) 3945 return -ENOTTY; 3946 3947 if (probe) 3948 return 0; 3949 3950 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); 3951 if (!bar) 3952 return -ENOTTY; 3953 3954 pci_read_config_word(dev, PCI_COMMAND, &cmd); 3955 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY); 3956 3957 cfg = readl(bar + NVME_REG_CC); 3958 3959 /* Disable controller if enabled */ 3960 if (cfg & NVME_CC_ENABLE) { 3961 u32 cap = readl(bar + NVME_REG_CAP); 3962 unsigned long timeout; 3963 3964 /* 3965 * Per nvme_disable_ctrl() skip shutdown notification as it 3966 * could complete commands to the admin queue. We only intend 3967 * to quiesce the device before reset. 3968 */ 3969 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE); 3970 3971 writel(cfg, bar + NVME_REG_CC); 3972 3973 /* 3974 * Some controllers require an additional delay here, see 3975 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet 3976 * supported by this quirk. 3977 */ 3978 3979 /* Cap register provides max timeout in 500ms increments */ 3980 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; 3981 3982 for (;;) { 3983 u32 status = readl(bar + NVME_REG_CSTS); 3984 3985 /* Ready status becomes zero on disable complete */ 3986 if (!(status & NVME_CSTS_RDY)) 3987 break; 3988 3989 msleep(100); 3990 3991 if (time_after(jiffies, timeout)) { 3992 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n"); 3993 break; 3994 } 3995 } 3996 } 3997 3998 pci_iounmap(dev, bar); 3999 4000 pcie_flr(dev); 4001 4002 return 0; 4003} 4004 4005/* 4006 * Intel DC P3700 NVMe controller will timeout waiting for ready status 4007 * to change after NVMe enable if the driver starts interacting with the 4008 * device too soon after FLR. A 250ms delay after FLR has heuristically 4009 * proven to produce reliably working results for device assignment cases. 4010 */ 4011static int delay_250ms_after_flr(struct pci_dev *dev, int probe) 4012{ 4013 if (!pcie_has_flr(dev)) 4014 return -ENOTTY; 4015 4016 if (probe) 4017 return 0; 4018 4019 pcie_flr(dev); 4020 4021 msleep(250); 4022 4023 return 0; 4024} 4025 4026#define PCI_DEVICE_ID_HINIC_VF 0x375E 4027#define HINIC_VF_FLR_TYPE 0x1000 4028#define HINIC_VF_FLR_CAP_BIT (1UL << 30) 4029#define HINIC_VF_OP 0xE80 4030#define HINIC_VF_FLR_PROC_BIT (1UL << 18) 4031#define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */ 4032 4033/* Device-specific reset method for Huawei Intelligent NIC virtual functions */ 4034static int reset_hinic_vf_dev(struct pci_dev *pdev, int probe) 4035{ 4036 unsigned long timeout; 4037 void __iomem *bar; 4038 u32 val; 4039 4040 if (probe) 4041 return 0; 4042 4043 bar = pci_iomap(pdev, 0, 0); 4044 if (!bar) 4045 return -ENOTTY; 4046 4047 /* Get and check firmware capabilities */ 4048 val = ioread32be(bar + HINIC_VF_FLR_TYPE); 4049 if (!(val & HINIC_VF_FLR_CAP_BIT)) { 4050 pci_iounmap(pdev, bar); 4051 return -ENOTTY; 4052 } 4053 4054 /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */ 4055 val = ioread32be(bar + HINIC_VF_OP); 4056 val = val | HINIC_VF_FLR_PROC_BIT; 4057 iowrite32be(val, bar + HINIC_VF_OP); 4058 4059 pcie_flr(pdev); 4060 4061 /* 4062 * The device must recapture its Bus and Device Numbers after FLR 4063 * in order generate Completions. Issue a config write to let the 4064 * device capture this information. 4065 */ 4066 pci_write_config_word(pdev, PCI_VENDOR_ID, 0); 4067 4068 /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */ 4069 timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT); 4070 do { 4071 val = ioread32be(bar + HINIC_VF_OP); 4072 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4073 goto reset_complete; 4074 msleep(20); 4075 } while (time_before(jiffies, timeout)); 4076 4077 val = ioread32be(bar + HINIC_VF_OP); 4078 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4079 goto reset_complete; 4080 4081 pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val); 4082 4083reset_complete: 4084 pci_iounmap(pdev, bar); 4085 4086 return 0; 4087} 4088 4089static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 4090 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 4091 reset_intel_82599_sfp_virtfn }, 4092 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, 4093 reset_ivb_igd }, 4094 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, 4095 reset_ivb_igd }, 4096 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr }, 4097 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr }, 4098 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4099 reset_chelsio_generic_dev }, 4100 { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF, 4101 reset_hinic_vf_dev }, 4102 { 0 } 4103}; 4104 4105/* 4106 * These device-specific reset methods are here rather than in a driver 4107 * because when a host assigns a device to a guest VM, the host may need 4108 * to reset the device but probably doesn't have a driver for it. 4109 */ 4110int pci_dev_specific_reset(struct pci_dev *dev, int probe) 4111{ 4112 const struct pci_dev_reset_methods *i; 4113 4114 for (i = pci_dev_reset_methods; i->reset; i++) { 4115 if ((i->vendor == dev->vendor || 4116 i->vendor == (u16)PCI_ANY_ID) && 4117 (i->device == dev->device || 4118 i->device == (u16)PCI_ANY_ID)) 4119 return i->reset(dev, probe); 4120 } 4121 4122 return -ENOTTY; 4123} 4124 4125static void quirk_dma_func0_alias(struct pci_dev *dev) 4126{ 4127 if (PCI_FUNC(dev->devfn) != 0) 4128 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); 4129} 4130 4131/* 4132 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 4133 * 4134 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. 4135 */ 4136DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 4137DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 4138 4139static void quirk_dma_func1_alias(struct pci_dev *dev) 4140{ 4141 if (PCI_FUNC(dev->devfn) != 1) 4142 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); 4143} 4144 4145/* 4146 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some 4147 * SKUs function 1 is present and is a legacy IDE controller, in other 4148 * SKUs this function is not present, making this a ghost requester. 4149 * https://bugzilla.kernel.org/show_bug.cgi?id=42679 4150 */ 4151DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, 4152 quirk_dma_func1_alias); 4153DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 4154 quirk_dma_func1_alias); 4155/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */ 4156DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125, 4157 quirk_dma_func1_alias); 4158DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128, 4159 quirk_dma_func1_alias); 4160/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 4161DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 4162 quirk_dma_func1_alias); 4163DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170, 4164 quirk_dma_func1_alias); 4165/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ 4166DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, 4167 quirk_dma_func1_alias); 4168/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ 4169DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, 4170 quirk_dma_func1_alias); 4171/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */ 4172DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182, 4173 quirk_dma_func1_alias); 4174/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */ 4175DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183, 4176 quirk_dma_func1_alias); 4177/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 4178DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 4179 quirk_dma_func1_alias); 4180/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */ 4181DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215, 4182 quirk_dma_func1_alias); 4183/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */ 4184DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220, 4185 quirk_dma_func1_alias); 4186/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ 4187DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, 4188 quirk_dma_func1_alias); 4189DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235, 4190 quirk_dma_func1_alias); 4191DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, 4192 quirk_dma_func1_alias); 4193DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645, 4194 quirk_dma_func1_alias); 4195/* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ 4196DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, 4197 PCI_DEVICE_ID_JMICRON_JMB388_ESD, 4198 quirk_dma_func1_alias); 4199/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */ 4200DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */ 4201 0x0122, /* Plextor M6E (Marvell 88SS9183)*/ 4202 quirk_dma_func1_alias); 4203 4204/* 4205 * Some devices DMA with the wrong devfn, not just the wrong function. 4206 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where 4207 * the alias is "fixed" and independent of the device devfn. 4208 * 4209 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O 4210 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a 4211 * single device on the secondary bus. In reality, the single exposed 4212 * device at 0e.0 is the Address Translation Unit (ATU) of the controller 4213 * that provides a bridge to the internal bus of the I/O processor. The 4214 * controller supports private devices, which can be hidden from PCI config 4215 * space. In the case of the Adaptec 3405, a private device at 01.0 4216 * appears to be the DMA engine, which therefore needs to become a DMA 4217 * alias for the device. 4218 */ 4219static const struct pci_device_id fixed_dma_alias_tbl[] = { 4220 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4221 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ 4222 .driver_data = PCI_DEVFN(1, 0) }, 4223 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4224 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */ 4225 .driver_data = PCI_DEVFN(1, 0) }, 4226 { 0 } 4227}; 4228 4229static void quirk_fixed_dma_alias(struct pci_dev *dev) 4230{ 4231 const struct pci_device_id *id; 4232 4233 id = pci_match_id(fixed_dma_alias_tbl, dev); 4234 if (id) 4235 pci_add_dma_alias(dev, id->driver_data, 1); 4236} 4237DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); 4238 4239/* 4240 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in 4241 * using the wrong DMA alias for the device. Some of these devices can be 4242 * used as either forward or reverse bridges, so we need to test whether the 4243 * device is operating in the correct mode. We could probably apply this 4244 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test 4245 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and 4246 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. 4247 */ 4248static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) 4249{ 4250 if (!pci_is_root_bus(pdev->bus) && 4251 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 4252 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && 4253 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) 4254 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; 4255} 4256/* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ 4257DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, 4258 quirk_use_pcie_bridge_dma_alias); 4259/* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ 4260DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); 4261/* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ 4262DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); 4263/* ITE 8893 has the same problem as the 8892 */ 4264DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias); 4265/* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ 4266DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); 4267 4268/* 4269 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to 4270 * be added as aliases to the DMA device in order to allow buffer access 4271 * when IOMMU is enabled. Following devfns have to match RIT-LUT table 4272 * programmed in the EEPROM. 4273 */ 4274static void quirk_mic_x200_dma_alias(struct pci_dev *pdev) 4275{ 4276 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1); 4277 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1); 4278 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1); 4279} 4280DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias); 4281DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias); 4282 4283/* 4284 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices 4285 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx). 4286 * 4287 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access 4288 * when IOMMU is enabled. These aliases allow computational unit access to 4289 * host memory. These aliases mark the whole VCA device as one IOMMU 4290 * group. 4291 * 4292 * All possible slot numbers (0x20) are used, since we are unable to tell 4293 * what slot is used on other side. This quirk is intended for both host 4294 * and computational unit sides. The VCA devices have up to five functions 4295 * (four for DMA channels and one additional). 4296 */ 4297static void quirk_pex_vca_alias(struct pci_dev *pdev) 4298{ 4299 const unsigned int num_pci_slots = 0x20; 4300 unsigned int slot; 4301 4302 for (slot = 0; slot < num_pci_slots; slot++) 4303 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5); 4304} 4305DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias); 4306DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias); 4307DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias); 4308DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias); 4309DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias); 4310DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias); 4311 4312/* 4313 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are 4314 * associated not at the root bus, but at a bridge below. This quirk avoids 4315 * generating invalid DMA aliases. 4316 */ 4317static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev) 4318{ 4319 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; 4320} 4321DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, 4322 quirk_bridge_cavm_thrx2_pcie_root); 4323DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, 4324 quirk_bridge_cavm_thrx2_pcie_root); 4325 4326/* 4327 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) 4328 * class code. Fix it. 4329 */ 4330static void quirk_tw686x_class(struct pci_dev *pdev) 4331{ 4332 u32 class = pdev->class; 4333 4334 /* Use "Multimedia controller" class */ 4335 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; 4336 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", 4337 class, pdev->class); 4338} 4339DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, 4340 quirk_tw686x_class); 4341DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8, 4342 quirk_tw686x_class); 4343DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8, 4344 quirk_tw686x_class); 4345DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, 4346 quirk_tw686x_class); 4347 4348/* 4349 * Some devices have problems with Transaction Layer Packets with the Relaxed 4350 * Ordering Attribute set. Such devices should mark themselves and other 4351 * device drivers should check before sending TLPs with RO set. 4352 */ 4353static void quirk_relaxedordering_disable(struct pci_dev *dev) 4354{ 4355 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; 4356 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); 4357} 4358 4359/* 4360 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root 4361 * Complex have a Flow Control Credit issue which can cause performance 4362 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set. 4363 */ 4364DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8, 4365 quirk_relaxedordering_disable); 4366DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, 4367 quirk_relaxedordering_disable); 4368DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8, 4369 quirk_relaxedordering_disable); 4370DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, 4371 quirk_relaxedordering_disable); 4372DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8, 4373 quirk_relaxedordering_disable); 4374DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8, 4375 quirk_relaxedordering_disable); 4376DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8, 4377 quirk_relaxedordering_disable); 4378DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, 4379 quirk_relaxedordering_disable); 4380DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8, 4381 quirk_relaxedordering_disable); 4382DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8, 4383 quirk_relaxedordering_disable); 4384DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8, 4385 quirk_relaxedordering_disable); 4386DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8, 4387 quirk_relaxedordering_disable); 4388DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8, 4389 quirk_relaxedordering_disable); 4390DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8, 4391 quirk_relaxedordering_disable); 4392DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8, 4393 quirk_relaxedordering_disable); 4394DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8, 4395 quirk_relaxedordering_disable); 4396DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8, 4397 quirk_relaxedordering_disable); 4398DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8, 4399 quirk_relaxedordering_disable); 4400DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8, 4401 quirk_relaxedordering_disable); 4402DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8, 4403 quirk_relaxedordering_disable); 4404DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8, 4405 quirk_relaxedordering_disable); 4406DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8, 4407 quirk_relaxedordering_disable); 4408DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8, 4409 quirk_relaxedordering_disable); 4410DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8, 4411 quirk_relaxedordering_disable); 4412DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8, 4413 quirk_relaxedordering_disable); 4414DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8, 4415 quirk_relaxedordering_disable); 4416DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8, 4417 quirk_relaxedordering_disable); 4418DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8, 4419 quirk_relaxedordering_disable); 4420 4421/* 4422 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex 4423 * where Upstream Transaction Layer Packets with the Relaxed Ordering 4424 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering 4425 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules 4426 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 4427 * November 10, 2010). As a result, on this platform we can't use Relaxed 4428 * Ordering for Upstream TLPs. 4429 */ 4430DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, 4431 quirk_relaxedordering_disable); 4432DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, 4433 quirk_relaxedordering_disable); 4434DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, 4435 quirk_relaxedordering_disable); 4436 4437/* 4438 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same 4439 * values for the Attribute as were supplied in the header of the 4440 * corresponding Request, except as explicitly allowed when IDO is used." 4441 * 4442 * If a non-compliant device generates a completion with a different 4443 * attribute than the request, the receiver may accept it (which itself 4444 * seems non-compliant based on sec 2.3.2), or it may handle it as a 4445 * Malformed TLP or an Unexpected Completion, which will probably lead to a 4446 * device access timeout. 4447 * 4448 * If the non-compliant device generates completions with zero attributes 4449 * (instead of copying the attributes from the request), we can work around 4450 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in 4451 * upstream devices so they always generate requests with zero attributes. 4452 * 4453 * This affects other devices under the same Root Port, but since these 4454 * attributes are performance hints, there should be no functional problem. 4455 * 4456 * Note that Configuration Space accesses are never supposed to have TLP 4457 * Attributes, so we're safe waiting till after any Configuration Space 4458 * accesses to do the Root Port fixup. 4459 */ 4460static void quirk_disable_root_port_attributes(struct pci_dev *pdev) 4461{ 4462 struct pci_dev *root_port = pcie_find_root_port(pdev); 4463 4464 if (!root_port) { 4465 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n"); 4466 return; 4467 } 4468 4469 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", 4470 dev_name(&pdev->dev)); 4471 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL, 4472 PCI_EXP_DEVCTL_RELAX_EN | 4473 PCI_EXP_DEVCTL_NOSNOOP_EN, 0); 4474} 4475 4476/* 4477 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the 4478 * Completion it generates. 4479 */ 4480static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev) 4481{ 4482 /* 4483 * This mask/compare operation selects for Physical Function 4 on a 4484 * T5. We only need to fix up the Root Port once for any of the 4485 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely 4486 * 0x54xx so we use that one. 4487 */ 4488 if ((pdev->device & 0xff00) == 0x5400) 4489 quirk_disable_root_port_attributes(pdev); 4490} 4491DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4492 quirk_chelsio_T5_disable_root_port_attributes); 4493 4494/* 4495 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided 4496 * by a device 4497 * @acs_ctrl_req: Bitmask of desired ACS controls 4498 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by 4499 * the hardware design 4500 * 4501 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included 4502 * in @acs_ctrl_ena, i.e., the device provides all the access controls the 4503 * caller desires. Return 0 otherwise. 4504 */ 4505static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena) 4506{ 4507 if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req) 4508 return 1; 4509 return 0; 4510} 4511 4512/* 4513 * AMD has indicated that the devices below do not support peer-to-peer 4514 * in any system where they are found in the southbridge with an AMD 4515 * IOMMU in the system. Multifunction devices that do not support 4516 * peer-to-peer between functions can claim to support a subset of ACS. 4517 * Such devices effectively enable request redirect (RR) and completion 4518 * redirect (CR) since all transactions are redirected to the upstream 4519 * root complex. 4520 * 4521 * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/ 4522 * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/ 4523 * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/ 4524 * 4525 * 1002:4385 SBx00 SMBus Controller 4526 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller 4527 * 1002:4383 SBx00 Azalia (Intel HDA) 4528 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller 4529 * 1002:4384 SBx00 PCI to PCI Bridge 4530 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 4531 * 4532 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 4533 * 4534 * 1022:780f [AMD] FCH PCI Bridge 4535 * 1022:7809 [AMD] FCH USB OHCI Controller 4536 */ 4537static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 4538{ 4539#ifdef CONFIG_ACPI 4540 struct acpi_table_header *header = NULL; 4541 acpi_status status; 4542 4543 /* Targeting multifunction devices on the SB (appears on root bus) */ 4544 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) 4545 return -ENODEV; 4546 4547 /* The IVRS table describes the AMD IOMMU */ 4548 status = acpi_get_table("IVRS", 0, &header); 4549 if (ACPI_FAILURE(status)) 4550 return -ENODEV; 4551 4552 acpi_put_table(header); 4553 4554 /* Filter out flags not applicable to multifunction */ 4555 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); 4556 4557 return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR); 4558#else 4559 return -ENODEV; 4560#endif 4561} 4562 4563static bool pci_quirk_cavium_acs_match(struct pci_dev *dev) 4564{ 4565 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4566 return false; 4567 4568 switch (dev->device) { 4569 /* 4570 * Effectively selects all downstream ports for whole ThunderX1 4571 * (which represents 8 SoCs). 4572 */ 4573 case 0xa000 ... 0xa7ff: /* ThunderX1 */ 4574 case 0xaf84: /* ThunderX2 */ 4575 case 0xb884: /* ThunderX3 */ 4576 return true; 4577 default: 4578 return false; 4579 } 4580} 4581 4582static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) 4583{ 4584 if (!pci_quirk_cavium_acs_match(dev)) 4585 return -ENOTTY; 4586 4587 /* 4588 * Cavium Root Ports don't advertise an ACS capability. However, 4589 * the RTL internally implements similar protection as if ACS had 4590 * Source Validation, Request Redirection, Completion Redirection, 4591 * and Upstream Forwarding features enabled. Assert that the 4592 * hardware implements and enables equivalent ACS functionality for 4593 * these flags. 4594 */ 4595 return pci_acs_ctrl_enabled(acs_flags, 4596 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4597} 4598 4599static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) 4600{ 4601 /* 4602 * X-Gene Root Ports matching this quirk do not allow peer-to-peer 4603 * transactions with others, allowing masking out these bits as if they 4604 * were unimplemented in the ACS capability. 4605 */ 4606 return pci_acs_ctrl_enabled(acs_flags, 4607 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4608} 4609 4610/* 4611 * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability. 4612 * But the implementation could block peer-to-peer transactions between them 4613 * and provide ACS-like functionality. 4614 */ 4615static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags) 4616{ 4617 if (!pci_is_pcie(dev) || 4618 ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) && 4619 (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))) 4620 return -ENOTTY; 4621 4622 /* 4623 * Future Zhaoxin Root Ports and Switch Downstream Ports will 4624 * implement ACS capability in accordance with the PCIe Spec. 4625 */ 4626 switch (dev->device) { 4627 case 0x0710 ... 0x071e: 4628 case 0x0721: 4629 case 0x0723 ... 0x0752: 4630 return pci_acs_ctrl_enabled(acs_flags, 4631 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4632 } 4633 4634 return false; 4635} 4636 4637/* 4638 * Many Intel PCH Root Ports do provide ACS-like features to disable peer 4639 * transactions and validate bus numbers in requests, but do not provide an 4640 * actual PCIe ACS capability. This is the list of device IDs known to fall 4641 * into that category as provided by Intel in Red Hat bugzilla 1037684. 4642 */ 4643static const u16 pci_quirk_intel_pch_acs_ids[] = { 4644 /* Ibexpeak PCH */ 4645 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, 4646 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, 4647 /* Cougarpoint PCH */ 4648 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, 4649 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, 4650 /* Pantherpoint PCH */ 4651 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, 4652 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, 4653 /* Lynxpoint-H PCH */ 4654 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, 4655 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 4656 /* Lynxpoint-LP PCH */ 4657 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, 4658 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, 4659 /* Wildcat PCH */ 4660 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 4661 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 4662 /* Patsburg (X79) PCH */ 4663 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, 4664 /* Wellsburg (X99) PCH */ 4665 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, 4666 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, 4667 /* Lynx Point (9 series) PCH */ 4668 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, 4669}; 4670 4671static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 4672{ 4673 int i; 4674 4675 /* Filter out a few obvious non-matches first */ 4676 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4677 return false; 4678 4679 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) 4680 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) 4681 return true; 4682 4683 return false; 4684} 4685 4686static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 4687{ 4688 if (!pci_quirk_intel_pch_acs_match(dev)) 4689 return -ENOTTY; 4690 4691 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) 4692 return pci_acs_ctrl_enabled(acs_flags, 4693 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4694 4695 return pci_acs_ctrl_enabled(acs_flags, 0); 4696} 4697 4698/* 4699 * These QCOM Root Ports do provide ACS-like features to disable peer 4700 * transactions and validate bus numbers in requests, but do not provide an 4701 * actual PCIe ACS capability. Hardware supports source validation but it 4702 * will report the issue as Completer Abort instead of ACS Violation. 4703 * Hardware doesn't support peer-to-peer and each Root Port is a Root 4704 * Complex with unique segment numbers. It is not possible for one Root 4705 * Port to pass traffic to another Root Port. All PCIe transactions are 4706 * terminated inside the Root Port. 4707 */ 4708static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) 4709{ 4710 return pci_acs_ctrl_enabled(acs_flags, 4711 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4712} 4713 4714/* 4715 * Each of these NXP Root Ports is in a Root Complex with a unique segment 4716 * number and does provide isolation features to disable peer transactions 4717 * and validate bus numbers in requests, but does not provide an ACS 4718 * capability. 4719 */ 4720static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags) 4721{ 4722 return pci_acs_ctrl_enabled(acs_flags, 4723 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4724} 4725 4726static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags) 4727{ 4728 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4729 return -ENOTTY; 4730 4731 /* 4732 * Amazon's Annapurna Labs root ports don't include an ACS capability, 4733 * but do include ACS-like functionality. The hardware doesn't support 4734 * peer-to-peer transactions via the root port and each has a unique 4735 * segment number. 4736 * 4737 * Additionally, the root ports cannot send traffic to each other. 4738 */ 4739 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4740 4741 return acs_flags ? 0 : 1; 4742} 4743 4744/* 4745 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in 4746 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, 4747 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and 4748 * control registers whereas the PCIe spec packs them into words (Rev 3.0, 4749 * 7.16 ACS Extended Capability). The bit definitions are correct, but the 4750 * control register is at offset 8 instead of 6 and we should probably use 4751 * dword accesses to them. This applies to the following PCI Device IDs, as 4752 * found in volume 1 of the datasheet[2]: 4753 * 4754 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16} 4755 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20} 4756 * 4757 * N.B. This doesn't fix what lspci shows. 4758 * 4759 * The 100 series chipset specification update includes this as errata #23[3]. 4760 * 4761 * The 200 series chipset (Union Point) has the same bug according to the 4762 * specification update (Intel 200 Series Chipset Family Platform Controller 4763 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, 4764 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this 4765 * chipset include: 4766 * 4767 * 0xa290-0xa29f PCI Express Root port #{0-16} 4768 * 0xa2e7-0xa2ee PCI Express Root port #{17-24} 4769 * 4770 * Mobile chipsets are also affected, 7th & 8th Generation 4771 * Specification update confirms ACS errata 22, status no fix: (7th Generation 4772 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel 4773 * Processor Family I/O for U Quad Core Platforms Specification Update, 4774 * August 2017, Revision 002, Document#: 334660-002)[6] 4775 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O 4776 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U 4777 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7] 4778 * 4779 * 0x9d10-0x9d1b PCI Express Root port #{1-12} 4780 * 4781 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html 4782 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html 4783 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html 4784 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html 4785 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html 4786 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html 4787 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html 4788 */ 4789static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) 4790{ 4791 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4792 return false; 4793 4794 switch (dev->device) { 4795 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ 4796 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ 4797 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */ 4798 return true; 4799 } 4800 4801 return false; 4802} 4803 4804#define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) 4805 4806static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) 4807{ 4808 int pos; 4809 u32 cap, ctrl; 4810 4811 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4812 return -ENOTTY; 4813 4814 pos = dev->acs_cap; 4815 if (!pos) 4816 return -ENOTTY; 4817 4818 /* see pci_acs_flags_enabled() */ 4819 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4820 acs_flags &= (cap | PCI_ACS_EC); 4821 4822 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4823 4824 return pci_acs_ctrl_enabled(acs_flags, ctrl); 4825} 4826 4827static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) 4828{ 4829 /* 4830 * SV, TB, and UF are not relevant to multifunction endpoints. 4831 * 4832 * Multifunction devices are only required to implement RR, CR, and DT 4833 * in their ACS capability if they support peer-to-peer transactions. 4834 * Devices matching this quirk have been verified by the vendor to not 4835 * perform peer-to-peer with other functions, allowing us to mask out 4836 * these bits as if they were unimplemented in the ACS capability. 4837 */ 4838 return pci_acs_ctrl_enabled(acs_flags, 4839 PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 4840 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 4841} 4842 4843static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags) 4844{ 4845 /* 4846 * Intel RCiEP's are required to allow p2p only on translated 4847 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16, 4848 * "Root-Complex Peer to Peer Considerations". 4849 */ 4850 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END) 4851 return -ENOTTY; 4852 4853 return pci_acs_ctrl_enabled(acs_flags, 4854 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4855} 4856 4857static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags) 4858{ 4859 /* 4860 * iProc PAXB Root Ports don't advertise an ACS capability, but 4861 * they do not allow peer-to-peer transactions between Root Ports. 4862 * Allow each Root Port to be in a separate IOMMU group by masking 4863 * SV/RR/CR/UF bits. 4864 */ 4865 return pci_acs_ctrl_enabled(acs_flags, 4866 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4867} 4868 4869/* 4870 * Wangxun 10G/1G NICs have no ACS capability, and on multi-function 4871 * devices, peer-to-peer transactions are not be used between the functions. 4872 * So add an ACS quirk for below devices to isolate functions. 4873 * SFxxx 1G NICs(em). 4874 * RP1000/RP2000 10G NICs(sp). 4875 */ 4876static int pci_quirk_wangxun_nic_acs(struct pci_dev *dev, u16 acs_flags) 4877{ 4878 switch (dev->device) { 4879 case 0x0100 ... 0x010F: 4880 case 0x1001: 4881 case 0x2001: 4882 return pci_acs_ctrl_enabled(acs_flags, 4883 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4884 } 4885 4886 return false; 4887} 4888 4889static const struct pci_dev_acs_enabled { 4890 u16 vendor; 4891 u16 device; 4892 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 4893} pci_dev_acs_enabled[] = { 4894 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, 4895 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, 4896 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, 4897 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 4898 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 4899 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 4900 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, 4901 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, 4902 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, 4903 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, 4904 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs }, 4905 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, 4906 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, 4907 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, 4908 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, 4909 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, 4910 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, 4911 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, 4912 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, 4913 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, 4914 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, 4915 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, 4916 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, 4917 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, 4918 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, 4919 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, 4920 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, 4921 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, 4922 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, 4923 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, 4924 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, 4925 /* 82580 */ 4926 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, 4927 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, 4928 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, 4929 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, 4930 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, 4931 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, 4932 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, 4933 /* 82576 */ 4934 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, 4935 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, 4936 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, 4937 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, 4938 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, 4939 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, 4940 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, 4941 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, 4942 /* 82575 */ 4943 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, 4944 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, 4945 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, 4946 /* I350 */ 4947 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, 4948 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, 4949 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, 4950 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, 4951 /* 82571 (Quads omitted due to non-ACS switch) */ 4952 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, 4953 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, 4954 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, 4955 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, 4956 /* I219 */ 4957 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, 4958 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, 4959 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs }, 4960 /* QCOM QDF2xxx root ports */ 4961 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs }, 4962 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs }, 4963 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */ 4964 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs }, 4965 /* Intel PCH root ports */ 4966 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 4967 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs }, 4968 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ 4969 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ 4970 /* Cavium ThunderX */ 4971 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, 4972 /* Cavium multi-function devices */ 4973 { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs }, 4974 { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs }, 4975 { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs }, 4976 /* APM X-Gene */ 4977 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, 4978 /* Ampere Computing */ 4979 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs }, 4980 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs }, 4981 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs }, 4982 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs }, 4983 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs }, 4984 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs }, 4985 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs }, 4986 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs }, 4987 /* Broadcom multi-function device */ 4988 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs }, 4989 { PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs }, 4990 { PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs }, 4991 { PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs }, 4992 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs }, 4993 /* Amazon Annapurna Labs */ 4994 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs }, 4995 /* Zhaoxin multi-function devices */ 4996 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs }, 4997 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs }, 4998 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs }, 4999 /* NXP root ports, xx=16, 12, or 08 cores */ 5000 /* LX2xx0A : without security features + CAN-FD */ 5001 { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs }, 5002 { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs }, 5003 { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs }, 5004 /* LX2xx0C : security features + CAN-FD */ 5005 { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs }, 5006 { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs }, 5007 { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs }, 5008 /* LX2xx0E : security features + CAN */ 5009 { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs }, 5010 { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs }, 5011 { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs }, 5012 /* LX2xx0N : without security features + CAN */ 5013 { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs }, 5014 { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs }, 5015 { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs }, 5016 /* LX2xx2A : without security features + CAN-FD */ 5017 { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs }, 5018 { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs }, 5019 { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs }, 5020 /* LX2xx2C : security features + CAN-FD */ 5021 { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs }, 5022 { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs }, 5023 { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs }, 5024 /* LX2xx2E : security features + CAN */ 5025 { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs }, 5026 { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs }, 5027 { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs }, 5028 /* LX2xx2N : without security features + CAN */ 5029 { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs }, 5030 { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs }, 5031 { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs }, 5032 /* Zhaoxin Root/Downstream Ports */ 5033 { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs }, 5034 /* Wangxun nics */ 5035 { PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs }, 5036 { 0 } 5037}; 5038 5039/* 5040 * pci_dev_specific_acs_enabled - check whether device provides ACS controls 5041 * @dev: PCI device 5042 * @acs_flags: Bitmask of desired ACS controls 5043 * 5044 * Returns: 5045 * -ENOTTY: No quirk applies to this device; we can't tell whether the 5046 * device provides the desired controls 5047 * 0: Device does not provide all the desired controls 5048 * >0: Device provides all the controls in @acs_flags 5049 */ 5050int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) 5051{ 5052 const struct pci_dev_acs_enabled *i; 5053 int ret; 5054 5055 /* 5056 * Allow devices that do not expose standard PCIe ACS capabilities 5057 * or control to indicate their support here. Multi-function express 5058 * devices which do not allow internal peer-to-peer between functions, 5059 * but do not implement PCIe ACS may wish to return true here. 5060 */ 5061 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { 5062 if ((i->vendor == dev->vendor || 5063 i->vendor == (u16)PCI_ANY_ID) && 5064 (i->device == dev->device || 5065 i->device == (u16)PCI_ANY_ID)) { 5066 ret = i->acs_enabled(dev, acs_flags); 5067 if (ret >= 0) 5068 return ret; 5069 } 5070 } 5071 5072 return -ENOTTY; 5073} 5074 5075/* Config space offset of Root Complex Base Address register */ 5076#define INTEL_LPC_RCBA_REG 0xf0 5077/* 31:14 RCBA address */ 5078#define INTEL_LPC_RCBA_MASK 0xffffc000 5079/* RCBA Enable */ 5080#define INTEL_LPC_RCBA_ENABLE (1 << 0) 5081 5082/* Backbone Scratch Pad Register */ 5083#define INTEL_BSPR_REG 0x1104 5084/* Backbone Peer Non-Posted Disable */ 5085#define INTEL_BSPR_REG_BPNPD (1 << 8) 5086/* Backbone Peer Posted Disable */ 5087#define INTEL_BSPR_REG_BPPD (1 << 9) 5088 5089/* Upstream Peer Decode Configuration Register */ 5090#define INTEL_UPDCR_REG 0x1014 5091/* 5:0 Peer Decode Enable bits */ 5092#define INTEL_UPDCR_REG_MASK 0x3f 5093 5094static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) 5095{ 5096 u32 rcba, bspr, updcr; 5097 void __iomem *rcba_mem; 5098 5099 /* 5100 * Read the RCBA register from the LPC (D31:F0). PCH root ports 5101 * are D28:F* and therefore get probed before LPC, thus we can't 5102 * use pci_get_slot()/pci_read_config_dword() here. 5103 */ 5104 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 5105 INTEL_LPC_RCBA_REG, &rcba); 5106 if (!(rcba & INTEL_LPC_RCBA_ENABLE)) 5107 return -EINVAL; 5108 5109 rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK, 5110 PAGE_ALIGN(INTEL_UPDCR_REG)); 5111 if (!rcba_mem) 5112 return -ENOMEM; 5113 5114 /* 5115 * The BSPR can disallow peer cycles, but it's set by soft strap and 5116 * therefore read-only. If both posted and non-posted peer cycles are 5117 * disallowed, we're ok. If either are allowed, then we need to use 5118 * the UPDCR to disable peer decodes for each port. This provides the 5119 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5120 */ 5121 bspr = readl(rcba_mem + INTEL_BSPR_REG); 5122 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; 5123 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 5124 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 5125 if (updcr & INTEL_UPDCR_REG_MASK) { 5126 pci_info(dev, "Disabling UPDCR peer decodes\n"); 5127 updcr &= ~INTEL_UPDCR_REG_MASK; 5128 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 5129 } 5130 } 5131 5132 iounmap(rcba_mem); 5133 return 0; 5134} 5135 5136/* Miscellaneous Port Configuration register */ 5137#define INTEL_MPC_REG 0xd8 5138/* MPC: Invalid Receive Bus Number Check Enable */ 5139#define INTEL_MPC_REG_IRBNCE (1 << 26) 5140 5141static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) 5142{ 5143 u32 mpc; 5144 5145 /* 5146 * When enabled, the IRBNCE bit of the MPC register enables the 5147 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which 5148 * ensures that requester IDs fall within the bus number range 5149 * of the bridge. Enable if not already. 5150 */ 5151 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 5152 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 5153 pci_info(dev, "Enabling MPC IRBNCE\n"); 5154 mpc |= INTEL_MPC_REG_IRBNCE; 5155 pci_write_config_word(dev, INTEL_MPC_REG, mpc); 5156 } 5157} 5158 5159/* 5160 * Currently this quirk does the equivalent of 5161 * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5162 * 5163 * TODO: This quirk also needs to do equivalent of PCI_ACS_TB, 5164 * if dev->external_facing || dev->untrusted 5165 */ 5166static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) 5167{ 5168 if (!pci_quirk_intel_pch_acs_match(dev)) 5169 return -ENOTTY; 5170 5171 if (pci_quirk_enable_intel_lpc_acs(dev)) { 5172 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n"); 5173 return 0; 5174 } 5175 5176 pci_quirk_enable_intel_rp_mpc_acs(dev); 5177 5178 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 5179 5180 pci_info(dev, "Intel PCH root port ACS workaround enabled\n"); 5181 5182 return 0; 5183} 5184 5185static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) 5186{ 5187 int pos; 5188 u32 cap, ctrl; 5189 5190 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5191 return -ENOTTY; 5192 5193 pos = dev->acs_cap; 5194 if (!pos) 5195 return -ENOTTY; 5196 5197 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5198 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5199 5200 ctrl |= (cap & PCI_ACS_SV); 5201 ctrl |= (cap & PCI_ACS_RR); 5202 ctrl |= (cap & PCI_ACS_CR); 5203 ctrl |= (cap & PCI_ACS_UF); 5204 5205 if (dev->external_facing || dev->untrusted) 5206 ctrl |= (cap & PCI_ACS_TB); 5207 5208 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5209 5210 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n"); 5211 5212 return 0; 5213} 5214 5215static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev) 5216{ 5217 int pos; 5218 u32 cap, ctrl; 5219 5220 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5221 return -ENOTTY; 5222 5223 pos = dev->acs_cap; 5224 if (!pos) 5225 return -ENOTTY; 5226 5227 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5228 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5229 5230 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); 5231 5232 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5233 5234 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n"); 5235 5236 return 0; 5237} 5238 5239static const struct pci_dev_acs_ops { 5240 u16 vendor; 5241 u16 device; 5242 int (*enable_acs)(struct pci_dev *dev); 5243 int (*disable_acs_redir)(struct pci_dev *dev); 5244} pci_dev_acs_ops[] = { 5245 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5246 .enable_acs = pci_quirk_enable_intel_pch_acs, 5247 }, 5248 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5249 .enable_acs = pci_quirk_enable_intel_spt_pch_acs, 5250 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir, 5251 }, 5252}; 5253 5254int pci_dev_specific_enable_acs(struct pci_dev *dev) 5255{ 5256 const struct pci_dev_acs_ops *p; 5257 int i, ret; 5258 5259 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5260 p = &pci_dev_acs_ops[i]; 5261 if ((p->vendor == dev->vendor || 5262 p->vendor == (u16)PCI_ANY_ID) && 5263 (p->device == dev->device || 5264 p->device == (u16)PCI_ANY_ID) && 5265 p->enable_acs) { 5266 ret = p->enable_acs(dev); 5267 if (ret >= 0) 5268 return ret; 5269 } 5270 } 5271 5272 return -ENOTTY; 5273} 5274 5275int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 5276{ 5277 const struct pci_dev_acs_ops *p; 5278 int i, ret; 5279 5280 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5281 p = &pci_dev_acs_ops[i]; 5282 if ((p->vendor == dev->vendor || 5283 p->vendor == (u16)PCI_ANY_ID) && 5284 (p->device == dev->device || 5285 p->device == (u16)PCI_ANY_ID) && 5286 p->disable_acs_redir) { 5287 ret = p->disable_acs_redir(dev); 5288 if (ret >= 0) 5289 return ret; 5290 } 5291 } 5292 5293 return -ENOTTY; 5294} 5295 5296/* 5297 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with 5298 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The 5299 * Next Capability pointer in the MSI Capability Structure should point to 5300 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating 5301 * the list. 5302 */ 5303static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) 5304{ 5305 int pos, i = 0; 5306 u8 next_cap; 5307 u16 reg16, *cap; 5308 struct pci_cap_saved_state *state; 5309 5310 /* Bail if the hardware bug is fixed */ 5311 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) 5312 return; 5313 5314 /* Bail if MSI Capability Structure is not found for some reason */ 5315 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); 5316 if (!pos) 5317 return; 5318 5319 /* 5320 * Bail if Next Capability pointer in the MSI Capability Structure 5321 * is not the expected incorrect 0x00. 5322 */ 5323 pci_read_config_byte(pdev, pos + 1, &next_cap); 5324 if (next_cap) 5325 return; 5326 5327 /* 5328 * PCIe Capability Structure is expected to be at 0x50 and should 5329 * terminate the list (Next Capability pointer is 0x00). Verify 5330 * Capability Id and Next Capability pointer is as expected. 5331 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() 5332 * to correctly set kernel data structures which have already been 5333 * set incorrectly due to the hardware bug. 5334 */ 5335 pos = 0x50; 5336 pci_read_config_word(pdev, pos, ®16); 5337 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { 5338 u32 status; 5339#ifndef PCI_EXP_SAVE_REGS 5340#define PCI_EXP_SAVE_REGS 7 5341#endif 5342 int size = PCI_EXP_SAVE_REGS * sizeof(u16); 5343 5344 pdev->pcie_cap = pos; 5345 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 5346 pdev->pcie_flags_reg = reg16; 5347 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 5348 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 5349 5350 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 5351 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) != 5352 PCIBIOS_SUCCESSFUL || (status == 0xffffffff)) 5353 pdev->cfg_size = PCI_CFG_SPACE_SIZE; 5354 5355 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) 5356 return; 5357 5358 /* Save PCIe cap */ 5359 state = kzalloc(sizeof(*state) + size, GFP_KERNEL); 5360 if (!state) 5361 return; 5362 5363 state->cap.cap_nr = PCI_CAP_ID_EXP; 5364 state->cap.cap_extended = 0; 5365 state->cap.size = size; 5366 cap = (u16 *)&state->cap.data[0]; 5367 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]); 5368 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]); 5369 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]); 5370 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]); 5371 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]); 5372 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]); 5373 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]); 5374 hlist_add_head(&state->next, &pdev->saved_cap_space); 5375 } 5376} 5377DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); 5378 5379/* 5380 * FLR may cause the following to devices to hang: 5381 * 5382 * AMD Starship/Matisse HD Audio Controller 0x1487 5383 * AMD Starship USB 3.0 Host Controller 0x148c 5384 * AMD Matisse USB 3.0 Host Controller 0x149c 5385 * Intel 82579LM Gigabit Ethernet Controller 0x1502 5386 * Intel 82579V Gigabit Ethernet Controller 0x1503 5387 * 5388 */ 5389static void quirk_no_flr(struct pci_dev *dev) 5390{ 5391 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; 5392} 5393DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr); 5394DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr); 5395DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr); 5396DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr); 5397DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr); 5398DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr); 5399 5400static void quirk_no_ext_tags(struct pci_dev *pdev) 5401{ 5402 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); 5403 5404 if (!bridge) 5405 return; 5406 5407 bridge->no_ext_tags = 1; 5408 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n"); 5409 5410 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); 5411} 5412DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags); 5413DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags); 5414DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags); 5415DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags); 5416DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags); 5417DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags); 5418DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags); 5419 5420#ifdef CONFIG_PCI_ATS 5421static void quirk_no_ats(struct pci_dev *pdev) 5422{ 5423 pci_info(pdev, "disabling ATS\n"); 5424 pdev->ats_cap = 0; 5425} 5426 5427/* 5428 * Some devices require additional driver setup to enable ATS. Don't use 5429 * ATS for those devices as ATS will be enabled before the driver has had a 5430 * chance to load and configure the device. 5431 */ 5432static void quirk_amd_harvest_no_ats(struct pci_dev *pdev) 5433{ 5434 if ((pdev->device == 0x7312 && pdev->revision != 0x00) || 5435 (pdev->device == 0x7340 && pdev->revision != 0xc5) || 5436 (pdev->device == 0x7341 && pdev->revision != 0x00)) 5437 return; 5438 5439 quirk_no_ats(pdev); 5440} 5441 5442/* AMD Stoney platform GPU */ 5443DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats); 5444/* AMD Iceland dGPU */ 5445DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats); 5446/* AMD Navi10 dGPU */ 5447DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats); 5448/* AMD Navi14 dGPU */ 5449DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats); 5450DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats); 5451 5452/* 5453 * Intel IPU E2000 revisions before C0 implement incorrect endianness 5454 * in ATS Invalidate Request message body. Disable ATS for those devices. 5455 */ 5456static void quirk_intel_e2000_no_ats(struct pci_dev *pdev) 5457{ 5458 if (pdev->revision < 0x20) 5459 quirk_no_ats(pdev); 5460} 5461DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1451, quirk_intel_e2000_no_ats); 5462DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1452, quirk_intel_e2000_no_ats); 5463DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1453, quirk_intel_e2000_no_ats); 5464DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1454, quirk_intel_e2000_no_ats); 5465DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1455, quirk_intel_e2000_no_ats); 5466DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats); 5467DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats); 5468DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats); 5469DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats); 5470#endif /* CONFIG_PCI_ATS */ 5471 5472/* Freescale PCIe doesn't support MSI in RC mode */ 5473static void quirk_fsl_no_msi(struct pci_dev *pdev) 5474{ 5475 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) 5476 pdev->no_msi = 1; 5477} 5478DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi); 5479 5480/* 5481 * Although not allowed by the spec, some multi-function devices have 5482 * dependencies of one function (consumer) on another (supplier). For the 5483 * consumer to work in D0, the supplier must also be in D0. Create a 5484 * device link from the consumer to the supplier to enforce this 5485 * dependency. Runtime PM is allowed by default on the consumer to prevent 5486 * it from permanently keeping the supplier awake. 5487 */ 5488static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer, 5489 unsigned int supplier, unsigned int class, 5490 unsigned int class_shift) 5491{ 5492 struct pci_dev *supplier_pdev; 5493 5494 if (PCI_FUNC(pdev->devfn) != consumer) 5495 return; 5496 5497 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), 5498 pdev->bus->number, 5499 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier)); 5500 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) { 5501 pci_dev_put(supplier_pdev); 5502 return; 5503 } 5504 5505 if (device_link_add(&pdev->dev, &supplier_pdev->dev, 5506 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) 5507 pci_info(pdev, "D0 power state depends on %s\n", 5508 pci_name(supplier_pdev)); 5509 else 5510 pci_err(pdev, "Cannot enforce power dependency on %s\n", 5511 pci_name(supplier_pdev)); 5512 5513 pm_runtime_allow(&pdev->dev); 5514 pci_dev_put(supplier_pdev); 5515} 5516 5517/* 5518 * Create device link for GPUs with integrated HDA controller for streaming 5519 * audio to attached displays. 5520 */ 5521static void quirk_gpu_hda(struct pci_dev *hda) 5522{ 5523 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16); 5524} 5525DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5526 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5527DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID, 5528 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5529DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5530 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5531 5532/* 5533 * Create device link for GPUs with integrated USB xHCI Host 5534 * controller to VGA. 5535 */ 5536static void quirk_gpu_usb(struct pci_dev *usb) 5537{ 5538 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16); 5539} 5540DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5541 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5542DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5543 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5544 5545/* 5546 * Create device link for GPUs with integrated Type-C UCSI controller 5547 * to VGA. Currently there is no class code defined for UCSI device over PCI 5548 * so using UNKNOWN class for now and it will be updated when UCSI 5549 * over PCI gets a class code. 5550 */ 5551#define PCI_CLASS_SERIAL_UNKNOWN 0x0c80 5552static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi) 5553{ 5554 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16); 5555} 5556DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5557 PCI_CLASS_SERIAL_UNKNOWN, 8, 5558 quirk_gpu_usb_typec_ucsi); 5559DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5560 PCI_CLASS_SERIAL_UNKNOWN, 8, 5561 quirk_gpu_usb_typec_ucsi); 5562 5563/* 5564 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it 5565 * disabled. https://devtalk.nvidia.com/default/topic/1024022 5566 */ 5567static void quirk_nvidia_hda(struct pci_dev *gpu) 5568{ 5569 u8 hdr_type; 5570 u32 val; 5571 5572 /* There was no integrated HDA controller before MCP89 */ 5573 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M) 5574 return; 5575 5576 /* Bit 25 at offset 0x488 enables the HDA controller */ 5577 pci_read_config_dword(gpu, 0x488, &val); 5578 if (val & BIT(25)) 5579 return; 5580 5581 pci_info(gpu, "Enabling HDA controller\n"); 5582 pci_write_config_dword(gpu, 0x488, val | BIT(25)); 5583 5584 /* The GPU becomes a multi-function device when the HDA is enabled */ 5585 pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type); 5586 gpu->multifunction = !!(hdr_type & 0x80); 5587} 5588DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5589 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5590DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5591 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5592 5593/* 5594 * Some IDT switches incorrectly flag an ACS Source Validation error on 5595 * completions for config read requests even though PCIe r4.0, sec 5596 * 6.12.1.1, says that completions are never affected by ACS Source 5597 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36: 5598 * 5599 * Item #36 - Downstream port applies ACS Source Validation to Completions 5600 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that 5601 * completions are never affected by ACS Source Validation. However, 5602 * completions received by a downstream port of the PCIe switch from a 5603 * device that has not yet captured a PCIe bus number are incorrectly 5604 * dropped by ACS Source Validation by the switch downstream port. 5605 * 5606 * The workaround suggested by IDT is to issue a config write to the 5607 * downstream device before issuing the first config read. This allows the 5608 * downstream device to capture its bus and device numbers (see PCIe r4.0, 5609 * sec 2.2.9), thus avoiding the ACS error on the completion. 5610 * 5611 * However, we don't know when the device is ready to accept the config 5612 * write, so we do config reads until we receive a non-Config Request Retry 5613 * Status, then do the config write. 5614 * 5615 * To avoid hitting the erratum when doing the config reads, we disable ACS 5616 * SV around this process. 5617 */ 5618int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout) 5619{ 5620 int pos; 5621 u16 ctrl = 0; 5622 bool found; 5623 struct pci_dev *bridge = bus->self; 5624 5625 pos = bridge->acs_cap; 5626 5627 /* Disable ACS SV before initial config reads */ 5628 if (pos) { 5629 pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl); 5630 if (ctrl & PCI_ACS_SV) 5631 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, 5632 ctrl & ~PCI_ACS_SV); 5633 } 5634 5635 found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 5636 5637 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ 5638 if (found) 5639 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0); 5640 5641 /* Re-enable ACS_SV if it was previously enabled */ 5642 if (ctrl & PCI_ACS_SV) 5643 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl); 5644 5645 return found; 5646} 5647 5648/* 5649 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between 5650 * NT endpoints via the internal switch fabric. These IDs replace the 5651 * originating requestor ID TLPs which access host memory on peer NTB 5652 * ports. Therefore, all proxy IDs must be aliased to the NTB device 5653 * to permit access when the IOMMU is turned on. 5654 */ 5655static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev) 5656{ 5657 void __iomem *mmio; 5658 struct ntb_info_regs __iomem *mmio_ntb; 5659 struct ntb_ctrl_regs __iomem *mmio_ctrl; 5660 u64 partition_map; 5661 u8 partition; 5662 int pp; 5663 5664 if (pci_enable_device(pdev)) { 5665 pci_err(pdev, "Cannot enable Switchtec device\n"); 5666 return; 5667 } 5668 5669 mmio = pci_iomap(pdev, 0, 0); 5670 if (mmio == NULL) { 5671 pci_disable_device(pdev); 5672 pci_err(pdev, "Cannot iomap Switchtec device\n"); 5673 return; 5674 } 5675 5676 pci_info(pdev, "Setting Switchtec proxy ID aliases\n"); 5677 5678 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET; 5679 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET; 5680 5681 partition = ioread8(&mmio_ntb->partition_id); 5682 5683 partition_map = ioread32(&mmio_ntb->ep_map); 5684 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; 5685 partition_map &= ~(1ULL << partition); 5686 5687 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) { 5688 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl; 5689 u32 table_sz = 0; 5690 int te; 5691 5692 if (!(partition_map & (1ULL << pp))) 5693 continue; 5694 5695 pci_dbg(pdev, "Processing partition %d\n", pp); 5696 5697 mmio_peer_ctrl = &mmio_ctrl[pp]; 5698 5699 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); 5700 if (!table_sz) { 5701 pci_warn(pdev, "Partition %d table_sz 0\n", pp); 5702 continue; 5703 } 5704 5705 if (table_sz > 512) { 5706 pci_warn(pdev, 5707 "Invalid Switchtec partition %d table_sz %d\n", 5708 pp, table_sz); 5709 continue; 5710 } 5711 5712 for (te = 0; te < table_sz; te++) { 5713 u32 rid_entry; 5714 u8 devfn; 5715 5716 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); 5717 devfn = (rid_entry >> 1) & 0xFF; 5718 pci_dbg(pdev, 5719 "Aliasing Partition %d Proxy ID %02x.%d\n", 5720 pp, PCI_SLOT(devfn), PCI_FUNC(devfn)); 5721 pci_add_dma_alias(pdev, devfn, 1); 5722 } 5723 } 5724 5725 pci_iounmap(pdev, mmio); 5726 pci_disable_device(pdev); 5727} 5728#define SWITCHTEC_QUIRK(vid) \ 5729 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \ 5730 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) 5731 5732SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */ 5733SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */ 5734SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */ 5735SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */ 5736SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */ 5737SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */ 5738SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */ 5739SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */ 5740SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */ 5741SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */ 5742SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */ 5743SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */ 5744SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */ 5745SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */ 5746SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */ 5747SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */ 5748SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */ 5749SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */ 5750SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */ 5751SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */ 5752SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */ 5753SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */ 5754SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */ 5755SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */ 5756SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */ 5757SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */ 5758SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */ 5759SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */ 5760SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */ 5761SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */ 5762SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */ 5763SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */ 5764SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */ 5765SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */ 5766SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */ 5767SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */ 5768SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */ 5769SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */ 5770SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */ 5771SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */ 5772SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */ 5773SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */ 5774SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */ 5775SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */ 5776SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */ 5777SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */ 5778SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */ 5779SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */ 5780 5781/* 5782 * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints. 5783 * These IDs are used to forward responses to the originator on the other 5784 * side of the NTB. Alias all possible IDs to the NTB to permit access when 5785 * the IOMMU is turned on. 5786 */ 5787static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev) 5788{ 5789 pci_info(pdev, "Setting PLX NTB proxy ID aliases\n"); 5790 /* PLX NTB may use all 256 devfns */ 5791 pci_add_dma_alias(pdev, 0, 256); 5792} 5793DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias); 5794DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias); 5795 5796/* 5797 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does 5798 * not always reset the secondary Nvidia GPU between reboots if the system 5799 * is configured to use Hybrid Graphics mode. This results in the GPU 5800 * being left in whatever state it was in during the *previous* boot, which 5801 * causes spurious interrupts from the GPU, which in turn causes us to 5802 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly, 5803 * this also completely breaks nouveau. 5804 * 5805 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a 5806 * clean state and fixes all these issues. 5807 * 5808 * When the machine is configured in Dedicated display mode, the issue 5809 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this 5810 * mode, so we can detect that and avoid resetting it. 5811 */ 5812static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev) 5813{ 5814 void __iomem *map; 5815 int ret; 5816 5817 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || 5818 pdev->subsystem_device != 0x222e || 5819 !pdev->reset_fn) 5820 return; 5821 5822 if (pci_enable_device_mem(pdev)) 5823 return; 5824 5825 /* 5826 * Based on nvkm_device_ctor() in 5827 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 5828 */ 5829 map = pci_iomap(pdev, 0, 0x23000); 5830 if (!map) { 5831 pci_err(pdev, "Can't map MMIO space\n"); 5832 goto out_disable; 5833 } 5834 5835 /* 5836 * Make sure the GPU looks like it's been POSTed before resetting 5837 * it. 5838 */ 5839 if (ioread32(map + 0x2240c) & 0x2) { 5840 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n"); 5841 ret = pci_reset_bus(pdev); 5842 if (ret < 0) 5843 pci_err(pdev, "Failed to reset GPU: %d\n", ret); 5844 } 5845 5846 iounmap(map); 5847out_disable: 5848 pci_disable_device(pdev); 5849} 5850DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1, 5851 PCI_CLASS_DISPLAY_VGA, 8, 5852 quirk_reset_lenovo_thinkpad_p50_nvgpu); 5853 5854/* 5855 * Device [1b21:2142] 5856 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device. 5857 */ 5858static void pci_fixup_no_d0_pme(struct pci_dev *dev) 5859{ 5860 pci_info(dev, "PME# does not work under D0, disabling it\n"); 5861 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); 5862} 5863DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme); 5864 5865/* 5866 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI] 5867 * 5868 * These devices advertise PME# support in all power states but don't 5869 * reliably assert it. 5870 * 5871 * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf) 5872 * says "The MSI Function is not implemented on this device" in chapters 5873 * 7.3.27, 7.3.29-7.3.31. 5874 */ 5875static void pci_fixup_no_msi_no_pme(struct pci_dev *dev) 5876{ 5877#ifdef CONFIG_PCI_MSI 5878 pci_info(dev, "MSI is not implemented on this device, disabling it\n"); 5879 dev->no_msi = 1; 5880#endif 5881 pci_info(dev, "PME# is unreliable, disabling it\n"); 5882 dev->pme_support = 0; 5883} 5884DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme); 5885DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme); 5886 5887static void apex_pci_fixup_class(struct pci_dev *pdev) 5888{ 5889 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class; 5890} 5891DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a, 5892 PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class); 5893 5894static void nvidia_ion_ahci_fixup(struct pci_dev *pdev) 5895{ 5896 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING; 5897} 5898DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup); 5899