18c2ecf20Sopenharmony_ci# SPDX-License-Identifier: GPL-2.0 28c2ecf20Sopenharmony_ci# 38c2ecf20Sopenharmony_ci# PCI Express Port Bus Configuration 48c2ecf20Sopenharmony_ci# 58c2ecf20Sopenharmony_ciconfig PCIEPORTBUS 68c2ecf20Sopenharmony_ci bool "PCI Express Port Bus support" 78c2ecf20Sopenharmony_ci help 88c2ecf20Sopenharmony_ci This enables PCI Express Port Bus support. Users can then enable 98c2ecf20Sopenharmony_ci support for Native Hot-Plug, Advanced Error Reporting, Power 108c2ecf20Sopenharmony_ci Management Events, and Downstream Port Containment. 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci# 138c2ecf20Sopenharmony_ci# Include service Kconfig here 148c2ecf20Sopenharmony_ci# 158c2ecf20Sopenharmony_ciconfig HOTPLUG_PCI_PCIE 168c2ecf20Sopenharmony_ci bool "PCI Express Hotplug driver" 178c2ecf20Sopenharmony_ci depends on HOTPLUG_PCI && PCIEPORTBUS 188c2ecf20Sopenharmony_ci help 198c2ecf20Sopenharmony_ci Say Y here if you have a motherboard that supports PCI Express Native 208c2ecf20Sopenharmony_ci Hotplug 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci When in doubt, say N. 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ciconfig PCIEAER 258c2ecf20Sopenharmony_ci bool "PCI Express Advanced Error Reporting support" 268c2ecf20Sopenharmony_ci depends on PCIEPORTBUS 278c2ecf20Sopenharmony_ci select RAS 288c2ecf20Sopenharmony_ci help 298c2ecf20Sopenharmony_ci This enables PCI Express Root Port Advanced Error Reporting 308c2ecf20Sopenharmony_ci (AER) driver support. Error reporting messages sent to Root 318c2ecf20Sopenharmony_ci Port will be handled by PCI Express AER driver. 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ciconfig PCIEAER_INJECT 348c2ecf20Sopenharmony_ci tristate "PCI Express error injection support" 358c2ecf20Sopenharmony_ci depends on PCIEAER 368c2ecf20Sopenharmony_ci select GENERIC_IRQ_INJECTION 378c2ecf20Sopenharmony_ci help 388c2ecf20Sopenharmony_ci This enables PCI Express Root Port Advanced Error Reporting 398c2ecf20Sopenharmony_ci (AER) software error injector. 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ci Debugging AER code is quite difficult because it is hard 428c2ecf20Sopenharmony_ci to trigger various real hardware errors. Software-based 438c2ecf20Sopenharmony_ci error injection can fake almost all kinds of errors with the 448c2ecf20Sopenharmony_ci help of a user space helper tool aer-inject, which can be 458c2ecf20Sopenharmony_ci gotten from: 468c2ecf20Sopenharmony_ci https://www.kernel.org/pub/linux/utils/pci/aer-inject/ 478c2ecf20Sopenharmony_ci 488c2ecf20Sopenharmony_ci# 498c2ecf20Sopenharmony_ci# PCI Express ECRC 508c2ecf20Sopenharmony_ci# 518c2ecf20Sopenharmony_ciconfig PCIE_ECRC 528c2ecf20Sopenharmony_ci bool "PCI Express ECRC settings control" 538c2ecf20Sopenharmony_ci depends on PCIEAER 548c2ecf20Sopenharmony_ci help 558c2ecf20Sopenharmony_ci Used to override firmware/bios settings for PCI Express ECRC 568c2ecf20Sopenharmony_ci (transaction layer end-to-end CRC checking). 578c2ecf20Sopenharmony_ci 588c2ecf20Sopenharmony_ci When in doubt, say N. 598c2ecf20Sopenharmony_ci 608c2ecf20Sopenharmony_ci# 618c2ecf20Sopenharmony_ci# PCI Express ASPM 628c2ecf20Sopenharmony_ci# 638c2ecf20Sopenharmony_ciconfig PCIEASPM 648c2ecf20Sopenharmony_ci bool "PCI Express ASPM control" if EXPERT 658c2ecf20Sopenharmony_ci default y 668c2ecf20Sopenharmony_ci help 678c2ecf20Sopenharmony_ci This enables OS control over PCI Express ASPM (Active State 688c2ecf20Sopenharmony_ci Power Management) and Clock Power Management. ASPM supports 698c2ecf20Sopenharmony_ci state L0/L0s/L1. 708c2ecf20Sopenharmony_ci 718c2ecf20Sopenharmony_ci ASPM is initially set up by the firmware. With this option enabled, 728c2ecf20Sopenharmony_ci Linux can modify this state in order to disable ASPM on known-bad 738c2ecf20Sopenharmony_ci hardware or configurations and enable it when known-safe. 748c2ecf20Sopenharmony_ci 758c2ecf20Sopenharmony_ci ASPM can be disabled or enabled at runtime via 768c2ecf20Sopenharmony_ci /sys/module/pcie_aspm/parameters/policy 778c2ecf20Sopenharmony_ci 788c2ecf20Sopenharmony_ci When in doubt, say Y. 798c2ecf20Sopenharmony_ci 808c2ecf20Sopenharmony_cichoice 818c2ecf20Sopenharmony_ci prompt "Default ASPM policy" 828c2ecf20Sopenharmony_ci default PCIEASPM_DEFAULT 838c2ecf20Sopenharmony_ci depends on PCIEASPM 848c2ecf20Sopenharmony_ci 858c2ecf20Sopenharmony_ciconfig PCIEASPM_DEFAULT 868c2ecf20Sopenharmony_ci bool "BIOS default" 878c2ecf20Sopenharmony_ci depends on PCIEASPM 888c2ecf20Sopenharmony_ci help 898c2ecf20Sopenharmony_ci Use the BIOS defaults for PCI Express ASPM. 908c2ecf20Sopenharmony_ci 918c2ecf20Sopenharmony_ciconfig PCIEASPM_POWERSAVE 928c2ecf20Sopenharmony_ci bool "Powersave" 938c2ecf20Sopenharmony_ci depends on PCIEASPM 948c2ecf20Sopenharmony_ci help 958c2ecf20Sopenharmony_ci Enable PCI Express ASPM L0s and L1 where possible, even if the 968c2ecf20Sopenharmony_ci BIOS did not. 978c2ecf20Sopenharmony_ci 988c2ecf20Sopenharmony_ciconfig PCIEASPM_POWER_SUPERSAVE 998c2ecf20Sopenharmony_ci bool "Power Supersave" 1008c2ecf20Sopenharmony_ci depends on PCIEASPM 1018c2ecf20Sopenharmony_ci help 1028c2ecf20Sopenharmony_ci Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where 1038c2ecf20Sopenharmony_ci possible. This would result in higher power savings while staying in L1 1048c2ecf20Sopenharmony_ci where the components support it. 1058c2ecf20Sopenharmony_ci 1068c2ecf20Sopenharmony_ciconfig PCIEASPM_PERFORMANCE 1078c2ecf20Sopenharmony_ci bool "Performance" 1088c2ecf20Sopenharmony_ci depends on PCIEASPM 1098c2ecf20Sopenharmony_ci help 1108c2ecf20Sopenharmony_ci Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them. 1118c2ecf20Sopenharmony_ciendchoice 1128c2ecf20Sopenharmony_ci 1138c2ecf20Sopenharmony_ciconfig PCIE_PME 1148c2ecf20Sopenharmony_ci def_bool y 1158c2ecf20Sopenharmony_ci depends on PCIEPORTBUS && PM 1168c2ecf20Sopenharmony_ci 1178c2ecf20Sopenharmony_ciconfig PCIE_DPC 1188c2ecf20Sopenharmony_ci bool "PCI Express Downstream Port Containment support" 1198c2ecf20Sopenharmony_ci depends on PCIEPORTBUS && PCIEAER 1208c2ecf20Sopenharmony_ci help 1218c2ecf20Sopenharmony_ci This enables PCI Express Downstream Port Containment (DPC) 1228c2ecf20Sopenharmony_ci driver support. DPC events from Root and Downstream ports 1238c2ecf20Sopenharmony_ci will be handled by the DPC driver. If your system doesn't 1248c2ecf20Sopenharmony_ci have this capability or you do not want to use this feature, 1258c2ecf20Sopenharmony_ci it is safe to answer N. 1268c2ecf20Sopenharmony_ci 1278c2ecf20Sopenharmony_ciconfig PCIE_PTM 1288c2ecf20Sopenharmony_ci bool "PCI Express Precision Time Measurement support" 1298c2ecf20Sopenharmony_ci help 1308c2ecf20Sopenharmony_ci This enables PCI Express Precision Time Measurement (PTM) 1318c2ecf20Sopenharmony_ci support. 1328c2ecf20Sopenharmony_ci 1338c2ecf20Sopenharmony_ci This is only useful if you have devices that support PTM, but it 1348c2ecf20Sopenharmony_ci is safe to enable even if you don't. 1358c2ecf20Sopenharmony_ci 1368c2ecf20Sopenharmony_ciconfig PCIE_EDR 1378c2ecf20Sopenharmony_ci bool "PCI Express Error Disconnect Recover support" 1388c2ecf20Sopenharmony_ci depends on PCIE_DPC && ACPI 1398c2ecf20Sopenharmony_ci help 1408c2ecf20Sopenharmony_ci This option adds Error Disconnect Recover support as specified 1418c2ecf20Sopenharmony_ci in the Downstream Port Containment Related Enhancements ECN to 1428c2ecf20Sopenharmony_ci the PCI Firmware Specification r3.2. Enable this if you want to 1438c2ecf20Sopenharmony_ci support hybrid DPC model which uses both firmware and OS to 1448c2ecf20Sopenharmony_ci implement DPC. 145