1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef DRIVERS_PCI_H 3#define DRIVERS_PCI_H 4 5#include <linux/pci.h> 6 7/* Number of possible devfns: 0.0 to 1f.7 inclusive */ 8#define MAX_NR_DEVFNS 256 9 10#define PCI_FIND_CAP_TTL 48 11 12#define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ 13 14extern const unsigned char pcie_link_speed[]; 15extern bool pci_early_dump; 16 17bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 18bool pcie_cap_has_rtctl(const struct pci_dev *dev); 19 20/* Functions internal to the PCI core code */ 21 22int pci_create_sysfs_dev_files(struct pci_dev *pdev); 23void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 24#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI) 25static inline void pci_create_firmware_label_files(struct pci_dev *pdev) 26{ return; } 27static inline void pci_remove_firmware_label_files(struct pci_dev *pdev) 28{ return; } 29#else 30void pci_create_firmware_label_files(struct pci_dev *pdev); 31void pci_remove_firmware_label_files(struct pci_dev *pdev); 32#endif 33void pci_cleanup_rom(struct pci_dev *dev); 34 35enum pci_mmap_api { 36 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 37 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 38}; 39int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 40 enum pci_mmap_api mmap_api); 41 42int pci_probe_reset_function(struct pci_dev *dev); 43int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 44int pci_bus_error_reset(struct pci_dev *dev); 45 46#define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ 47#define PCI_PM_D3HOT_WAIT 10 /* msec */ 48#define PCI_PM_D3COLD_WAIT 100 /* msec */ 49 50/* 51 * Following exit from Conventional Reset, devices must be ready within 1 sec 52 * (PCIe r6.0 sec 6.6.1). A D3cold to D0 transition implies a Conventional 53 * Reset (PCIe r6.0 sec 5.8). 54 */ 55#define PCI_RESET_WAIT 1000 /* msec */ 56/* 57 * Devices may extend the 1 sec period through Request Retry Status completions 58 * (PCIe r6.0 sec 2.3.1). The spec does not provide an upper limit, but 60 sec 59 * ought to be enough for any device to become responsive. 60 */ 61#define PCIE_RESET_READY_POLL_MS 60000 /* msec */ 62 63/** 64 * struct pci_platform_pm_ops - Firmware PM callbacks 65 * 66 * @bridge_d3: Does the bridge allow entering into D3 67 * 68 * @is_manageable: returns 'true' if given device is power manageable by the 69 * platform firmware 70 * 71 * @set_state: invokes the platform firmware to set the device's power state 72 * 73 * @get_state: queries the platform firmware for a device's current power state 74 * 75 * @refresh_state: asks the platform to refresh the device's power state data 76 * 77 * @choose_state: returns PCI power state of given device preferred by the 78 * platform; to be used during system-wide transitions from a 79 * sleeping state to the working state and vice versa 80 * 81 * @set_wakeup: enables/disables wakeup capability for the device 82 * 83 * @need_resume: returns 'true' if the given device (which is currently 84 * suspended) needs to be resumed to be configured for system 85 * wakeup. 86 * 87 * If given platform is generally capable of power managing PCI devices, all of 88 * these callbacks are mandatory. 89 */ 90struct pci_platform_pm_ops { 91 bool (*bridge_d3)(struct pci_dev *dev); 92 bool (*is_manageable)(struct pci_dev *dev); 93 int (*set_state)(struct pci_dev *dev, pci_power_t state); 94 pci_power_t (*get_state)(struct pci_dev *dev); 95 void (*refresh_state)(struct pci_dev *dev); 96 pci_power_t (*choose_state)(struct pci_dev *dev); 97 int (*set_wakeup)(struct pci_dev *dev, bool enable); 98 bool (*need_resume)(struct pci_dev *dev); 99}; 100 101int pci_set_platform_pm(const struct pci_platform_pm_ops *ops); 102void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 103void pci_refresh_power_state(struct pci_dev *dev); 104int pci_power_up(struct pci_dev *dev); 105void pci_disable_enabled_device(struct pci_dev *dev); 106int pci_finish_runtime_suspend(struct pci_dev *dev); 107void pcie_clear_device_status(struct pci_dev *dev); 108void pcie_clear_root_pme_status(struct pci_dev *dev); 109bool pci_check_pme_status(struct pci_dev *dev); 110void pci_pme_wakeup_bus(struct pci_bus *bus); 111int __pci_pme_wakeup(struct pci_dev *dev, void *ign); 112void pci_pme_restore(struct pci_dev *dev); 113bool pci_dev_need_resume(struct pci_dev *dev); 114void pci_dev_adjust_pme(struct pci_dev *dev); 115void pci_dev_complete_resume(struct pci_dev *pci_dev); 116void pci_config_pm_runtime_get(struct pci_dev *dev); 117void pci_config_pm_runtime_put(struct pci_dev *dev); 118void pci_pm_init(struct pci_dev *dev); 119void pci_ea_init(struct pci_dev *dev); 120void pci_allocate_cap_save_buffers(struct pci_dev *dev); 121void pci_free_cap_save_buffers(struct pci_dev *dev); 122bool pci_bridge_d3_possible(struct pci_dev *dev); 123void pci_bridge_d3_update(struct pci_dev *dev); 124int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type, 125 int timeout); 126 127static inline void pci_wakeup_event(struct pci_dev *dev) 128{ 129 /* Wait 100 ms before the system can be put into a sleep state. */ 130 pm_wakeup_event(&dev->dev, 100); 131} 132 133static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 134{ 135 return !!(pci_dev->subordinate); 136} 137 138static inline bool pci_power_manageable(struct pci_dev *pci_dev) 139{ 140 /* 141 * Currently we allow normal PCI devices and PCI bridges transition 142 * into D3 if their bridge_d3 is set. 143 */ 144 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; 145} 146 147static inline bool pcie_downstream_port(const struct pci_dev *dev) 148{ 149 int type = pci_pcie_type(dev); 150 151 return type == PCI_EXP_TYPE_ROOT_PORT || 152 type == PCI_EXP_TYPE_DOWNSTREAM || 153 type == PCI_EXP_TYPE_PCIE_BRIDGE; 154} 155 156int pci_vpd_init(struct pci_dev *dev); 157void pci_vpd_release(struct pci_dev *dev); 158void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev); 159void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev); 160 161/* PCI Virtual Channel */ 162int pci_save_vc_state(struct pci_dev *dev); 163void pci_restore_vc_state(struct pci_dev *dev); 164void pci_allocate_vc_save_buffers(struct pci_dev *dev); 165 166/* PCI /proc functions */ 167#ifdef CONFIG_PROC_FS 168int pci_proc_attach_device(struct pci_dev *dev); 169int pci_proc_detach_device(struct pci_dev *dev); 170int pci_proc_detach_bus(struct pci_bus *bus); 171#else 172static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 173static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 174static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 175#endif 176 177/* Functions for PCI Hotplug drivers to use */ 178int pci_hp_add_bridge(struct pci_dev *dev); 179 180#ifdef HAVE_PCI_LEGACY 181void pci_create_legacy_files(struct pci_bus *bus); 182void pci_remove_legacy_files(struct pci_bus *bus); 183#else 184static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } 185static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; } 186#endif 187 188/* Lock for read/write access to pci device and bus lists */ 189extern struct rw_semaphore pci_bus_sem; 190extern struct mutex pci_slot_mutex; 191 192extern raw_spinlock_t pci_lock; 193 194extern unsigned int pci_pm_d3hot_delay; 195 196#ifdef CONFIG_PCI_MSI 197void pci_no_msi(void); 198#else 199static inline void pci_no_msi(void) { } 200#endif 201 202static inline void pci_msi_set_enable(struct pci_dev *dev, int enable) 203{ 204 u16 control; 205 206 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); 207 control &= ~PCI_MSI_FLAGS_ENABLE; 208 if (enable) 209 control |= PCI_MSI_FLAGS_ENABLE; 210 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); 211} 212 213static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) 214{ 215 u16 ctrl; 216 217 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 218 ctrl &= ~clear; 219 ctrl |= set; 220 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); 221} 222 223void pci_realloc_get_opt(char *); 224 225static inline int pci_no_d1d2(struct pci_dev *dev) 226{ 227 unsigned int parent_dstates = 0; 228 229 if (dev->bus->self) 230 parent_dstates = dev->bus->self->no_d1d2; 231 return (dev->no_d1d2 || parent_dstates); 232 233} 234extern const struct attribute_group *pci_dev_groups[]; 235extern const struct attribute_group *pcibus_groups[]; 236extern const struct device_type pci_dev_type; 237extern const struct attribute_group *pci_bus_groups[]; 238 239extern unsigned long pci_hotplug_io_size; 240extern unsigned long pci_hotplug_mmio_size; 241extern unsigned long pci_hotplug_mmio_pref_size; 242extern unsigned long pci_hotplug_bus_size; 243 244/** 245 * pci_match_one_device - Tell if a PCI device structure has a matching 246 * PCI device id structure 247 * @id: single PCI device id structure to match 248 * @dev: the PCI device structure to match against 249 * 250 * Returns the matching pci_device_id structure or %NULL if there is no match. 251 */ 252static inline const struct pci_device_id * 253pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 254{ 255 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 256 (id->device == PCI_ANY_ID || id->device == dev->device) && 257 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 258 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 259 !((id->class ^ dev->class) & id->class_mask)) 260 return id; 261 return NULL; 262} 263 264/* PCI slot sysfs helper code */ 265#define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 266 267extern struct kset *pci_slots_kset; 268 269struct pci_slot_attribute { 270 struct attribute attr; 271 ssize_t (*show)(struct pci_slot *, char *); 272 ssize_t (*store)(struct pci_slot *, const char *, size_t); 273}; 274#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 275 276enum pci_bar_type { 277 pci_bar_unknown, /* Standard PCI BAR probe */ 278 pci_bar_io, /* An I/O port BAR */ 279 pci_bar_mem32, /* A 32-bit memory BAR */ 280 pci_bar_mem64, /* A 64-bit memory BAR */ 281}; 282 283struct device *pci_get_host_bridge_device(struct pci_dev *dev); 284void pci_put_host_bridge_device(struct device *dev); 285 286int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 287bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 288 int crs_timeout); 289bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 290 int crs_timeout); 291int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); 292 293int pci_setup_device(struct pci_dev *dev); 294int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 295 struct resource *res, unsigned int reg); 296void pci_configure_ari(struct pci_dev *dev); 297void __pci_bus_size_bridges(struct pci_bus *bus, 298 struct list_head *realloc_head); 299void __pci_bus_assign_resources(const struct pci_bus *bus, 300 struct list_head *realloc_head, 301 struct list_head *fail_head); 302bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 303 304void pci_reassigndev_resource_alignment(struct pci_dev *dev); 305void pci_disable_bridge_window(struct pci_dev *dev); 306struct pci_bus *pci_bus_get(struct pci_bus *bus); 307void pci_bus_put(struct pci_bus *bus); 308 309/* PCIe link information from Link Capabilities 2 */ 310#define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ 311 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 312 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 313 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 314 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 315 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 316 PCI_SPEED_UNKNOWN) 317 318/* PCIe speed to Mb/s reduced by encoding overhead */ 319#define PCIE_SPEED2MBS_ENC(speed) \ 320 ((speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ 321 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 322 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 323 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ 324 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 325 0) 326 327const char *pci_speed_string(enum pci_bus_speed speed); 328enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 329enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 330u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, 331 enum pcie_link_width *width); 332void __pcie_print_link_status(struct pci_dev *dev, bool verbose); 333void pcie_report_downtraining(struct pci_dev *dev); 334void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 335 336/* Single Root I/O Virtualization */ 337struct pci_sriov { 338 int pos; /* Capability position */ 339 int nres; /* Number of resources */ 340 u32 cap; /* SR-IOV Capabilities */ 341 u16 ctrl; /* SR-IOV Control */ 342 u16 total_VFs; /* Total VFs associated with the PF */ 343 u16 initial_VFs; /* Initial VFs associated with the PF */ 344 u16 num_VFs; /* Number of VFs available */ 345 u16 offset; /* First VF Routing ID offset */ 346 u16 stride; /* Following VF stride */ 347 u16 vf_device; /* VF device ID */ 348 u32 pgsz; /* Page size for BAR alignment */ 349 u8 link; /* Function Dependency Link */ 350 u8 max_VF_buses; /* Max buses consumed by VFs */ 351 u16 driver_max_VFs; /* Max num VFs driver supports */ 352 struct pci_dev *dev; /* Lowest numbered PF */ 353 struct pci_dev *self; /* This PF */ 354 u32 class; /* VF device */ 355 u8 hdr_type; /* VF header type */ 356 u16 subsystem_vendor; /* VF subsystem vendor */ 357 u16 subsystem_device; /* VF subsystem device */ 358 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 359 bool drivers_autoprobe; /* Auto probing of VFs by driver */ 360}; 361 362/** 363 * pci_dev_set_io_state - Set the new error state if possible. 364 * 365 * @dev - pci device to set new error_state 366 * @new - the state we want dev to be in 367 * 368 * If the device is experiencing perm_failure, it has to remain in that state. 369 * Any other transition is allowed. 370 * 371 * Returns true if state has been changed to the requested state. 372 */ 373static inline bool pci_dev_set_io_state(struct pci_dev *dev, 374 pci_channel_state_t new) 375{ 376 pci_channel_state_t old; 377 378 switch (new) { 379 case pci_channel_io_perm_failure: 380 xchg(&dev->error_state, pci_channel_io_perm_failure); 381 return true; 382 case pci_channel_io_frozen: 383 old = cmpxchg(&dev->error_state, pci_channel_io_normal, 384 pci_channel_io_frozen); 385 return old != pci_channel_io_perm_failure; 386 case pci_channel_io_normal: 387 old = cmpxchg(&dev->error_state, pci_channel_io_frozen, 388 pci_channel_io_normal); 389 return old != pci_channel_io_perm_failure; 390 default: 391 return false; 392 } 393} 394 395static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) 396{ 397 pci_dev_set_io_state(dev, pci_channel_io_perm_failure); 398 399 return 0; 400} 401 402static inline bool pci_dev_is_disconnected(const struct pci_dev *dev) 403{ 404 return dev->error_state == pci_channel_io_perm_failure; 405} 406 407/* pci_dev priv_flags */ 408#define PCI_DEV_ADDED 0 409#define PCI_DPC_RECOVERED 1 410#define PCI_DPC_RECOVERING 2 411 412static inline void pci_dev_assign_added(struct pci_dev *dev, bool added) 413{ 414 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added); 415} 416 417static inline bool pci_dev_is_added(const struct pci_dev *dev) 418{ 419 return test_bit(PCI_DEV_ADDED, &dev->priv_flags); 420} 421 422#ifdef CONFIG_PCIEAER 423#include <linux/aer.h> 424 425#define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ 426 427struct aer_err_info { 428 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 429 int error_dev_num; 430 431 unsigned int id:16; 432 433 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ 434 unsigned int __pad1:5; 435 unsigned int multi_error_valid:1; 436 437 unsigned int first_error:5; 438 unsigned int __pad2:2; 439 unsigned int tlp_header_valid:1; 440 441 unsigned int status; /* COR/UNCOR Error Status */ 442 unsigned int mask; /* COR/UNCOR Error Mask */ 443 struct aer_header_log_regs tlp; /* TLP Header */ 444}; 445 446int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); 447void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); 448#endif /* CONFIG_PCIEAER */ 449 450#ifdef CONFIG_PCIE_DPC 451void pci_save_dpc_state(struct pci_dev *dev); 452void pci_restore_dpc_state(struct pci_dev *dev); 453void pci_dpc_init(struct pci_dev *pdev); 454void dpc_process_error(struct pci_dev *pdev); 455pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); 456bool pci_dpc_recovered(struct pci_dev *pdev); 457#else 458static inline void pci_save_dpc_state(struct pci_dev *dev) {} 459static inline void pci_restore_dpc_state(struct pci_dev *dev) {} 460static inline void pci_dpc_init(struct pci_dev *pdev) {} 461static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; } 462#endif 463 464#ifdef CONFIG_PCI_ATS 465/* Address Translation Service */ 466void pci_ats_init(struct pci_dev *dev); 467void pci_restore_ats_state(struct pci_dev *dev); 468#else 469static inline void pci_ats_init(struct pci_dev *d) { } 470static inline void pci_restore_ats_state(struct pci_dev *dev) { } 471#endif /* CONFIG_PCI_ATS */ 472 473#ifdef CONFIG_PCI_PRI 474void pci_pri_init(struct pci_dev *dev); 475void pci_restore_pri_state(struct pci_dev *pdev); 476#else 477static inline void pci_pri_init(struct pci_dev *dev) { } 478static inline void pci_restore_pri_state(struct pci_dev *pdev) { } 479#endif 480 481#ifdef CONFIG_PCI_PASID 482void pci_pasid_init(struct pci_dev *dev); 483void pci_restore_pasid_state(struct pci_dev *pdev); 484#else 485static inline void pci_pasid_init(struct pci_dev *dev) { } 486static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } 487#endif 488 489#ifdef CONFIG_PCI_IOV 490int pci_iov_init(struct pci_dev *dev); 491void pci_iov_release(struct pci_dev *dev); 492void pci_iov_remove(struct pci_dev *dev); 493void pci_iov_update_resource(struct pci_dev *dev, int resno); 494resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); 495void pci_restore_iov_state(struct pci_dev *dev); 496int pci_iov_bus_range(struct pci_bus *bus); 497extern const struct attribute_group sriov_dev_attr_group; 498#else 499static inline int pci_iov_init(struct pci_dev *dev) 500{ 501 return -ENODEV; 502} 503static inline void pci_iov_release(struct pci_dev *dev) 504 505{ 506} 507static inline void pci_iov_remove(struct pci_dev *dev) 508{ 509} 510static inline void pci_restore_iov_state(struct pci_dev *dev) 511{ 512} 513static inline int pci_iov_bus_range(struct pci_bus *bus) 514{ 515 return 0; 516} 517 518#endif /* CONFIG_PCI_IOV */ 519 520unsigned long pci_cardbus_resource_alignment(struct resource *); 521 522static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 523 struct resource *res) 524{ 525#ifdef CONFIG_PCI_IOV 526 int resno = res - dev->resource; 527 528 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) 529 return pci_sriov_resource_alignment(dev, resno); 530#endif 531 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 532 return pci_cardbus_resource_alignment(res); 533 return resource_alignment(res); 534} 535 536void pci_acs_init(struct pci_dev *dev); 537#ifdef CONFIG_PCI_QUIRKS 538int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 539int pci_dev_specific_enable_acs(struct pci_dev *dev); 540int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 541#else 542static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 543 u16 acs_flags) 544{ 545 return -ENOTTY; 546} 547static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 548{ 549 return -ENOTTY; 550} 551static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 552{ 553 return -ENOTTY; 554} 555#endif 556 557/* PCI error reporting and recovery */ 558pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 559 pci_channel_state_t state, 560 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); 561 562bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 563#ifdef CONFIG_PCIEASPM 564void pcie_aspm_init_link_state(struct pci_dev *pdev); 565void pcie_aspm_exit_link_state(struct pci_dev *pdev); 566void pcie_aspm_pm_state_change(struct pci_dev *pdev); 567void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 568#else 569static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 570static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 571static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { } 572static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 573#endif 574 575#ifdef CONFIG_PCIE_ECRC 576void pcie_set_ecrc_checking(struct pci_dev *dev); 577void pcie_ecrc_get_policy(char *str); 578#else 579static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 580static inline void pcie_ecrc_get_policy(char *str) { } 581#endif 582 583#ifdef CONFIG_PCIE_PTM 584void pci_ptm_init(struct pci_dev *dev); 585#else 586static inline void pci_ptm_init(struct pci_dev *dev) { } 587#endif 588 589struct pci_dev_reset_methods { 590 u16 vendor; 591 u16 device; 592 int (*reset)(struct pci_dev *dev, int probe); 593}; 594 595#ifdef CONFIG_PCI_QUIRKS 596int pci_dev_specific_reset(struct pci_dev *dev, int probe); 597#else 598static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe) 599{ 600 return -ENOTTY; 601} 602#endif 603 604#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 605int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 606 struct resource *res); 607#else 608static inline int acpi_get_rc_resources(struct device *dev, const char *hid, 609 u16 segment, struct resource *res) 610{ 611 return -ENODEV; 612} 613#endif 614 615u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); 616int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); 617int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); 618static inline u64 pci_rebar_size_to_bytes(int size) 619{ 620 return 1ULL << (size + 20); 621} 622 623struct device_node; 624 625#ifdef CONFIG_OF 626int of_pci_parse_bus_range(struct device_node *node, struct resource *res); 627int of_get_pci_domain_nr(struct device_node *node); 628int of_pci_get_max_link_speed(struct device_node *node); 629void pci_set_of_node(struct pci_dev *dev); 630void pci_release_of_node(struct pci_dev *dev); 631void pci_set_bus_of_node(struct pci_bus *bus); 632void pci_release_bus_of_node(struct pci_bus *bus); 633 634int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); 635 636#else 637static inline int 638of_pci_parse_bus_range(struct device_node *node, struct resource *res) 639{ 640 return -EINVAL; 641} 642 643static inline int 644of_get_pci_domain_nr(struct device_node *node) 645{ 646 return -1; 647} 648 649static inline int 650of_pci_get_max_link_speed(struct device_node *node) 651{ 652 return -EINVAL; 653} 654 655static inline void pci_set_of_node(struct pci_dev *dev) { } 656static inline void pci_release_of_node(struct pci_dev *dev) { } 657static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 658static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 659 660static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) 661{ 662 return 0; 663} 664 665#endif /* CONFIG_OF */ 666 667#ifdef CONFIG_PCIEAER 668void pci_no_aer(void); 669void pci_aer_init(struct pci_dev *dev); 670void pci_aer_exit(struct pci_dev *dev); 671extern const struct attribute_group aer_stats_attr_group; 672void pci_aer_clear_fatal_status(struct pci_dev *dev); 673int pci_aer_clear_status(struct pci_dev *dev); 674int pci_aer_raw_clear_status(struct pci_dev *dev); 675#else 676static inline void pci_no_aer(void) { } 677static inline void pci_aer_init(struct pci_dev *d) { } 678static inline void pci_aer_exit(struct pci_dev *d) { } 679static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } 680static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } 681static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } 682#endif 683 684#ifdef CONFIG_ACPI 685int pci_acpi_program_hp_params(struct pci_dev *dev); 686#else 687static inline int pci_acpi_program_hp_params(struct pci_dev *dev) 688{ 689 return -ENODEV; 690} 691#endif 692 693#ifdef CONFIG_PCIEASPM 694extern const struct attribute_group aspm_ctrl_attr_group; 695#endif 696 697#endif /* DRIVERS_PCI_H */ 698