18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Intel MID platform PM support 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright (C) 2016, Intel Corporation 68c2ecf20Sopenharmony_ci * 78c2ecf20Sopenharmony_ci * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 88c2ecf20Sopenharmony_ci */ 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci#include <linux/init.h> 118c2ecf20Sopenharmony_ci#include <linux/pci.h> 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci#include <asm/cpu_device_id.h> 148c2ecf20Sopenharmony_ci#include <asm/intel-family.h> 158c2ecf20Sopenharmony_ci#include <asm/intel-mid.h> 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ci#include "pci.h" 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_cistatic bool mid_pci_power_manageable(struct pci_dev *dev) 208c2ecf20Sopenharmony_ci{ 218c2ecf20Sopenharmony_ci return true; 228c2ecf20Sopenharmony_ci} 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_cistatic int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state) 258c2ecf20Sopenharmony_ci{ 268c2ecf20Sopenharmony_ci return intel_mid_pci_set_power_state(pdev, state); 278c2ecf20Sopenharmony_ci} 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_cistatic pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) 308c2ecf20Sopenharmony_ci{ 318c2ecf20Sopenharmony_ci return intel_mid_pci_get_power_state(pdev); 328c2ecf20Sopenharmony_ci} 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_cistatic pci_power_t mid_pci_choose_state(struct pci_dev *pdev) 358c2ecf20Sopenharmony_ci{ 368c2ecf20Sopenharmony_ci return PCI_D3hot; 378c2ecf20Sopenharmony_ci} 388c2ecf20Sopenharmony_ci 398c2ecf20Sopenharmony_cistatic int mid_pci_wakeup(struct pci_dev *dev, bool enable) 408c2ecf20Sopenharmony_ci{ 418c2ecf20Sopenharmony_ci return 0; 428c2ecf20Sopenharmony_ci} 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_cistatic bool mid_pci_need_resume(struct pci_dev *dev) 458c2ecf20Sopenharmony_ci{ 468c2ecf20Sopenharmony_ci return false; 478c2ecf20Sopenharmony_ci} 488c2ecf20Sopenharmony_ci 498c2ecf20Sopenharmony_cistatic const struct pci_platform_pm_ops mid_pci_platform_pm = { 508c2ecf20Sopenharmony_ci .is_manageable = mid_pci_power_manageable, 518c2ecf20Sopenharmony_ci .set_state = mid_pci_set_power_state, 528c2ecf20Sopenharmony_ci .get_state = mid_pci_get_power_state, 538c2ecf20Sopenharmony_ci .choose_state = mid_pci_choose_state, 548c2ecf20Sopenharmony_ci .set_wakeup = mid_pci_wakeup, 558c2ecf20Sopenharmony_ci .need_resume = mid_pci_need_resume, 568c2ecf20Sopenharmony_ci}; 578c2ecf20Sopenharmony_ci 588c2ecf20Sopenharmony_ci/* 598c2ecf20Sopenharmony_ci * This table should be in sync with the one in 608c2ecf20Sopenharmony_ci * arch/x86/platform/intel-mid/pwr.c. 618c2ecf20Sopenharmony_ci */ 628c2ecf20Sopenharmony_cistatic const struct x86_cpu_id lpss_cpu_ids[] = { 638c2ecf20Sopenharmony_ci X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL_MID, NULL), 648c2ecf20Sopenharmony_ci X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, NULL), 658c2ecf20Sopenharmony_ci {} 668c2ecf20Sopenharmony_ci}; 678c2ecf20Sopenharmony_ci 688c2ecf20Sopenharmony_cistatic int __init mid_pci_init(void) 698c2ecf20Sopenharmony_ci{ 708c2ecf20Sopenharmony_ci const struct x86_cpu_id *id; 718c2ecf20Sopenharmony_ci 728c2ecf20Sopenharmony_ci id = x86_match_cpu(lpss_cpu_ids); 738c2ecf20Sopenharmony_ci if (id) 748c2ecf20Sopenharmony_ci pci_set_platform_pm(&mid_pci_platform_pm); 758c2ecf20Sopenharmony_ci return 0; 768c2ecf20Sopenharmony_ci} 778c2ecf20Sopenharmony_ciarch_initcall(mid_pci_init); 78