1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Standard PCI Hot Plug Driver 4 * 5 * Copyright (C) 1995,2001 Compaq Computer Corporation 6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 7 * Copyright (C) 2001 IBM Corp. 8 * Copyright (C) 2003-2004 Intel Corporation 9 * 10 * All rights reserved. 11 * 12 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 13 * 14 */ 15 16#include <linux/kernel.h> 17#include <linux/module.h> 18#include <linux/types.h> 19#include <linux/pci.h> 20#include <linux/interrupt.h> 21 22#include "shpchp.h" 23 24/* Slot Available Register I field definition */ 25#define SLOT_33MHZ 0x0000001f 26#define SLOT_66MHZ_PCIX 0x00001f00 27#define SLOT_100MHZ_PCIX 0x001f0000 28#define SLOT_133MHZ_PCIX 0x1f000000 29 30/* Slot Available Register II field definition */ 31#define SLOT_66MHZ 0x0000001f 32#define SLOT_66MHZ_PCIX_266 0x00000f00 33#define SLOT_100MHZ_PCIX_266 0x0000f000 34#define SLOT_133MHZ_PCIX_266 0x000f0000 35#define SLOT_66MHZ_PCIX_533 0x00f00000 36#define SLOT_100MHZ_PCIX_533 0x0f000000 37#define SLOT_133MHZ_PCIX_533 0xf0000000 38 39/* Slot Configuration */ 40#define SLOT_NUM 0x0000001F 41#define FIRST_DEV_NUM 0x00001F00 42#define PSN 0x07FF0000 43#define UPDOWN 0x20000000 44#define MRLSENSOR 0x40000000 45#define ATTN_BUTTON 0x80000000 46 47/* 48 * Interrupt Locator Register definitions 49 */ 50#define CMD_INTR_PENDING (1 << 0) 51#define SLOT_INTR_PENDING(i) (1 << (i + 1)) 52 53/* 54 * Controller SERR-INT Register 55 */ 56#define GLOBAL_INTR_MASK (1 << 0) 57#define GLOBAL_SERR_MASK (1 << 1) 58#define COMMAND_INTR_MASK (1 << 2) 59#define ARBITER_SERR_MASK (1 << 3) 60#define COMMAND_DETECTED (1 << 16) 61#define ARBITER_DETECTED (1 << 17) 62#define SERR_INTR_RSVDZ_MASK 0xfffc0000 63 64/* 65 * Logical Slot Register definitions 66 */ 67#define SLOT_REG(i) (SLOT1 + (4 * i)) 68 69#define SLOT_STATE_SHIFT (0) 70#define SLOT_STATE_MASK (3 << 0) 71#define SLOT_STATE_PWRONLY (1) 72#define SLOT_STATE_ENABLED (2) 73#define SLOT_STATE_DISABLED (3) 74#define PWR_LED_STATE_SHIFT (2) 75#define PWR_LED_STATE_MASK (3 << 2) 76#define ATN_LED_STATE_SHIFT (4) 77#define ATN_LED_STATE_MASK (3 << 4) 78#define ATN_LED_STATE_ON (1) 79#define ATN_LED_STATE_BLINK (2) 80#define ATN_LED_STATE_OFF (3) 81#define POWER_FAULT (1 << 6) 82#define ATN_BUTTON (1 << 7) 83#define MRL_SENSOR (1 << 8) 84#define MHZ66_CAP (1 << 9) 85#define PRSNT_SHIFT (10) 86#define PRSNT_MASK (3 << 10) 87#define PCIX_CAP_SHIFT (12) 88#define PCIX_CAP_MASK_PI1 (3 << 12) 89#define PCIX_CAP_MASK_PI2 (7 << 12) 90#define PRSNT_CHANGE_DETECTED (1 << 16) 91#define ISO_PFAULT_DETECTED (1 << 17) 92#define BUTTON_PRESS_DETECTED (1 << 18) 93#define MRL_CHANGE_DETECTED (1 << 19) 94#define CON_PFAULT_DETECTED (1 << 20) 95#define PRSNT_CHANGE_INTR_MASK (1 << 24) 96#define ISO_PFAULT_INTR_MASK (1 << 25) 97#define BUTTON_PRESS_INTR_MASK (1 << 26) 98#define MRL_CHANGE_INTR_MASK (1 << 27) 99#define CON_PFAULT_INTR_MASK (1 << 28) 100#define MRL_CHANGE_SERR_MASK (1 << 29) 101#define CON_PFAULT_SERR_MASK (1 << 30) 102#define SLOT_REG_RSVDZ_MASK ((1 << 15) | (7 << 21)) 103 104/* 105 * SHPC Command Code definitions 106 * 107 * Slot Operation 00h - 3Fh 108 * Set Bus Segment Speed/Mode A 40h - 47h 109 * Power-Only All Slots 48h 110 * Enable All Slots 49h 111 * Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh 112 * Reserved Command Codes 60h - BFh 113 * Vendor Specific Commands C0h - FFh 114 */ 115#define SET_SLOT_PWR 0x01 /* Slot Operation */ 116#define SET_SLOT_ENABLE 0x02 117#define SET_SLOT_DISABLE 0x03 118#define SET_PWR_ON 0x04 119#define SET_PWR_BLINK 0x08 120#define SET_PWR_OFF 0x0c 121#define SET_ATTN_ON 0x10 122#define SET_ATTN_BLINK 0x20 123#define SET_ATTN_OFF 0x30 124#define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */ 125#define SETA_PCI_66MHZ 0x41 126#define SETA_PCIX_66MHZ 0x42 127#define SETA_PCIX_100MHZ 0x43 128#define SETA_PCIX_133MHZ 0x44 129#define SETA_RESERVED1 0x45 130#define SETA_RESERVED2 0x46 131#define SETA_RESERVED3 0x47 132#define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */ 133#define SET_ENABLE_ALL 0x49 /* Enable All Slots */ 134#define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */ 135#define SETB_PCI_66MHZ 0x51 136#define SETB_PCIX_66MHZ_PM 0x52 137#define SETB_PCIX_100MHZ_PM 0x53 138#define SETB_PCIX_133MHZ_PM 0x54 139#define SETB_PCIX_66MHZ_EM 0x55 140#define SETB_PCIX_100MHZ_EM 0x56 141#define SETB_PCIX_133MHZ_EM 0x57 142#define SETB_PCIX_66MHZ_266 0x58 143#define SETB_PCIX_100MHZ_266 0x59 144#define SETB_PCIX_133MHZ_266 0x5a 145#define SETB_PCIX_66MHZ_533 0x5b 146#define SETB_PCIX_100MHZ_533 0x5c 147#define SETB_PCIX_133MHZ_533 0x5d 148#define SETB_RESERVED1 0x5e 149#define SETB_RESERVED2 0x5f 150 151/* 152 * SHPC controller command error code 153 */ 154#define SWITCH_OPEN 0x1 155#define INVALID_CMD 0x2 156#define INVALID_SPEED_MODE 0x4 157 158/* 159 * For accessing SHPC Working Register Set via PCI Configuration Space 160 */ 161#define DWORD_SELECT 0x2 162#define DWORD_DATA 0x4 163 164/* Field Offset in Logical Slot Register - byte boundary */ 165#define SLOT_EVENT_LATCH 0x2 166#define SLOT_SERR_INT_MASK 0x3 167 168static irqreturn_t shpc_isr(int irq, void *dev_id); 169static void start_int_poll_timer(struct controller *ctrl, int sec); 170static int hpc_check_cmd_status(struct controller *ctrl); 171 172static inline u8 shpc_readb(struct controller *ctrl, int reg) 173{ 174 return readb(ctrl->creg + reg); 175} 176 177static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val) 178{ 179 writeb(val, ctrl->creg + reg); 180} 181 182static inline u16 shpc_readw(struct controller *ctrl, int reg) 183{ 184 return readw(ctrl->creg + reg); 185} 186 187static inline void shpc_writew(struct controller *ctrl, int reg, u16 val) 188{ 189 writew(val, ctrl->creg + reg); 190} 191 192static inline u32 shpc_readl(struct controller *ctrl, int reg) 193{ 194 return readl(ctrl->creg + reg); 195} 196 197static inline void shpc_writel(struct controller *ctrl, int reg, u32 val) 198{ 199 writel(val, ctrl->creg + reg); 200} 201 202static inline int shpc_indirect_read(struct controller *ctrl, int index, 203 u32 *value) 204{ 205 int rc; 206 u32 cap_offset = ctrl->cap_offset; 207 struct pci_dev *pdev = ctrl->pci_dev; 208 209 rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index); 210 if (rc) 211 return rc; 212 return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value); 213} 214 215/* 216 * This is the interrupt polling timeout function. 217 */ 218static void int_poll_timeout(struct timer_list *t) 219{ 220 struct controller *ctrl = from_timer(ctrl, t, poll_timer); 221 222 /* Poll for interrupt events. regs == NULL => polling */ 223 shpc_isr(0, ctrl); 224 225 if (!shpchp_poll_time) 226 shpchp_poll_time = 2; /* default polling interval is 2 sec */ 227 228 start_int_poll_timer(ctrl, shpchp_poll_time); 229} 230 231/* 232 * This function starts the interrupt polling timer. 233 */ 234static void start_int_poll_timer(struct controller *ctrl, int sec) 235{ 236 /* Clamp to sane value */ 237 if ((sec <= 0) || (sec > 60)) 238 sec = 2; 239 240 ctrl->poll_timer.expires = jiffies + sec * HZ; 241 add_timer(&ctrl->poll_timer); 242} 243 244static inline int is_ctrl_busy(struct controller *ctrl) 245{ 246 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS); 247 return cmd_status & 0x1; 248} 249 250/* 251 * Returns 1 if SHPC finishes executing a command within 1 sec, 252 * otherwise returns 0. 253 */ 254static inline int shpc_poll_ctrl_busy(struct controller *ctrl) 255{ 256 int i; 257 258 if (!is_ctrl_busy(ctrl)) 259 return 1; 260 261 /* Check every 0.1 sec for a total of 1 sec */ 262 for (i = 0; i < 10; i++) { 263 msleep(100); 264 if (!is_ctrl_busy(ctrl)) 265 return 1; 266 } 267 268 return 0; 269} 270 271static inline int shpc_wait_cmd(struct controller *ctrl) 272{ 273 int retval = 0; 274 unsigned long timeout = msecs_to_jiffies(1000); 275 int rc; 276 277 if (shpchp_poll_mode) 278 rc = shpc_poll_ctrl_busy(ctrl); 279 else 280 rc = wait_event_interruptible_timeout(ctrl->queue, 281 !is_ctrl_busy(ctrl), timeout); 282 if (!rc && is_ctrl_busy(ctrl)) { 283 retval = -EIO; 284 ctrl_err(ctrl, "Command not completed in 1000 msec\n"); 285 } else if (rc < 0) { 286 retval = -EINTR; 287 ctrl_info(ctrl, "Command was interrupted by a signal\n"); 288 } 289 290 return retval; 291} 292 293static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) 294{ 295 struct controller *ctrl = slot->ctrl; 296 u16 cmd_status; 297 int retval = 0; 298 u16 temp_word; 299 300 mutex_lock(&slot->ctrl->cmd_lock); 301 302 if (!shpc_poll_ctrl_busy(ctrl)) { 303 /* After 1 sec and and the controller is still busy */ 304 ctrl_err(ctrl, "Controller is still busy after 1 sec\n"); 305 retval = -EBUSY; 306 goto out; 307 } 308 309 ++t_slot; 310 temp_word = (t_slot << 8) | (cmd & 0xFF); 311 ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd); 312 313 /* To make sure the Controller Busy bit is 0 before we send out the 314 * command. 315 */ 316 shpc_writew(ctrl, CMD, temp_word); 317 318 /* 319 * Wait for command completion. 320 */ 321 retval = shpc_wait_cmd(slot->ctrl); 322 if (retval) 323 goto out; 324 325 cmd_status = hpc_check_cmd_status(slot->ctrl); 326 if (cmd_status) { 327 ctrl_err(ctrl, "Failed to issued command 0x%x (error code = %d)\n", 328 cmd, cmd_status); 329 retval = -EIO; 330 } 331 out: 332 mutex_unlock(&slot->ctrl->cmd_lock); 333 return retval; 334} 335 336static int hpc_check_cmd_status(struct controller *ctrl) 337{ 338 int retval = 0; 339 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F; 340 341 switch (cmd_status >> 1) { 342 case 0: 343 retval = 0; 344 break; 345 case 1: 346 retval = SWITCH_OPEN; 347 ctrl_err(ctrl, "Switch opened!\n"); 348 break; 349 case 2: 350 retval = INVALID_CMD; 351 ctrl_err(ctrl, "Invalid HPC command!\n"); 352 break; 353 case 4: 354 retval = INVALID_SPEED_MODE; 355 ctrl_err(ctrl, "Invalid bus speed/mode!\n"); 356 break; 357 default: 358 retval = cmd_status; 359 } 360 361 return retval; 362} 363 364 365static int hpc_get_attention_status(struct slot *slot, u8 *status) 366{ 367 struct controller *ctrl = slot->ctrl; 368 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 369 u8 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT; 370 371 switch (state) { 372 case ATN_LED_STATE_ON: 373 *status = 1; /* On */ 374 break; 375 case ATN_LED_STATE_BLINK: 376 *status = 2; /* Blink */ 377 break; 378 case ATN_LED_STATE_OFF: 379 *status = 0; /* Off */ 380 break; 381 default: 382 *status = 0xFF; /* Reserved */ 383 break; 384 } 385 386 return 0; 387} 388 389static int hpc_get_power_status(struct slot *slot, u8 *status) 390{ 391 struct controller *ctrl = slot->ctrl; 392 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 393 u8 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT; 394 395 switch (state) { 396 case SLOT_STATE_PWRONLY: 397 *status = 2; /* Powered only */ 398 break; 399 case SLOT_STATE_ENABLED: 400 *status = 1; /* Enabled */ 401 break; 402 case SLOT_STATE_DISABLED: 403 *status = 0; /* Disabled */ 404 break; 405 default: 406 *status = 0xFF; /* Reserved */ 407 break; 408 } 409 410 return 0; 411} 412 413 414static int hpc_get_latch_status(struct slot *slot, u8 *status) 415{ 416 struct controller *ctrl = slot->ctrl; 417 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 418 419 *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */ 420 421 return 0; 422} 423 424static int hpc_get_adapter_status(struct slot *slot, u8 *status) 425{ 426 struct controller *ctrl = slot->ctrl; 427 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 428 u8 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT; 429 430 *status = (state != 0x3) ? 1 : 0; 431 432 return 0; 433} 434 435static int hpc_get_prog_int(struct slot *slot, u8 *prog_int) 436{ 437 struct controller *ctrl = slot->ctrl; 438 439 *prog_int = shpc_readb(ctrl, PROG_INTERFACE); 440 441 return 0; 442} 443 444static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) 445{ 446 int retval = 0; 447 struct controller *ctrl = slot->ctrl; 448 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 449 u8 m66_cap = !!(slot_reg & MHZ66_CAP); 450 u8 pi, pcix_cap; 451 452 retval = hpc_get_prog_int(slot, &pi); 453 if (retval) 454 return retval; 455 456 switch (pi) { 457 case 1: 458 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT; 459 break; 460 case 2: 461 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT; 462 break; 463 default: 464 return -ENODEV; 465 } 466 467 ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n", 468 __func__, slot_reg, pcix_cap, m66_cap); 469 470 switch (pcix_cap) { 471 case 0x0: 472 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz; 473 break; 474 case 0x1: 475 *value = PCI_SPEED_66MHz_PCIX; 476 break; 477 case 0x3: 478 *value = PCI_SPEED_133MHz_PCIX; 479 break; 480 case 0x4: 481 *value = PCI_SPEED_133MHz_PCIX_266; 482 break; 483 case 0x5: 484 *value = PCI_SPEED_133MHz_PCIX_533; 485 break; 486 case 0x2: 487 default: 488 *value = PCI_SPEED_UNKNOWN; 489 retval = -ENODEV; 490 break; 491 } 492 493 ctrl_dbg(ctrl, "Adapter speed = %d\n", *value); 494 return retval; 495} 496 497static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode) 498{ 499 int retval = 0; 500 struct controller *ctrl = slot->ctrl; 501 u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG); 502 u8 pi = shpc_readb(ctrl, PROG_INTERFACE); 503 504 if (pi == 2) { 505 *mode = (sec_bus_status & 0x0100) >> 8; 506 } else { 507 retval = -1; 508 } 509 510 ctrl_dbg(ctrl, "Mode 1 ECC cap = %d\n", *mode); 511 return retval; 512} 513 514static int hpc_query_power_fault(struct slot *slot) 515{ 516 struct controller *ctrl = slot->ctrl; 517 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 518 519 /* Note: Logic 0 => fault */ 520 return !(slot_reg & POWER_FAULT); 521} 522 523static int hpc_set_attention_status(struct slot *slot, u8 value) 524{ 525 u8 slot_cmd = 0; 526 527 switch (value) { 528 case 0: 529 slot_cmd = SET_ATTN_OFF; /* OFF */ 530 break; 531 case 1: 532 slot_cmd = SET_ATTN_ON; /* ON */ 533 break; 534 case 2: 535 slot_cmd = SET_ATTN_BLINK; /* BLINK */ 536 break; 537 default: 538 return -1; 539 } 540 541 return shpc_write_cmd(slot, slot->hp_slot, slot_cmd); 542} 543 544 545static void hpc_set_green_led_on(struct slot *slot) 546{ 547 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON); 548} 549 550static void hpc_set_green_led_off(struct slot *slot) 551{ 552 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF); 553} 554 555static void hpc_set_green_led_blink(struct slot *slot) 556{ 557 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK); 558} 559 560static void hpc_release_ctlr(struct controller *ctrl) 561{ 562 int i; 563 u32 slot_reg, serr_int; 564 565 /* 566 * Mask event interrupts and SERRs of all slots 567 */ 568 for (i = 0; i < ctrl->num_slots; i++) { 569 slot_reg = shpc_readl(ctrl, SLOT_REG(i)); 570 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 571 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 572 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | 573 CON_PFAULT_SERR_MASK); 574 slot_reg &= ~SLOT_REG_RSVDZ_MASK; 575 shpc_writel(ctrl, SLOT_REG(i), slot_reg); 576 } 577 578 cleanup_slots(ctrl); 579 580 /* 581 * Mask SERR and System Interrupt generation 582 */ 583 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 584 serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | 585 COMMAND_INTR_MASK | ARBITER_SERR_MASK); 586 serr_int &= ~SERR_INTR_RSVDZ_MASK; 587 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 588 589 if (shpchp_poll_mode) 590 del_timer(&ctrl->poll_timer); 591 else { 592 free_irq(ctrl->pci_dev->irq, ctrl); 593 pci_disable_msi(ctrl->pci_dev); 594 } 595 596 iounmap(ctrl->creg); 597 release_mem_region(ctrl->mmio_base, ctrl->mmio_size); 598} 599 600static int hpc_power_on_slot(struct slot *slot) 601{ 602 int retval; 603 604 retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR); 605 if (retval) 606 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); 607 608 return retval; 609} 610 611static int hpc_slot_enable(struct slot *slot) 612{ 613 int retval; 614 615 /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */ 616 retval = shpc_write_cmd(slot, slot->hp_slot, 617 SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF); 618 if (retval) 619 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); 620 621 return retval; 622} 623 624static int hpc_slot_disable(struct slot *slot) 625{ 626 int retval; 627 628 /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */ 629 retval = shpc_write_cmd(slot, slot->hp_slot, 630 SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON); 631 if (retval) 632 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); 633 634 return retval; 635} 636 637static int shpc_get_cur_bus_speed(struct controller *ctrl) 638{ 639 int retval = 0; 640 struct pci_bus *bus = ctrl->pci_dev->subordinate; 641 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; 642 u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG); 643 u8 pi = shpc_readb(ctrl, PROG_INTERFACE); 644 u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7); 645 646 if ((pi == 1) && (speed_mode > 4)) { 647 retval = -ENODEV; 648 goto out; 649 } 650 651 switch (speed_mode) { 652 case 0x0: 653 bus_speed = PCI_SPEED_33MHz; 654 break; 655 case 0x1: 656 bus_speed = PCI_SPEED_66MHz; 657 break; 658 case 0x2: 659 bus_speed = PCI_SPEED_66MHz_PCIX; 660 break; 661 case 0x3: 662 bus_speed = PCI_SPEED_100MHz_PCIX; 663 break; 664 case 0x4: 665 bus_speed = PCI_SPEED_133MHz_PCIX; 666 break; 667 case 0x5: 668 bus_speed = PCI_SPEED_66MHz_PCIX_ECC; 669 break; 670 case 0x6: 671 bus_speed = PCI_SPEED_100MHz_PCIX_ECC; 672 break; 673 case 0x7: 674 bus_speed = PCI_SPEED_133MHz_PCIX_ECC; 675 break; 676 case 0x8: 677 bus_speed = PCI_SPEED_66MHz_PCIX_266; 678 break; 679 case 0x9: 680 bus_speed = PCI_SPEED_100MHz_PCIX_266; 681 break; 682 case 0xa: 683 bus_speed = PCI_SPEED_133MHz_PCIX_266; 684 break; 685 case 0xb: 686 bus_speed = PCI_SPEED_66MHz_PCIX_533; 687 break; 688 case 0xc: 689 bus_speed = PCI_SPEED_100MHz_PCIX_533; 690 break; 691 case 0xd: 692 bus_speed = PCI_SPEED_133MHz_PCIX_533; 693 break; 694 default: 695 retval = -ENODEV; 696 break; 697 } 698 699 out: 700 bus->cur_bus_speed = bus_speed; 701 dbg("Current bus speed = %d\n", bus_speed); 702 return retval; 703} 704 705 706static int hpc_set_bus_speed_mode(struct slot *slot, enum pci_bus_speed value) 707{ 708 int retval; 709 struct controller *ctrl = slot->ctrl; 710 u8 pi, cmd; 711 712 pi = shpc_readb(ctrl, PROG_INTERFACE); 713 if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX)) 714 return -EINVAL; 715 716 switch (value) { 717 case PCI_SPEED_33MHz: 718 cmd = SETA_PCI_33MHZ; 719 break; 720 case PCI_SPEED_66MHz: 721 cmd = SETA_PCI_66MHZ; 722 break; 723 case PCI_SPEED_66MHz_PCIX: 724 cmd = SETA_PCIX_66MHZ; 725 break; 726 case PCI_SPEED_100MHz_PCIX: 727 cmd = SETA_PCIX_100MHZ; 728 break; 729 case PCI_SPEED_133MHz_PCIX: 730 cmd = SETA_PCIX_133MHZ; 731 break; 732 case PCI_SPEED_66MHz_PCIX_ECC: 733 cmd = SETB_PCIX_66MHZ_EM; 734 break; 735 case PCI_SPEED_100MHz_PCIX_ECC: 736 cmd = SETB_PCIX_100MHZ_EM; 737 break; 738 case PCI_SPEED_133MHz_PCIX_ECC: 739 cmd = SETB_PCIX_133MHZ_EM; 740 break; 741 case PCI_SPEED_66MHz_PCIX_266: 742 cmd = SETB_PCIX_66MHZ_266; 743 break; 744 case PCI_SPEED_100MHz_PCIX_266: 745 cmd = SETB_PCIX_100MHZ_266; 746 break; 747 case PCI_SPEED_133MHz_PCIX_266: 748 cmd = SETB_PCIX_133MHZ_266; 749 break; 750 case PCI_SPEED_66MHz_PCIX_533: 751 cmd = SETB_PCIX_66MHZ_533; 752 break; 753 case PCI_SPEED_100MHz_PCIX_533: 754 cmd = SETB_PCIX_100MHZ_533; 755 break; 756 case PCI_SPEED_133MHz_PCIX_533: 757 cmd = SETB_PCIX_133MHZ_533; 758 break; 759 default: 760 return -EINVAL; 761 } 762 763 retval = shpc_write_cmd(slot, 0, cmd); 764 if (retval) 765 ctrl_err(ctrl, "%s: Write command failed!\n", __func__); 766 else 767 shpc_get_cur_bus_speed(ctrl); 768 769 return retval; 770} 771 772static irqreturn_t shpc_isr(int irq, void *dev_id) 773{ 774 struct controller *ctrl = (struct controller *)dev_id; 775 u32 serr_int, slot_reg, intr_loc, intr_loc2; 776 int hp_slot; 777 778 /* Check to see if it was our interrupt */ 779 intr_loc = shpc_readl(ctrl, INTR_LOC); 780 if (!intr_loc) 781 return IRQ_NONE; 782 783 ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc); 784 785 if (!shpchp_poll_mode) { 786 /* 787 * Mask Global Interrupt Mask - see implementation 788 * note on p. 139 of SHPC spec rev 1.0 789 */ 790 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 791 serr_int |= GLOBAL_INTR_MASK; 792 serr_int &= ~SERR_INTR_RSVDZ_MASK; 793 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 794 795 intr_loc2 = shpc_readl(ctrl, INTR_LOC); 796 ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2); 797 } 798 799 if (intr_loc & CMD_INTR_PENDING) { 800 /* 801 * Command Complete Interrupt Pending 802 * RO only - clear by writing 1 to the Command Completion 803 * Detect bit in Controller SERR-INT register 804 */ 805 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 806 serr_int &= ~SERR_INTR_RSVDZ_MASK; 807 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 808 809 wake_up_interruptible(&ctrl->queue); 810 } 811 812 if (!(intr_loc & ~CMD_INTR_PENDING)) 813 goto out; 814 815 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 816 /* To find out which slot has interrupt pending */ 817 if (!(intr_loc & SLOT_INTR_PENDING(hp_slot))) 818 continue; 819 820 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 821 ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n", 822 hp_slot, slot_reg); 823 824 if (slot_reg & MRL_CHANGE_DETECTED) 825 shpchp_handle_switch_change(hp_slot, ctrl); 826 827 if (slot_reg & BUTTON_PRESS_DETECTED) 828 shpchp_handle_attention_button(hp_slot, ctrl); 829 830 if (slot_reg & PRSNT_CHANGE_DETECTED) 831 shpchp_handle_presence_change(hp_slot, ctrl); 832 833 if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED)) 834 shpchp_handle_power_fault(hp_slot, ctrl); 835 836 /* Clear all slot events */ 837 slot_reg &= ~SLOT_REG_RSVDZ_MASK; 838 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); 839 } 840 out: 841 if (!shpchp_poll_mode) { 842 /* Unmask Global Interrupt Mask */ 843 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 844 serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK); 845 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 846 } 847 848 return IRQ_HANDLED; 849} 850 851static int shpc_get_max_bus_speed(struct controller *ctrl) 852{ 853 int retval = 0; 854 struct pci_bus *bus = ctrl->pci_dev->subordinate; 855 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; 856 u8 pi = shpc_readb(ctrl, PROG_INTERFACE); 857 u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1); 858 u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2); 859 860 if (pi == 2) { 861 if (slot_avail2 & SLOT_133MHZ_PCIX_533) 862 bus_speed = PCI_SPEED_133MHz_PCIX_533; 863 else if (slot_avail2 & SLOT_100MHZ_PCIX_533) 864 bus_speed = PCI_SPEED_100MHz_PCIX_533; 865 else if (slot_avail2 & SLOT_66MHZ_PCIX_533) 866 bus_speed = PCI_SPEED_66MHz_PCIX_533; 867 else if (slot_avail2 & SLOT_133MHZ_PCIX_266) 868 bus_speed = PCI_SPEED_133MHz_PCIX_266; 869 else if (slot_avail2 & SLOT_100MHZ_PCIX_266) 870 bus_speed = PCI_SPEED_100MHz_PCIX_266; 871 else if (slot_avail2 & SLOT_66MHZ_PCIX_266) 872 bus_speed = PCI_SPEED_66MHz_PCIX_266; 873 } 874 875 if (bus_speed == PCI_SPEED_UNKNOWN) { 876 if (slot_avail1 & SLOT_133MHZ_PCIX) 877 bus_speed = PCI_SPEED_133MHz_PCIX; 878 else if (slot_avail1 & SLOT_100MHZ_PCIX) 879 bus_speed = PCI_SPEED_100MHz_PCIX; 880 else if (slot_avail1 & SLOT_66MHZ_PCIX) 881 bus_speed = PCI_SPEED_66MHz_PCIX; 882 else if (slot_avail2 & SLOT_66MHZ) 883 bus_speed = PCI_SPEED_66MHz; 884 else if (slot_avail1 & SLOT_33MHZ) 885 bus_speed = PCI_SPEED_33MHz; 886 else 887 retval = -ENODEV; 888 } 889 890 bus->max_bus_speed = bus_speed; 891 ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed); 892 893 return retval; 894} 895 896static const struct hpc_ops shpchp_hpc_ops = { 897 .power_on_slot = hpc_power_on_slot, 898 .slot_enable = hpc_slot_enable, 899 .slot_disable = hpc_slot_disable, 900 .set_bus_speed_mode = hpc_set_bus_speed_mode, 901 .set_attention_status = hpc_set_attention_status, 902 .get_power_status = hpc_get_power_status, 903 .get_attention_status = hpc_get_attention_status, 904 .get_latch_status = hpc_get_latch_status, 905 .get_adapter_status = hpc_get_adapter_status, 906 907 .get_adapter_speed = hpc_get_adapter_speed, 908 .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap, 909 .get_prog_int = hpc_get_prog_int, 910 911 .query_power_fault = hpc_query_power_fault, 912 .green_led_on = hpc_set_green_led_on, 913 .green_led_off = hpc_set_green_led_off, 914 .green_led_blink = hpc_set_green_led_blink, 915 916 .release_ctlr = hpc_release_ctlr, 917}; 918 919int shpc_init(struct controller *ctrl, struct pci_dev *pdev) 920{ 921 int rc = -1, num_slots = 0; 922 u8 hp_slot; 923 u32 shpc_base_offset; 924 u32 tempdword, slot_reg, slot_config; 925 u8 i; 926 927 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ 928 ctrl_dbg(ctrl, "Hotplug Controller:\n"); 929 930 if (pdev->vendor == PCI_VENDOR_ID_AMD && 931 pdev->device == PCI_DEVICE_ID_AMD_GOLAM_7450) { 932 /* amd shpc driver doesn't use Base Offset; assume 0 */ 933 ctrl->mmio_base = pci_resource_start(pdev, 0); 934 ctrl->mmio_size = pci_resource_len(pdev, 0); 935 } else { 936 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC); 937 if (!ctrl->cap_offset) { 938 ctrl_err(ctrl, "Cannot find PCI capability\n"); 939 goto abort; 940 } 941 ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset); 942 943 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset); 944 if (rc) { 945 ctrl_err(ctrl, "Cannot read base_offset\n"); 946 goto abort; 947 } 948 949 rc = shpc_indirect_read(ctrl, 3, &tempdword); 950 if (rc) { 951 ctrl_err(ctrl, "Cannot read slot config\n"); 952 goto abort; 953 } 954 num_slots = tempdword & SLOT_NUM; 955 ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots); 956 957 for (i = 0; i < 9 + num_slots; i++) { 958 rc = shpc_indirect_read(ctrl, i, &tempdword); 959 if (rc) { 960 ctrl_err(ctrl, "Cannot read creg (index = %d)\n", 961 i); 962 goto abort; 963 } 964 ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword); 965 } 966 967 ctrl->mmio_base = 968 pci_resource_start(pdev, 0) + shpc_base_offset; 969 ctrl->mmio_size = 0x24 + 0x4 * num_slots; 970 } 971 972 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", 973 pdev->vendor, pdev->device, pdev->subsystem_vendor, 974 pdev->subsystem_device); 975 976 rc = pci_enable_device(pdev); 977 if (rc) { 978 ctrl_err(ctrl, "pci_enable_device failed\n"); 979 goto abort; 980 } 981 982 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) { 983 ctrl_err(ctrl, "Cannot reserve MMIO region\n"); 984 rc = -1; 985 goto abort; 986 } 987 988 ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size); 989 if (!ctrl->creg) { 990 ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n", 991 ctrl->mmio_size, ctrl->mmio_base); 992 release_mem_region(ctrl->mmio_base, ctrl->mmio_size); 993 rc = -1; 994 goto abort; 995 } 996 ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg); 997 998 mutex_init(&ctrl->crit_sect); 999 mutex_init(&ctrl->cmd_lock); 1000 1001 /* Setup wait queue */ 1002 init_waitqueue_head(&ctrl->queue); 1003 1004 ctrl->hpc_ops = &shpchp_hpc_ops; 1005 1006 /* Return PCI Controller Info */ 1007 slot_config = shpc_readl(ctrl, SLOT_CONFIG); 1008 ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8; 1009 ctrl->num_slots = slot_config & SLOT_NUM; 1010 ctrl->first_slot = (slot_config & PSN) >> 16; 1011 ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1; 1012 1013 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */ 1014 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1015 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); 1016 tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | 1017 COMMAND_INTR_MASK | ARBITER_SERR_MASK); 1018 tempdword &= ~SERR_INTR_RSVDZ_MASK; 1019 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); 1020 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1021 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); 1022 1023 /* Mask the MRL sensor SERR Mask of individual slot in 1024 * Slot SERR-INT Mask & clear all the existing event if any 1025 */ 1026 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 1027 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 1028 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n", 1029 hp_slot, slot_reg); 1030 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 1031 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 1032 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | 1033 CON_PFAULT_SERR_MASK); 1034 slot_reg &= ~SLOT_REG_RSVDZ_MASK; 1035 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); 1036 } 1037 1038 if (shpchp_poll_mode) { 1039 /* Install interrupt polling timer. Start with 10 sec delay */ 1040 timer_setup(&ctrl->poll_timer, int_poll_timeout, 0); 1041 start_int_poll_timer(ctrl, 10); 1042 } else { 1043 /* Installs the interrupt handler */ 1044 rc = pci_enable_msi(pdev); 1045 if (rc) { 1046 ctrl_info(ctrl, "Can't get msi for the hotplug controller\n"); 1047 ctrl_info(ctrl, "Use INTx for the hotplug controller\n"); 1048 } else { 1049 pci_set_master(pdev); 1050 } 1051 1052 rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED, 1053 MY_NAME, (void *)ctrl); 1054 ctrl_dbg(ctrl, "request_irq %d (returns %d)\n", 1055 ctrl->pci_dev->irq, rc); 1056 if (rc) { 1057 ctrl_err(ctrl, "Can't get irq %d for the hotplug controller\n", 1058 ctrl->pci_dev->irq); 1059 goto abort_iounmap; 1060 } 1061 } 1062 ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq); 1063 1064 shpc_get_max_bus_speed(ctrl); 1065 shpc_get_cur_bus_speed(ctrl); 1066 1067 /* 1068 * Unmask all event interrupts of all slots 1069 */ 1070 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 1071 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 1072 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n", 1073 hp_slot, slot_reg); 1074 slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 1075 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 1076 CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK); 1077 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); 1078 } 1079 if (!shpchp_poll_mode) { 1080 /* Unmask all general input interrupts and SERR */ 1081 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1082 tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK | 1083 SERR_INTR_RSVDZ_MASK); 1084 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); 1085 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1086 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); 1087 } 1088 1089 return 0; 1090 1091 /* We end up here for the many possible ways to fail this API. */ 1092abort_iounmap: 1093 iounmap(ctrl->creg); 1094abort: 1095 return rc; 1096} 1097