1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Rockchip AXI PCIe host controller driver 4 * 5 * Copyright (c) 2016 Rockchip, Inc. 6 * 7 * Author: Shawn Lin <shawn.lin@rock-chips.com> 8 * Wenrui Li <wenrui.li@rock-chips.com> 9 * 10 * Bits taken from Synopsys DesignWare Host controller driver and 11 * ARM PCI Host generic driver. 12 */ 13 14#include <linux/clk.h> 15#include <linux/delay.h> 16#include <linux/gpio/consumer.h> 17#include <linux/iopoll.h> 18#include <linux/of_pci.h> 19#include <linux/phy/phy.h> 20#include <linux/platform_device.h> 21#include <linux/reset.h> 22 23#include "../pci.h" 24#include "pcie-rockchip.h" 25 26int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) 27{ 28 struct device *dev = rockchip->dev; 29 struct platform_device *pdev = to_platform_device(dev); 30 struct device_node *node = dev->of_node; 31 struct resource *regs; 32 int err; 33 34 if (rockchip->is_rc) { 35 regs = platform_get_resource_byname(pdev, 36 IORESOURCE_MEM, 37 "axi-base"); 38 rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs); 39 if (IS_ERR(rockchip->reg_base)) 40 return PTR_ERR(rockchip->reg_base); 41 } else { 42 rockchip->mem_res = 43 platform_get_resource_byname(pdev, IORESOURCE_MEM, 44 "mem-base"); 45 if (!rockchip->mem_res) 46 return -EINVAL; 47 } 48 49 rockchip->apb_base = 50 devm_platform_ioremap_resource_byname(pdev, "apb-base"); 51 if (IS_ERR(rockchip->apb_base)) 52 return PTR_ERR(rockchip->apb_base); 53 54 err = rockchip_pcie_get_phys(rockchip); 55 if (err) 56 return err; 57 58 rockchip->lanes = 1; 59 err = of_property_read_u32(node, "num-lanes", &rockchip->lanes); 60 if (!err && (rockchip->lanes == 0 || 61 rockchip->lanes == 3 || 62 rockchip->lanes > 4)) { 63 dev_warn(dev, "invalid num-lanes, default to use one lane\n"); 64 rockchip->lanes = 1; 65 } 66 67 rockchip->link_gen = of_pci_get_max_link_speed(node); 68 if (rockchip->link_gen < 0 || rockchip->link_gen > 2) 69 rockchip->link_gen = 2; 70 71 rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core"); 72 if (IS_ERR(rockchip->core_rst)) { 73 if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER) 74 dev_err(dev, "missing core reset property in node\n"); 75 return PTR_ERR(rockchip->core_rst); 76 } 77 78 rockchip->mgmt_rst = devm_reset_control_get_exclusive(dev, "mgmt"); 79 if (IS_ERR(rockchip->mgmt_rst)) { 80 if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER) 81 dev_err(dev, "missing mgmt reset property in node\n"); 82 return PTR_ERR(rockchip->mgmt_rst); 83 } 84 85 rockchip->mgmt_sticky_rst = devm_reset_control_get_exclusive(dev, 86 "mgmt-sticky"); 87 if (IS_ERR(rockchip->mgmt_sticky_rst)) { 88 if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER) 89 dev_err(dev, "missing mgmt-sticky reset property in node\n"); 90 return PTR_ERR(rockchip->mgmt_sticky_rst); 91 } 92 93 rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe"); 94 if (IS_ERR(rockchip->pipe_rst)) { 95 if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER) 96 dev_err(dev, "missing pipe reset property in node\n"); 97 return PTR_ERR(rockchip->pipe_rst); 98 } 99 100 rockchip->pm_rst = devm_reset_control_get_exclusive(dev, "pm"); 101 if (IS_ERR(rockchip->pm_rst)) { 102 if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER) 103 dev_err(dev, "missing pm reset property in node\n"); 104 return PTR_ERR(rockchip->pm_rst); 105 } 106 107 rockchip->pclk_rst = devm_reset_control_get_exclusive(dev, "pclk"); 108 if (IS_ERR(rockchip->pclk_rst)) { 109 if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER) 110 dev_err(dev, "missing pclk reset property in node\n"); 111 return PTR_ERR(rockchip->pclk_rst); 112 } 113 114 rockchip->aclk_rst = devm_reset_control_get_exclusive(dev, "aclk"); 115 if (IS_ERR(rockchip->aclk_rst)) { 116 if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER) 117 dev_err(dev, "missing aclk reset property in node\n"); 118 return PTR_ERR(rockchip->aclk_rst); 119 } 120 121 if (rockchip->is_rc) { 122 rockchip->ep_gpio = devm_gpiod_get_optional(dev, "ep", 123 GPIOD_OUT_HIGH); 124 if (IS_ERR(rockchip->ep_gpio)) 125 return dev_err_probe(dev, PTR_ERR(rockchip->ep_gpio), 126 "failed to get ep GPIO\n"); 127 } 128 129 rockchip->aclk_pcie = devm_clk_get(dev, "aclk"); 130 if (IS_ERR(rockchip->aclk_pcie)) { 131 dev_err(dev, "aclk clock not found\n"); 132 return PTR_ERR(rockchip->aclk_pcie); 133 } 134 135 rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf"); 136 if (IS_ERR(rockchip->aclk_perf_pcie)) { 137 dev_err(dev, "aclk_perf clock not found\n"); 138 return PTR_ERR(rockchip->aclk_perf_pcie); 139 } 140 141 rockchip->hclk_pcie = devm_clk_get(dev, "hclk"); 142 if (IS_ERR(rockchip->hclk_pcie)) { 143 dev_err(dev, "hclk clock not found\n"); 144 return PTR_ERR(rockchip->hclk_pcie); 145 } 146 147 rockchip->clk_pcie_pm = devm_clk_get(dev, "pm"); 148 if (IS_ERR(rockchip->clk_pcie_pm)) { 149 dev_err(dev, "pm clock not found\n"); 150 return PTR_ERR(rockchip->clk_pcie_pm); 151 } 152 153 return 0; 154} 155EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt); 156 157#define rockchip_pcie_read_addr(addr) rockchip_pcie_read(rockchip, addr) 158/* 100 ms max wait time for PHY PLLs to lock */ 159#define RK_PHY_PLL_LOCK_TIMEOUT_US 100000 160/* Sleep should be less than 20ms */ 161#define RK_PHY_PLL_LOCK_SLEEP_US 1000 162 163int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) 164{ 165 struct device *dev = rockchip->dev; 166 int err, i; 167 u32 regs; 168 169 err = reset_control_assert(rockchip->aclk_rst); 170 if (err) { 171 dev_err(dev, "assert aclk_rst err %d\n", err); 172 return err; 173 } 174 175 err = reset_control_assert(rockchip->pclk_rst); 176 if (err) { 177 dev_err(dev, "assert pclk_rst err %d\n", err); 178 return err; 179 } 180 181 err = reset_control_assert(rockchip->pm_rst); 182 if (err) { 183 dev_err(dev, "assert pm_rst err %d\n", err); 184 return err; 185 } 186 187 for (i = 0; i < MAX_LANE_NUM; i++) { 188 err = phy_init(rockchip->phys[i]); 189 if (err) { 190 dev_err(dev, "init phy%d err %d\n", i, err); 191 goto err_exit_phy; 192 } 193 } 194 195 err = reset_control_assert(rockchip->core_rst); 196 if (err) { 197 dev_err(dev, "assert core_rst err %d\n", err); 198 goto err_exit_phy; 199 } 200 201 err = reset_control_assert(rockchip->mgmt_rst); 202 if (err) { 203 dev_err(dev, "assert mgmt_rst err %d\n", err); 204 goto err_exit_phy; 205 } 206 207 err = reset_control_assert(rockchip->mgmt_sticky_rst); 208 if (err) { 209 dev_err(dev, "assert mgmt_sticky_rst err %d\n", err); 210 goto err_exit_phy; 211 } 212 213 err = reset_control_assert(rockchip->pipe_rst); 214 if (err) { 215 dev_err(dev, "assert pipe_rst err %d\n", err); 216 goto err_exit_phy; 217 } 218 219 udelay(10); 220 221 err = reset_control_deassert(rockchip->pm_rst); 222 if (err) { 223 dev_err(dev, "deassert pm_rst err %d\n", err); 224 goto err_exit_phy; 225 } 226 227 err = reset_control_deassert(rockchip->aclk_rst); 228 if (err) { 229 dev_err(dev, "deassert aclk_rst err %d\n", err); 230 goto err_exit_phy; 231 } 232 233 err = reset_control_deassert(rockchip->pclk_rst); 234 if (err) { 235 dev_err(dev, "deassert pclk_rst err %d\n", err); 236 goto err_exit_phy; 237 } 238 239 if (rockchip->link_gen == 2) 240 rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2, 241 PCIE_CLIENT_CONFIG); 242 else 243 rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1, 244 PCIE_CLIENT_CONFIG); 245 246 regs = PCIE_CLIENT_LINK_TRAIN_ENABLE | PCIE_CLIENT_ARI_ENABLE | 247 PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes); 248 249 if (rockchip->is_rc) 250 regs |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC; 251 else 252 regs |= PCIE_CLIENT_CONF_DISABLE | PCIE_CLIENT_MODE_EP; 253 254 rockchip_pcie_write(rockchip, regs, PCIE_CLIENT_CONFIG); 255 256 for (i = 0; i < MAX_LANE_NUM; i++) { 257 err = phy_power_on(rockchip->phys[i]); 258 if (err) { 259 dev_err(dev, "power on phy%d err %d\n", i, err); 260 goto err_power_off_phy; 261 } 262 } 263 264 err = readx_poll_timeout(rockchip_pcie_read_addr, 265 PCIE_CLIENT_SIDE_BAND_STATUS, 266 regs, !(regs & PCIE_CLIENT_PHY_ST), 267 RK_PHY_PLL_LOCK_SLEEP_US, 268 RK_PHY_PLL_LOCK_TIMEOUT_US); 269 if (err) { 270 dev_err(dev, "PHY PLLs could not lock, %d\n", err); 271 goto err_power_off_phy; 272 } 273 274 /* 275 * Please don't reorder the deassert sequence of the following 276 * four reset pins. 277 */ 278 err = reset_control_deassert(rockchip->mgmt_sticky_rst); 279 if (err) { 280 dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err); 281 goto err_power_off_phy; 282 } 283 284 err = reset_control_deassert(rockchip->core_rst); 285 if (err) { 286 dev_err(dev, "deassert core_rst err %d\n", err); 287 goto err_power_off_phy; 288 } 289 290 err = reset_control_deassert(rockchip->mgmt_rst); 291 if (err) { 292 dev_err(dev, "deassert mgmt_rst err %d\n", err); 293 goto err_power_off_phy; 294 } 295 296 err = reset_control_deassert(rockchip->pipe_rst); 297 if (err) { 298 dev_err(dev, "deassert pipe_rst err %d\n", err); 299 goto err_power_off_phy; 300 } 301 302 return 0; 303err_power_off_phy: 304 while (i--) 305 phy_power_off(rockchip->phys[i]); 306 i = MAX_LANE_NUM; 307err_exit_phy: 308 while (i--) 309 phy_exit(rockchip->phys[i]); 310 return err; 311} 312EXPORT_SYMBOL_GPL(rockchip_pcie_init_port); 313 314int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip) 315{ 316 struct device *dev = rockchip->dev; 317 struct phy *phy; 318 char *name; 319 u32 i; 320 321 phy = devm_phy_get(dev, "pcie-phy"); 322 if (!IS_ERR(phy)) { 323 rockchip->legacy_phy = true; 324 rockchip->phys[0] = phy; 325 dev_warn(dev, "legacy phy model is deprecated!\n"); 326 return 0; 327 } 328 329 if (PTR_ERR(phy) == -EPROBE_DEFER) 330 return PTR_ERR(phy); 331 332 dev_dbg(dev, "missing legacy phy; search for per-lane PHY\n"); 333 334 for (i = 0; i < MAX_LANE_NUM; i++) { 335 name = kasprintf(GFP_KERNEL, "pcie-phy-%u", i); 336 if (!name) 337 return -ENOMEM; 338 339 phy = devm_of_phy_get(dev, dev->of_node, name); 340 kfree(name); 341 342 if (IS_ERR(phy)) { 343 if (PTR_ERR(phy) != -EPROBE_DEFER) 344 dev_err(dev, "missing phy for lane %d: %ld\n", 345 i, PTR_ERR(phy)); 346 return PTR_ERR(phy); 347 } 348 349 rockchip->phys[i] = phy; 350 } 351 352 return 0; 353} 354EXPORT_SYMBOL_GPL(rockchip_pcie_get_phys); 355 356void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip) 357{ 358 int i; 359 360 for (i = 0; i < MAX_LANE_NUM; i++) { 361 /* inactive lanes are already powered off */ 362 if (rockchip->lanes_map & BIT(i)) 363 phy_power_off(rockchip->phys[i]); 364 phy_exit(rockchip->phys[i]); 365 } 366} 367EXPORT_SYMBOL_GPL(rockchip_pcie_deinit_phys); 368 369int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip) 370{ 371 struct device *dev = rockchip->dev; 372 int err; 373 374 err = clk_prepare_enable(rockchip->aclk_pcie); 375 if (err) { 376 dev_err(dev, "unable to enable aclk_pcie clock\n"); 377 return err; 378 } 379 380 err = clk_prepare_enable(rockchip->aclk_perf_pcie); 381 if (err) { 382 dev_err(dev, "unable to enable aclk_perf_pcie clock\n"); 383 goto err_aclk_perf_pcie; 384 } 385 386 err = clk_prepare_enable(rockchip->hclk_pcie); 387 if (err) { 388 dev_err(dev, "unable to enable hclk_pcie clock\n"); 389 goto err_hclk_pcie; 390 } 391 392 err = clk_prepare_enable(rockchip->clk_pcie_pm); 393 if (err) { 394 dev_err(dev, "unable to enable clk_pcie_pm clock\n"); 395 goto err_clk_pcie_pm; 396 } 397 398 return 0; 399 400err_clk_pcie_pm: 401 clk_disable_unprepare(rockchip->hclk_pcie); 402err_hclk_pcie: 403 clk_disable_unprepare(rockchip->aclk_perf_pcie); 404err_aclk_perf_pcie: 405 clk_disable_unprepare(rockchip->aclk_pcie); 406 return err; 407} 408EXPORT_SYMBOL_GPL(rockchip_pcie_enable_clocks); 409 410void rockchip_pcie_disable_clocks(void *data) 411{ 412 struct rockchip_pcie *rockchip = data; 413 414 clk_disable_unprepare(rockchip->clk_pcie_pm); 415 clk_disable_unprepare(rockchip->hclk_pcie); 416 clk_disable_unprepare(rockchip->aclk_perf_pcie); 417 clk_disable_unprepare(rockchip->aclk_pcie); 418} 419EXPORT_SYMBOL_GPL(rockchip_pcie_disable_clocks); 420 421void rockchip_pcie_cfg_configuration_accesses( 422 struct rockchip_pcie *rockchip, u32 type) 423{ 424 u32 ob_desc_0; 425 426 /* Configuration Accesses for region 0 */ 427 rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF); 428 429 rockchip_pcie_write(rockchip, 430 (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS), 431 PCIE_CORE_OB_REGION_ADDR0); 432 rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H, 433 PCIE_CORE_OB_REGION_ADDR1); 434 ob_desc_0 = rockchip_pcie_read(rockchip, PCIE_CORE_OB_REGION_DESC0); 435 ob_desc_0 &= ~(RC_REGION_0_TYPE_MASK); 436 ob_desc_0 |= (type | (0x1 << 23)); 437 rockchip_pcie_write(rockchip, ob_desc_0, PCIE_CORE_OB_REGION_DESC0); 438 rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1); 439} 440EXPORT_SYMBOL_GPL(rockchip_pcie_cfg_configuration_accesses); 441