1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2015 - 2016 Cavium, Inc.
4 */
5
6#include <linux/bitfield.h>
7#include <linux/kernel.h>
8#include <linux/init.h>
9#include <linux/pci.h>
10#include <linux/of_address.h>
11#include <linux/of_pci.h>
12#include <linux/pci-acpi.h>
13#include <linux/pci-ecam.h>
14#include <linux/platform_device.h>
15#include <linux/io-64-nonatomic-lo-hi.h>
16#include "../pci.h"
17
18#if defined(CONFIG_PCI_HOST_THUNDER_PEM) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
19
20#define PEM_CFG_WR 0x28
21#define PEM_CFG_RD 0x30
22
23struct thunder_pem_pci {
24	u32		ea_entry[3];
25	void __iomem	*pem_reg_base;
26};
27
28static int thunder_pem_bridge_read(struct pci_bus *bus, unsigned int devfn,
29				   int where, int size, u32 *val)
30{
31	u64 read_val, tmp_val;
32	struct pci_config_window *cfg = bus->sysdata;
33	struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
34
35	if (devfn != 0 || where >= 2048) {
36		*val = ~0;
37		return PCIBIOS_DEVICE_NOT_FOUND;
38	}
39
40	/*
41	 * 32-bit accesses only.  Write the address to the low order
42	 * bits of PEM_CFG_RD, then trigger the read by reading back.
43	 * The config data lands in the upper 32-bits of PEM_CFG_RD.
44	 */
45	read_val = where & ~3ull;
46	writeq(read_val, pem_pci->pem_reg_base + PEM_CFG_RD);
47	read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
48	read_val >>= 32;
49
50	/*
51	 * The config space contains some garbage, fix it up.  Also
52	 * synthesize an EA capability for the BAR used by MSI-X.
53	 */
54	switch (where & ~3) {
55	case 0x40:
56		read_val &= 0xffff00ff;
57		read_val |= 0x00007000; /* Skip MSI CAP */
58		break;
59	case 0x70: /* Express Cap */
60		/*
61		 * Change PME interrupt to vector 2 on T88 where it
62		 * reads as 0, else leave it alone.
63		 */
64		if (!(read_val & (0x1f << 25)))
65			read_val |= (2u << 25);
66		break;
67	case 0xb0: /* MSI-X Cap */
68		/* TableSize=2 or 4, Next Cap is EA */
69		read_val &= 0xc00000ff;
70		/*
71		 * If Express Cap(0x70) raw PME vector reads as 0 we are on
72		 * T88 and TableSize is reported as 4, else TableSize
73		 * is 2.
74		 */
75		writeq(0x70, pem_pci->pem_reg_base + PEM_CFG_RD);
76		tmp_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
77		tmp_val >>= 32;
78		if (!(tmp_val & (0x1f << 25)))
79			read_val |= 0x0003bc00;
80		else
81			read_val |= 0x0001bc00;
82		break;
83	case 0xb4:
84		/* Table offset=0, BIR=0 */
85		read_val = 0x00000000;
86		break;
87	case 0xb8:
88		/* BPA offset=0xf0000, BIR=0 */
89		read_val = 0x000f0000;
90		break;
91	case 0xbc:
92		/* EA, 1 entry, no next Cap */
93		read_val = 0x00010014;
94		break;
95	case 0xc0:
96		/* DW2 for type-1 */
97		read_val = 0x00000000;
98		break;
99	case 0xc4:
100		/* Entry BEI=0, PP=0x00, SP=0xff, ES=3 */
101		read_val = 0x80ff0003;
102		break;
103	case 0xc8:
104		read_val = pem_pci->ea_entry[0];
105		break;
106	case 0xcc:
107		read_val = pem_pci->ea_entry[1];
108		break;
109	case 0xd0:
110		read_val = pem_pci->ea_entry[2];
111		break;
112	default:
113		break;
114	}
115	read_val >>= (8 * (where & 3));
116	switch (size) {
117	case 1:
118		read_val &= 0xff;
119		break;
120	case 2:
121		read_val &= 0xffff;
122		break;
123	default:
124		break;
125	}
126	*val = read_val;
127	return PCIBIOS_SUCCESSFUL;
128}
129
130static int thunder_pem_config_read(struct pci_bus *bus, unsigned int devfn,
131				   int where, int size, u32 *val)
132{
133	struct pci_config_window *cfg = bus->sysdata;
134
135	if (bus->number < cfg->busr.start ||
136	    bus->number > cfg->busr.end)
137		return PCIBIOS_DEVICE_NOT_FOUND;
138
139	/*
140	 * The first device on the bus is the PEM PCIe bridge.
141	 * Special case its config access.
142	 */
143	if (bus->number == cfg->busr.start)
144		return thunder_pem_bridge_read(bus, devfn, where, size, val);
145
146	return pci_generic_config_read(bus, devfn, where, size, val);
147}
148
149/*
150 * Some of the w1c_bits below also include read-only or non-writable
151 * reserved bits, this makes the code simpler and is OK as the bits
152 * are not affected by writing zeros to them.
153 */
154static u32 thunder_pem_bridge_w1c_bits(u64 where_aligned)
155{
156	u32 w1c_bits = 0;
157
158	switch (where_aligned) {
159	case 0x04: /* Command/Status */
160	case 0x1c: /* Base and I/O Limit/Secondary Status */
161		w1c_bits = 0xff000000;
162		break;
163	case 0x44: /* Power Management Control and Status */
164		w1c_bits = 0xfffffe00;
165		break;
166	case 0x78: /* Device Control/Device Status */
167	case 0x80: /* Link Control/Link Status */
168	case 0x88: /* Slot Control/Slot Status */
169	case 0x90: /* Root Status */
170	case 0xa0: /* Link Control 2 Registers/Link Status 2 */
171		w1c_bits = 0xffff0000;
172		break;
173	case 0x104: /* Uncorrectable Error Status */
174	case 0x110: /* Correctable Error Status */
175	case 0x130: /* Error Status */
176	case 0x160: /* Link Control 4 */
177		w1c_bits = 0xffffffff;
178		break;
179	default:
180		break;
181	}
182	return w1c_bits;
183}
184
185/* Some bits must be written to one so they appear to be read-only. */
186static u32 thunder_pem_bridge_w1_bits(u64 where_aligned)
187{
188	u32 w1_bits;
189
190	switch (where_aligned) {
191	case 0x1c: /* I/O Base / I/O Limit, Secondary Status */
192		/* Force 32-bit I/O addressing. */
193		w1_bits = 0x0101;
194		break;
195	case 0x24: /* Prefetchable Memory Base / Prefetchable Memory Limit */
196		/* Force 64-bit addressing */
197		w1_bits = 0x00010001;
198		break;
199	default:
200		w1_bits = 0;
201		break;
202	}
203	return w1_bits;
204}
205
206static int thunder_pem_bridge_write(struct pci_bus *bus, unsigned int devfn,
207				    int where, int size, u32 val)
208{
209	struct pci_config_window *cfg = bus->sysdata;
210	struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
211	u64 write_val, read_val;
212	u64 where_aligned = where & ~3ull;
213	u32 mask = 0;
214
215
216	if (devfn != 0 || where >= 2048)
217		return PCIBIOS_DEVICE_NOT_FOUND;
218
219	/*
220	 * 32-bit accesses only.  If the write is for a size smaller
221	 * than 32-bits, we must first read the 32-bit value and merge
222	 * in the desired bits and then write the whole 32-bits back
223	 * out.
224	 */
225	switch (size) {
226	case 1:
227		writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);
228		read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
229		read_val >>= 32;
230		mask = ~(0xff << (8 * (where & 3)));
231		read_val &= mask;
232		val = (val & 0xff) << (8 * (where & 3));
233		val |= (u32)read_val;
234		break;
235	case 2:
236		writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);
237		read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
238		read_val >>= 32;
239		mask = ~(0xffff << (8 * (where & 3)));
240		read_val &= mask;
241		val = (val & 0xffff) << (8 * (where & 3));
242		val |= (u32)read_val;
243		break;
244	default:
245		break;
246	}
247
248	/*
249	 * By expanding the write width to 32 bits, we may
250	 * inadvertently hit some W1C bits that were not intended to
251	 * be written.  Calculate the mask that must be applied to the
252	 * data to be written to avoid these cases.
253	 */
254	if (mask) {
255		u32 w1c_bits = thunder_pem_bridge_w1c_bits(where);
256
257		if (w1c_bits) {
258			mask &= w1c_bits;
259			val &= ~mask;
260		}
261	}
262
263	/*
264	 * Some bits must be read-only with value of one.  Since the
265	 * access method allows these to be cleared if a zero is
266	 * written, force them to one before writing.
267	 */
268	val |= thunder_pem_bridge_w1_bits(where_aligned);
269
270	/*
271	 * Low order bits are the config address, the high order 32
272	 * bits are the data to be written.
273	 */
274	write_val = (((u64)val) << 32) | where_aligned;
275	writeq(write_val, pem_pci->pem_reg_base + PEM_CFG_WR);
276	return PCIBIOS_SUCCESSFUL;
277}
278
279static int thunder_pem_config_write(struct pci_bus *bus, unsigned int devfn,
280				    int where, int size, u32 val)
281{
282	struct pci_config_window *cfg = bus->sysdata;
283
284	if (bus->number < cfg->busr.start ||
285	    bus->number > cfg->busr.end)
286		return PCIBIOS_DEVICE_NOT_FOUND;
287	/*
288	 * The first device on the bus is the PEM PCIe bridge.
289	 * Special case its config access.
290	 */
291	if (bus->number == cfg->busr.start)
292		return thunder_pem_bridge_write(bus, devfn, where, size, val);
293
294
295	return pci_generic_config_write(bus, devfn, where, size, val);
296}
297
298static int thunder_pem_init(struct device *dev, struct pci_config_window *cfg,
299			    struct resource *res_pem)
300{
301	struct thunder_pem_pci *pem_pci;
302	resource_size_t bar4_start;
303
304	pem_pci = devm_kzalloc(dev, sizeof(*pem_pci), GFP_KERNEL);
305	if (!pem_pci)
306		return -ENOMEM;
307
308	pem_pci->pem_reg_base = devm_ioremap(dev, res_pem->start, 0x10000);
309	if (!pem_pci->pem_reg_base)
310		return -ENOMEM;
311
312	/*
313	 * The MSI-X BAR for the PEM and AER interrupts is located at
314	 * a fixed offset from the PEM register base.  Generate a
315	 * fragment of the synthesized Enhanced Allocation capability
316	 * structure here for the BAR.
317	 */
318	bar4_start = res_pem->start + 0xf00000;
319	pem_pci->ea_entry[0] = lower_32_bits(bar4_start) | 2;
320	pem_pci->ea_entry[1] = lower_32_bits(res_pem->end - bar4_start) & ~3u;
321	pem_pci->ea_entry[2] = upper_32_bits(bar4_start);
322
323	cfg->priv = pem_pci;
324	return 0;
325}
326
327#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
328
329#define PEM_RES_BASE		0x87e0c0000000ULL
330#define PEM_NODE_MASK		GENMASK_ULL(45, 44)
331#define PEM_INDX_MASK		GENMASK_ULL(26, 24)
332#define PEM_MIN_DOM_IN_NODE	4
333#define PEM_MAX_DOM_IN_NODE	10
334
335static void thunder_pem_reserve_range(struct device *dev, int seg,
336				      struct resource *r)
337{
338	resource_size_t start = r->start, end = r->end;
339	struct resource *res;
340	const char *regionid;
341
342	regionid = kasprintf(GFP_KERNEL, "PEM RC:%d", seg);
343	if (!regionid)
344		return;
345
346	res = request_mem_region(start, end - start + 1, regionid);
347	if (res)
348		res->flags &= ~IORESOURCE_BUSY;
349	else
350		kfree(regionid);
351
352	dev_info(dev, "%pR %s reserved\n", r,
353		 res ? "has been" : "could not be");
354}
355
356static void thunder_pem_legacy_fw(struct acpi_pci_root *root,
357				 struct resource *res_pem)
358{
359	int node = acpi_get_node(root->device->handle);
360	int index;
361
362	if (node == NUMA_NO_NODE)
363		node = 0;
364
365	index = root->segment - PEM_MIN_DOM_IN_NODE;
366	index -= node * PEM_MAX_DOM_IN_NODE;
367	res_pem->start = PEM_RES_BASE | FIELD_PREP(PEM_NODE_MASK, node) |
368					FIELD_PREP(PEM_INDX_MASK, index);
369	res_pem->flags = IORESOURCE_MEM;
370}
371
372static int thunder_pem_acpi_init(struct pci_config_window *cfg)
373{
374	struct device *dev = cfg->parent;
375	struct acpi_device *adev = to_acpi_device(dev);
376	struct acpi_pci_root *root = acpi_driver_data(adev);
377	struct resource *res_pem;
378	int ret;
379
380	res_pem = devm_kzalloc(&adev->dev, sizeof(*res_pem), GFP_KERNEL);
381	if (!res_pem)
382		return -ENOMEM;
383
384	ret = acpi_get_rc_resources(dev, "CAVA02B", root->segment, res_pem);
385
386	/*
387	 * If we fail to gather resources it means that we run with old
388	 * FW where we need to calculate PEM-specific resources manually.
389	 */
390	if (ret) {
391		thunder_pem_legacy_fw(root, res_pem);
392		/*
393		 * Reserve 64K size PEM specific resources. The full 16M range
394		 * size is required for thunder_pem_init() call.
395		 */
396		res_pem->end = res_pem->start + SZ_64K - 1;
397		thunder_pem_reserve_range(dev, root->segment, res_pem);
398		res_pem->end = res_pem->start + SZ_16M - 1;
399
400		/* Reserve PCI configuration space as well. */
401		thunder_pem_reserve_range(dev, root->segment, &cfg->res);
402	}
403
404	return thunder_pem_init(dev, cfg, res_pem);
405}
406
407const struct pci_ecam_ops thunder_pem_ecam_ops = {
408	.bus_shift	= 24,
409	.init		= thunder_pem_acpi_init,
410	.pci_ops	= {
411		.map_bus	= pci_ecam_map_bus,
412		.read		= thunder_pem_config_read,
413		.write		= thunder_pem_config_write,
414	}
415};
416
417#endif
418
419#ifdef CONFIG_PCI_HOST_THUNDER_PEM
420
421static int thunder_pem_platform_init(struct pci_config_window *cfg)
422{
423	struct device *dev = cfg->parent;
424	struct platform_device *pdev = to_platform_device(dev);
425	struct resource *res_pem;
426
427	if (!dev->of_node)
428		return -EINVAL;
429
430	/*
431	 * The second register range is the PEM bridge to the PCIe
432	 * bus.  It has a different config access method than those
433	 * devices behind the bridge.
434	 */
435	res_pem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
436	if (!res_pem) {
437		dev_err(dev, "missing \"reg[1]\"property\n");
438		return -EINVAL;
439	}
440
441	return thunder_pem_init(dev, cfg, res_pem);
442}
443
444static const struct pci_ecam_ops pci_thunder_pem_ops = {
445	.bus_shift	= 24,
446	.init		= thunder_pem_platform_init,
447	.pci_ops	= {
448		.map_bus	= pci_ecam_map_bus,
449		.read		= thunder_pem_config_read,
450		.write		= thunder_pem_config_write,
451	}
452};
453
454static const struct of_device_id thunder_pem_of_match[] = {
455	{
456		.compatible = "cavium,pci-host-thunder-pem",
457		.data = &pci_thunder_pem_ops,
458	},
459	{ },
460};
461
462static struct platform_driver thunder_pem_driver = {
463	.driver = {
464		.name = KBUILD_MODNAME,
465		.of_match_table = thunder_pem_of_match,
466		.suppress_bind_attrs = true,
467	},
468	.probe = pci_host_common_probe,
469};
470builtin_platform_driver(thunder_pem_driver);
471
472#endif
473#endif
474