1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCIe host controller driver for UniPhier SoCs
4 * Copyright 2018 Socionext Inc.
5 * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
6 */
7
8#include <linux/bitops.h>
9#include <linux/bitfield.h>
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/iopoll.h>
15#include <linux/irqchip/chained_irq.h>
16#include <linux/irqdomain.h>
17#include <linux/of_irq.h>
18#include <linux/pci.h>
19#include <linux/phy/phy.h>
20#include <linux/platform_device.h>
21#include <linux/reset.h>
22
23#include "pcie-designware.h"
24
25#define PCL_PINCTRL0			0x002c
26#define PCL_PERST_PLDN_REGEN		BIT(12)
27#define PCL_PERST_NOE_REGEN		BIT(11)
28#define PCL_PERST_OUT_REGEN		BIT(8)
29#define PCL_PERST_PLDN_REGVAL		BIT(4)
30#define PCL_PERST_NOE_REGVAL		BIT(3)
31#define PCL_PERST_OUT_REGVAL		BIT(0)
32
33#define PCL_PIPEMON			0x0044
34#define PCL_PCLK_ALIVE			BIT(15)
35
36#define PCL_MODE			0x8000
37#define PCL_MODE_REGEN			BIT(8)
38#define PCL_MODE_REGVAL			BIT(0)
39
40#define PCL_APP_READY_CTRL		0x8008
41#define PCL_APP_LTSSM_ENABLE		BIT(0)
42
43#define PCL_APP_PM0			0x8078
44#define PCL_SYS_AUX_PWR_DET		BIT(8)
45
46#define PCL_RCV_INT			0x8108
47#define PCL_RCV_INT_ALL_ENABLE		GENMASK(20, 17)
48#define PCL_CFG_BW_MGT_STATUS		BIT(4)
49#define PCL_CFG_LINK_AUTO_BW_STATUS	BIT(3)
50#define PCL_CFG_AER_RC_ERR_MSI_STATUS	BIT(2)
51#define PCL_CFG_PME_MSI_STATUS		BIT(1)
52
53#define PCL_RCV_INTX			0x810c
54#define PCL_RCV_INTX_ALL_ENABLE		GENMASK(19, 16)
55#define PCL_RCV_INTX_ALL_MASK		GENMASK(11, 8)
56#define PCL_RCV_INTX_MASK_SHIFT		8
57#define PCL_RCV_INTX_ALL_STATUS		GENMASK(3, 0)
58#define PCL_RCV_INTX_STATUS_SHIFT	0
59
60#define PCL_STATUS_LINK			0x8140
61#define PCL_RDLH_LINK_UP		BIT(1)
62#define PCL_XMLH_LINK_UP		BIT(0)
63
64struct uniphier_pcie_priv {
65	void __iomem *base;
66	struct dw_pcie pci;
67	struct clk *clk;
68	struct reset_control *rst;
69	struct phy *phy;
70	struct irq_domain *legacy_irq_domain;
71};
72
73#define to_uniphier_pcie(x)	dev_get_drvdata((x)->dev)
74
75static void uniphier_pcie_ltssm_enable(struct uniphier_pcie_priv *priv,
76				       bool enable)
77{
78	u32 val;
79
80	val = readl(priv->base + PCL_APP_READY_CTRL);
81	if (enable)
82		val |= PCL_APP_LTSSM_ENABLE;
83	else
84		val &= ~PCL_APP_LTSSM_ENABLE;
85	writel(val, priv->base + PCL_APP_READY_CTRL);
86}
87
88static void uniphier_pcie_init_rc(struct uniphier_pcie_priv *priv)
89{
90	u32 val;
91
92	/* set RC MODE */
93	val = readl(priv->base + PCL_MODE);
94	val |= PCL_MODE_REGEN;
95	val &= ~PCL_MODE_REGVAL;
96	writel(val, priv->base + PCL_MODE);
97
98	/* use auxiliary power detection */
99	val = readl(priv->base + PCL_APP_PM0);
100	val |= PCL_SYS_AUX_PWR_DET;
101	writel(val, priv->base + PCL_APP_PM0);
102
103	/* assert PERST# */
104	val = readl(priv->base + PCL_PINCTRL0);
105	val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL
106		 | PCL_PERST_PLDN_REGVAL);
107	val |= PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN
108		| PCL_PERST_PLDN_REGEN;
109	writel(val, priv->base + PCL_PINCTRL0);
110
111	uniphier_pcie_ltssm_enable(priv, false);
112
113	usleep_range(100000, 200000);
114
115	/* deassert PERST# */
116	val = readl(priv->base + PCL_PINCTRL0);
117	val |= PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN;
118	writel(val, priv->base + PCL_PINCTRL0);
119}
120
121static int uniphier_pcie_wait_rc(struct uniphier_pcie_priv *priv)
122{
123	u32 status;
124	int ret;
125
126	/* wait PIPE clock */
127	ret = readl_poll_timeout(priv->base + PCL_PIPEMON, status,
128				 status & PCL_PCLK_ALIVE, 100000, 1000000);
129	if (ret) {
130		dev_err(priv->pci.dev,
131			"Failed to initialize controller in RC mode\n");
132		return ret;
133	}
134
135	return 0;
136}
137
138static int uniphier_pcie_link_up(struct dw_pcie *pci)
139{
140	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
141	u32 val, mask;
142
143	val = readl(priv->base + PCL_STATUS_LINK);
144	mask = PCL_RDLH_LINK_UP | PCL_XMLH_LINK_UP;
145
146	return (val & mask) == mask;
147}
148
149static int uniphier_pcie_establish_link(struct dw_pcie *pci)
150{
151	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
152
153	if (dw_pcie_link_up(pci))
154		return 0;
155
156	uniphier_pcie_ltssm_enable(priv, true);
157
158	return dw_pcie_wait_for_link(pci);
159}
160
161static void uniphier_pcie_stop_link(struct dw_pcie *pci)
162{
163	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
164
165	uniphier_pcie_ltssm_enable(priv, false);
166}
167
168static void uniphier_pcie_irq_enable(struct uniphier_pcie_priv *priv)
169{
170	writel(PCL_RCV_INT_ALL_ENABLE, priv->base + PCL_RCV_INT);
171	writel(PCL_RCV_INTX_ALL_ENABLE, priv->base + PCL_RCV_INTX);
172}
173
174static void uniphier_pcie_irq_mask(struct irq_data *d)
175{
176	struct pcie_port *pp = irq_data_get_irq_chip_data(d);
177	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
178	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
179	unsigned long flags;
180	u32 val;
181
182	raw_spin_lock_irqsave(&pp->lock, flags);
183
184	val = readl(priv->base + PCL_RCV_INTX);
185	val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
186	writel(val, priv->base + PCL_RCV_INTX);
187
188	raw_spin_unlock_irqrestore(&pp->lock, flags);
189}
190
191static void uniphier_pcie_irq_unmask(struct irq_data *d)
192{
193	struct pcie_port *pp = irq_data_get_irq_chip_data(d);
194	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
195	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
196	unsigned long flags;
197	u32 val;
198
199	raw_spin_lock_irqsave(&pp->lock, flags);
200
201	val = readl(priv->base + PCL_RCV_INTX);
202	val &= ~BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
203	writel(val, priv->base + PCL_RCV_INTX);
204
205	raw_spin_unlock_irqrestore(&pp->lock, flags);
206}
207
208static struct irq_chip uniphier_pcie_irq_chip = {
209	.name = "PCI",
210	.irq_mask = uniphier_pcie_irq_mask,
211	.irq_unmask = uniphier_pcie_irq_unmask,
212};
213
214static int uniphier_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
215				  irq_hw_number_t hwirq)
216{
217	irq_set_chip_and_handler(irq, &uniphier_pcie_irq_chip,
218				 handle_level_irq);
219	irq_set_chip_data(irq, domain->host_data);
220
221	return 0;
222}
223
224static const struct irq_domain_ops uniphier_intx_domain_ops = {
225	.map = uniphier_pcie_intx_map,
226};
227
228static void uniphier_pcie_irq_handler(struct irq_desc *desc)
229{
230	struct pcie_port *pp = irq_desc_get_handler_data(desc);
231	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
232	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
233	struct irq_chip *chip = irq_desc_get_chip(desc);
234	unsigned long reg;
235	u32 val, bit, virq;
236
237	/* INT for debug */
238	val = readl(priv->base + PCL_RCV_INT);
239
240	if (val & PCL_CFG_BW_MGT_STATUS)
241		dev_dbg(pci->dev, "Link Bandwidth Management Event\n");
242	if (val & PCL_CFG_LINK_AUTO_BW_STATUS)
243		dev_dbg(pci->dev, "Link Autonomous Bandwidth Event\n");
244	if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS)
245		dev_dbg(pci->dev, "Root Error\n");
246	if (val & PCL_CFG_PME_MSI_STATUS)
247		dev_dbg(pci->dev, "PME Interrupt\n");
248
249	writel(val, priv->base + PCL_RCV_INT);
250
251	/* INTx */
252	chained_irq_enter(chip, desc);
253
254	val = readl(priv->base + PCL_RCV_INTX);
255	reg = FIELD_GET(PCL_RCV_INTX_ALL_STATUS, val);
256
257	for_each_set_bit(bit, &reg, PCI_NUM_INTX) {
258		virq = irq_linear_revmap(priv->legacy_irq_domain, bit);
259		generic_handle_irq(virq);
260	}
261
262	chained_irq_exit(chip, desc);
263}
264
265static int uniphier_pcie_config_legacy_irq(struct pcie_port *pp)
266{
267	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
268	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
269	struct device_node *np = pci->dev->of_node;
270	struct device_node *np_intc;
271	int ret = 0;
272
273	np_intc = of_get_child_by_name(np, "legacy-interrupt-controller");
274	if (!np_intc) {
275		dev_err(pci->dev, "Failed to get legacy-interrupt-controller node\n");
276		return -EINVAL;
277	}
278
279	pp->irq = irq_of_parse_and_map(np_intc, 0);
280	if (!pp->irq) {
281		dev_err(pci->dev, "Failed to get an IRQ entry in legacy-interrupt-controller\n");
282		ret = -EINVAL;
283		goto out_put_node;
284	}
285
286	priv->legacy_irq_domain = irq_domain_add_linear(np_intc, PCI_NUM_INTX,
287						&uniphier_intx_domain_ops, pp);
288	if (!priv->legacy_irq_domain) {
289		dev_err(pci->dev, "Failed to get INTx domain\n");
290		ret = -ENODEV;
291		goto out_put_node;
292	}
293
294	irq_set_chained_handler_and_data(pp->irq, uniphier_pcie_irq_handler,
295					 pp);
296
297out_put_node:
298	of_node_put(np_intc);
299	return ret;
300}
301
302static int uniphier_pcie_host_init(struct pcie_port *pp)
303{
304	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
305	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
306	int ret;
307
308	ret = uniphier_pcie_config_legacy_irq(pp);
309	if (ret)
310		return ret;
311
312	uniphier_pcie_irq_enable(priv);
313
314	dw_pcie_setup_rc(pp);
315	ret = uniphier_pcie_establish_link(pci);
316	if (ret)
317		return ret;
318
319	dw_pcie_msi_init(pp);
320
321	return 0;
322}
323
324static const struct dw_pcie_host_ops uniphier_pcie_host_ops = {
325	.host_init = uniphier_pcie_host_init,
326};
327
328static int uniphier_add_pcie_port(struct uniphier_pcie_priv *priv,
329				  struct platform_device *pdev)
330{
331	struct dw_pcie *pci = &priv->pci;
332	struct pcie_port *pp = &pci->pp;
333	struct device *dev = &pdev->dev;
334	int ret;
335
336	pp->ops = &uniphier_pcie_host_ops;
337
338	if (IS_ENABLED(CONFIG_PCI_MSI)) {
339		pp->msi_irq = platform_get_irq_byname(pdev, "msi");
340		if (pp->msi_irq < 0)
341			return pp->msi_irq;
342	}
343
344	ret = dw_pcie_host_init(pp);
345	if (ret) {
346		dev_err(dev, "Failed to initialize host (%d)\n", ret);
347		return ret;
348	}
349
350	return 0;
351}
352
353static int uniphier_pcie_host_enable(struct uniphier_pcie_priv *priv)
354{
355	int ret;
356
357	ret = clk_prepare_enable(priv->clk);
358	if (ret)
359		return ret;
360
361	ret = reset_control_deassert(priv->rst);
362	if (ret)
363		goto out_clk_disable;
364
365	uniphier_pcie_init_rc(priv);
366
367	ret = phy_init(priv->phy);
368	if (ret)
369		goto out_rst_assert;
370
371	ret = uniphier_pcie_wait_rc(priv);
372	if (ret)
373		goto out_phy_exit;
374
375	return 0;
376
377out_phy_exit:
378	phy_exit(priv->phy);
379out_rst_assert:
380	reset_control_assert(priv->rst);
381out_clk_disable:
382	clk_disable_unprepare(priv->clk);
383
384	return ret;
385}
386
387static const struct dw_pcie_ops dw_pcie_ops = {
388	.start_link = uniphier_pcie_establish_link,
389	.stop_link = uniphier_pcie_stop_link,
390	.link_up = uniphier_pcie_link_up,
391};
392
393static int uniphier_pcie_probe(struct platform_device *pdev)
394{
395	struct device *dev = &pdev->dev;
396	struct uniphier_pcie_priv *priv;
397	struct resource *res;
398	int ret;
399
400	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
401	if (!priv)
402		return -ENOMEM;
403
404	priv->pci.dev = dev;
405	priv->pci.ops = &dw_pcie_ops;
406
407	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
408	priv->pci.dbi_base = devm_pci_remap_cfg_resource(dev, res);
409	if (IS_ERR(priv->pci.dbi_base))
410		return PTR_ERR(priv->pci.dbi_base);
411
412	priv->base = devm_platform_ioremap_resource_byname(pdev, "link");
413	if (IS_ERR(priv->base))
414		return PTR_ERR(priv->base);
415
416	priv->clk = devm_clk_get(dev, NULL);
417	if (IS_ERR(priv->clk))
418		return PTR_ERR(priv->clk);
419
420	priv->rst = devm_reset_control_get_shared(dev, NULL);
421	if (IS_ERR(priv->rst))
422		return PTR_ERR(priv->rst);
423
424	priv->phy = devm_phy_optional_get(dev, "pcie-phy");
425	if (IS_ERR(priv->phy))
426		return PTR_ERR(priv->phy);
427
428	platform_set_drvdata(pdev, priv);
429
430	ret = uniphier_pcie_host_enable(priv);
431	if (ret)
432		return ret;
433
434	return uniphier_add_pcie_port(priv, pdev);
435}
436
437static const struct of_device_id uniphier_pcie_match[] = {
438	{ .compatible = "socionext,uniphier-pcie", },
439	{ /* sentinel */ },
440};
441
442static struct platform_driver uniphier_pcie_driver = {
443	.probe  = uniphier_pcie_probe,
444	.driver = {
445		.name = "uniphier-pcie",
446		.of_match_table = uniphier_pcie_match,
447	},
448};
449builtin_platform_driver(uniphier_pcie_driver);
450