1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCIe host controller driver for Amlogic MESON SoCs
4 *
5 * Copyright (c) 2018 Amlogic, inc.
6 * Author: Yue Wang <yue.wang@amlogic.com>
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/gpio/consumer.h>
12#include <linux/of_device.h>
13#include <linux/of_gpio.h>
14#include <linux/pci.h>
15#include <linux/platform_device.h>
16#include <linux/reset.h>
17#include <linux/resource.h>
18#include <linux/types.h>
19#include <linux/phy/phy.h>
20#include <linux/module.h>
21
22#include "pcie-designware.h"
23
24#define to_meson_pcie(x) dev_get_drvdata((x)->dev)
25
26#define PCIE_CAP_MAX_PAYLOAD_SIZE(x)	((x) << 5)
27#define PCIE_CAP_MAX_READ_REQ_SIZE(x)	((x) << 12)
28
29/* PCIe specific config registers */
30#define PCIE_CFG0			0x0
31#define APP_LTSSM_ENABLE		BIT(7)
32
33#define PCIE_CFG_STATUS12		0x30
34#define IS_SMLH_LINK_UP(x)		((x) & (1 << 6))
35#define IS_RDLH_LINK_UP(x)		((x) & (1 << 16))
36#define IS_LTSSM_UP(x)			((((x) >> 10) & 0x1f) == 0x11)
37
38#define PCIE_CFG_STATUS17		0x44
39#define PM_CURRENT_STATE(x)		(((x) >> 7) & 0x1)
40
41#define WAIT_LINKUP_TIMEOUT		4000
42#define PORT_CLK_RATE			100000000UL
43#define MAX_PAYLOAD_SIZE		256
44#define MAX_READ_REQ_SIZE		256
45#define PCIE_RESET_DELAY		500
46#define PCIE_SHARED_RESET		1
47#define PCIE_NORMAL_RESET		0
48
49enum pcie_data_rate {
50	PCIE_GEN1,
51	PCIE_GEN2,
52	PCIE_GEN3,
53	PCIE_GEN4
54};
55
56struct meson_pcie_clk_res {
57	struct clk *clk;
58	struct clk *port_clk;
59	struct clk *general_clk;
60};
61
62struct meson_pcie_rc_reset {
63	struct reset_control *port;
64	struct reset_control *apb;
65};
66
67struct meson_pcie {
68	struct dw_pcie pci;
69	void __iomem *cfg_base;
70	struct meson_pcie_clk_res clk_res;
71	struct meson_pcie_rc_reset mrst;
72	struct gpio_desc *reset_gpio;
73	struct phy *phy;
74};
75
76static struct reset_control *meson_pcie_get_reset(struct meson_pcie *mp,
77						  const char *id,
78						  u32 reset_type)
79{
80	struct device *dev = mp->pci.dev;
81	struct reset_control *reset;
82
83	if (reset_type == PCIE_SHARED_RESET)
84		reset = devm_reset_control_get_shared(dev, id);
85	else
86		reset = devm_reset_control_get(dev, id);
87
88	return reset;
89}
90
91static int meson_pcie_get_resets(struct meson_pcie *mp)
92{
93	struct meson_pcie_rc_reset *mrst = &mp->mrst;
94
95	mrst->port = meson_pcie_get_reset(mp, "port", PCIE_NORMAL_RESET);
96	if (IS_ERR(mrst->port))
97		return PTR_ERR(mrst->port);
98	reset_control_deassert(mrst->port);
99
100	mrst->apb = meson_pcie_get_reset(mp, "apb", PCIE_SHARED_RESET);
101	if (IS_ERR(mrst->apb))
102		return PTR_ERR(mrst->apb);
103	reset_control_deassert(mrst->apb);
104
105	return 0;
106}
107
108static int meson_pcie_get_mems(struct platform_device *pdev,
109			       struct meson_pcie *mp)
110{
111	struct dw_pcie *pci = &mp->pci;
112
113	pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "elbi");
114	if (IS_ERR(pci->dbi_base))
115		return PTR_ERR(pci->dbi_base);
116
117	mp->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
118	if (IS_ERR(mp->cfg_base))
119		return PTR_ERR(mp->cfg_base);
120
121	return 0;
122}
123
124static int meson_pcie_power_on(struct meson_pcie *mp)
125{
126	int ret = 0;
127
128	ret = phy_init(mp->phy);
129	if (ret)
130		return ret;
131
132	ret = phy_power_on(mp->phy);
133	if (ret) {
134		phy_exit(mp->phy);
135		return ret;
136	}
137
138	return 0;
139}
140
141static void meson_pcie_power_off(struct meson_pcie *mp)
142{
143	phy_power_off(mp->phy);
144	phy_exit(mp->phy);
145}
146
147static int meson_pcie_reset(struct meson_pcie *mp)
148{
149	struct meson_pcie_rc_reset *mrst = &mp->mrst;
150	int ret = 0;
151
152	ret = phy_reset(mp->phy);
153	if (ret)
154		return ret;
155
156	reset_control_assert(mrst->port);
157	reset_control_assert(mrst->apb);
158	udelay(PCIE_RESET_DELAY);
159	reset_control_deassert(mrst->port);
160	reset_control_deassert(mrst->apb);
161	udelay(PCIE_RESET_DELAY);
162
163	return 0;
164}
165
166static inline struct clk *meson_pcie_probe_clock(struct device *dev,
167						 const char *id, u64 rate)
168{
169	struct clk *clk;
170	int ret;
171
172	clk = devm_clk_get(dev, id);
173	if (IS_ERR(clk))
174		return clk;
175
176	if (rate) {
177		ret = clk_set_rate(clk, rate);
178		if (ret) {
179			dev_err(dev, "set clk rate failed, ret = %d\n", ret);
180			return ERR_PTR(ret);
181		}
182	}
183
184	ret = clk_prepare_enable(clk);
185	if (ret) {
186		dev_err(dev, "couldn't enable clk\n");
187		return ERR_PTR(ret);
188	}
189
190	devm_add_action_or_reset(dev,
191				 (void (*) (void *))clk_disable_unprepare,
192				 clk);
193
194	return clk;
195}
196
197static int meson_pcie_probe_clocks(struct meson_pcie *mp)
198{
199	struct device *dev = mp->pci.dev;
200	struct meson_pcie_clk_res *res = &mp->clk_res;
201
202	res->port_clk = meson_pcie_probe_clock(dev, "port", PORT_CLK_RATE);
203	if (IS_ERR(res->port_clk))
204		return PTR_ERR(res->port_clk);
205
206	res->general_clk = meson_pcie_probe_clock(dev, "general", 0);
207	if (IS_ERR(res->general_clk))
208		return PTR_ERR(res->general_clk);
209
210	res->clk = meson_pcie_probe_clock(dev, "pclk", 0);
211	if (IS_ERR(res->clk))
212		return PTR_ERR(res->clk);
213
214	return 0;
215}
216
217static inline u32 meson_cfg_readl(struct meson_pcie *mp, u32 reg)
218{
219	return readl(mp->cfg_base + reg);
220}
221
222static inline void meson_cfg_writel(struct meson_pcie *mp, u32 val, u32 reg)
223{
224	writel(val, mp->cfg_base + reg);
225}
226
227static void meson_pcie_assert_reset(struct meson_pcie *mp)
228{
229	gpiod_set_value_cansleep(mp->reset_gpio, 1);
230	udelay(500);
231	gpiod_set_value_cansleep(mp->reset_gpio, 0);
232}
233
234static void meson_pcie_init_dw(struct meson_pcie *mp)
235{
236	u32 val;
237
238	val = meson_cfg_readl(mp, PCIE_CFG0);
239	val |= APP_LTSSM_ENABLE;
240	meson_cfg_writel(mp, val, PCIE_CFG0);
241}
242
243static int meson_size_to_payload(struct meson_pcie *mp, int size)
244{
245	struct device *dev = mp->pci.dev;
246
247	/*
248	 * dwc supports 2^(val+7) payload size, which val is 0~5 default to 1.
249	 * So if input size is not 2^order alignment or less than 2^7 or bigger
250	 * than 2^12, just set to default size 2^(1+7).
251	 */
252	if (!is_power_of_2(size) || size < 128 || size > 4096) {
253		dev_warn(dev, "payload size %d, set to default 256\n", size);
254		return 1;
255	}
256
257	return fls(size) - 8;
258}
259
260static void meson_set_max_payload(struct meson_pcie *mp, int size)
261{
262	struct dw_pcie *pci = &mp->pci;
263	u32 val;
264	u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
265	int max_payload_size = meson_size_to_payload(mp, size);
266
267	val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
268	val &= ~PCI_EXP_DEVCTL_PAYLOAD;
269	dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
270
271	val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
272	val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size);
273	dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
274}
275
276static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size)
277{
278	struct dw_pcie *pci = &mp->pci;
279	u32 val;
280	u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
281	int max_rd_req_size = meson_size_to_payload(mp, size);
282
283	val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
284	val &= ~PCI_EXP_DEVCTL_READRQ;
285	dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
286
287	val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
288	val |= PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size);
289	dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
290}
291
292static int meson_pcie_establish_link(struct meson_pcie *mp)
293{
294	struct dw_pcie *pci = &mp->pci;
295	struct pcie_port *pp = &pci->pp;
296
297	meson_pcie_init_dw(mp);
298	meson_set_max_payload(mp, MAX_PAYLOAD_SIZE);
299	meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE);
300
301	dw_pcie_setup_rc(pp);
302
303	meson_pcie_assert_reset(mp);
304
305	return dw_pcie_wait_for_link(pci);
306}
307
308static int meson_pcie_rd_own_conf(struct pci_bus *bus, u32 devfn,
309				  int where, int size, u32 *val)
310{
311	int ret;
312
313	ret = pci_generic_config_read(bus, devfn, where, size, val);
314	if (ret != PCIBIOS_SUCCESSFUL)
315		return ret;
316
317	/*
318	 * There is a bug in the MESON AXG PCIe controller whereby software
319	 * cannot program the PCI_CLASS_DEVICE register, so we must fabricate
320	 * the return value in the config accessors.
321	 */
322	if (where == PCI_CLASS_REVISION && size == 4)
323		*val = (PCI_CLASS_BRIDGE_PCI << 16) | (*val & 0xffff);
324	else if (where == PCI_CLASS_DEVICE && size == 2)
325		*val = PCI_CLASS_BRIDGE_PCI;
326	else if (where == PCI_CLASS_DEVICE && size == 1)
327		*val = PCI_CLASS_BRIDGE_PCI & 0xff;
328	else if (where == PCI_CLASS_DEVICE + 1 && size == 1)
329		*val = (PCI_CLASS_BRIDGE_PCI >> 8) & 0xff;
330
331	return PCIBIOS_SUCCESSFUL;
332}
333
334static struct pci_ops meson_pci_ops = {
335	.map_bus = dw_pcie_own_conf_map_bus,
336	.read = meson_pcie_rd_own_conf,
337	.write = pci_generic_config_write,
338};
339
340static int meson_pcie_link_up(struct dw_pcie *pci)
341{
342	struct meson_pcie *mp = to_meson_pcie(pci);
343	struct device *dev = pci->dev;
344	u32 speed_okay = 0;
345	u32 cnt = 0;
346	u32 state12, state17, smlh_up, ltssm_up, rdlh_up;
347
348	do {
349		state12 = meson_cfg_readl(mp, PCIE_CFG_STATUS12);
350		state17 = meson_cfg_readl(mp, PCIE_CFG_STATUS17);
351		smlh_up = IS_SMLH_LINK_UP(state12);
352		rdlh_up = IS_RDLH_LINK_UP(state12);
353		ltssm_up = IS_LTSSM_UP(state12);
354
355		if (PM_CURRENT_STATE(state17) < PCIE_GEN3)
356			speed_okay = 1;
357
358		if (smlh_up)
359			dev_dbg(dev, "smlh_link_up is on\n");
360		if (rdlh_up)
361			dev_dbg(dev, "rdlh_link_up is on\n");
362		if (ltssm_up)
363			dev_dbg(dev, "ltssm_up is on\n");
364		if (speed_okay)
365			dev_dbg(dev, "speed_okay\n");
366
367		if (smlh_up && rdlh_up && ltssm_up && speed_okay)
368			return 1;
369
370		cnt++;
371
372		udelay(10);
373	} while (cnt < WAIT_LINKUP_TIMEOUT);
374
375	dev_err(dev, "error: wait linkup timeout\n");
376	return 0;
377}
378
379static int meson_pcie_host_init(struct pcie_port *pp)
380{
381	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
382	struct meson_pcie *mp = to_meson_pcie(pci);
383	int ret;
384
385	pp->bridge->ops = &meson_pci_ops;
386
387	ret = meson_pcie_establish_link(mp);
388	if (ret)
389		return ret;
390
391	dw_pcie_msi_init(pp);
392
393	return 0;
394}
395
396static const struct dw_pcie_host_ops meson_pcie_host_ops = {
397	.host_init = meson_pcie_host_init,
398};
399
400static int meson_add_pcie_port(struct meson_pcie *mp,
401			       struct platform_device *pdev)
402{
403	struct dw_pcie *pci = &mp->pci;
404	struct pcie_port *pp = &pci->pp;
405	struct device *dev = &pdev->dev;
406	int ret;
407
408	if (IS_ENABLED(CONFIG_PCI_MSI)) {
409		pp->msi_irq = platform_get_irq(pdev, 0);
410		if (pp->msi_irq < 0)
411			return pp->msi_irq;
412	}
413
414	pp->ops = &meson_pcie_host_ops;
415
416	ret = dw_pcie_host_init(pp);
417	if (ret) {
418		dev_err(dev, "failed to initialize host\n");
419		return ret;
420	}
421
422	return 0;
423}
424
425static const struct dw_pcie_ops dw_pcie_ops = {
426	.link_up = meson_pcie_link_up,
427};
428
429static int meson_pcie_probe(struct platform_device *pdev)
430{
431	struct device *dev = &pdev->dev;
432	struct dw_pcie *pci;
433	struct meson_pcie *mp;
434	int ret;
435
436	mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL);
437	if (!mp)
438		return -ENOMEM;
439
440	pci = &mp->pci;
441	pci->dev = dev;
442	pci->ops = &dw_pcie_ops;
443	pci->num_lanes = 1;
444
445	mp->phy = devm_phy_get(dev, "pcie");
446	if (IS_ERR(mp->phy)) {
447		dev_err(dev, "get phy failed, %ld\n", PTR_ERR(mp->phy));
448		return PTR_ERR(mp->phy);
449	}
450
451	mp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
452	if (IS_ERR(mp->reset_gpio)) {
453		dev_err(dev, "get reset gpio failed\n");
454		return PTR_ERR(mp->reset_gpio);
455	}
456
457	ret = meson_pcie_get_resets(mp);
458	if (ret) {
459		dev_err(dev, "get reset resource failed, %d\n", ret);
460		return ret;
461	}
462
463	ret = meson_pcie_get_mems(pdev, mp);
464	if (ret) {
465		dev_err(dev, "get memory resource failed, %d\n", ret);
466		return ret;
467	}
468
469	ret = meson_pcie_power_on(mp);
470	if (ret) {
471		dev_err(dev, "phy power on failed, %d\n", ret);
472		return ret;
473	}
474
475	ret = meson_pcie_reset(mp);
476	if (ret) {
477		dev_err(dev, "reset failed, %d\n", ret);
478		goto err_phy;
479	}
480
481	ret = meson_pcie_probe_clocks(mp);
482	if (ret) {
483		dev_err(dev, "init clock resources failed, %d\n", ret);
484		goto err_phy;
485	}
486
487	platform_set_drvdata(pdev, mp);
488
489	ret = meson_add_pcie_port(mp, pdev);
490	if (ret < 0) {
491		dev_err(dev, "Add PCIe port failed, %d\n", ret);
492		goto err_phy;
493	}
494
495	return 0;
496
497err_phy:
498	meson_pcie_power_off(mp);
499	return ret;
500}
501
502static const struct of_device_id meson_pcie_of_match[] = {
503	{
504		.compatible = "amlogic,axg-pcie",
505	},
506	{
507		.compatible = "amlogic,g12a-pcie",
508	},
509	{},
510};
511MODULE_DEVICE_TABLE(of, meson_pcie_of_match);
512
513static struct platform_driver meson_pcie_driver = {
514	.probe = meson_pcie_probe,
515	.driver = {
516		.name = "meson-pcie",
517		.of_match_table = meson_pcie_of_match,
518	},
519};
520
521module_platform_driver(meson_pcie_driver);
522
523MODULE_AUTHOR("Yue Wang <yue.wang@amlogic.com>");
524MODULE_DESCRIPTION("Amlogic PCIe Controller driver");
525MODULE_LICENSE("GPL v2");
526