1// SPDX-License-Identifier: GPL-2.0 2/* 3 * PCIe host controller driver for Freescale i.MX6 SoCs 4 * 5 * Copyright (C) 2013 Kosagi 6 * https://www.kosagi.com 7 * 8 * Author: Sean Cross <xobs@kosagi.com> 9 */ 10 11#include <linux/bitfield.h> 12#include <linux/clk.h> 13#include <linux/delay.h> 14#include <linux/gpio.h> 15#include <linux/kernel.h> 16#include <linux/mfd/syscon.h> 17#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 18#include <linux/mfd/syscon/imx7-iomuxc-gpr.h> 19#include <linux/module.h> 20#include <linux/of_gpio.h> 21#include <linux/of_device.h> 22#include <linux/of_address.h> 23#include <linux/pci.h> 24#include <linux/platform_device.h> 25#include <linux/regmap.h> 26#include <linux/regulator/consumer.h> 27#include <linux/resource.h> 28#include <linux/signal.h> 29#include <linux/types.h> 30#include <linux/interrupt.h> 31#include <linux/reset.h> 32#include <linux/pm_domain.h> 33#include <linux/pm_runtime.h> 34 35#include "pcie-designware.h" 36 37#define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9) 38#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10) 39#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11) 40#define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8) 41#define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000 42 43#define to_imx6_pcie(x) dev_get_drvdata((x)->dev) 44 45enum imx6_pcie_variants { 46 IMX6Q, 47 IMX6SX, 48 IMX6QP, 49 IMX7D, 50 IMX8MQ, 51}; 52 53#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) 54#define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) 55#define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) 56 57struct imx6_pcie_drvdata { 58 enum imx6_pcie_variants variant; 59 u32 flags; 60 int dbi_length; 61}; 62 63struct imx6_pcie { 64 struct dw_pcie *pci; 65 int reset_gpio; 66 bool gpio_active_high; 67 struct clk *pcie_bus; 68 struct clk *pcie_phy; 69 struct clk *pcie_inbound_axi; 70 struct clk *pcie; 71 struct clk *pcie_aux; 72 struct regmap *iomuxc_gpr; 73 u32 controller_id; 74 struct reset_control *pciephy_reset; 75 struct reset_control *apps_reset; 76 struct reset_control *turnoff_reset; 77 u32 tx_deemph_gen1; 78 u32 tx_deemph_gen2_3p5db; 79 u32 tx_deemph_gen2_6db; 80 u32 tx_swing_full; 81 u32 tx_swing_low; 82 struct regulator *vpcie; 83 void __iomem *phy_base; 84 85 /* power domain for pcie */ 86 struct device *pd_pcie; 87 /* power domain for pcie phy */ 88 struct device *pd_pcie_phy; 89 const struct imx6_pcie_drvdata *drvdata; 90}; 91 92/* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ 93#define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200 94#define PHY_PLL_LOCK_WAIT_TIMEOUT (2000 * PHY_PLL_LOCK_WAIT_USLEEP_MAX) 95 96/* PCIe Port Logic registers (memory-mapped) */ 97#define PL_OFFSET 0x700 98 99#define PCIE_PHY_CTRL (PL_OFFSET + 0x114) 100#define PCIE_PHY_CTRL_DATA(x) FIELD_PREP(GENMASK(15, 0), (x)) 101#define PCIE_PHY_CTRL_CAP_ADR BIT(16) 102#define PCIE_PHY_CTRL_CAP_DAT BIT(17) 103#define PCIE_PHY_CTRL_WR BIT(18) 104#define PCIE_PHY_CTRL_RD BIT(19) 105 106#define PCIE_PHY_STAT (PL_OFFSET + 0x110) 107#define PCIE_PHY_STAT_ACK BIT(16) 108 109/* PHY registers (not memory-mapped) */ 110#define PCIE_PHY_ATEOVRD 0x10 111#define PCIE_PHY_ATEOVRD_EN BIT(2) 112#define PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT 0 113#define PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK 0x1 114 115#define PCIE_PHY_MPLL_OVRD_IN_LO 0x11 116#define PCIE_PHY_MPLL_MULTIPLIER_SHIFT 2 117#define PCIE_PHY_MPLL_MULTIPLIER_MASK 0x7f 118#define PCIE_PHY_MPLL_MULTIPLIER_OVRD BIT(9) 119 120#define PCIE_PHY_RX_ASIC_OUT 0x100D 121#define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0) 122 123/* iMX7 PCIe PHY registers */ 124#define PCIE_PHY_CMN_REG4 0x14 125/* These are probably the bits that *aren't* DCC_FB_EN */ 126#define PCIE_PHY_CMN_REG4_DCC_FB_EN 0x29 127 128#define PCIE_PHY_CMN_REG15 0x54 129#define PCIE_PHY_CMN_REG15_DLY_4 BIT(2) 130#define PCIE_PHY_CMN_REG15_PLL_PD BIT(5) 131#define PCIE_PHY_CMN_REG15_OVRD_PLL_PD BIT(7) 132 133#define PCIE_PHY_CMN_REG24 0x90 134#define PCIE_PHY_CMN_REG24_RX_EQ BIT(6) 135#define PCIE_PHY_CMN_REG24_RX_EQ_SEL BIT(3) 136 137#define PCIE_PHY_CMN_REG26 0x98 138#define PCIE_PHY_CMN_REG26_ATT_MODE 0xBC 139 140#define PHY_RX_OVRD_IN_LO 0x1005 141#define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5) 142#define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3) 143 144static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) 145{ 146 struct dw_pcie *pci = imx6_pcie->pci; 147 bool val; 148 u32 max_iterations = 10; 149 u32 wait_counter = 0; 150 151 do { 152 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT) & 153 PCIE_PHY_STAT_ACK; 154 wait_counter++; 155 156 if (val == exp_val) 157 return 0; 158 159 udelay(1); 160 } while (wait_counter < max_iterations); 161 162 return -ETIMEDOUT; 163} 164 165static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr) 166{ 167 struct dw_pcie *pci = imx6_pcie->pci; 168 u32 val; 169 int ret; 170 171 val = PCIE_PHY_CTRL_DATA(addr); 172 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 173 174 val |= PCIE_PHY_CTRL_CAP_ADR; 175 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 176 177 ret = pcie_phy_poll_ack(imx6_pcie, true); 178 if (ret) 179 return ret; 180 181 val = PCIE_PHY_CTRL_DATA(addr); 182 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 183 184 return pcie_phy_poll_ack(imx6_pcie, false); 185} 186 187/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ 188static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data) 189{ 190 struct dw_pcie *pci = imx6_pcie->pci; 191 u32 phy_ctl; 192 int ret; 193 194 ret = pcie_phy_wait_ack(imx6_pcie, addr); 195 if (ret) 196 return ret; 197 198 /* assert Read signal */ 199 phy_ctl = PCIE_PHY_CTRL_RD; 200 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl); 201 202 ret = pcie_phy_poll_ack(imx6_pcie, true); 203 if (ret) 204 return ret; 205 206 *data = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT); 207 208 /* deassert Read signal */ 209 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00); 210 211 return pcie_phy_poll_ack(imx6_pcie, false); 212} 213 214static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) 215{ 216 struct dw_pcie *pci = imx6_pcie->pci; 217 u32 var; 218 int ret; 219 220 /* write addr */ 221 /* cap addr */ 222 ret = pcie_phy_wait_ack(imx6_pcie, addr); 223 if (ret) 224 return ret; 225 226 var = PCIE_PHY_CTRL_DATA(data); 227 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 228 229 /* capture data */ 230 var |= PCIE_PHY_CTRL_CAP_DAT; 231 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 232 233 ret = pcie_phy_poll_ack(imx6_pcie, true); 234 if (ret) 235 return ret; 236 237 /* deassert cap data */ 238 var = PCIE_PHY_CTRL_DATA(data); 239 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 240 241 /* wait for ack de-assertion */ 242 ret = pcie_phy_poll_ack(imx6_pcie, false); 243 if (ret) 244 return ret; 245 246 /* assert wr signal */ 247 var = PCIE_PHY_CTRL_WR; 248 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 249 250 /* wait for ack */ 251 ret = pcie_phy_poll_ack(imx6_pcie, true); 252 if (ret) 253 return ret; 254 255 /* deassert wr signal */ 256 var = PCIE_PHY_CTRL_DATA(data); 257 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 258 259 /* wait for ack de-assertion */ 260 ret = pcie_phy_poll_ack(imx6_pcie, false); 261 if (ret) 262 return ret; 263 264 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0); 265 266 return 0; 267} 268 269static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie) 270{ 271 u16 tmp; 272 273 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) 274 return; 275 276 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); 277 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | 278 PHY_RX_OVRD_IN_LO_RX_PLL_EN); 279 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); 280 281 usleep_range(2000, 3000); 282 283 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); 284 tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | 285 PHY_RX_OVRD_IN_LO_RX_PLL_EN); 286 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); 287} 288 289#ifdef CONFIG_ARM 290/* Added for PCI abort handling */ 291static int imx6q_pcie_abort_handler(unsigned long addr, 292 unsigned int fsr, struct pt_regs *regs) 293{ 294 unsigned long pc = instruction_pointer(regs); 295 unsigned long instr = *(unsigned long *)pc; 296 int reg = (instr >> 12) & 15; 297 298 /* 299 * If the instruction being executed was a read, 300 * make it look like it read all-ones. 301 */ 302 if ((instr & 0x0c100000) == 0x04100000) { 303 unsigned long val; 304 305 if (instr & 0x00400000) 306 val = 255; 307 else 308 val = -1; 309 310 regs->uregs[reg] = val; 311 regs->ARM_pc += 4; 312 return 0; 313 } 314 315 if ((instr & 0x0e100090) == 0x00100090) { 316 regs->uregs[reg] = -1; 317 regs->ARM_pc += 4; 318 return 0; 319 } 320 321 return 1; 322} 323#endif 324 325static int imx6_pcie_attach_pd(struct device *dev) 326{ 327 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 328 struct device_link *link; 329 330 /* Do nothing when in a single power domain */ 331 if (dev->pm_domain) 332 return 0; 333 334 imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie"); 335 if (IS_ERR(imx6_pcie->pd_pcie)) 336 return PTR_ERR(imx6_pcie->pd_pcie); 337 /* Do nothing when power domain missing */ 338 if (!imx6_pcie->pd_pcie) 339 return 0; 340 link = device_link_add(dev, imx6_pcie->pd_pcie, 341 DL_FLAG_STATELESS | 342 DL_FLAG_PM_RUNTIME | 343 DL_FLAG_RPM_ACTIVE); 344 if (!link) { 345 dev_err(dev, "Failed to add device_link to pcie pd.\n"); 346 return -EINVAL; 347 } 348 349 imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy"); 350 if (IS_ERR(imx6_pcie->pd_pcie_phy)) 351 return PTR_ERR(imx6_pcie->pd_pcie_phy); 352 353 link = device_link_add(dev, imx6_pcie->pd_pcie_phy, 354 DL_FLAG_STATELESS | 355 DL_FLAG_PM_RUNTIME | 356 DL_FLAG_RPM_ACTIVE); 357 if (!link) { 358 dev_err(dev, "Failed to add device_link to pcie_phy pd.\n"); 359 return -EINVAL; 360 } 361 362 return 0; 363} 364 365static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) 366{ 367 struct device *dev = imx6_pcie->pci->dev; 368 369 switch (imx6_pcie->drvdata->variant) { 370 case IMX7D: 371 case IMX8MQ: 372 reset_control_assert(imx6_pcie->pciephy_reset); 373 reset_control_assert(imx6_pcie->apps_reset); 374 break; 375 case IMX6SX: 376 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 377 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 378 IMX6SX_GPR12_PCIE_TEST_POWERDOWN); 379 /* Force PCIe PHY reset */ 380 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, 381 IMX6SX_GPR5_PCIE_BTNRST_RESET, 382 IMX6SX_GPR5_PCIE_BTNRST_RESET); 383 break; 384 case IMX6QP: 385 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 386 IMX6Q_GPR1_PCIE_SW_RST, 387 IMX6Q_GPR1_PCIE_SW_RST); 388 break; 389 case IMX6Q: 390 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 391 IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); 392 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 393 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); 394 break; 395 } 396 397 if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) { 398 int ret = regulator_disable(imx6_pcie->vpcie); 399 400 if (ret) 401 dev_err(dev, "failed to disable vpcie regulator: %d\n", 402 ret); 403 } 404 405 /* Some boards don't have PCIe reset GPIO. */ 406 if (gpio_is_valid(imx6_pcie->reset_gpio)) 407 gpio_set_value_cansleep(imx6_pcie->reset_gpio, 408 imx6_pcie->gpio_active_high); 409} 410 411static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie) 412{ 413 WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ); 414 return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; 415} 416 417static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) 418{ 419 struct dw_pcie *pci = imx6_pcie->pci; 420 struct device *dev = pci->dev; 421 unsigned int offset; 422 int ret = 0; 423 424 switch (imx6_pcie->drvdata->variant) { 425 case IMX6SX: 426 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi); 427 if (ret) { 428 dev_err(dev, "unable to enable pcie_axi clock\n"); 429 break; 430 } 431 432 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 433 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); 434 break; 435 case IMX6QP: 436 case IMX6Q: 437 /* power up core phy and enable ref clock */ 438 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 439 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); 440 /* 441 * the async reset input need ref clock to sync internally, 442 * when the ref clock comes after reset, internal synced 443 * reset time is too short, cannot meet the requirement. 444 * add one ~10us delay here. 445 */ 446 usleep_range(10, 100); 447 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 448 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); 449 break; 450 case IMX7D: 451 break; 452 case IMX8MQ: 453 ret = clk_prepare_enable(imx6_pcie->pcie_aux); 454 if (ret) { 455 dev_err(dev, "unable to enable pcie_aux clock\n"); 456 break; 457 } 458 459 offset = imx6_pcie_grp_offset(imx6_pcie); 460 /* 461 * Set the over ride low and enabled 462 * make sure that REF_CLK is turned on. 463 */ 464 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, 465 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, 466 0); 467 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, 468 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, 469 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); 470 break; 471 } 472 473 return ret; 474} 475 476static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) 477{ 478 u32 val; 479 struct device *dev = imx6_pcie->pci->dev; 480 481 if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr, 482 IOMUXC_GPR22, val, 483 val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED, 484 PHY_PLL_LOCK_WAIT_USLEEP_MAX, 485 PHY_PLL_LOCK_WAIT_TIMEOUT)) 486 dev_err(dev, "PCIe PLL lock timeout\n"); 487} 488 489static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) 490{ 491 struct dw_pcie *pci = imx6_pcie->pci; 492 struct device *dev = pci->dev; 493 int ret; 494 495 if (imx6_pcie->vpcie && !regulator_is_enabled(imx6_pcie->vpcie)) { 496 ret = regulator_enable(imx6_pcie->vpcie); 497 if (ret) { 498 dev_err(dev, "failed to enable vpcie regulator: %d\n", 499 ret); 500 return; 501 } 502 } 503 504 ret = clk_prepare_enable(imx6_pcie->pcie_phy); 505 if (ret) { 506 dev_err(dev, "unable to enable pcie_phy clock\n"); 507 goto err_pcie_phy; 508 } 509 510 ret = clk_prepare_enable(imx6_pcie->pcie_bus); 511 if (ret) { 512 dev_err(dev, "unable to enable pcie_bus clock\n"); 513 goto err_pcie_bus; 514 } 515 516 ret = clk_prepare_enable(imx6_pcie->pcie); 517 if (ret) { 518 dev_err(dev, "unable to enable pcie clock\n"); 519 goto err_pcie; 520 } 521 522 ret = imx6_pcie_enable_ref_clk(imx6_pcie); 523 if (ret) { 524 dev_err(dev, "unable to enable pcie ref clock\n"); 525 goto err_ref_clk; 526 } 527 528 /* allow the clocks to stabilize */ 529 usleep_range(200, 500); 530 531 switch (imx6_pcie->drvdata->variant) { 532 case IMX8MQ: 533 reset_control_deassert(imx6_pcie->pciephy_reset); 534 break; 535 case IMX7D: 536 reset_control_deassert(imx6_pcie->pciephy_reset); 537 538 /* Workaround for ERR010728, failure of PCI-e PLL VCO to 539 * oscillate, especially when cold. This turns off "Duty-cycle 540 * Corrector" and other mysterious undocumented things. 541 */ 542 if (likely(imx6_pcie->phy_base)) { 543 /* De-assert DCC_FB_EN */ 544 writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, 545 imx6_pcie->phy_base + PCIE_PHY_CMN_REG4); 546 /* Assert RX_EQS and RX_EQS_SEL */ 547 writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL 548 | PCIE_PHY_CMN_REG24_RX_EQ, 549 imx6_pcie->phy_base + PCIE_PHY_CMN_REG24); 550 /* Assert ATT_MODE */ 551 writel(PCIE_PHY_CMN_REG26_ATT_MODE, 552 imx6_pcie->phy_base + PCIE_PHY_CMN_REG26); 553 } else { 554 dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); 555 } 556 557 imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie); 558 break; 559 case IMX6SX: 560 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, 561 IMX6SX_GPR5_PCIE_BTNRST_RESET, 0); 562 break; 563 case IMX6QP: 564 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 565 IMX6Q_GPR1_PCIE_SW_RST, 0); 566 567 usleep_range(200, 500); 568 break; 569 case IMX6Q: /* Nothing to do */ 570 break; 571 } 572 573 /* Some boards don't have PCIe reset GPIO. */ 574 if (gpio_is_valid(imx6_pcie->reset_gpio)) { 575 msleep(100); 576 gpio_set_value_cansleep(imx6_pcie->reset_gpio, 577 !imx6_pcie->gpio_active_high); 578 /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */ 579 msleep(100); 580 } 581 582 return; 583 584err_ref_clk: 585 clk_disable_unprepare(imx6_pcie->pcie); 586err_pcie: 587 clk_disable_unprepare(imx6_pcie->pcie_bus); 588err_pcie_bus: 589 clk_disable_unprepare(imx6_pcie->pcie_phy); 590err_pcie_phy: 591 if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) { 592 ret = regulator_disable(imx6_pcie->vpcie); 593 if (ret) 594 dev_err(dev, "failed to disable vpcie regulator: %d\n", 595 ret); 596 } 597} 598 599static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) 600{ 601 unsigned int mask, val; 602 603 if (imx6_pcie->drvdata->variant == IMX8MQ && 604 imx6_pcie->controller_id == 1) { 605 mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE; 606 val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, 607 PCI_EXP_TYPE_ROOT_PORT); 608 } else { 609 mask = IMX6Q_GPR12_DEVICE_TYPE; 610 val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, 611 PCI_EXP_TYPE_ROOT_PORT); 612 } 613 614 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val); 615} 616 617static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) 618{ 619 switch (imx6_pcie->drvdata->variant) { 620 case IMX8MQ: 621 /* 622 * TODO: Currently this code assumes external 623 * oscillator is being used 624 */ 625 regmap_update_bits(imx6_pcie->iomuxc_gpr, 626 imx6_pcie_grp_offset(imx6_pcie), 627 IMX8MQ_GPR_PCIE_REF_USE_PAD, 628 IMX8MQ_GPR_PCIE_REF_USE_PAD); 629 break; 630 case IMX7D: 631 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 632 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); 633 break; 634 case IMX6SX: 635 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 636 IMX6SX_GPR12_PCIE_RX_EQ_MASK, 637 IMX6SX_GPR12_PCIE_RX_EQ_2); 638 fallthrough; 639 default: 640 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 641 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); 642 643 /* configure constant input signal to the pcie ctrl and phy */ 644 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 645 IMX6Q_GPR12_LOS_LEVEL, 9 << 4); 646 647 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 648 IMX6Q_GPR8_TX_DEEMPH_GEN1, 649 imx6_pcie->tx_deemph_gen1 << 0); 650 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 651 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 652 imx6_pcie->tx_deemph_gen2_3p5db << 6); 653 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 654 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 655 imx6_pcie->tx_deemph_gen2_6db << 12); 656 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 657 IMX6Q_GPR8_TX_SWING_FULL, 658 imx6_pcie->tx_swing_full << 18); 659 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 660 IMX6Q_GPR8_TX_SWING_LOW, 661 imx6_pcie->tx_swing_low << 25); 662 break; 663 } 664 665 imx6_pcie_configure_type(imx6_pcie); 666} 667 668static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie) 669{ 670 unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy); 671 int mult, div; 672 u16 val; 673 674 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) 675 return 0; 676 677 switch (phy_rate) { 678 case 125000000: 679 /* 680 * The default settings of the MPLL are for a 125MHz input 681 * clock, so no need to reconfigure anything in that case. 682 */ 683 return 0; 684 case 100000000: 685 mult = 25; 686 div = 0; 687 break; 688 case 200000000: 689 mult = 25; 690 div = 1; 691 break; 692 default: 693 dev_err(imx6_pcie->pci->dev, 694 "Unsupported PHY reference clock rate %lu\n", phy_rate); 695 return -EINVAL; 696 } 697 698 pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val); 699 val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK << 700 PCIE_PHY_MPLL_MULTIPLIER_SHIFT); 701 val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT; 702 val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD; 703 pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val); 704 705 pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val); 706 val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK << 707 PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT); 708 val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT; 709 val |= PCIE_PHY_ATEOVRD_EN; 710 pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val); 711 712 return 0; 713} 714 715static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) 716{ 717 struct dw_pcie *pci = imx6_pcie->pci; 718 struct device *dev = pci->dev; 719 u32 tmp; 720 unsigned int retries; 721 722 for (retries = 0; retries < 200; retries++) { 723 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 724 /* Test if the speed change finished. */ 725 if (!(tmp & PORT_LOGIC_SPEED_CHANGE)) 726 return 0; 727 usleep_range(100, 1000); 728 } 729 730 dev_err(dev, "Speed change timeout\n"); 731 return -ETIMEDOUT; 732} 733 734static void imx6_pcie_ltssm_enable(struct device *dev) 735{ 736 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 737 738 switch (imx6_pcie->drvdata->variant) { 739 case IMX6Q: 740 case IMX6SX: 741 case IMX6QP: 742 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 743 IMX6Q_GPR12_PCIE_CTL_2, 744 IMX6Q_GPR12_PCIE_CTL_2); 745 break; 746 case IMX7D: 747 case IMX8MQ: 748 reset_control_deassert(imx6_pcie->apps_reset); 749 break; 750 } 751} 752 753static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) 754{ 755 struct dw_pcie *pci = imx6_pcie->pci; 756 struct device *dev = pci->dev; 757 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 758 u32 tmp; 759 int ret; 760 761 /* 762 * Force Gen1 operation when starting the link. In case the link is 763 * started in Gen2 mode, there is a possibility the devices on the 764 * bus will not be detected at all. This happens with PCIe switches. 765 */ 766 tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 767 tmp &= ~PCI_EXP_LNKCAP_SLS; 768 tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; 769 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); 770 771 /* Start LTSSM. */ 772 imx6_pcie_ltssm_enable(dev); 773 774 ret = dw_pcie_wait_for_link(pci); 775 if (ret) 776 goto err_reset_phy; 777 778 if (pci->link_gen == 2) { 779 /* Allow Gen2 mode after the link is up. */ 780 tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 781 tmp &= ~PCI_EXP_LNKCAP_SLS; 782 tmp |= PCI_EXP_LNKCAP_SLS_5_0GB; 783 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); 784 785 /* 786 * Start Directed Speed Change so the best possible 787 * speed both link partners support can be negotiated. 788 */ 789 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 790 tmp |= PORT_LOGIC_SPEED_CHANGE; 791 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); 792 793 if (imx6_pcie->drvdata->flags & 794 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) { 795 /* 796 * On i.MX7, DIRECT_SPEED_CHANGE behaves differently 797 * from i.MX6 family when no link speed transition 798 * occurs and we go Gen1 -> yep, Gen1. The difference 799 * is that, in such case, it will not be cleared by HW 800 * which will cause the following code to report false 801 * failure. 802 */ 803 804 ret = imx6_pcie_wait_for_speed_change(imx6_pcie); 805 if (ret) { 806 dev_err(dev, "Failed to bring link up!\n"); 807 goto err_reset_phy; 808 } 809 } 810 811 /* Make sure link training is finished as well! */ 812 ret = dw_pcie_wait_for_link(pci); 813 if (ret) { 814 dev_err(dev, "Failed to bring link up!\n"); 815 goto err_reset_phy; 816 } 817 } else { 818 dev_info(dev, "Link: Gen2 disabled\n"); 819 } 820 821 tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); 822 dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS); 823 return 0; 824 825err_reset_phy: 826 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", 827 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0), 828 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1)); 829 imx6_pcie_reset_phy(imx6_pcie); 830 return ret; 831} 832 833static int imx6_pcie_host_init(struct pcie_port *pp) 834{ 835 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 836 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 837 838 imx6_pcie_assert_core_reset(imx6_pcie); 839 imx6_pcie_init_phy(imx6_pcie); 840 imx6_pcie_deassert_core_reset(imx6_pcie); 841 imx6_setup_phy_mpll(imx6_pcie); 842 dw_pcie_setup_rc(pp); 843 imx6_pcie_establish_link(imx6_pcie); 844 dw_pcie_msi_init(pp); 845 846 return 0; 847} 848 849static const struct dw_pcie_host_ops imx6_pcie_host_ops = { 850 .host_init = imx6_pcie_host_init, 851}; 852 853static int imx6_add_pcie_port(struct imx6_pcie *imx6_pcie, 854 struct platform_device *pdev) 855{ 856 struct dw_pcie *pci = imx6_pcie->pci; 857 struct pcie_port *pp = &pci->pp; 858 struct device *dev = &pdev->dev; 859 int ret; 860 861 if (IS_ENABLED(CONFIG_PCI_MSI)) { 862 pp->msi_irq = platform_get_irq_byname(pdev, "msi"); 863 if (pp->msi_irq < 0) 864 return pp->msi_irq; 865 } 866 867 pp->ops = &imx6_pcie_host_ops; 868 869 ret = dw_pcie_host_init(pp); 870 if (ret) { 871 dev_err(dev, "failed to initialize host\n"); 872 return ret; 873 } 874 875 return 0; 876} 877 878static const struct dw_pcie_ops dw_pcie_ops = { 879 /* No special ops needed, but pcie-designware still expects this struct */ 880}; 881 882#ifdef CONFIG_PM_SLEEP 883static void imx6_pcie_ltssm_disable(struct device *dev) 884{ 885 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 886 887 switch (imx6_pcie->drvdata->variant) { 888 case IMX6SX: 889 case IMX6QP: 890 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 891 IMX6Q_GPR12_PCIE_CTL_2, 0); 892 break; 893 case IMX7D: 894 reset_control_assert(imx6_pcie->apps_reset); 895 break; 896 default: 897 dev_err(dev, "ltssm_disable not supported\n"); 898 } 899} 900 901static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) 902{ 903 struct device *dev = imx6_pcie->pci->dev; 904 905 /* Some variants have a turnoff reset in DT */ 906 if (imx6_pcie->turnoff_reset) { 907 reset_control_assert(imx6_pcie->turnoff_reset); 908 reset_control_deassert(imx6_pcie->turnoff_reset); 909 goto pm_turnoff_sleep; 910 } 911 912 /* Others poke directly at IOMUXC registers */ 913 switch (imx6_pcie->drvdata->variant) { 914 case IMX6SX: 915 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 916 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 917 IMX6SX_GPR12_PCIE_PM_TURN_OFF); 918 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 919 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0); 920 break; 921 default: 922 dev_err(dev, "PME_Turn_Off not implemented\n"); 923 return; 924 } 925 926 /* 927 * Components with an upstream port must respond to 928 * PME_Turn_Off with PME_TO_Ack but we can't check. 929 * 930 * The standard recommends a 1-10ms timeout after which to 931 * proceed anyway as if acks were received. 932 */ 933pm_turnoff_sleep: 934 usleep_range(1000, 10000); 935} 936 937static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) 938{ 939 clk_disable_unprepare(imx6_pcie->pcie); 940 clk_disable_unprepare(imx6_pcie->pcie_phy); 941 clk_disable_unprepare(imx6_pcie->pcie_bus); 942 943 switch (imx6_pcie->drvdata->variant) { 944 case IMX6SX: 945 clk_disable_unprepare(imx6_pcie->pcie_inbound_axi); 946 break; 947 case IMX7D: 948 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 949 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 950 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); 951 break; 952 case IMX8MQ: 953 clk_disable_unprepare(imx6_pcie->pcie_aux); 954 break; 955 default: 956 break; 957 } 958} 959 960static int imx6_pcie_suspend_noirq(struct device *dev) 961{ 962 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 963 964 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) 965 return 0; 966 967 imx6_pcie_pm_turnoff(imx6_pcie); 968 imx6_pcie_clk_disable(imx6_pcie); 969 imx6_pcie_ltssm_disable(dev); 970 971 return 0; 972} 973 974static int imx6_pcie_resume_noirq(struct device *dev) 975{ 976 int ret; 977 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 978 struct pcie_port *pp = &imx6_pcie->pci->pp; 979 980 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) 981 return 0; 982 983 imx6_pcie_assert_core_reset(imx6_pcie); 984 imx6_pcie_init_phy(imx6_pcie); 985 imx6_pcie_deassert_core_reset(imx6_pcie); 986 dw_pcie_setup_rc(pp); 987 988 ret = imx6_pcie_establish_link(imx6_pcie); 989 if (ret < 0) 990 dev_info(dev, "pcie link is down after resume.\n"); 991 992 return 0; 993} 994#endif 995 996static const struct dev_pm_ops imx6_pcie_pm_ops = { 997 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq, 998 imx6_pcie_resume_noirq) 999}; 1000 1001static int imx6_pcie_probe(struct platform_device *pdev) 1002{ 1003 struct device *dev = &pdev->dev; 1004 struct dw_pcie *pci; 1005 struct imx6_pcie *imx6_pcie; 1006 struct device_node *np; 1007 struct resource *dbi_base; 1008 struct device_node *node = dev->of_node; 1009 int ret; 1010 u16 val; 1011 1012 imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL); 1013 if (!imx6_pcie) 1014 return -ENOMEM; 1015 1016 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 1017 if (!pci) 1018 return -ENOMEM; 1019 1020 pci->dev = dev; 1021 pci->ops = &dw_pcie_ops; 1022 1023 imx6_pcie->pci = pci; 1024 imx6_pcie->drvdata = of_device_get_match_data(dev); 1025 1026 /* Find the PHY if one is defined, only imx7d uses it */ 1027 np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); 1028 if (np) { 1029 struct resource res; 1030 1031 ret = of_address_to_resource(np, 0, &res); 1032 if (ret) { 1033 dev_err(dev, "Unable to map PCIe PHY\n"); 1034 return ret; 1035 } 1036 imx6_pcie->phy_base = devm_ioremap_resource(dev, &res); 1037 if (IS_ERR(imx6_pcie->phy_base)) { 1038 dev_err(dev, "Unable to map PCIe PHY\n"); 1039 return PTR_ERR(imx6_pcie->phy_base); 1040 } 1041 } 1042 1043 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1044 pci->dbi_base = devm_ioremap_resource(dev, dbi_base); 1045 if (IS_ERR(pci->dbi_base)) 1046 return PTR_ERR(pci->dbi_base); 1047 1048 /* Fetch GPIOs */ 1049 imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0); 1050 imx6_pcie->gpio_active_high = of_property_read_bool(node, 1051 "reset-gpio-active-high"); 1052 if (gpio_is_valid(imx6_pcie->reset_gpio)) { 1053 ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio, 1054 imx6_pcie->gpio_active_high ? 1055 GPIOF_OUT_INIT_HIGH : 1056 GPIOF_OUT_INIT_LOW, 1057 "PCIe reset"); 1058 if (ret) { 1059 dev_err(dev, "unable to get reset gpio\n"); 1060 return ret; 1061 } 1062 } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) { 1063 return imx6_pcie->reset_gpio; 1064 } 1065 1066 /* Fetch clocks */ 1067 imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy"); 1068 if (IS_ERR(imx6_pcie->pcie_phy)) 1069 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_phy), 1070 "pcie_phy clock source missing or invalid\n"); 1071 1072 imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus"); 1073 if (IS_ERR(imx6_pcie->pcie_bus)) 1074 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_bus), 1075 "pcie_bus clock source missing or invalid\n"); 1076 1077 imx6_pcie->pcie = devm_clk_get(dev, "pcie"); 1078 if (IS_ERR(imx6_pcie->pcie)) 1079 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie), 1080 "pcie clock source missing or invalid\n"); 1081 1082 switch (imx6_pcie->drvdata->variant) { 1083 case IMX6SX: 1084 imx6_pcie->pcie_inbound_axi = devm_clk_get(dev, 1085 "pcie_inbound_axi"); 1086 if (IS_ERR(imx6_pcie->pcie_inbound_axi)) 1087 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_inbound_axi), 1088 "pcie_inbound_axi clock missing or invalid\n"); 1089 break; 1090 case IMX8MQ: 1091 imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux"); 1092 if (IS_ERR(imx6_pcie->pcie_aux)) 1093 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux), 1094 "pcie_aux clock source missing or invalid\n"); 1095 fallthrough; 1096 case IMX7D: 1097 if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) 1098 imx6_pcie->controller_id = 1; 1099 1100 imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, 1101 "pciephy"); 1102 if (IS_ERR(imx6_pcie->pciephy_reset)) { 1103 dev_err(dev, "Failed to get PCIEPHY reset control\n"); 1104 return PTR_ERR(imx6_pcie->pciephy_reset); 1105 } 1106 1107 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, 1108 "apps"); 1109 if (IS_ERR(imx6_pcie->apps_reset)) { 1110 dev_err(dev, "Failed to get PCIE APPS reset control\n"); 1111 return PTR_ERR(imx6_pcie->apps_reset); 1112 } 1113 break; 1114 default: 1115 break; 1116 } 1117 1118 /* Grab turnoff reset */ 1119 imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); 1120 if (IS_ERR(imx6_pcie->turnoff_reset)) { 1121 dev_err(dev, "Failed to get TURNOFF reset control\n"); 1122 return PTR_ERR(imx6_pcie->turnoff_reset); 1123 } 1124 1125 /* Grab GPR config register range */ 1126 imx6_pcie->iomuxc_gpr = 1127 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); 1128 if (IS_ERR(imx6_pcie->iomuxc_gpr)) { 1129 dev_err(dev, "unable to find iomuxc registers\n"); 1130 return PTR_ERR(imx6_pcie->iomuxc_gpr); 1131 } 1132 1133 /* Grab PCIe PHY Tx Settings */ 1134 if (of_property_read_u32(node, "fsl,tx-deemph-gen1", 1135 &imx6_pcie->tx_deemph_gen1)) 1136 imx6_pcie->tx_deemph_gen1 = 0; 1137 1138 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db", 1139 &imx6_pcie->tx_deemph_gen2_3p5db)) 1140 imx6_pcie->tx_deemph_gen2_3p5db = 0; 1141 1142 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db", 1143 &imx6_pcie->tx_deemph_gen2_6db)) 1144 imx6_pcie->tx_deemph_gen2_6db = 20; 1145 1146 if (of_property_read_u32(node, "fsl,tx-swing-full", 1147 &imx6_pcie->tx_swing_full)) 1148 imx6_pcie->tx_swing_full = 127; 1149 1150 if (of_property_read_u32(node, "fsl,tx-swing-low", 1151 &imx6_pcie->tx_swing_low)) 1152 imx6_pcie->tx_swing_low = 127; 1153 1154 /* Limit link speed */ 1155 pci->link_gen = 1; 1156 ret = of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen); 1157 1158 imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie"); 1159 if (IS_ERR(imx6_pcie->vpcie)) { 1160 if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV) 1161 return PTR_ERR(imx6_pcie->vpcie); 1162 imx6_pcie->vpcie = NULL; 1163 } 1164 1165 platform_set_drvdata(pdev, imx6_pcie); 1166 1167 ret = imx6_pcie_attach_pd(dev); 1168 if (ret) 1169 return ret; 1170 1171 ret = imx6_add_pcie_port(imx6_pcie, pdev); 1172 if (ret < 0) 1173 return ret; 1174 1175 if (pci_msi_enabled()) { 1176 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); 1177 val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); 1178 val |= PCI_MSI_FLAGS_ENABLE; 1179 dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val); 1180 } 1181 1182 return 0; 1183} 1184 1185static void imx6_pcie_shutdown(struct platform_device *pdev) 1186{ 1187 struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev); 1188 1189 /* bring down link, so bootloader gets clean state in case of reboot */ 1190 imx6_pcie_assert_core_reset(imx6_pcie); 1191} 1192 1193static const struct imx6_pcie_drvdata drvdata[] = { 1194 [IMX6Q] = { 1195 .variant = IMX6Q, 1196 .flags = IMX6_PCIE_FLAG_IMX6_PHY | 1197 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE, 1198 .dbi_length = 0x200, 1199 }, 1200 [IMX6SX] = { 1201 .variant = IMX6SX, 1202 .flags = IMX6_PCIE_FLAG_IMX6_PHY | 1203 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | 1204 IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, 1205 }, 1206 [IMX6QP] = { 1207 .variant = IMX6QP, 1208 .flags = IMX6_PCIE_FLAG_IMX6_PHY | 1209 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE, 1210 }, 1211 [IMX7D] = { 1212 .variant = IMX7D, 1213 .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, 1214 }, 1215 [IMX8MQ] = { 1216 .variant = IMX8MQ, 1217 }, 1218}; 1219 1220static const struct of_device_id imx6_pcie_of_match[] = { 1221 { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], }, 1222 { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], }, 1223 { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], }, 1224 { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], }, 1225 { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], } , 1226 {}, 1227}; 1228 1229static struct platform_driver imx6_pcie_driver = { 1230 .driver = { 1231 .name = "imx6q-pcie", 1232 .of_match_table = imx6_pcie_of_match, 1233 .suppress_bind_attrs = true, 1234 .pm = &imx6_pcie_pm_ops, 1235 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1236 }, 1237 .probe = imx6_pcie_probe, 1238 .shutdown = imx6_pcie_shutdown, 1239}; 1240 1241static void imx6_pcie_quirk(struct pci_dev *dev) 1242{ 1243 struct pci_bus *bus = dev->bus; 1244 struct pcie_port *pp = bus->sysdata; 1245 1246 /* Bus parent is the PCI bridge, its parent is this platform driver */ 1247 if (!bus->dev.parent || !bus->dev.parent->parent) 1248 return; 1249 1250 /* Make sure we only quirk devices associated with this driver */ 1251 if (bus->dev.parent->parent->driver != &imx6_pcie_driver.driver) 1252 return; 1253 1254 if (pci_is_root_bus(bus)) { 1255 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 1256 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 1257 1258 /* 1259 * Limit config length to avoid the kernel reading beyond 1260 * the register set and causing an abort on i.MX 6Quad 1261 */ 1262 if (imx6_pcie->drvdata->dbi_length) { 1263 dev->cfg_size = imx6_pcie->drvdata->dbi_length; 1264 dev_info(&dev->dev, "Limiting cfg_size to %d\n", 1265 dev->cfg_size); 1266 } 1267 } 1268} 1269DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, 0xabcd, 1270 PCI_CLASS_BRIDGE_PCI, 8, imx6_pcie_quirk); 1271 1272static int __init imx6_pcie_init(void) 1273{ 1274#ifdef CONFIG_ARM 1275 struct device_node *np; 1276 1277 np = of_find_matching_node(NULL, imx6_pcie_of_match); 1278 if (!np) 1279 return -ENODEV; 1280 of_node_put(np); 1281 1282 /* 1283 * Since probe() can be deferred we need to make sure that 1284 * hook_fault_code is not called after __init memory is freed 1285 * by kernel and since imx6q_pcie_abort_handler() is a no-op, 1286 * we can install the handler here without risking it 1287 * accessing some uninitialized driver state. 1288 */ 1289 hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0, 1290 "external abort on non-linefetch"); 1291#endif 1292 1293 return platform_driver_register(&imx6_pcie_driver); 1294} 1295device_initcall(imx6_pcie_init); 1296