1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2017 Cadence 3// Cadence PCIe endpoint controller driver. 4// Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com> 5 6#include <linux/delay.h> 7#include <linux/kernel.h> 8#include <linux/of.h> 9#include <linux/pci-epc.h> 10#include <linux/platform_device.h> 11#include <linux/sizes.h> 12 13#include "pcie-cadence.h" 14 15#define CDNS_PCIE_EP_MIN_APERTURE 128 /* 128 bytes */ 16#define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE 0x1 17#define CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY 0x3 18 19static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, 20 struct pci_epf_header *hdr) 21{ 22 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); 23 struct cdns_pcie *pcie = &ep->pcie; 24 25 cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); 26 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid); 27 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code); 28 cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE, 29 hdr->subclass_code | hdr->baseclass_code << 8); 30 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE, 31 hdr->cache_line_size); 32 cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, hdr->subsys_id); 33 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, hdr->interrupt_pin); 34 35 /* 36 * Vendor ID can only be modified from function 0, all other functions 37 * use the same vendor ID as function 0. 38 */ 39 if (fn == 0) { 40 /* Update the vendor IDs. */ 41 u32 id = CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) | 42 CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id); 43 44 cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id); 45 } 46 47 return 0; 48} 49 50static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, 51 struct pci_epf_bar *epf_bar) 52{ 53 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); 54 struct cdns_pcie_epf *epf = &ep->epf[fn]; 55 struct cdns_pcie *pcie = &ep->pcie; 56 dma_addr_t bar_phys = epf_bar->phys_addr; 57 enum pci_barno bar = epf_bar->barno; 58 int flags = epf_bar->flags; 59 u32 addr0, addr1, reg, cfg, b, aperture, ctrl; 60 u64 sz; 61 62 /* BAR size is 2^(aperture + 7) */ 63 sz = max_t(size_t, epf_bar->size, CDNS_PCIE_EP_MIN_APERTURE); 64 /* 65 * roundup_pow_of_two() returns an unsigned long, which is not suited 66 * for 64bit values. 67 */ 68 sz = 1ULL << fls64(sz - 1); 69 aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */ 70 71 if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { 72 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS; 73 } else { 74 bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH); 75 bool is_64bits = sz > SZ_2G; 76 77 if (is_64bits && (bar & 1)) 78 return -EINVAL; 79 80 if (is_64bits && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64)) 81 epf_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64; 82 83 if (is_64bits && is_prefetch) 84 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS; 85 else if (is_prefetch) 86 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS; 87 else if (is_64bits) 88 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS; 89 else 90 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS; 91 } 92 93 addr0 = lower_32_bits(bar_phys); 94 addr1 = upper_32_bits(bar_phys); 95 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), 96 addr0); 97 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), 98 addr1); 99 100 if (bar < BAR_4) { 101 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn); 102 b = bar; 103 } else { 104 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn); 105 b = bar - BAR_4; 106 } 107 108 cfg = cdns_pcie_readl(pcie, reg); 109 cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | 110 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); 111 cfg |= (CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) | 112 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl)); 113 cdns_pcie_writel(pcie, reg, cfg); 114 115 epf->epf_bar[bar] = epf_bar; 116 117 return 0; 118} 119 120static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, 121 struct pci_epf_bar *epf_bar) 122{ 123 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); 124 struct cdns_pcie_epf *epf = &ep->epf[fn]; 125 struct cdns_pcie *pcie = &ep->pcie; 126 enum pci_barno bar = epf_bar->barno; 127 u32 reg, cfg, b, ctrl; 128 129 if (bar < BAR_4) { 130 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn); 131 b = bar; 132 } else { 133 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn); 134 b = bar - BAR_4; 135 } 136 137 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED; 138 cfg = cdns_pcie_readl(pcie, reg); 139 cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | 140 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); 141 cfg |= CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl); 142 cdns_pcie_writel(pcie, reg, cfg); 143 144 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), 0); 145 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), 0); 146 147 epf->epf_bar[bar] = NULL; 148} 149 150static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, phys_addr_t addr, 151 u64 pci_addr, size_t size) 152{ 153 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); 154 struct cdns_pcie *pcie = &ep->pcie; 155 u32 r; 156 157 r = find_first_zero_bit(&ep->ob_region_map, BITS_PER_LONG); 158 if (r >= ep->max_regions - 1) { 159 dev_err(&epc->dev, "no free outbound region\n"); 160 return -EINVAL; 161 } 162 163 cdns_pcie_set_outbound_region(pcie, 0, fn, r, false, addr, pci_addr, size); 164 165 set_bit(r, &ep->ob_region_map); 166 ep->ob_addr[r] = addr; 167 168 return 0; 169} 170 171static void cdns_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn, 172 phys_addr_t addr) 173{ 174 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); 175 struct cdns_pcie *pcie = &ep->pcie; 176 u32 r; 177 178 for (r = 0; r < ep->max_regions - 1; r++) 179 if (ep->ob_addr[r] == addr) 180 break; 181 182 if (r == ep->max_regions - 1) 183 return; 184 185 cdns_pcie_reset_outbound_region(pcie, r); 186 187 ep->ob_addr[r] = 0; 188 clear_bit(r, &ep->ob_region_map); 189} 190 191static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 mmc) 192{ 193 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); 194 struct cdns_pcie *pcie = &ep->pcie; 195 u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; 196 u16 flags; 197 198 /* 199 * Set the Multiple Message Capable bitfield into the Message Control 200 * register. 201 */ 202 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); 203 flags = (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1); 204 flags |= PCI_MSI_FLAGS_64BIT; 205 flags &= ~PCI_MSI_FLAGS_MASKBIT; 206 cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags); 207 208 return 0; 209} 210 211static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn) 212{ 213 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); 214 struct cdns_pcie *pcie = &ep->pcie; 215 u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; 216 u16 flags, mme; 217 218 /* Validate that the MSI feature is actually enabled. */ 219 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); 220 if (!(flags & PCI_MSI_FLAGS_ENABLE)) 221 return -EINVAL; 222 223 /* 224 * Get the Multiple Message Enable bitfield from the Message Control 225 * register. 226 */ 227 mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4; 228 229 return mme; 230} 231 232static int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no) 233{ 234 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); 235 struct cdns_pcie *pcie = &ep->pcie; 236 u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; 237 u32 val, reg; 238 239 reg = cap + PCI_MSIX_FLAGS; 240 val = cdns_pcie_ep_fn_readw(pcie, func_no, reg); 241 if (!(val & PCI_MSIX_FLAGS_ENABLE)) 242 return -EINVAL; 243 244 val &= PCI_MSIX_FLAGS_QSIZE; 245 246 return val; 247} 248 249static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u16 interrupts, 250 enum pci_barno bir, u32 offset) 251{ 252 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); 253 struct cdns_pcie *pcie = &ep->pcie; 254 u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; 255 u32 val, reg; 256 257 reg = cap + PCI_MSIX_FLAGS; 258 val = cdns_pcie_ep_fn_readw(pcie, fn, reg); 259 val &= ~PCI_MSIX_FLAGS_QSIZE; 260 val |= interrupts; 261 cdns_pcie_ep_fn_writew(pcie, fn, reg, val); 262 263 /* Set MSIX BAR and offset */ 264 reg = cap + PCI_MSIX_TABLE; 265 val = offset | bir; 266 cdns_pcie_ep_fn_writel(pcie, fn, reg, val); 267 268 /* Set PBA BAR and offset. BAR must match MSIX BAR */ 269 reg = cap + PCI_MSIX_PBA; 270 val = (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir; 271 cdns_pcie_ep_fn_writel(pcie, fn, reg, val); 272 273 return 0; 274} 275 276static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, 277 u8 intx, bool is_asserted) 278{ 279 struct cdns_pcie *pcie = &ep->pcie; 280 unsigned long flags; 281 u32 offset; 282 u16 status; 283 u8 msg_code; 284 285 intx &= 3; 286 287 /* Set the outbound region if needed. */ 288 if (unlikely(ep->irq_pci_addr != CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY || 289 ep->irq_pci_fn != fn)) { 290 /* First region was reserved for IRQ writes. */ 291 cdns_pcie_set_outbound_region_for_normal_msg(pcie, 0, fn, 0, 292 ep->irq_phys_addr); 293 ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY; 294 ep->irq_pci_fn = fn; 295 } 296 297 if (is_asserted) { 298 ep->irq_pending |= BIT(intx); 299 msg_code = MSG_CODE_ASSERT_INTA + intx; 300 } else { 301 ep->irq_pending &= ~BIT(intx); 302 msg_code = MSG_CODE_DEASSERT_INTA + intx; 303 } 304 305 spin_lock_irqsave(&ep->lock, flags); 306 status = cdns_pcie_ep_fn_readw(pcie, fn, PCI_STATUS); 307 if (((status & PCI_STATUS_INTERRUPT) != 0) ^ (ep->irq_pending != 0)) { 308 status ^= PCI_STATUS_INTERRUPT; 309 cdns_pcie_ep_fn_writew(pcie, fn, PCI_STATUS, status); 310 } 311 spin_unlock_irqrestore(&ep->lock, flags); 312 313 offset = CDNS_PCIE_NORMAL_MSG_ROUTING(MSG_ROUTING_LOCAL) | 314 CDNS_PCIE_NORMAL_MSG_CODE(msg_code) | 315 CDNS_PCIE_MSG_NO_DATA; 316 writel(0, ep->irq_cpu_addr + offset); 317} 318 319static int cdns_pcie_ep_send_legacy_irq(struct cdns_pcie_ep *ep, u8 fn, u8 intx) 320{ 321 u16 cmd; 322 323 cmd = cdns_pcie_ep_fn_readw(&ep->pcie, fn, PCI_COMMAND); 324 if (cmd & PCI_COMMAND_INTX_DISABLE) 325 return -EINVAL; 326 327 cdns_pcie_ep_assert_intx(ep, fn, intx, true); 328 /* 329 * The mdelay() value was taken from dra7xx_pcie_raise_legacy_irq() 330 */ 331 mdelay(1); 332 cdns_pcie_ep_assert_intx(ep, fn, intx, false); 333 return 0; 334} 335 336static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn, 337 u8 interrupt_num) 338{ 339 struct cdns_pcie *pcie = &ep->pcie; 340 u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; 341 u16 flags, mme, data, data_mask; 342 u8 msi_count; 343 u64 pci_addr, pci_addr_mask = 0xff; 344 345 /* Check whether the MSI feature has been enabled by the PCI host. */ 346 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); 347 if (!(flags & PCI_MSI_FLAGS_ENABLE)) 348 return -EINVAL; 349 350 /* Get the number of enabled MSIs */ 351 mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4; 352 msi_count = 1 << mme; 353 if (!interrupt_num || interrupt_num > msi_count) 354 return -EINVAL; 355 356 /* Compute the data value to be written. */ 357 data_mask = msi_count - 1; 358 data = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64); 359 data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask); 360 361 /* Get the PCI address where to write the data into. */ 362 pci_addr = cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI); 363 pci_addr <<= 32; 364 pci_addr |= cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO); 365 pci_addr &= GENMASK_ULL(63, 2); 366 367 /* Set the outbound region if needed. */ 368 if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) || 369 ep->irq_pci_fn != fn)) { 370 /* First region was reserved for IRQ writes. */ 371 cdns_pcie_set_outbound_region(pcie, 0, fn, 0, 372 false, 373 ep->irq_phys_addr, 374 pci_addr & ~pci_addr_mask, 375 pci_addr_mask + 1); 376 ep->irq_pci_addr = (pci_addr & ~pci_addr_mask); 377 ep->irq_pci_fn = fn; 378 } 379 writel(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask)); 380 381 return 0; 382} 383 384static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, 385 u16 interrupt_num) 386{ 387 u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; 388 u32 tbl_offset, msg_data, reg; 389 struct cdns_pcie *pcie = &ep->pcie; 390 struct pci_epf_msix_tbl *msix_tbl; 391 struct cdns_pcie_epf *epf; 392 u64 pci_addr_mask = 0xff; 393 u64 msg_addr; 394 u16 flags; 395 u8 bir; 396 397 /* Check whether the MSI-X feature has been enabled by the PCI host. */ 398 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSIX_FLAGS); 399 if (!(flags & PCI_MSIX_FLAGS_ENABLE)) 400 return -EINVAL; 401 402 reg = cap + PCI_MSIX_TABLE; 403 tbl_offset = cdns_pcie_ep_fn_readl(pcie, fn, reg); 404 bir = tbl_offset & PCI_MSIX_TABLE_BIR; 405 tbl_offset &= PCI_MSIX_TABLE_OFFSET; 406 407 epf = &ep->epf[fn]; 408 msix_tbl = epf->epf_bar[bir]->addr + tbl_offset; 409 msg_addr = msix_tbl[(interrupt_num - 1)].msg_addr; 410 msg_data = msix_tbl[(interrupt_num - 1)].msg_data; 411 412 /* Set the outbound region if needed. */ 413 if (ep->irq_pci_addr != (msg_addr & ~pci_addr_mask) || 414 ep->irq_pci_fn != fn) { 415 /* First region was reserved for IRQ writes. */ 416 cdns_pcie_set_outbound_region(pcie, 0, fn, 0, 417 false, 418 ep->irq_phys_addr, 419 msg_addr & ~pci_addr_mask, 420 pci_addr_mask + 1); 421 ep->irq_pci_addr = (msg_addr & ~pci_addr_mask); 422 ep->irq_pci_fn = fn; 423 } 424 writel(msg_data, ep->irq_cpu_addr + (msg_addr & pci_addr_mask)); 425 426 return 0; 427} 428 429static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, 430 enum pci_epc_irq_type type, 431 u16 interrupt_num) 432{ 433 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); 434 435 switch (type) { 436 case PCI_EPC_IRQ_LEGACY: 437 return cdns_pcie_ep_send_legacy_irq(ep, fn, 0); 438 439 case PCI_EPC_IRQ_MSI: 440 return cdns_pcie_ep_send_msi_irq(ep, fn, interrupt_num); 441 442 case PCI_EPC_IRQ_MSIX: 443 return cdns_pcie_ep_send_msix_irq(ep, fn, interrupt_num); 444 445 default: 446 break; 447 } 448 449 return -EINVAL; 450} 451 452static int cdns_pcie_ep_start(struct pci_epc *epc) 453{ 454 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); 455 struct cdns_pcie *pcie = &ep->pcie; 456 struct device *dev = pcie->dev; 457 struct pci_epf *epf; 458 u32 cfg; 459 int ret; 460 461 /* 462 * BIT(0) is hardwired to 1, hence function 0 is always enabled 463 * and can't be disabled anyway. 464 */ 465 cfg = BIT(0); 466 list_for_each_entry(epf, &epc->pci_epf, list) 467 cfg |= BIT(epf->func_no); 468 cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, cfg); 469 470 ret = cdns_pcie_start_link(pcie); 471 if (ret) { 472 dev_err(dev, "Failed to start link\n"); 473 return ret; 474 } 475 476 return 0; 477} 478 479static const struct pci_epc_features cdns_pcie_epc_features = { 480 .linkup_notifier = false, 481 .msi_capable = true, 482 .msix_capable = true, 483}; 484 485static const struct pci_epc_features* 486cdns_pcie_ep_get_features(struct pci_epc *epc, u8 func_no) 487{ 488 return &cdns_pcie_epc_features; 489} 490 491static const struct pci_epc_ops cdns_pcie_epc_ops = { 492 .write_header = cdns_pcie_ep_write_header, 493 .set_bar = cdns_pcie_ep_set_bar, 494 .clear_bar = cdns_pcie_ep_clear_bar, 495 .map_addr = cdns_pcie_ep_map_addr, 496 .unmap_addr = cdns_pcie_ep_unmap_addr, 497 .set_msi = cdns_pcie_ep_set_msi, 498 .get_msi = cdns_pcie_ep_get_msi, 499 .set_msix = cdns_pcie_ep_set_msix, 500 .get_msix = cdns_pcie_ep_get_msix, 501 .raise_irq = cdns_pcie_ep_raise_irq, 502 .start = cdns_pcie_ep_start, 503 .get_features = cdns_pcie_ep_get_features, 504}; 505 506 507int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) 508{ 509 struct device *dev = ep->pcie.dev; 510 struct platform_device *pdev = to_platform_device(dev); 511 struct device_node *np = dev->of_node; 512 struct cdns_pcie *pcie = &ep->pcie; 513 struct resource *res; 514 struct pci_epc *epc; 515 int ret; 516 517 pcie->is_rc = false; 518 519 pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg"); 520 if (IS_ERR(pcie->reg_base)) { 521 dev_err(dev, "missing \"reg\"\n"); 522 return PTR_ERR(pcie->reg_base); 523 } 524 525 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem"); 526 if (!res) { 527 dev_err(dev, "missing \"mem\"\n"); 528 return -EINVAL; 529 } 530 pcie->mem_res = res; 531 532 ret = of_property_read_u32(np, "cdns,max-outbound-regions", 533 &ep->max_regions); 534 if (ret < 0) { 535 dev_err(dev, "missing \"cdns,max-outbound-regions\"\n"); 536 return ret; 537 } 538 ep->ob_addr = devm_kcalloc(dev, 539 ep->max_regions, sizeof(*ep->ob_addr), 540 GFP_KERNEL); 541 if (!ep->ob_addr) 542 return -ENOMEM; 543 544 /* Disable all but function 0 (anyway BIT(0) is hardwired to 1). */ 545 cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, BIT(0)); 546 547 epc = devm_pci_epc_create(dev, &cdns_pcie_epc_ops); 548 if (IS_ERR(epc)) { 549 dev_err(dev, "failed to create epc device\n"); 550 return PTR_ERR(epc); 551 } 552 553 epc_set_drvdata(epc, ep); 554 555 if (of_property_read_u8(np, "max-functions", &epc->max_functions) < 0) 556 epc->max_functions = 1; 557 558 ep->epf = devm_kcalloc(dev, epc->max_functions, sizeof(*ep->epf), 559 GFP_KERNEL); 560 if (!ep->epf) 561 return -ENOMEM; 562 563 ret = pci_epc_mem_init(epc, pcie->mem_res->start, 564 resource_size(pcie->mem_res), PAGE_SIZE); 565 if (ret < 0) { 566 dev_err(dev, "failed to initialize the memory space\n"); 567 return ret; 568 } 569 570 ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, 571 SZ_128K); 572 if (!ep->irq_cpu_addr) { 573 dev_err(dev, "failed to reserve memory space for MSI\n"); 574 ret = -ENOMEM; 575 goto free_epc_mem; 576 } 577 ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE; 578 /* Reserve region 0 for IRQs */ 579 set_bit(0, &ep->ob_region_map); 580 581 if (ep->quirk_detect_quiet_flag) 582 cdns_pcie_detect_quiet_min_delay_set(&ep->pcie); 583 584 spin_lock_init(&ep->lock); 585 586 return 0; 587 588 free_epc_mem: 589 pci_epc_mem_exit(epc); 590 591 return ret; 592} 593