1// SPDX-License-Identifier: GPL-2.0
2/**
3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
4 *
5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 */
8
9#include <linux/delay.h>
10#include <linux/gpio/consumer.h>
11#include <linux/io.h>
12#include <linux/irqchip/chained_irq.h>
13#include <linux/irqdomain.h>
14#include <linux/mfd/syscon.h>
15#include <linux/of_device.h>
16#include <linux/of_irq.h>
17#include <linux/pci.h>
18#include <linux/pm_runtime.h>
19#include <linux/regmap.h>
20
21#include "../../pci.h"
22#include "pcie-cadence.h"
23
24#define ENABLE_REG_SYS_2	0x108
25#define STATUS_REG_SYS_2	0x508
26#define STATUS_CLR_REG_SYS_2	0x708
27#define LINK_DOWN		BIT(1)
28#define J7200_LINK_DOWN		BIT(10)
29
30#define J721E_PCIE_USER_CMD_STATUS	0x4
31#define LINK_TRAINING_ENABLE		BIT(0)
32
33#define J721E_PCIE_USER_LINKSTATUS	0x14
34#define LINK_STATUS			GENMASK(1, 0)
35
36enum link_status {
37	NO_RECEIVERS_DETECTED,
38	LINK_TRAINING_IN_PROGRESS,
39	LINK_UP_DL_IN_PROGRESS,
40	LINK_UP_DL_COMPLETED,
41};
42
43#define J721E_MODE_RC			BIT(7)
44#define LANE_COUNT_MASK			BIT(8)
45#define LANE_COUNT(n)			((n) << 8)
46
47#define GENERATION_SEL_MASK		GENMASK(1, 0)
48
49#define MAX_LANES			2
50
51struct j721e_pcie {
52	struct device		*dev;
53	u32			mode;
54	u32			num_lanes;
55	struct cdns_pcie	*cdns_pcie;
56	void __iomem		*user_cfg_base;
57	void __iomem		*intd_cfg_base;
58	u32			linkdown_irq_regfield;
59};
60
61enum j721e_pcie_mode {
62	PCI_MODE_RC,
63	PCI_MODE_EP,
64};
65
66struct j721e_pcie_data {
67	enum j721e_pcie_mode	mode;
68	unsigned int		quirk_retrain_flag:1;
69	unsigned int		quirk_detect_quiet_flag:1;
70	u32			linkdown_irq_regfield;
71	unsigned int		byte_access_allowed:1;
72};
73
74static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
75{
76	return readl(pcie->user_cfg_base + offset);
77}
78
79static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset,
80					  u32 value)
81{
82	writel(value, pcie->user_cfg_base + offset);
83}
84
85static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset)
86{
87	return readl(pcie->intd_cfg_base + offset);
88}
89
90static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset,
91					  u32 value)
92{
93	writel(value, pcie->intd_cfg_base + offset);
94}
95
96static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv)
97{
98	struct j721e_pcie *pcie = priv;
99	struct device *dev = pcie->dev;
100	u32 reg;
101
102	reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2);
103	if (!(reg & pcie->linkdown_irq_regfield))
104		return IRQ_NONE;
105
106	dev_err(dev, "LINK DOWN!\n");
107
108	j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, pcie->linkdown_irq_regfield);
109	return IRQ_HANDLED;
110}
111
112static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie)
113{
114	u32 reg;
115
116	reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2);
117	reg |= pcie->linkdown_irq_regfield;
118	j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg);
119}
120
121static int j721e_pcie_start_link(struct cdns_pcie *cdns_pcie)
122{
123	struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
124	u32 reg;
125
126	reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);
127	reg |= LINK_TRAINING_ENABLE;
128	j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);
129
130	return 0;
131}
132
133static void j721e_pcie_stop_link(struct cdns_pcie *cdns_pcie)
134{
135	struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
136	u32 reg;
137
138	reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);
139	reg &= ~LINK_TRAINING_ENABLE;
140	j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);
141}
142
143static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie)
144{
145	struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
146	u32 reg;
147
148	reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS);
149	reg &= LINK_STATUS;
150	if (reg == LINK_UP_DL_COMPLETED)
151		return true;
152
153	return false;
154}
155
156static const struct cdns_pcie_ops j721e_pcie_ops = {
157	.start_link = j721e_pcie_start_link,
158	.stop_link = j721e_pcie_stop_link,
159	.link_up = j721e_pcie_link_up,
160};
161
162static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon)
163{
164	struct device *dev = pcie->dev;
165	u32 mask = J721E_MODE_RC;
166	u32 mode = pcie->mode;
167	u32 val = 0;
168	int ret = 0;
169
170	if (mode == PCI_MODE_RC)
171		val = J721E_MODE_RC;
172
173	ret = regmap_update_bits(syscon, 0, mask, val);
174	if (ret)
175		dev_err(dev, "failed to set pcie mode\n");
176
177	return ret;
178}
179
180static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie,
181				     struct regmap *syscon)
182{
183	struct device *dev = pcie->dev;
184	struct device_node *np = dev->of_node;
185	int link_speed;
186	u32 val = 0;
187	int ret;
188
189	link_speed = of_pci_get_max_link_speed(np);
190	if (link_speed < 2)
191		link_speed = 2;
192
193	val = link_speed - 1;
194	ret = regmap_update_bits(syscon, 0, GENERATION_SEL_MASK, val);
195	if (ret)
196		dev_err(dev, "failed to set link speed\n");
197
198	return ret;
199}
200
201static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
202				     struct regmap *syscon)
203{
204	struct device *dev = pcie->dev;
205	u32 lanes = pcie->num_lanes;
206	u32 val = 0;
207	int ret;
208
209	val = LANE_COUNT(lanes - 1);
210	ret = regmap_update_bits(syscon, 0, LANE_COUNT_MASK, val);
211	if (ret)
212		dev_err(dev, "failed to set link count\n");
213
214	return ret;
215}
216
217static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie)
218{
219	struct device *dev = pcie->dev;
220	struct device_node *node = dev->of_node;
221	struct regmap *syscon;
222	int ret;
223
224	syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl");
225	if (IS_ERR(syscon)) {
226		dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n");
227		return PTR_ERR(syscon);
228	}
229
230	ret = j721e_pcie_set_mode(pcie, syscon);
231	if (ret < 0) {
232		dev_err(dev, "Failed to set pci mode\n");
233		return ret;
234	}
235
236	ret = j721e_pcie_set_link_speed(pcie, syscon);
237	if (ret < 0) {
238		dev_err(dev, "Failed to set link speed\n");
239		return ret;
240	}
241
242	ret = j721e_pcie_set_lane_count(pcie, syscon);
243	if (ret < 0) {
244		dev_err(dev, "Failed to set num-lanes\n");
245		return ret;
246	}
247
248	return 0;
249}
250
251static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
252				    int where, int size, u32 *value)
253{
254	if (pci_is_root_bus(bus))
255		return pci_generic_config_read32(bus, devfn, where, size,
256						 value);
257
258	return pci_generic_config_read(bus, devfn, where, size, value);
259}
260
261static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
262				     int where, int size, u32 value)
263{
264	if (pci_is_root_bus(bus))
265		return pci_generic_config_write32(bus, devfn, where, size,
266						  value);
267
268	return pci_generic_config_write(bus, devfn, where, size, value);
269}
270
271static struct pci_ops cdns_ti_pcie_host_ops = {
272	.map_bus	= cdns_pci_map_bus,
273	.read		= cdns_ti_pcie_config_read,
274	.write		= cdns_ti_pcie_config_write,
275};
276
277static const struct j721e_pcie_data j721e_pcie_rc_data = {
278	.mode = PCI_MODE_RC,
279	.quirk_retrain_flag = true,
280	.byte_access_allowed = false,
281	.linkdown_irq_regfield = LINK_DOWN,
282};
283
284static const struct j721e_pcie_data j721e_pcie_ep_data = {
285	.mode = PCI_MODE_EP,
286	.linkdown_irq_regfield = LINK_DOWN,
287};
288
289static const struct j721e_pcie_data j7200_pcie_rc_data = {
290	.mode = PCI_MODE_RC,
291	.quirk_detect_quiet_flag = true,
292	.linkdown_irq_regfield = J7200_LINK_DOWN,
293	.byte_access_allowed = true,
294};
295
296static const struct j721e_pcie_data j7200_pcie_ep_data = {
297	.mode = PCI_MODE_EP,
298	.quirk_detect_quiet_flag = true,
299};
300
301static const struct j721e_pcie_data am64_pcie_rc_data = {
302	.mode = PCI_MODE_RC,
303	.linkdown_irq_regfield = J7200_LINK_DOWN,
304	.byte_access_allowed = true,
305};
306
307static const struct j721e_pcie_data am64_pcie_ep_data = {
308	.mode = PCI_MODE_EP,
309	.linkdown_irq_regfield = J7200_LINK_DOWN,
310};
311
312static const struct of_device_id of_j721e_pcie_match[] = {
313	{
314		.compatible = "ti,j721e-pcie-host",
315		.data = &j721e_pcie_rc_data,
316	},
317	{
318		.compatible = "ti,j721e-pcie-ep",
319		.data = &j721e_pcie_ep_data,
320	},
321	{
322		.compatible = "ti,j7200-pcie-host",
323		.data = &j7200_pcie_rc_data,
324	},
325	{
326		.compatible = "ti,j7200-pcie-ep",
327		.data = &j7200_pcie_ep_data,
328	},
329	{
330		.compatible = "ti,am64-pcie-host",
331		.data = &am64_pcie_rc_data,
332	},
333	{
334		.compatible = "ti,am64-pcie-ep",
335		.data = &am64_pcie_ep_data,
336	},
337	{},
338};
339
340static int j721e_pcie_probe(struct platform_device *pdev)
341{
342	struct device *dev = &pdev->dev;
343	struct device_node *node = dev->of_node;
344	struct pci_host_bridge *bridge;
345	struct j721e_pcie_data *data;
346	struct cdns_pcie *cdns_pcie;
347	struct j721e_pcie *pcie;
348	struct cdns_pcie_rc *rc;
349	struct cdns_pcie_ep *ep;
350	struct gpio_desc *gpiod;
351	void __iomem *base;
352	u32 num_lanes;
353	u32 mode;
354	int ret;
355	int irq;
356
357	data = (struct j721e_pcie_data *)of_device_get_match_data(dev);
358	if (!data)
359		return -EINVAL;
360
361	mode = (u32)data->mode;
362
363	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
364	if (!pcie)
365		return -ENOMEM;
366
367	pcie->dev = dev;
368	pcie->mode = mode;
369	pcie->linkdown_irq_regfield = data->linkdown_irq_regfield;
370
371	base = devm_platform_ioremap_resource_byname(pdev, "intd_cfg");
372	if (IS_ERR(base))
373		return PTR_ERR(base);
374	pcie->intd_cfg_base = base;
375
376	base = devm_platform_ioremap_resource_byname(pdev, "user_cfg");
377	if (IS_ERR(base))
378		return PTR_ERR(base);
379	pcie->user_cfg_base = base;
380
381	ret = of_property_read_u32(node, "num-lanes", &num_lanes);
382	if (ret || num_lanes > MAX_LANES)
383		num_lanes = 1;
384	pcie->num_lanes = num_lanes;
385
386	if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
387		return -EINVAL;
388
389	irq = platform_get_irq_byname(pdev, "link_state");
390	if (irq < 0)
391		return irq;
392
393	dev_set_drvdata(dev, pcie);
394	pm_runtime_enable(dev);
395	ret = pm_runtime_get_sync(dev);
396	if (ret < 0) {
397		dev_err(dev, "pm_runtime_get_sync failed\n");
398		goto err_get_sync;
399	}
400
401	ret = j721e_pcie_ctrl_init(pcie);
402	if (ret < 0) {
403		dev_err(dev, "pm_runtime_get_sync failed\n");
404		goto err_get_sync;
405	}
406
407	ret = devm_request_irq(dev, irq, j721e_pcie_link_irq_handler, 0,
408			       "j721e-pcie-link-down-irq", pcie);
409	if (ret < 0) {
410		dev_err(dev, "failed to request link state IRQ %d\n", irq);
411		goto err_get_sync;
412	}
413
414	j721e_pcie_config_link_irq(pcie);
415
416	switch (mode) {
417	case PCI_MODE_RC:
418		if (!IS_ENABLED(CONFIG_PCIE_CADENCE_HOST)) {
419			ret = -ENODEV;
420			goto err_get_sync;
421		}
422
423		bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
424		if (!bridge) {
425			ret = -ENOMEM;
426			goto err_get_sync;
427		}
428
429		if (!data->byte_access_allowed)
430			bridge->ops = &cdns_ti_pcie_host_ops;
431		rc = pci_host_bridge_priv(bridge);
432		rc->quirk_retrain_flag = data->quirk_retrain_flag;
433		rc->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag;
434
435		cdns_pcie = &rc->pcie;
436		cdns_pcie->dev = dev;
437		cdns_pcie->ops = &j721e_pcie_ops;
438		pcie->cdns_pcie = cdns_pcie;
439
440		gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
441		if (IS_ERR(gpiod)) {
442			ret = PTR_ERR(gpiod);
443			if (ret != -EPROBE_DEFER)
444				dev_err(dev, "Failed to get reset GPIO\n");
445			goto err_get_sync;
446		}
447
448		ret = cdns_pcie_init_phy(dev, cdns_pcie);
449		if (ret) {
450			dev_err(dev, "Failed to init phy\n");
451			goto err_get_sync;
452		}
453
454		/*
455		 * "Power Sequencing and Reset Signal Timings" table in
456		 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0
457		 * indicates PERST# should be deasserted after minimum of 100us
458		 * once REFCLK is stable. The REFCLK to the connector in RC
459		 * mode is selected while enabling the PHY. So deassert PERST#
460		 * after 100 us.
461		 */
462		if (gpiod) {
463			usleep_range(100, 200);
464			gpiod_set_value_cansleep(gpiod, 1);
465		}
466
467		ret = cdns_pcie_host_setup(rc);
468		if (ret < 0)
469			goto err_pcie_setup;
470
471		break;
472	case PCI_MODE_EP:
473		if (!IS_ENABLED(CONFIG_PCIE_CADENCE_EP)) {
474			ret = -ENODEV;
475			goto err_get_sync;
476		}
477
478		ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
479		if (!ep) {
480			ret = -ENOMEM;
481			goto err_get_sync;
482		}
483		ep->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag;
484
485		cdns_pcie = &ep->pcie;
486		cdns_pcie->dev = dev;
487		cdns_pcie->ops = &j721e_pcie_ops;
488		pcie->cdns_pcie = cdns_pcie;
489
490		ret = cdns_pcie_init_phy(dev, cdns_pcie);
491		if (ret) {
492			dev_err(dev, "Failed to init phy\n");
493			goto err_get_sync;
494		}
495
496		ret = cdns_pcie_ep_setup(ep);
497		if (ret < 0)
498			goto err_pcie_setup;
499
500		break;
501	default:
502		dev_err(dev, "INVALID device type %d\n", mode);
503	}
504
505	return 0;
506
507err_pcie_setup:
508	cdns_pcie_disable_phy(cdns_pcie);
509
510err_get_sync:
511	pm_runtime_put(dev);
512	pm_runtime_disable(dev);
513
514	return ret;
515}
516
517static int j721e_pcie_remove(struct platform_device *pdev)
518{
519	struct j721e_pcie *pcie = platform_get_drvdata(pdev);
520	struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;
521	struct device *dev = &pdev->dev;
522
523	cdns_pcie_disable_phy(cdns_pcie);
524	pm_runtime_put(dev);
525	pm_runtime_disable(dev);
526
527	return 0;
528}
529
530static struct platform_driver j721e_pcie_driver = {
531	.probe  = j721e_pcie_probe,
532	.remove = j721e_pcie_remove,
533	.driver = {
534		.name	= "j721e-pcie",
535		.of_match_table = of_j721e_pcie_match,
536		.suppress_bind_attrs = true,
537	},
538};
539builtin_platform_driver(j721e_pcie_driver);
540