1// SPDX-License-Identifier: GPL-2.0 2#include <linux/pci.h> 3#include <linux/module.h> 4#include <linux/slab.h> 5#include <linux/ioport.h> 6#include <linux/wait.h> 7 8#include "pci.h" 9 10/* 11 * This interrupt-safe spinlock protects all accesses to PCI 12 * configuration space. 13 */ 14 15DEFINE_RAW_SPINLOCK(pci_lock); 16 17/* 18 * Wrappers for all PCI configuration access functions. They just check 19 * alignment, do locking and call the low-level functions pointed to 20 * by pci_dev->ops. 21 */ 22 23#define PCI_byte_BAD 0 24#define PCI_word_BAD (pos & 1) 25#define PCI_dword_BAD (pos & 3) 26 27#ifdef CONFIG_PCI_LOCKLESS_CONFIG 28# define pci_lock_config(f) do { (void)(f); } while (0) 29# define pci_unlock_config(f) do { (void)(f); } while (0) 30#else 31# define pci_lock_config(f) raw_spin_lock_irqsave(&pci_lock, f) 32# define pci_unlock_config(f) raw_spin_unlock_irqrestore(&pci_lock, f) 33#endif 34 35#define PCI_OP_READ(size, type, len) \ 36int noinline pci_bus_read_config_##size \ 37 (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \ 38{ \ 39 int res; \ 40 unsigned long flags; \ 41 u32 data = 0; \ 42 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ 43 pci_lock_config(flags); \ 44 res = bus->ops->read(bus, devfn, pos, len, &data); \ 45 *value = (type)data; \ 46 pci_unlock_config(flags); \ 47 return res; \ 48} 49 50#define PCI_OP_WRITE(size, type, len) \ 51int noinline pci_bus_write_config_##size \ 52 (struct pci_bus *bus, unsigned int devfn, int pos, type value) \ 53{ \ 54 int res; \ 55 unsigned long flags; \ 56 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ 57 pci_lock_config(flags); \ 58 res = bus->ops->write(bus, devfn, pos, len, value); \ 59 pci_unlock_config(flags); \ 60 return res; \ 61} 62 63PCI_OP_READ(byte, u8, 1) 64PCI_OP_READ(word, u16, 2) 65PCI_OP_READ(dword, u32, 4) 66PCI_OP_WRITE(byte, u8, 1) 67PCI_OP_WRITE(word, u16, 2) 68PCI_OP_WRITE(dword, u32, 4) 69 70EXPORT_SYMBOL(pci_bus_read_config_byte); 71EXPORT_SYMBOL(pci_bus_read_config_word); 72EXPORT_SYMBOL(pci_bus_read_config_dword); 73EXPORT_SYMBOL(pci_bus_write_config_byte); 74EXPORT_SYMBOL(pci_bus_write_config_word); 75EXPORT_SYMBOL(pci_bus_write_config_dword); 76 77int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 78 int where, int size, u32 *val) 79{ 80 void __iomem *addr; 81 82 addr = bus->ops->map_bus(bus, devfn, where); 83 if (!addr) { 84 *val = ~0; 85 return PCIBIOS_DEVICE_NOT_FOUND; 86 } 87 88 if (size == 1) 89 *val = readb(addr); 90 else if (size == 2) 91 *val = readw(addr); 92 else 93 *val = readl(addr); 94 95 return PCIBIOS_SUCCESSFUL; 96} 97EXPORT_SYMBOL_GPL(pci_generic_config_read); 98 99int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 100 int where, int size, u32 val) 101{ 102 void __iomem *addr; 103 104 addr = bus->ops->map_bus(bus, devfn, where); 105 if (!addr) 106 return PCIBIOS_DEVICE_NOT_FOUND; 107 108 if (size == 1) 109 writeb(val, addr); 110 else if (size == 2) 111 writew(val, addr); 112 else 113 writel(val, addr); 114 115 return PCIBIOS_SUCCESSFUL; 116} 117EXPORT_SYMBOL_GPL(pci_generic_config_write); 118 119int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 120 int where, int size, u32 *val) 121{ 122 void __iomem *addr; 123 124 addr = bus->ops->map_bus(bus, devfn, where & ~0x3); 125 if (!addr) { 126 *val = ~0; 127 return PCIBIOS_DEVICE_NOT_FOUND; 128 } 129 130 *val = readl(addr); 131 132 if (size <= 2) 133 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); 134 135 return PCIBIOS_SUCCESSFUL; 136} 137EXPORT_SYMBOL_GPL(pci_generic_config_read32); 138 139int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 140 int where, int size, u32 val) 141{ 142 void __iomem *addr; 143 u32 mask, tmp; 144 145 addr = bus->ops->map_bus(bus, devfn, where & ~0x3); 146 if (!addr) 147 return PCIBIOS_DEVICE_NOT_FOUND; 148 149 if (size == 4) { 150 writel(val, addr); 151 return PCIBIOS_SUCCESSFUL; 152 } 153 154 /* 155 * In general, hardware that supports only 32-bit writes on PCI is 156 * not spec-compliant. For example, software may perform a 16-bit 157 * write. If the hardware only supports 32-bit accesses, we must 158 * do a 32-bit read, merge in the 16 bits we intend to write, 159 * followed by a 32-bit write. If the 16 bits we *don't* intend to 160 * write happen to have any RW1C (write-one-to-clear) bits set, we 161 * just inadvertently cleared something we shouldn't have. 162 */ 163 if (!bus->unsafe_warn) { 164 dev_warn(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n", 165 size, pci_domain_nr(bus), bus->number, 166 PCI_SLOT(devfn), PCI_FUNC(devfn), where); 167 bus->unsafe_warn = 1; 168 } 169 170 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8)); 171 tmp = readl(addr) & mask; 172 tmp |= val << ((where & 0x3) * 8); 173 writel(tmp, addr); 174 175 return PCIBIOS_SUCCESSFUL; 176} 177EXPORT_SYMBOL_GPL(pci_generic_config_write32); 178 179/** 180 * pci_bus_set_ops - Set raw operations of pci bus 181 * @bus: pci bus struct 182 * @ops: new raw operations 183 * 184 * Return previous raw operations 185 */ 186struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops) 187{ 188 struct pci_ops *old_ops; 189 unsigned long flags; 190 191 raw_spin_lock_irqsave(&pci_lock, flags); 192 old_ops = bus->ops; 193 bus->ops = ops; 194 raw_spin_unlock_irqrestore(&pci_lock, flags); 195 return old_ops; 196} 197EXPORT_SYMBOL(pci_bus_set_ops); 198 199/* 200 * The following routines are to prevent the user from accessing PCI config 201 * space when it's unsafe to do so. Some devices require this during BIST and 202 * we're required to prevent it during D-state transitions. 203 * 204 * We have a bit per device to indicate it's blocked and a global wait queue 205 * for callers to sleep on until devices are unblocked. 206 */ 207static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait); 208 209static noinline void pci_wait_cfg(struct pci_dev *dev) 210 __must_hold(&pci_lock) 211{ 212 do { 213 raw_spin_unlock_irq(&pci_lock); 214 wait_event(pci_cfg_wait, !dev->block_cfg_access); 215 raw_spin_lock_irq(&pci_lock); 216 } while (dev->block_cfg_access); 217} 218 219/* Returns 0 on success, negative values indicate error. */ 220#define PCI_USER_READ_CONFIG(size, type) \ 221int pci_user_read_config_##size \ 222 (struct pci_dev *dev, int pos, type *val) \ 223{ \ 224 int ret = PCIBIOS_SUCCESSFUL; \ 225 u32 data = -1; \ 226 if (PCI_##size##_BAD) \ 227 return -EINVAL; \ 228 raw_spin_lock_irq(&pci_lock); \ 229 if (unlikely(dev->block_cfg_access)) \ 230 pci_wait_cfg(dev); \ 231 ret = dev->bus->ops->read(dev->bus, dev->devfn, \ 232 pos, sizeof(type), &data); \ 233 raw_spin_unlock_irq(&pci_lock); \ 234 *val = (type)data; \ 235 return pcibios_err_to_errno(ret); \ 236} \ 237EXPORT_SYMBOL_GPL(pci_user_read_config_##size); 238 239/* Returns 0 on success, negative values indicate error. */ 240#define PCI_USER_WRITE_CONFIG(size, type) \ 241int pci_user_write_config_##size \ 242 (struct pci_dev *dev, int pos, type val) \ 243{ \ 244 int ret = PCIBIOS_SUCCESSFUL; \ 245 if (PCI_##size##_BAD) \ 246 return -EINVAL; \ 247 raw_spin_lock_irq(&pci_lock); \ 248 if (unlikely(dev->block_cfg_access)) \ 249 pci_wait_cfg(dev); \ 250 ret = dev->bus->ops->write(dev->bus, dev->devfn, \ 251 pos, sizeof(type), val); \ 252 raw_spin_unlock_irq(&pci_lock); \ 253 return pcibios_err_to_errno(ret); \ 254} \ 255EXPORT_SYMBOL_GPL(pci_user_write_config_##size); 256 257PCI_USER_READ_CONFIG(byte, u8) 258PCI_USER_READ_CONFIG(word, u16) 259PCI_USER_READ_CONFIG(dword, u32) 260PCI_USER_WRITE_CONFIG(byte, u8) 261PCI_USER_WRITE_CONFIG(word, u16) 262PCI_USER_WRITE_CONFIG(dword, u32) 263 264/** 265 * pci_cfg_access_lock - Lock PCI config reads/writes 266 * @dev: pci device struct 267 * 268 * When access is locked, any userspace reads or writes to config 269 * space and concurrent lock requests will sleep until access is 270 * allowed via pci_cfg_access_unlock() again. 271 */ 272void pci_cfg_access_lock(struct pci_dev *dev) 273{ 274 might_sleep(); 275 276 raw_spin_lock_irq(&pci_lock); 277 if (dev->block_cfg_access) 278 pci_wait_cfg(dev); 279 dev->block_cfg_access = 1; 280 raw_spin_unlock_irq(&pci_lock); 281} 282EXPORT_SYMBOL_GPL(pci_cfg_access_lock); 283 284/** 285 * pci_cfg_access_trylock - try to lock PCI config reads/writes 286 * @dev: pci device struct 287 * 288 * Same as pci_cfg_access_lock, but will return 0 if access is 289 * already locked, 1 otherwise. This function can be used from 290 * atomic contexts. 291 */ 292bool pci_cfg_access_trylock(struct pci_dev *dev) 293{ 294 unsigned long flags; 295 bool locked = true; 296 297 raw_spin_lock_irqsave(&pci_lock, flags); 298 if (dev->block_cfg_access) 299 locked = false; 300 else 301 dev->block_cfg_access = 1; 302 raw_spin_unlock_irqrestore(&pci_lock, flags); 303 304 return locked; 305} 306EXPORT_SYMBOL_GPL(pci_cfg_access_trylock); 307 308/** 309 * pci_cfg_access_unlock - Unlock PCI config reads/writes 310 * @dev: pci device struct 311 * 312 * This function allows PCI config accesses to resume. 313 */ 314void pci_cfg_access_unlock(struct pci_dev *dev) 315{ 316 unsigned long flags; 317 318 raw_spin_lock_irqsave(&pci_lock, flags); 319 320 /* 321 * This indicates a problem in the caller, but we don't need 322 * to kill them, unlike a double-block above. 323 */ 324 WARN_ON(!dev->block_cfg_access); 325 326 dev->block_cfg_access = 0; 327 raw_spin_unlock_irqrestore(&pci_lock, flags); 328 329 wake_up_all(&pci_cfg_wait); 330} 331EXPORT_SYMBOL_GPL(pci_cfg_access_unlock); 332 333static inline int pcie_cap_version(const struct pci_dev *dev) 334{ 335 return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS; 336} 337 338bool pcie_cap_has_lnkctl(const struct pci_dev *dev) 339{ 340 int type = pci_pcie_type(dev); 341 342 return type == PCI_EXP_TYPE_ENDPOINT || 343 type == PCI_EXP_TYPE_LEG_END || 344 type == PCI_EXP_TYPE_ROOT_PORT || 345 type == PCI_EXP_TYPE_UPSTREAM || 346 type == PCI_EXP_TYPE_DOWNSTREAM || 347 type == PCI_EXP_TYPE_PCI_BRIDGE || 348 type == PCI_EXP_TYPE_PCIE_BRIDGE; 349} 350 351static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev) 352{ 353 return pcie_downstream_port(dev) && 354 pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT; 355} 356 357bool pcie_cap_has_rtctl(const struct pci_dev *dev) 358{ 359 int type = pci_pcie_type(dev); 360 361 return type == PCI_EXP_TYPE_ROOT_PORT || 362 type == PCI_EXP_TYPE_RC_EC; 363} 364 365static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 366{ 367 if (!pci_is_pcie(dev)) 368 return false; 369 370 switch (pos) { 371 case PCI_EXP_FLAGS: 372 return true; 373 case PCI_EXP_DEVCAP: 374 case PCI_EXP_DEVCTL: 375 case PCI_EXP_DEVSTA: 376 return true; 377 case PCI_EXP_LNKCAP: 378 case PCI_EXP_LNKCTL: 379 case PCI_EXP_LNKSTA: 380 return pcie_cap_has_lnkctl(dev); 381 case PCI_EXP_SLTCAP: 382 case PCI_EXP_SLTCTL: 383 case PCI_EXP_SLTSTA: 384 return pcie_cap_has_sltctl(dev); 385 case PCI_EXP_RTCTL: 386 case PCI_EXP_RTCAP: 387 case PCI_EXP_RTSTA: 388 return pcie_cap_has_rtctl(dev); 389 case PCI_EXP_DEVCAP2: 390 case PCI_EXP_DEVCTL2: 391 case PCI_EXP_LNKCAP2: 392 case PCI_EXP_LNKCTL2: 393 case PCI_EXP_LNKSTA2: 394 return pcie_cap_version(dev) > 1; 395 default: 396 return false; 397 } 398} 399 400/* 401 * Note that these accessor functions are only for the "PCI Express 402 * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the 403 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.) 404 */ 405int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val) 406{ 407 int ret; 408 409 *val = 0; 410 if (pos & 1) 411 return PCIBIOS_BAD_REGISTER_NUMBER; 412 413 if (pcie_capability_reg_implemented(dev, pos)) { 414 ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val); 415 /* 416 * Reset *val to 0 if pci_read_config_word() fails, it may 417 * have been written as 0xFFFF if hardware error happens 418 * during pci_read_config_word(). 419 */ 420 if (ret) 421 *val = 0; 422 return ret; 423 } 424 425 /* 426 * For Functions that do not implement the Slot Capabilities, 427 * Slot Status, and Slot Control registers, these spaces must 428 * be hardwired to 0b, with the exception of the Presence Detect 429 * State bit in the Slot Status register of Downstream Ports, 430 * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8) 431 */ 432 if (pci_is_pcie(dev) && pcie_downstream_port(dev) && 433 pos == PCI_EXP_SLTSTA) 434 *val = PCI_EXP_SLTSTA_PDS; 435 436 return 0; 437} 438EXPORT_SYMBOL(pcie_capability_read_word); 439 440int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val) 441{ 442 int ret; 443 444 *val = 0; 445 if (pos & 3) 446 return PCIBIOS_BAD_REGISTER_NUMBER; 447 448 if (pcie_capability_reg_implemented(dev, pos)) { 449 ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val); 450 /* 451 * Reset *val to 0 if pci_read_config_dword() fails, it may 452 * have been written as 0xFFFFFFFF if hardware error happens 453 * during pci_read_config_dword(). 454 */ 455 if (ret) 456 *val = 0; 457 return ret; 458 } 459 460 if (pci_is_pcie(dev) && pcie_downstream_port(dev) && 461 pos == PCI_EXP_SLTSTA) 462 *val = PCI_EXP_SLTSTA_PDS; 463 464 return 0; 465} 466EXPORT_SYMBOL(pcie_capability_read_dword); 467 468int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 469{ 470 if (pos & 1) 471 return PCIBIOS_BAD_REGISTER_NUMBER; 472 473 if (!pcie_capability_reg_implemented(dev, pos)) 474 return 0; 475 476 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 477} 478EXPORT_SYMBOL(pcie_capability_write_word); 479 480int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val) 481{ 482 if (pos & 3) 483 return PCIBIOS_BAD_REGISTER_NUMBER; 484 485 if (!pcie_capability_reg_implemented(dev, pos)) 486 return 0; 487 488 return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val); 489} 490EXPORT_SYMBOL(pcie_capability_write_dword); 491 492int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 493 u16 clear, u16 set) 494{ 495 int ret; 496 u16 val; 497 498 ret = pcie_capability_read_word(dev, pos, &val); 499 if (!ret) { 500 val &= ~clear; 501 val |= set; 502 ret = pcie_capability_write_word(dev, pos, val); 503 } 504 505 return ret; 506} 507EXPORT_SYMBOL(pcie_capability_clear_and_set_word); 508 509int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 510 u32 clear, u32 set) 511{ 512 int ret; 513 u32 val; 514 515 ret = pcie_capability_read_dword(dev, pos, &val); 516 if (!ret) { 517 val &= ~clear; 518 val |= set; 519 ret = pcie_capability_write_dword(dev, pos, val); 520 } 521 522 return ret; 523} 524EXPORT_SYMBOL(pcie_capability_clear_and_set_dword); 525 526int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val) 527{ 528 if (pci_dev_is_disconnected(dev)) { 529 *val = ~0; 530 return PCIBIOS_DEVICE_NOT_FOUND; 531 } 532 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); 533} 534EXPORT_SYMBOL(pci_read_config_byte); 535 536int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val) 537{ 538 if (pci_dev_is_disconnected(dev)) { 539 *val = ~0; 540 return PCIBIOS_DEVICE_NOT_FOUND; 541 } 542 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); 543} 544EXPORT_SYMBOL(pci_read_config_word); 545 546int pci_read_config_dword(const struct pci_dev *dev, int where, 547 u32 *val) 548{ 549 if (pci_dev_is_disconnected(dev)) { 550 *val = ~0; 551 return PCIBIOS_DEVICE_NOT_FOUND; 552 } 553 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); 554} 555EXPORT_SYMBOL(pci_read_config_dword); 556 557int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val) 558{ 559 if (pci_dev_is_disconnected(dev)) 560 return PCIBIOS_DEVICE_NOT_FOUND; 561 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); 562} 563EXPORT_SYMBOL(pci_write_config_byte); 564 565int pci_write_config_word(const struct pci_dev *dev, int where, u16 val) 566{ 567 if (pci_dev_is_disconnected(dev)) 568 return PCIBIOS_DEVICE_NOT_FOUND; 569 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); 570} 571EXPORT_SYMBOL(pci_write_config_word); 572 573int pci_write_config_dword(const struct pci_dev *dev, int where, 574 u32 val) 575{ 576 if (pci_dev_is_disconnected(dev)) 577 return PCIBIOS_DEVICE_NOT_FOUND; 578 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); 579} 580EXPORT_SYMBOL(pci_write_config_dword); 581