18c2ecf20Sopenharmony_ci# SPDX-License-Identifier: GPL-2.0
28c2ecf20Sopenharmony_ci#
38c2ecf20Sopenharmony_ci# PCI configuration
48c2ecf20Sopenharmony_ci#
58c2ecf20Sopenharmony_ci
68c2ecf20Sopenharmony_ci# select this to offer the PCI prompt
78c2ecf20Sopenharmony_ciconfig HAVE_PCI
88c2ecf20Sopenharmony_ci	bool
98c2ecf20Sopenharmony_ci
108c2ecf20Sopenharmony_ci# select this to unconditionally force on PCI support
118c2ecf20Sopenharmony_ciconfig FORCE_PCI
128c2ecf20Sopenharmony_ci	bool
138c2ecf20Sopenharmony_ci	select HAVE_PCI
148c2ecf20Sopenharmony_ci	select PCI
158c2ecf20Sopenharmony_ci
168c2ecf20Sopenharmony_cimenuconfig PCI
178c2ecf20Sopenharmony_ci	bool "PCI support"
188c2ecf20Sopenharmony_ci	depends on HAVE_PCI
198c2ecf20Sopenharmony_ci	help
208c2ecf20Sopenharmony_ci	  This option enables support for the PCI local bus, including
218c2ecf20Sopenharmony_ci	  support for PCI-X and the foundations for PCI Express support.
228c2ecf20Sopenharmony_ci	  Say 'Y' here unless you know what you are doing.
238c2ecf20Sopenharmony_ci
248c2ecf20Sopenharmony_ciif PCI
258c2ecf20Sopenharmony_ci
268c2ecf20Sopenharmony_ciconfig PCI_DOMAINS
278c2ecf20Sopenharmony_ci	bool
288c2ecf20Sopenharmony_ci	depends on PCI
298c2ecf20Sopenharmony_ci
308c2ecf20Sopenharmony_ciconfig PCI_DOMAINS_GENERIC
318c2ecf20Sopenharmony_ci	bool
328c2ecf20Sopenharmony_ci	select PCI_DOMAINS
338c2ecf20Sopenharmony_ci
348c2ecf20Sopenharmony_ciconfig PCI_SYSCALL
358c2ecf20Sopenharmony_ci	bool
368c2ecf20Sopenharmony_ci
378c2ecf20Sopenharmony_cisource "drivers/pci/pcie/Kconfig"
388c2ecf20Sopenharmony_ci
398c2ecf20Sopenharmony_ciconfig PCI_MSI
408c2ecf20Sopenharmony_ci	bool "Message Signaled Interrupts (MSI and MSI-X)"
418c2ecf20Sopenharmony_ci	select GENERIC_MSI_IRQ
428c2ecf20Sopenharmony_ci	help
438c2ecf20Sopenharmony_ci	   This allows device drivers to enable MSI (Message Signaled
448c2ecf20Sopenharmony_ci	   Interrupts).  Message Signaled Interrupts enable a device to
458c2ecf20Sopenharmony_ci	   generate an interrupt using an inbound Memory Write on its
468c2ecf20Sopenharmony_ci	   PCI bus instead of asserting a device IRQ pin.
478c2ecf20Sopenharmony_ci
488c2ecf20Sopenharmony_ci	   Use of PCI MSI interrupts can be disabled at kernel boot time
498c2ecf20Sopenharmony_ci	   by using the 'pci=nomsi' option.  This disables MSI for the
508c2ecf20Sopenharmony_ci	   entire system.
518c2ecf20Sopenharmony_ci
528c2ecf20Sopenharmony_ci	   If you don't know what to do here, say Y.
538c2ecf20Sopenharmony_ci
548c2ecf20Sopenharmony_ciconfig PCI_MSI_IRQ_DOMAIN
558c2ecf20Sopenharmony_ci	def_bool y
568c2ecf20Sopenharmony_ci	depends on PCI_MSI
578c2ecf20Sopenharmony_ci	select GENERIC_MSI_IRQ_DOMAIN
588c2ecf20Sopenharmony_ci
598c2ecf20Sopenharmony_ciconfig PCI_MSI_ARCH_FALLBACKS
608c2ecf20Sopenharmony_ci	bool
618c2ecf20Sopenharmony_ci
628c2ecf20Sopenharmony_ciconfig PCI_QUIRKS
638c2ecf20Sopenharmony_ci	default y
648c2ecf20Sopenharmony_ci	bool "Enable PCI quirk workarounds" if EXPERT
658c2ecf20Sopenharmony_ci	help
668c2ecf20Sopenharmony_ci	  This enables workarounds for various PCI chipset bugs/quirks.
678c2ecf20Sopenharmony_ci	  Disable this only if your target machine is unaffected by PCI
688c2ecf20Sopenharmony_ci	  quirks.
698c2ecf20Sopenharmony_ci
708c2ecf20Sopenharmony_ciconfig PCI_DEBUG
718c2ecf20Sopenharmony_ci	bool "PCI Debugging"
728c2ecf20Sopenharmony_ci	depends on DEBUG_KERNEL
738c2ecf20Sopenharmony_ci	help
748c2ecf20Sopenharmony_ci	  Say Y here if you want the PCI core to produce a bunch of debug
758c2ecf20Sopenharmony_ci	  messages to the system log.  Select this if you are having a
768c2ecf20Sopenharmony_ci	  problem with PCI support and want to see more of what is going on.
778c2ecf20Sopenharmony_ci
788c2ecf20Sopenharmony_ci	  When in doubt, say N.
798c2ecf20Sopenharmony_ci
808c2ecf20Sopenharmony_ciconfig PCI_REALLOC_ENABLE_AUTO
818c2ecf20Sopenharmony_ci	bool "Enable PCI resource re-allocation detection"
828c2ecf20Sopenharmony_ci	depends on PCI_IOV
838c2ecf20Sopenharmony_ci	help
848c2ecf20Sopenharmony_ci	  Say Y here if you want the PCI core to detect if PCI resource
858c2ecf20Sopenharmony_ci	  re-allocation needs to be enabled. You can always use pci=realloc=on
868c2ecf20Sopenharmony_ci	  or pci=realloc=off to override it.  It will automatically
878c2ecf20Sopenharmony_ci	  re-allocate PCI resources if SR-IOV BARs have not been allocated by
888c2ecf20Sopenharmony_ci	  the BIOS.
898c2ecf20Sopenharmony_ci
908c2ecf20Sopenharmony_ci	  When in doubt, say N.
918c2ecf20Sopenharmony_ci
928c2ecf20Sopenharmony_ciconfig PCI_STUB
938c2ecf20Sopenharmony_ci	tristate "PCI Stub driver"
948c2ecf20Sopenharmony_ci	help
958c2ecf20Sopenharmony_ci	  Say Y or M here if you want be able to reserve a PCI device
968c2ecf20Sopenharmony_ci	  when it is going to be assigned to a guest operating system.
978c2ecf20Sopenharmony_ci
988c2ecf20Sopenharmony_ci	  When in doubt, say N.
998c2ecf20Sopenharmony_ci
1008c2ecf20Sopenharmony_ciconfig PCI_PF_STUB
1018c2ecf20Sopenharmony_ci	tristate "PCI PF Stub driver"
1028c2ecf20Sopenharmony_ci	depends on PCI_IOV
1038c2ecf20Sopenharmony_ci	help
1048c2ecf20Sopenharmony_ci	  Say Y or M here if you want to enable support for devices that
1058c2ecf20Sopenharmony_ci	  require SR-IOV support, while at the same time the PF (Physical
1068c2ecf20Sopenharmony_ci	  Function) itself is not providing any actual services on the
1078c2ecf20Sopenharmony_ci	  host itself such as storage or networking.
1088c2ecf20Sopenharmony_ci
1098c2ecf20Sopenharmony_ci	  When in doubt, say N.
1108c2ecf20Sopenharmony_ci
1118c2ecf20Sopenharmony_ciconfig XEN_PCIDEV_FRONTEND
1128c2ecf20Sopenharmony_ci	tristate "Xen PCI Frontend"
1138c2ecf20Sopenharmony_ci	depends on X86 && XEN
1148c2ecf20Sopenharmony_ci	select PCI_XEN
1158c2ecf20Sopenharmony_ci	select XEN_XENBUS_FRONTEND
1168c2ecf20Sopenharmony_ci	default y
1178c2ecf20Sopenharmony_ci	help
1188c2ecf20Sopenharmony_ci	  The PCI device frontend driver allows the kernel to import arbitrary
1198c2ecf20Sopenharmony_ci	  PCI devices from a PCI backend to support PCI driver domains.
1208c2ecf20Sopenharmony_ci
1218c2ecf20Sopenharmony_ciconfig PCI_ATS
1228c2ecf20Sopenharmony_ci	bool
1238c2ecf20Sopenharmony_ci
1248c2ecf20Sopenharmony_ciconfig PCI_ECAM
1258c2ecf20Sopenharmony_ci	bool
1268c2ecf20Sopenharmony_ci
1278c2ecf20Sopenharmony_ciconfig PCI_LOCKLESS_CONFIG
1288c2ecf20Sopenharmony_ci	bool
1298c2ecf20Sopenharmony_ci
1308c2ecf20Sopenharmony_ciconfig PCI_BRIDGE_EMUL
1318c2ecf20Sopenharmony_ci	bool
1328c2ecf20Sopenharmony_ci
1338c2ecf20Sopenharmony_ciconfig PCI_IOV
1348c2ecf20Sopenharmony_ci	bool "PCI IOV support"
1358c2ecf20Sopenharmony_ci	select PCI_ATS
1368c2ecf20Sopenharmony_ci	help
1378c2ecf20Sopenharmony_ci	  I/O Virtualization is a PCI feature supported by some devices
1388c2ecf20Sopenharmony_ci	  which allows them to create virtual devices which share their
1398c2ecf20Sopenharmony_ci	  physical resources.
1408c2ecf20Sopenharmony_ci
1418c2ecf20Sopenharmony_ci	  If unsure, say N.
1428c2ecf20Sopenharmony_ci
1438c2ecf20Sopenharmony_ciconfig PCI_PRI
1448c2ecf20Sopenharmony_ci	bool "PCI PRI support"
1458c2ecf20Sopenharmony_ci	select PCI_ATS
1468c2ecf20Sopenharmony_ci	help
1478c2ecf20Sopenharmony_ci	  PRI is the PCI Page Request Interface. It allows PCI devices that are
1488c2ecf20Sopenharmony_ci	  behind an IOMMU to recover from page faults.
1498c2ecf20Sopenharmony_ci
1508c2ecf20Sopenharmony_ci	  If unsure, say N.
1518c2ecf20Sopenharmony_ci
1528c2ecf20Sopenharmony_ciconfig PCI_PASID
1538c2ecf20Sopenharmony_ci	bool "PCI PASID support"
1548c2ecf20Sopenharmony_ci	select PCI_ATS
1558c2ecf20Sopenharmony_ci	help
1568c2ecf20Sopenharmony_ci	  Process Address Space Identifiers (PASIDs) can be used by PCI devices
1578c2ecf20Sopenharmony_ci	  to access more than one IO address space at the same time. To make
1588c2ecf20Sopenharmony_ci	  use of this feature an IOMMU is required which also supports PASIDs.
1598c2ecf20Sopenharmony_ci	  Select this option if you have such an IOMMU and want to compile the
1608c2ecf20Sopenharmony_ci	  driver for it into your kernel.
1618c2ecf20Sopenharmony_ci
1628c2ecf20Sopenharmony_ci	  If unsure, say N.
1638c2ecf20Sopenharmony_ci
1648c2ecf20Sopenharmony_ciconfig PCI_P2PDMA
1658c2ecf20Sopenharmony_ci	bool "PCI peer-to-peer transfer support"
1668c2ecf20Sopenharmony_ci	depends on ZONE_DEVICE
1678c2ecf20Sopenharmony_ci	select GENERIC_ALLOCATOR
1688c2ecf20Sopenharmony_ci	help
1698c2ecf20Sopenharmony_ci	  Enableѕ drivers to do PCI peer-to-peer transactions to and from
1708c2ecf20Sopenharmony_ci	  BARs that are exposed in other devices that are the part of
1718c2ecf20Sopenharmony_ci	  the hierarchy where peer-to-peer DMA is guaranteed by the PCI
1728c2ecf20Sopenharmony_ci	  specification to work (ie. anything below a single PCI bridge).
1738c2ecf20Sopenharmony_ci
1748c2ecf20Sopenharmony_ci	  Many PCIe root complexes do not support P2P transactions and
1758c2ecf20Sopenharmony_ci	  it's hard to tell which support it at all, so at this time,
1768c2ecf20Sopenharmony_ci	  P2P DMA transactions must be between devices behind the same root
1778c2ecf20Sopenharmony_ci	  port.
1788c2ecf20Sopenharmony_ci
1798c2ecf20Sopenharmony_ci	  If unsure, say N.
1808c2ecf20Sopenharmony_ci
1818c2ecf20Sopenharmony_ciconfig PCI_LABEL
1828c2ecf20Sopenharmony_ci	def_bool y if (DMI || ACPI)
1838c2ecf20Sopenharmony_ci	select NLS
1848c2ecf20Sopenharmony_ci
1858c2ecf20Sopenharmony_ciconfig PCI_HYPERV
1868c2ecf20Sopenharmony_ci	tristate "Hyper-V PCI Frontend"
1878c2ecf20Sopenharmony_ci	depends on X86_64 && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN && SYSFS
1888c2ecf20Sopenharmony_ci	select PCI_HYPERV_INTERFACE
1898c2ecf20Sopenharmony_ci	help
1908c2ecf20Sopenharmony_ci	  The PCI device frontend driver allows the kernel to import arbitrary
1918c2ecf20Sopenharmony_ci	  PCI devices from a PCI backend to support PCI driver domains.
1928c2ecf20Sopenharmony_ci
1938c2ecf20Sopenharmony_cichoice
1948c2ecf20Sopenharmony_ci	prompt "PCI Express hierarchy optimization setting"
1958c2ecf20Sopenharmony_ci	default PCIE_BUS_DEFAULT
1968c2ecf20Sopenharmony_ci	depends on PCI && EXPERT
1978c2ecf20Sopenharmony_ci	help
1988c2ecf20Sopenharmony_ci	  MPS (Max Payload Size) and MRRS (Max Read Request Size) are PCIe
1998c2ecf20Sopenharmony_ci	  device parameters that affect performance and the ability to
2008c2ecf20Sopenharmony_ci	  support hotplug and peer-to-peer DMA.
2018c2ecf20Sopenharmony_ci
2028c2ecf20Sopenharmony_ci	  The following choices set the MPS and MRRS optimization strategy
2038c2ecf20Sopenharmony_ci	  at compile-time.  The choices are the same as those offered for
2048c2ecf20Sopenharmony_ci	  the kernel command-line parameter 'pci', i.e.,
2058c2ecf20Sopenharmony_ci	  'pci=pcie_bus_tune_off', 'pci=pcie_bus_safe',
2068c2ecf20Sopenharmony_ci	  'pci=pcie_bus_perf', and 'pci=pcie_bus_peer2peer'.
2078c2ecf20Sopenharmony_ci
2088c2ecf20Sopenharmony_ci	  This is a compile-time setting and can be overridden by the above
2098c2ecf20Sopenharmony_ci	  command-line parameters.  If unsure, choose PCIE_BUS_DEFAULT.
2108c2ecf20Sopenharmony_ci
2118c2ecf20Sopenharmony_ciconfig PCIE_BUS_TUNE_OFF
2128c2ecf20Sopenharmony_ci	bool "Tune Off"
2138c2ecf20Sopenharmony_ci	depends on PCI
2148c2ecf20Sopenharmony_ci	help
2158c2ecf20Sopenharmony_ci	  Use the BIOS defaults; don't touch MPS at all.  This is the same
2168c2ecf20Sopenharmony_ci	  as booting with 'pci=pcie_bus_tune_off'.
2178c2ecf20Sopenharmony_ci
2188c2ecf20Sopenharmony_ciconfig PCIE_BUS_DEFAULT
2198c2ecf20Sopenharmony_ci	bool "Default"
2208c2ecf20Sopenharmony_ci	depends on PCI
2218c2ecf20Sopenharmony_ci	help
2228c2ecf20Sopenharmony_ci	  Default choice; ensure that the MPS matches upstream bridge.
2238c2ecf20Sopenharmony_ci
2248c2ecf20Sopenharmony_ciconfig PCIE_BUS_SAFE
2258c2ecf20Sopenharmony_ci	bool "Safe"
2268c2ecf20Sopenharmony_ci	depends on PCI
2278c2ecf20Sopenharmony_ci	help
2288c2ecf20Sopenharmony_ci	  Use largest MPS that boot-time devices support.  If you have a
2298c2ecf20Sopenharmony_ci	  closed system with no possibility of adding new devices, this
2308c2ecf20Sopenharmony_ci	  will use the largest MPS that's supported by all devices.  This
2318c2ecf20Sopenharmony_ci	  is the same as booting with 'pci=pcie_bus_safe'.
2328c2ecf20Sopenharmony_ci
2338c2ecf20Sopenharmony_ciconfig PCIE_BUS_PERFORMANCE
2348c2ecf20Sopenharmony_ci	bool "Performance"
2358c2ecf20Sopenharmony_ci	depends on PCI
2368c2ecf20Sopenharmony_ci	help
2378c2ecf20Sopenharmony_ci	  Use MPS and MRRS for best performance.  Ensure that a given
2388c2ecf20Sopenharmony_ci	  device's MPS is no larger than its parent MPS, which allows us to
2398c2ecf20Sopenharmony_ci	  keep all switches/bridges to the max MPS supported by their
2408c2ecf20Sopenharmony_ci	  parent.  This is the same as booting with 'pci=pcie_bus_perf'.
2418c2ecf20Sopenharmony_ci
2428c2ecf20Sopenharmony_ciconfig PCIE_BUS_PEER2PEER
2438c2ecf20Sopenharmony_ci	bool "Peer2peer"
2448c2ecf20Sopenharmony_ci	depends on PCI
2458c2ecf20Sopenharmony_ci	help
2468c2ecf20Sopenharmony_ci	  Set MPS = 128 for all devices.  MPS configuration effected by the
2478c2ecf20Sopenharmony_ci	  other options could cause the MPS on one root port to be
2488c2ecf20Sopenharmony_ci	  different than that of the MPS on another, which may cause
2498c2ecf20Sopenharmony_ci	  hot-added devices or peer-to-peer DMA to fail.  Set MPS to the
2508c2ecf20Sopenharmony_ci	  smallest possible value (128B) system-wide to avoid these issues.
2518c2ecf20Sopenharmony_ci	  This is the same as booting with 'pci=pcie_bus_peer2peer'.
2528c2ecf20Sopenharmony_ci
2538c2ecf20Sopenharmony_ciendchoice
2548c2ecf20Sopenharmony_ci
2558c2ecf20Sopenharmony_cisource "drivers/pci/hotplug/Kconfig"
2568c2ecf20Sopenharmony_cisource "drivers/pci/controller/Kconfig"
2578c2ecf20Sopenharmony_cisource "drivers/pci/endpoint/Kconfig"
2588c2ecf20Sopenharmony_cisource "drivers/pci/switch/Kconfig"
2598c2ecf20Sopenharmony_ci
2608c2ecf20Sopenharmony_ciendif
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