1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2/* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5#include <linux/module.h> 6#include "main.h" 7#include "coex.h" 8#include "fw.h" 9#include "tx.h" 10#include "rx.h" 11#include "phy.h" 12#include "rtw8822c.h" 13#include "rtw8822c_table.h" 14#include "mac.h" 15#include "reg.h" 16#include "debug.h" 17#include "util.h" 18#include "bf.h" 19#include "efuse.h" 20 21static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 22 u8 rx_path, bool is_tx2_path); 23 24static void rtw8822ce_efuse_parsing(struct rtw_efuse *efuse, 25 struct rtw8822c_efuse *map) 26{ 27 ether_addr_copy(efuse->addr, map->e.mac_addr); 28} 29 30static int rtw8822c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 31{ 32 struct rtw_efuse *efuse = &rtwdev->efuse; 33 struct rtw8822c_efuse *map; 34 int i; 35 36 map = (struct rtw8822c_efuse *)log_map; 37 38 efuse->rfe_option = map->rfe_option; 39 efuse->rf_board_option = map->rf_board_option; 40 efuse->crystal_cap = map->xtal_k; 41 efuse->channel_plan = map->channel_plan; 42 efuse->country_code[0] = map->country_code[0]; 43 efuse->country_code[1] = map->country_code[1]; 44 efuse->bt_setting = map->rf_bt_setting; 45 efuse->regd = map->rf_board_option & 0x7; 46 efuse->thermal_meter[RF_PATH_A] = map->path_a_thermal; 47 efuse->thermal_meter[RF_PATH_B] = map->path_b_thermal; 48 efuse->thermal_meter_k = 49 (map->path_a_thermal + map->path_b_thermal) >> 1; 50 efuse->power_track_type = (map->tx_pwr_calibrate_rate >> 4) & 0xf; 51 52 for (i = 0; i < 4; i++) 53 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 54 55 switch (rtw_hci_type(rtwdev)) { 56 case RTW_HCI_TYPE_PCIE: 57 rtw8822ce_efuse_parsing(efuse, map); 58 break; 59 default: 60 /* unsupported now */ 61 return -ENOTSUPP; 62 } 63 64 return 0; 65} 66 67static void rtw8822c_header_file_init(struct rtw_dev *rtwdev, bool pre) 68{ 69 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN); 70 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_PI_ON); 71 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN); 72 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_PI_ON); 73 74 if (pre) 75 rtw_write32_clr(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN); 76 else 77 rtw_write32_set(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN); 78} 79 80static void rtw8822c_dac_backup_reg(struct rtw_dev *rtwdev, 81 struct rtw_backup_info *backup, 82 struct rtw_backup_info *backup_rf) 83{ 84 u32 path, i; 85 u32 val; 86 u32 reg; 87 u32 rf_addr[DACK_RF_8822C] = {0x8f}; 88 u32 addrs[DACK_REG_8822C] = {0x180c, 0x1810, 0x410c, 0x4110, 89 0x1c3c, 0x1c24, 0x1d70, 0x9b4, 90 0x1a00, 0x1a14, 0x1d58, 0x1c38, 91 0x1e24, 0x1e28, 0x1860, 0x4160}; 92 93 for (i = 0; i < DACK_REG_8822C; i++) { 94 backup[i].len = 4; 95 backup[i].reg = addrs[i]; 96 backup[i].val = rtw_read32(rtwdev, addrs[i]); 97 } 98 99 for (path = 0; path < DACK_PATH_8822C; path++) { 100 for (i = 0; i < DACK_RF_8822C; i++) { 101 reg = rf_addr[i]; 102 val = rtw_read_rf(rtwdev, path, reg, RFREG_MASK); 103 backup_rf[path * i + i].reg = reg; 104 backup_rf[path * i + i].val = val; 105 } 106 } 107} 108 109static void rtw8822c_dac_restore_reg(struct rtw_dev *rtwdev, 110 struct rtw_backup_info *backup, 111 struct rtw_backup_info *backup_rf) 112{ 113 u32 path, i; 114 u32 val; 115 u32 reg; 116 117 rtw_restore_reg(rtwdev, backup, DACK_REG_8822C); 118 119 for (path = 0; path < DACK_PATH_8822C; path++) { 120 for (i = 0; i < DACK_RF_8822C; i++) { 121 val = backup_rf[path * i + i].val; 122 reg = backup_rf[path * i + i].reg; 123 rtw_write_rf(rtwdev, path, reg, RFREG_MASK, val); 124 } 125 } 126} 127 128static void rtw8822c_rf_minmax_cmp(struct rtw_dev *rtwdev, u32 value, 129 u32 *min, u32 *max) 130{ 131 if (value >= 0x200) { 132 if (*min >= 0x200) { 133 if (*min > value) 134 *min = value; 135 } else { 136 *min = value; 137 } 138 if (*max >= 0x200) { 139 if (*max < value) 140 *max = value; 141 } 142 } else { 143 if (*min < 0x200) { 144 if (*min > value) 145 *min = value; 146 } 147 148 if (*max >= 0x200) { 149 *max = value; 150 } else { 151 if (*max < value) 152 *max = value; 153 } 154 } 155} 156 157static void __rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *v1, u32 *v2) 158{ 159 if (*v1 >= 0x200 && *v2 >= 0x200) { 160 if (*v1 > *v2) 161 swap(*v1, *v2); 162 } else if (*v1 < 0x200 && *v2 < 0x200) { 163 if (*v1 > *v2) 164 swap(*v1, *v2); 165 } else if (*v1 < 0x200 && *v2 >= 0x200) { 166 swap(*v1, *v2); 167 } 168} 169 170static void rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *iv, u32 *qv) 171{ 172 u32 i, j; 173 174 for (i = 0; i < DACK_SN_8822C - 1; i++) { 175 for (j = 0; j < (DACK_SN_8822C - 1 - i) ; j++) { 176 __rtw8822c_dac_iq_sort(rtwdev, &iv[j], &iv[j + 1]); 177 __rtw8822c_dac_iq_sort(rtwdev, &qv[j], &qv[j + 1]); 178 } 179 } 180} 181 182static void rtw8822c_dac_iq_offset(struct rtw_dev *rtwdev, u32 *vec, u32 *val) 183{ 184 u32 p, m, t, i; 185 186 m = 0; 187 p = 0; 188 for (i = 10; i < DACK_SN_8822C - 10; i++) { 189 if (vec[i] > 0x200) 190 m = (0x400 - vec[i]) + m; 191 else 192 p = vec[i] + p; 193 } 194 195 if (p > m) { 196 t = p - m; 197 t = t / (DACK_SN_8822C - 20); 198 } else { 199 t = m - p; 200 t = t / (DACK_SN_8822C - 20); 201 if (t != 0x0) 202 t = 0x400 - t; 203 } 204 205 *val = t; 206} 207 208static u32 rtw8822c_get_path_write_addr(u8 path) 209{ 210 u32 base_addr; 211 212 switch (path) { 213 case RF_PATH_A: 214 base_addr = 0x1800; 215 break; 216 case RF_PATH_B: 217 base_addr = 0x4100; 218 break; 219 default: 220 WARN_ON(1); 221 return -1; 222 } 223 224 return base_addr; 225} 226 227static u32 rtw8822c_get_path_read_addr(u8 path) 228{ 229 u32 base_addr; 230 231 switch (path) { 232 case RF_PATH_A: 233 base_addr = 0x2800; 234 break; 235 case RF_PATH_B: 236 base_addr = 0x4500; 237 break; 238 default: 239 WARN_ON(1); 240 return -1; 241 } 242 243 return base_addr; 244} 245 246static bool rtw8822c_dac_iq_check(struct rtw_dev *rtwdev, u32 value) 247{ 248 bool ret = true; 249 250 if ((value >= 0x200 && (0x400 - value) > 0x64) || 251 (value < 0x200 && value > 0x64)) { 252 ret = false; 253 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] Error overflow\n"); 254 } 255 256 return ret; 257} 258 259static void rtw8822c_dac_cal_iq_sample(struct rtw_dev *rtwdev, u32 *iv, u32 *qv) 260{ 261 u32 temp; 262 int i = 0, cnt = 0; 263 264 while (i < DACK_SN_8822C && cnt < 10000) { 265 cnt++; 266 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 267 iv[i] = (temp & 0x3ff000) >> 12; 268 qv[i] = temp & 0x3ff; 269 270 if (rtw8822c_dac_iq_check(rtwdev, iv[i]) && 271 rtw8822c_dac_iq_check(rtwdev, qv[i])) 272 i++; 273 } 274} 275 276static void rtw8822c_dac_cal_iq_search(struct rtw_dev *rtwdev, 277 u32 *iv, u32 *qv, 278 u32 *i_value, u32 *q_value) 279{ 280 u32 i_max = 0, q_max = 0, i_min = 0, q_min = 0; 281 u32 i_delta, q_delta; 282 u32 temp; 283 int i, cnt = 0; 284 285 do { 286 i_min = iv[0]; 287 i_max = iv[0]; 288 q_min = qv[0]; 289 q_max = qv[0]; 290 for (i = 0; i < DACK_SN_8822C; i++) { 291 rtw8822c_rf_minmax_cmp(rtwdev, iv[i], &i_min, &i_max); 292 rtw8822c_rf_minmax_cmp(rtwdev, qv[i], &q_min, &q_max); 293 } 294 295 if (i_max < 0x200 && i_min < 0x200) 296 i_delta = i_max - i_min; 297 else if (i_max >= 0x200 && i_min >= 0x200) 298 i_delta = i_max - i_min; 299 else 300 i_delta = i_max + (0x400 - i_min); 301 302 if (q_max < 0x200 && q_min < 0x200) 303 q_delta = q_max - q_min; 304 else if (q_max >= 0x200 && q_min >= 0x200) 305 q_delta = q_max - q_min; 306 else 307 q_delta = q_max + (0x400 - q_min); 308 309 rtw_dbg(rtwdev, RTW_DBG_RFK, 310 "[DACK] i: min=0x%08x, max=0x%08x, delta=0x%08x\n", 311 i_min, i_max, i_delta); 312 rtw_dbg(rtwdev, RTW_DBG_RFK, 313 "[DACK] q: min=0x%08x, max=0x%08x, delta=0x%08x\n", 314 q_min, q_max, q_delta); 315 316 rtw8822c_dac_iq_sort(rtwdev, iv, qv); 317 318 if (i_delta > 5 || q_delta > 5) { 319 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 320 iv[0] = (temp & 0x3ff000) >> 12; 321 qv[0] = temp & 0x3ff; 322 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 323 iv[DACK_SN_8822C - 1] = (temp & 0x3ff000) >> 12; 324 qv[DACK_SN_8822C - 1] = temp & 0x3ff; 325 } else { 326 break; 327 } 328 } while (cnt++ < 100); 329 330 rtw8822c_dac_iq_offset(rtwdev, iv, i_value); 331 rtw8822c_dac_iq_offset(rtwdev, qv, q_value); 332} 333 334static void rtw8822c_dac_cal_rf_mode(struct rtw_dev *rtwdev, 335 u32 *i_value, u32 *q_value) 336{ 337 u32 iv[DACK_SN_8822C], qv[DACK_SN_8822C]; 338 u32 rf_a, rf_b; 339 340 rf_a = rtw_read_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK); 341 rf_b = rtw_read_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK); 342 343 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a); 344 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b); 345 346 rtw8822c_dac_cal_iq_sample(rtwdev, iv, qv); 347 rtw8822c_dac_cal_iq_search(rtwdev, iv, qv, i_value, q_value); 348} 349 350static void rtw8822c_dac_bb_setting(struct rtw_dev *rtwdev) 351{ 352 rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff); 353 rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2); 354 rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3); 355 rtw_write32(rtwdev, 0x1d70, 0x7e7e7e7e); 356 rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0); 357 rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0); 358 rtw_write32(rtwdev, 0x1b00, 0x00000008); 359 rtw_write8(rtwdev, 0x1bcc, 0x3f); 360 rtw_write32(rtwdev, 0x1b00, 0x0000000a); 361 rtw_write8(rtwdev, 0x1bcc, 0x3f); 362 rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0); 363 rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3); 364} 365 366static void rtw8822c_dac_cal_adc(struct rtw_dev *rtwdev, 367 u8 path, u32 *adc_ic, u32 *adc_qc) 368{ 369 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 370 u32 ic = 0, qc = 0, temp = 0; 371 u32 base_addr; 372 u32 path_sel; 373 int i; 374 375 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK path(%d)\n", path); 376 377 base_addr = rtw8822c_get_path_write_addr(path); 378 switch (path) { 379 case RF_PATH_A: 380 path_sel = 0xa0000; 381 break; 382 case RF_PATH_B: 383 path_sel = 0x80000; 384 break; 385 default: 386 WARN_ON(1); 387 return; 388 } 389 390 /* ADCK step1 */ 391 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0); 392 if (path == RF_PATH_B) 393 rtw_write32(rtwdev, base_addr + 0x30, 0x30db8041); 394 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0); 395 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 396 rtw_write32(rtwdev, base_addr + 0x10, 0x02dd08c4); 397 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260); 398 rtw_write_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK, 0x10000); 399 rtw_write_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK, 0x10000); 400 for (i = 0; i < 10; i++) { 401 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK count=%d\n", i); 402 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8003); 403 rtw_write32(rtwdev, 0x1c24, 0x00010002); 404 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 405 rtw_dbg(rtwdev, RTW_DBG_RFK, 406 "[DACK] before: i=0x%x, q=0x%x\n", ic, qc); 407 408 /* compensation value */ 409 if (ic != 0x0) { 410 ic = 0x400 - ic; 411 *adc_ic = ic; 412 } 413 if (qc != 0x0) { 414 qc = 0x400 - qc; 415 *adc_qc = qc; 416 } 417 temp = (ic & 0x3ff) | ((qc & 0x3ff) << 10); 418 rtw_write32(rtwdev, base_addr + 0x68, temp); 419 dm_info->dack_adck[path] = temp; 420 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK 0x%08x=0x08%x\n", 421 base_addr + 0x68, temp); 422 /* check ADC DC offset */ 423 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8103); 424 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 425 rtw_dbg(rtwdev, RTW_DBG_RFK, 426 "[DACK] after: i=0x%08x, q=0x%08x\n", ic, qc); 427 if (ic >= 0x200) 428 ic = 0x400 - ic; 429 if (qc >= 0x200) 430 qc = 0x400 - qc; 431 if (ic < 5 && qc < 5) 432 break; 433 } 434 435 /* ADCK step2 */ 436 rtw_write32(rtwdev, 0x1c3c, 0x00000003); 437 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260); 438 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4); 439 440 /* release pull low switch on IQ path */ 441 rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1); 442} 443 444static void rtw8822c_dac_cal_step1(struct rtw_dev *rtwdev, u8 path) 445{ 446 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 447 u32 base_addr; 448 u32 read_addr; 449 450 base_addr = rtw8822c_get_path_write_addr(path); 451 read_addr = rtw8822c_get_path_read_addr(path); 452 453 rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]); 454 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 455 if (path == RF_PATH_A) { 456 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0); 457 rtw_write32(rtwdev, 0x1c38, 0xffffffff); 458 } 459 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 460 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 461 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88); 462 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff81); 463 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208); 464 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88); 465 rtw_write32(rtwdev, base_addr + 0xd8, 0x0008ff81); 466 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208); 467 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000); 468 mdelay(2); 469 rtw_write32(rtwdev, base_addr + 0xbc, 0x000aff8d); 470 mdelay(2); 471 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89); 472 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89); 473 mdelay(1); 474 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000); 475 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000); 476 mdelay(20); 477 if (!check_hw_ready(rtwdev, read_addr + 0x08, 0x7fff80, 0xffff) || 478 !check_hw_ready(rtwdev, read_addr + 0x34, 0x7fff80, 0xffff)) 479 rtw_err(rtwdev, "failed to wait for dack ready\n"); 480 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000); 481 mdelay(1); 482 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87); 483 rtw_write32(rtwdev, 0x9b4, 0xdb6db600); 484 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 485 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87); 486 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000); 487} 488 489static void rtw8822c_dac_cal_step2(struct rtw_dev *rtwdev, 490 u8 path, u32 *ic_out, u32 *qc_out) 491{ 492 u32 base_addr; 493 u32 ic, qc, ic_in, qc_in; 494 495 base_addr = rtw8822c_get_path_write_addr(path); 496 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0); 497 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, 0x8); 498 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, 0x0); 499 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, 0x8); 500 501 rtw_write32(rtwdev, 0x1b00, 0x00000008); 502 rtw_write8(rtwdev, 0x1bcc, 0x03f); 503 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 504 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 505 rtw_write32(rtwdev, 0x1c3c, 0x00088103); 506 507 rtw8822c_dac_cal_rf_mode(rtwdev, &ic_in, &qc_in); 508 ic = ic_in; 509 qc = qc_in; 510 511 /* compensation value */ 512 if (ic != 0x0) 513 ic = 0x400 - ic; 514 if (qc != 0x0) 515 qc = 0x400 - qc; 516 if (ic < 0x300) { 517 ic = ic * 2 * 6 / 5; 518 ic = ic + 0x80; 519 } else { 520 ic = (0x400 - ic) * 2 * 6 / 5; 521 ic = 0x7f - ic; 522 } 523 if (qc < 0x300) { 524 qc = qc * 2 * 6 / 5; 525 qc = qc + 0x80; 526 } else { 527 qc = (0x400 - qc) * 2 * 6 / 5; 528 qc = 0x7f - qc; 529 } 530 531 *ic_out = ic; 532 *qc_out = qc; 533 534 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] before i=0x%x, q=0x%x\n", ic_in, qc_in); 535 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] after i=0x%x, q=0x%x\n", ic, qc); 536} 537 538static void rtw8822c_dac_cal_step3(struct rtw_dev *rtwdev, u8 path, 539 u32 adc_ic, u32 adc_qc, 540 u32 *ic_in, u32 *qc_in, 541 u32 *i_out, u32 *q_out) 542{ 543 u32 base_addr; 544 u32 read_addr; 545 u32 ic, qc; 546 u32 temp; 547 548 base_addr = rtw8822c_get_path_write_addr(path); 549 read_addr = rtw8822c_get_path_read_addr(path); 550 ic = *ic_in; 551 qc = *qc_in; 552 553 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 554 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 555 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 556 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88); 557 rtw_write32(rtwdev, base_addr + 0xbc, 0xc008ff81); 558 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208); 559 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, ic & 0xf); 560 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, (ic & 0xf0) >> 4); 561 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88); 562 rtw_write32(rtwdev, base_addr + 0xd8, 0xe008ff81); 563 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208); 564 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, qc & 0xf); 565 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, (qc & 0xf0) >> 4); 566 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000); 567 mdelay(2); 568 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x6); 569 mdelay(2); 570 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89); 571 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89); 572 mdelay(1); 573 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000); 574 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000); 575 mdelay(20); 576 if (!check_hw_ready(rtwdev, read_addr + 0x24, 0x07f80000, ic) || 577 !check_hw_ready(rtwdev, read_addr + 0x50, 0x07f80000, qc)) 578 rtw_err(rtwdev, "failed to write IQ vector to hardware\n"); 579 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000); 580 mdelay(1); 581 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x3); 582 rtw_write32(rtwdev, 0x9b4, 0xdb6db600); 583 584 /* check DAC DC offset */ 585 temp = ((adc_ic + 0x10) & 0x3ff) | (((adc_qc + 0x10) & 0x3ff) << 10); 586 rtw_write32(rtwdev, base_addr + 0x68, temp); 587 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 588 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000); 589 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 590 if (ic >= 0x10) 591 ic = ic - 0x10; 592 else 593 ic = 0x400 - (0x10 - ic); 594 595 if (qc >= 0x10) 596 qc = qc - 0x10; 597 else 598 qc = 0x400 - (0x10 - qc); 599 600 *i_out = ic; 601 *q_out = qc; 602 603 if (ic >= 0x200) 604 ic = 0x400 - ic; 605 if (qc >= 0x200) 606 qc = 0x400 - qc; 607 608 *ic_in = ic; 609 *qc_in = qc; 610 611 rtw_dbg(rtwdev, RTW_DBG_RFK, 612 "[DACK] after DACK i=0x%x, q=0x%x\n", *i_out, *q_out); 613} 614 615static void rtw8822c_dac_cal_step4(struct rtw_dev *rtwdev, u8 path) 616{ 617 u32 base_addr = rtw8822c_get_path_write_addr(path); 618 619 rtw_write32(rtwdev, base_addr + 0x68, 0x0); 620 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4); 621 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0x1, 0x0); 622 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x1); 623} 624 625static void rtw8822c_dac_cal_backup_vec(struct rtw_dev *rtwdev, 626 u8 path, u8 vec, u32 w_addr, u32 r_addr) 627{ 628 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 629 u16 val; 630 u32 i; 631 632 if (WARN_ON(vec >= 2)) 633 return; 634 635 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 636 rtw_write32_mask(rtwdev, w_addr, 0xf0000000, i); 637 val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000); 638 dm_info->dack_msbk[path][vec][i] = val; 639 } 640} 641 642static void rtw8822c_dac_cal_backup_path(struct rtw_dev *rtwdev, u8 path) 643{ 644 u32 w_off = 0x1c; 645 u32 r_off = 0x2c; 646 u32 w_addr, r_addr; 647 648 if (WARN_ON(path >= 2)) 649 return; 650 651 /* backup I vector */ 652 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0; 653 r_addr = rtw8822c_get_path_read_addr(path) + 0x10; 654 rtw8822c_dac_cal_backup_vec(rtwdev, path, 0, w_addr, r_addr); 655 656 /* backup Q vector */ 657 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off; 658 r_addr = rtw8822c_get_path_read_addr(path) + 0x10 + r_off; 659 rtw8822c_dac_cal_backup_vec(rtwdev, path, 1, w_addr, r_addr); 660} 661 662static void rtw8822c_dac_cal_backup_dck(struct rtw_dev *rtwdev) 663{ 664 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 665 u8 val; 666 667 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000); 668 dm_info->dack_dck[RF_PATH_A][0][0] = val; 669 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf); 670 dm_info->dack_dck[RF_PATH_A][0][1] = val; 671 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000); 672 dm_info->dack_dck[RF_PATH_A][1][0] = val; 673 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf); 674 dm_info->dack_dck[RF_PATH_A][1][1] = val; 675 676 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000); 677 dm_info->dack_dck[RF_PATH_B][0][0] = val; 678 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf); 679 dm_info->dack_dck[RF_PATH_B][1][0] = val; 680 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000); 681 dm_info->dack_dck[RF_PATH_B][0][1] = val; 682 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf); 683 dm_info->dack_dck[RF_PATH_B][1][1] = val; 684} 685 686static void rtw8822c_dac_cal_backup(struct rtw_dev *rtwdev) 687{ 688 u32 temp[3]; 689 690 temp[0] = rtw_read32(rtwdev, 0x1860); 691 temp[1] = rtw_read32(rtwdev, 0x4160); 692 temp[2] = rtw_read32(rtwdev, 0x9b4); 693 694 /* set clock */ 695 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 696 697 /* backup path-A I/Q */ 698 rtw_write32_clr(rtwdev, 0x1830, BIT(30)); 699 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c); 700 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_A); 701 702 /* backup path-B I/Q */ 703 rtw_write32_clr(rtwdev, 0x4130, BIT(30)); 704 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c); 705 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_B); 706 707 rtw8822c_dac_cal_backup_dck(rtwdev); 708 rtw_write32_set(rtwdev, 0x1830, BIT(30)); 709 rtw_write32_set(rtwdev, 0x4130, BIT(30)); 710 711 rtw_write32(rtwdev, 0x1860, temp[0]); 712 rtw_write32(rtwdev, 0x4160, temp[1]); 713 rtw_write32(rtwdev, 0x9b4, temp[2]); 714} 715 716static void rtw8822c_dac_cal_restore_dck(struct rtw_dev *rtwdev) 717{ 718 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 719 u8 val; 720 721 rtw_write32_set(rtwdev, REG_DCKA_I_0, BIT(19)); 722 val = dm_info->dack_dck[RF_PATH_A][0][0]; 723 rtw_write32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000, val); 724 val = dm_info->dack_dck[RF_PATH_A][0][1]; 725 rtw_write32_mask(rtwdev, REG_DCKA_I_1, 0xf, val); 726 727 rtw_write32_set(rtwdev, REG_DCKA_Q_0, BIT(19)); 728 val = dm_info->dack_dck[RF_PATH_A][1][0]; 729 rtw_write32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000, val); 730 val = dm_info->dack_dck[RF_PATH_A][1][1]; 731 rtw_write32_mask(rtwdev, REG_DCKA_Q_1, 0xf, val); 732 733 rtw_write32_set(rtwdev, REG_DCKB_I_0, BIT(19)); 734 val = dm_info->dack_dck[RF_PATH_B][0][0]; 735 rtw_write32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000, val); 736 val = dm_info->dack_dck[RF_PATH_B][0][1]; 737 rtw_write32_mask(rtwdev, REG_DCKB_I_1, 0xf, val); 738 739 rtw_write32_set(rtwdev, REG_DCKB_Q_0, BIT(19)); 740 val = dm_info->dack_dck[RF_PATH_B][1][0]; 741 rtw_write32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000, val); 742 val = dm_info->dack_dck[RF_PATH_B][1][1]; 743 rtw_write32_mask(rtwdev, REG_DCKB_Q_1, 0xf, val); 744} 745 746static void rtw8822c_dac_cal_restore_prepare(struct rtw_dev *rtwdev) 747{ 748 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 749 750 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x0); 751 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x0); 752 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x0); 753 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x0); 754 755 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x0); 756 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c); 757 rtw_write32_mask(rtwdev, 0x18b4, BIT(0), 0x1); 758 rtw_write32_mask(rtwdev, 0x18d0, BIT(0), 0x1); 759 760 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x0); 761 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c); 762 rtw_write32_mask(rtwdev, 0x41b4, BIT(0), 0x1); 763 rtw_write32_mask(rtwdev, 0x41d0, BIT(0), 0x1); 764 765 rtw_write32_mask(rtwdev, 0x18b0, 0xf00, 0x0); 766 rtw_write32_mask(rtwdev, 0x18c0, BIT(14), 0x0); 767 rtw_write32_mask(rtwdev, 0x18cc, 0xf00, 0x0); 768 rtw_write32_mask(rtwdev, 0x18dc, BIT(14), 0x0); 769 770 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x0); 771 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x0); 772 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x1); 773 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x1); 774 775 rtw8822c_dac_cal_restore_dck(rtwdev); 776 777 rtw_write32_mask(rtwdev, 0x18c0, 0x38000, 0x7); 778 rtw_write32_mask(rtwdev, 0x18dc, 0x38000, 0x7); 779 rtw_write32_mask(rtwdev, 0x41c0, 0x38000, 0x7); 780 rtw_write32_mask(rtwdev, 0x41dc, 0x38000, 0x7); 781 782 rtw_write32_mask(rtwdev, 0x18b8, BIT(26) | BIT(25), 0x1); 783 rtw_write32_mask(rtwdev, 0x18d4, BIT(26) | BIT(25), 0x1); 784 785 rtw_write32_mask(rtwdev, 0x41b0, 0xf00, 0x0); 786 rtw_write32_mask(rtwdev, 0x41c0, BIT(14), 0x0); 787 rtw_write32_mask(rtwdev, 0x41cc, 0xf00, 0x0); 788 rtw_write32_mask(rtwdev, 0x41dc, BIT(14), 0x0); 789 790 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x0); 791 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x0); 792 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x1); 793 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x1); 794 795 rtw_write32_mask(rtwdev, 0x41b8, BIT(26) | BIT(25), 0x1); 796 rtw_write32_mask(rtwdev, 0x41d4, BIT(26) | BIT(25), 0x1); 797} 798 799static bool rtw8822c_dac_cal_restore_wait(struct rtw_dev *rtwdev, 800 u32 target_addr, u32 toggle_addr) 801{ 802 u32 cnt = 0; 803 804 do { 805 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x0); 806 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x2); 807 808 if (rtw_read32_mask(rtwdev, target_addr, 0xf) == 0x6) 809 return true; 810 811 } while (cnt++ < 100); 812 813 return false; 814} 815 816static bool rtw8822c_dac_cal_restore_path(struct rtw_dev *rtwdev, u8 path) 817{ 818 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 819 u32 w_off = 0x1c; 820 u32 r_off = 0x2c; 821 u32 w_i, r_i, w_q, r_q; 822 u32 value; 823 u32 i; 824 825 w_i = rtw8822c_get_path_write_addr(path) + 0xb0; 826 r_i = rtw8822c_get_path_read_addr(path) + 0x08; 827 w_q = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off; 828 r_q = rtw8822c_get_path_read_addr(path) + 0x08 + r_off; 829 830 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_i, w_i + 0x8)) 831 return false; 832 833 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 834 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); 835 value = dm_info->dack_msbk[path][0][i]; 836 rtw_write32_mask(rtwdev, w_i + 0x4, 0xff8, value); 837 rtw_write32_mask(rtwdev, w_i, 0xf0000000, i); 838 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x1); 839 } 840 841 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); 842 843 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_q, w_q + 0x8)) 844 return false; 845 846 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 847 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); 848 value = dm_info->dack_msbk[path][1][i]; 849 rtw_write32_mask(rtwdev, w_q + 0x4, 0xff8, value); 850 rtw_write32_mask(rtwdev, w_q, 0xf0000000, i); 851 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x1); 852 } 853 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); 854 855 rtw_write32_mask(rtwdev, w_i + 0x8, BIT(26) | BIT(25), 0x0); 856 rtw_write32_mask(rtwdev, w_q + 0x8, BIT(26) | BIT(25), 0x0); 857 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(0), 0x0); 858 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(0), 0x0); 859 860 return true; 861} 862 863static bool __rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev) 864{ 865 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_A)) 866 return false; 867 868 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_B)) 869 return false; 870 871 return true; 872} 873 874static bool rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev) 875{ 876 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 877 u32 temp[3]; 878 879 /* sample the first element for both path's IQ vector */ 880 if (dm_info->dack_msbk[RF_PATH_A][0][0] == 0 && 881 dm_info->dack_msbk[RF_PATH_A][1][0] == 0 && 882 dm_info->dack_msbk[RF_PATH_B][0][0] == 0 && 883 dm_info->dack_msbk[RF_PATH_B][1][0] == 0) 884 return false; 885 886 temp[0] = rtw_read32(rtwdev, 0x1860); 887 temp[1] = rtw_read32(rtwdev, 0x4160); 888 temp[2] = rtw_read32(rtwdev, 0x9b4); 889 890 rtw8822c_dac_cal_restore_prepare(rtwdev); 891 if (!check_hw_ready(rtwdev, 0x2808, 0x7fff80, 0xffff) || 892 !check_hw_ready(rtwdev, 0x2834, 0x7fff80, 0xffff) || 893 !check_hw_ready(rtwdev, 0x4508, 0x7fff80, 0xffff) || 894 !check_hw_ready(rtwdev, 0x4534, 0x7fff80, 0xffff)) 895 return false; 896 897 if (!__rtw8822c_dac_cal_restore(rtwdev)) { 898 rtw_err(rtwdev, "failed to restore dack vectors\n"); 899 return false; 900 } 901 902 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x1); 903 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); 904 rtw_write32(rtwdev, 0x1860, temp[0]); 905 rtw_write32(rtwdev, 0x4160, temp[1]); 906 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x1); 907 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x1); 908 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x1); 909 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x1); 910 rtw_write32(rtwdev, 0x9b4, temp[2]); 911 912 return true; 913} 914 915static void rtw8822c_rf_dac_cal(struct rtw_dev *rtwdev) 916{ 917 struct rtw_backup_info backup_rf[DACK_RF_8822C * DACK_PATH_8822C]; 918 struct rtw_backup_info backup[DACK_REG_8822C]; 919 u32 ic = 0, qc = 0, i; 920 u32 i_a = 0x0, q_a = 0x0, i_b = 0x0, q_b = 0x0; 921 u32 ic_a = 0x0, qc_a = 0x0, ic_b = 0x0, qc_b = 0x0; 922 u32 adc_ic_a = 0x0, adc_qc_a = 0x0, adc_ic_b = 0x0, adc_qc_b = 0x0; 923 924 if (rtw8822c_dac_cal_restore(rtwdev)) 925 return; 926 927 /* not able to restore, do it */ 928 929 rtw8822c_dac_backup_reg(rtwdev, backup, backup_rf); 930 931 rtw8822c_dac_bb_setting(rtwdev); 932 933 /* path-A */ 934 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_A, &adc_ic_a, &adc_qc_a); 935 for (i = 0; i < 10; i++) { 936 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_A); 937 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_A, &ic, &qc); 938 ic_a = ic; 939 qc_a = qc; 940 941 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_A, adc_ic_a, adc_qc_a, 942 &ic, &qc, &i_a, &q_a); 943 944 if (ic < 5 && qc < 5) 945 break; 946 } 947 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_A); 948 949 /* path-B */ 950 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_B, &adc_ic_b, &adc_qc_b); 951 for (i = 0; i < 10; i++) { 952 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_B); 953 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_B, &ic, &qc); 954 ic_b = ic; 955 qc_b = qc; 956 957 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_B, adc_ic_b, adc_qc_b, 958 &ic, &qc, &i_b, &q_b); 959 960 if (ic < 5 && qc < 5) 961 break; 962 } 963 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_B); 964 965 rtw_write32(rtwdev, 0x1b00, 0x00000008); 966 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); 967 rtw_write8(rtwdev, 0x1bcc, 0x0); 968 rtw_write32(rtwdev, 0x1b00, 0x0000000a); 969 rtw_write8(rtwdev, 0x1bcc, 0x0); 970 971 rtw8822c_dac_restore_reg(rtwdev, backup, backup_rf); 972 973 /* backup results to restore, saving a lot of time */ 974 rtw8822c_dac_cal_backup(rtwdev); 975 976 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: ic=0x%x, qc=0x%x\n", ic_a, qc_a); 977 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: ic=0x%x, qc=0x%x\n", ic_b, qc_b); 978 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: i=0x%x, q=0x%x\n", i_a, q_a); 979 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: i=0x%x, q=0x%x\n", i_b, q_b); 980} 981 982static void rtw8822c_rf_x2_check(struct rtw_dev *rtwdev) 983{ 984 u8 x2k_busy; 985 986 mdelay(1); 987 x2k_busy = rtw_read_rf(rtwdev, RF_PATH_A, 0xb8, BIT(15)); 988 if (x2k_busy == 1) { 989 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0xC4440); 990 rtw_write_rf(rtwdev, RF_PATH_A, 0xba, RFREG_MASK, 0x6840D); 991 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0x80440); 992 mdelay(1); 993 } 994} 995 996static void rtw8822c_set_power_trim(struct rtw_dev *rtwdev, s8 bb_gain[2][8]) 997{ 998#define RF_SET_POWER_TRIM(_path, _seq, _idx) \ 999 do { \ 1000 rtw_write_rf(rtwdev, _path, 0x33, RFREG_MASK, _seq); \ 1001 rtw_write_rf(rtwdev, _path, 0x3f, RFREG_MASK, \ 1002 bb_gain[_path][_idx]); \ 1003 } while (0) 1004 u8 path; 1005 1006 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1007 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 1); 1008 RF_SET_POWER_TRIM(path, 0x0, 0); 1009 RF_SET_POWER_TRIM(path, 0x1, 1); 1010 RF_SET_POWER_TRIM(path, 0x2, 2); 1011 RF_SET_POWER_TRIM(path, 0x3, 2); 1012 RF_SET_POWER_TRIM(path, 0x4, 3); 1013 RF_SET_POWER_TRIM(path, 0x5, 4); 1014 RF_SET_POWER_TRIM(path, 0x6, 5); 1015 RF_SET_POWER_TRIM(path, 0x7, 6); 1016 RF_SET_POWER_TRIM(path, 0x8, 7); 1017 RF_SET_POWER_TRIM(path, 0x9, 3); 1018 RF_SET_POWER_TRIM(path, 0xa, 4); 1019 RF_SET_POWER_TRIM(path, 0xb, 5); 1020 RF_SET_POWER_TRIM(path, 0xc, 6); 1021 RF_SET_POWER_TRIM(path, 0xd, 7); 1022 RF_SET_POWER_TRIM(path, 0xe, 7); 1023 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 0); 1024 } 1025#undef RF_SET_POWER_TRIM 1026} 1027 1028static void rtw8822c_power_trim(struct rtw_dev *rtwdev) 1029{ 1030 u8 pg_pwr = 0xff, i, path, idx; 1031 s8 bb_gain[2][8] = {}; 1032 u16 rf_efuse_2g[3] = {PPG_2GL_TXAB, PPG_2GM_TXAB, PPG_2GH_TXAB}; 1033 u16 rf_efuse_5g[2][5] = {{PPG_5GL1_TXA, PPG_5GL2_TXA, PPG_5GM1_TXA, 1034 PPG_5GM2_TXA, PPG_5GH1_TXA}, 1035 {PPG_5GL1_TXB, PPG_5GL2_TXB, PPG_5GM1_TXB, 1036 PPG_5GM2_TXB, PPG_5GH1_TXB} }; 1037 bool set = false; 1038 1039 for (i = 0; i < ARRAY_SIZE(rf_efuse_2g); i++) { 1040 rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[i], &pg_pwr); 1041 if (pg_pwr == EFUSE_READ_FAIL) 1042 continue; 1043 set = true; 1044 bb_gain[RF_PATH_A][i] = FIELD_GET(PPG_2G_A_MASK, pg_pwr); 1045 bb_gain[RF_PATH_B][i] = FIELD_GET(PPG_2G_B_MASK, pg_pwr); 1046 } 1047 1048 for (i = 0; i < ARRAY_SIZE(rf_efuse_5g[0]); i++) { 1049 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1050 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path][i], 1051 &pg_pwr); 1052 if (pg_pwr == EFUSE_READ_FAIL) 1053 continue; 1054 set = true; 1055 idx = i + ARRAY_SIZE(rf_efuse_2g); 1056 bb_gain[path][idx] = FIELD_GET(PPG_5G_MASK, pg_pwr); 1057 } 1058 } 1059 if (set) 1060 rtw8822c_set_power_trim(rtwdev, bb_gain); 1061 1062 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL); 1063} 1064 1065static void rtw8822c_thermal_trim(struct rtw_dev *rtwdev) 1066{ 1067 u16 rf_efuse[2] = {PPG_THERMAL_A, PPG_THERMAL_B}; 1068 u8 pg_therm = 0xff, thermal[2] = {0}, path; 1069 1070 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1071 rtw_read8_physical_efuse(rtwdev, rf_efuse[path], &pg_therm); 1072 if (pg_therm == EFUSE_READ_FAIL) 1073 return; 1074 /* Efuse value of BIT(0) shall be move to BIT(3), and the value 1075 * of BIT(1) to BIT(3) should be right shifted 1 bit. 1076 */ 1077 thermal[path] = FIELD_GET(GENMASK(3, 1), pg_therm); 1078 thermal[path] |= FIELD_PREP(BIT(3), pg_therm & BIT(0)); 1079 rtw_write_rf(rtwdev, path, 0x43, RF_THEMAL_MASK, thermal[path]); 1080 } 1081} 1082 1083static void rtw8822c_pa_bias(struct rtw_dev *rtwdev) 1084{ 1085 u16 rf_efuse_2g[2] = {PPG_PABIAS_2GA, PPG_PABIAS_2GB}; 1086 u16 rf_efuse_5g[2] = {PPG_PABIAS_5GA, PPG_PABIAS_5GB}; 1087 u8 pg_pa_bias = 0xff, path; 1088 1089 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1090 rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[path], 1091 &pg_pa_bias); 1092 if (pg_pa_bias == EFUSE_READ_FAIL) 1093 return; 1094 pg_pa_bias = FIELD_GET(PPG_PABIAS_MASK, pg_pa_bias); 1095 rtw_write_rf(rtwdev, path, 0x60, RF_PABIAS_2G_MASK, pg_pa_bias); 1096 } 1097 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1098 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path], 1099 &pg_pa_bias); 1100 pg_pa_bias = FIELD_GET(PPG_PABIAS_MASK, pg_pa_bias); 1101 rtw_write_rf(rtwdev, path, 0x60, RF_PABIAS_5G_MASK, pg_pa_bias); 1102 } 1103} 1104 1105static void rtw8822c_rf_init(struct rtw_dev *rtwdev) 1106{ 1107 rtw8822c_rf_dac_cal(rtwdev); 1108 rtw8822c_rf_x2_check(rtwdev); 1109 rtw8822c_thermal_trim(rtwdev); 1110 rtw8822c_power_trim(rtwdev); 1111 rtw8822c_pa_bias(rtwdev); 1112} 1113 1114static void rtw8822c_pwrtrack_init(struct rtw_dev *rtwdev) 1115{ 1116 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1117 u8 path; 1118 1119 for (path = RF_PATH_A; path < RTW_RF_PATH_MAX; path++) { 1120 dm_info->delta_power_index[path] = 0; 1121 ewma_thermal_init(&dm_info->avg_thermal[path]); 1122 dm_info->thermal_avg[path] = 0xff; 1123 } 1124 1125 dm_info->pwr_trk_triggered = false; 1126 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 1127 dm_info->thermal_meter_lck = rtwdev->efuse.thermal_meter_k; 1128} 1129 1130static void rtw8822c_phy_set_param(struct rtw_dev *rtwdev) 1131{ 1132 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1133 struct rtw_hal *hal = &rtwdev->hal; 1134 u8 crystal_cap; 1135 u8 cck_gi_u_bnd_msb = 0; 1136 u8 cck_gi_u_bnd_lsb = 0; 1137 u8 cck_gi_l_bnd_msb = 0; 1138 u8 cck_gi_l_bnd_lsb = 0; 1139 bool is_tx2_path; 1140 1141 /* power on BB/RF domain */ 1142 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, 1143 BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB); 1144 rtw_write8_set(rtwdev, REG_RF_CTRL, 1145 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 1146 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN); 1147 1148 /* disable low rate DPD */ 1149 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL); 1150 1151 /* pre init before header files config */ 1152 rtw8822c_header_file_init(rtwdev, true); 1153 1154 rtw_phy_load_tables(rtwdev); 1155 1156 crystal_cap = rtwdev->efuse.crystal_cap & 0x7f; 1157 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, 0xfffc00, 1158 crystal_cap | (crystal_cap << 7)); 1159 1160 /* post init after header files config */ 1161 rtw8822c_header_file_init(rtwdev, false); 1162 1163 is_tx2_path = false; 1164 rtw8822c_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx, 1165 is_tx2_path); 1166 rtw_phy_init(rtwdev); 1167 1168 cck_gi_u_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc000); 1169 cck_gi_u_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1aa8, 0xf0000); 1170 cck_gi_l_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc0); 1171 cck_gi_l_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1a70, 0x0f000000); 1172 1173 dm_info->cck_gi_u_bnd = ((cck_gi_u_bnd_msb << 4) | (cck_gi_u_bnd_lsb)); 1174 dm_info->cck_gi_l_bnd = ((cck_gi_l_bnd_msb << 4) | (cck_gi_l_bnd_lsb)); 1175 1176 rtw8822c_rf_init(rtwdev); 1177 rtw8822c_pwrtrack_init(rtwdev); 1178 1179 rtw_bf_phy_init(rtwdev); 1180} 1181 1182#define WLAN_TXQ_RPT_EN 0x1F 1183#define WLAN_SLOT_TIME 0x09 1184#define WLAN_PIFS_TIME 0x1C 1185#define WLAN_SIFS_CCK_CONT_TX 0x0A 1186#define WLAN_SIFS_OFDM_CONT_TX 0x0E 1187#define WLAN_SIFS_CCK_TRX 0x0A 1188#define WLAN_SIFS_OFDM_TRX 0x10 1189#define WLAN_NAV_MAX 0xC8 1190#define WLAN_RDG_NAV 0x05 1191#define WLAN_TXOP_NAV 0x1B 1192#define WLAN_CCK_RX_TSF 0x30 1193#define WLAN_OFDM_RX_TSF 0x30 1194#define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */ 1195#define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */ 1196#define WLAN_DRV_EARLY_INT 0x04 1197#define WLAN_BCN_CTRL_CLT0 0x10 1198#define WLAN_BCN_DMA_TIME 0x02 1199#define WLAN_BCN_MAX_ERR 0xFF 1200#define WLAN_SIFS_CCK_DUR_TUNE 0x0A 1201#define WLAN_SIFS_OFDM_DUR_TUNE 0x10 1202#define WLAN_SIFS_CCK_CTX 0x0A 1203#define WLAN_SIFS_CCK_IRX 0x0A 1204#define WLAN_SIFS_OFDM_CTX 0x0E 1205#define WLAN_SIFS_OFDM_IRX 0x0E 1206#define WLAN_EIFS_DUR_TUNE 0x40 1207#define WLAN_EDCA_VO_PARAM 0x002FA226 1208#define WLAN_EDCA_VI_PARAM 0x005EA328 1209#define WLAN_EDCA_BE_PARAM 0x005EA42B 1210#define WLAN_EDCA_BK_PARAM 0x0000A44F 1211 1212#define WLAN_RX_FILTER0 0xFFFFFFFF 1213#define WLAN_RX_FILTER2 0xFFFF 1214#define WLAN_RCR_CFG 0xE400220E 1215#define WLAN_RXPKT_MAX_SZ 12288 1216#define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9) 1217 1218#define WLAN_AMPDU_MAX_TIME 0x70 1219#define WLAN_RTS_LEN_TH 0xFF 1220#define WLAN_RTS_TX_TIME_TH 0x08 1221#define WLAN_MAX_AGG_PKT_LIMIT 0x3f 1222#define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x3f 1223#define WLAN_PRE_TXCNT_TIME_TH 0x1E0 1224#define FAST_EDCA_VO_TH 0x06 1225#define FAST_EDCA_VI_TH 0x06 1226#define FAST_EDCA_BE_TH 0x06 1227#define FAST_EDCA_BK_TH 0x06 1228#define WLAN_BAR_RETRY_LIMIT 0x01 1229#define WLAN_BAR_ACK_TYPE 0x05 1230#define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08 1231#define WLAN_RESP_TXRATE 0x84 1232#define WLAN_ACK_TO 0x21 1233#define WLAN_ACK_TO_CCK 0x6A 1234#define WLAN_DATA_RATE_FB_CNT_1_4 0x01000000 1235#define WLAN_DATA_RATE_FB_CNT_5_8 0x08070504 1236#define WLAN_RTS_RATE_FB_CNT_5_8 0x08070504 1237#define WLAN_DATA_RATE_FB_RATE0 0xFE01F010 1238#define WLAN_DATA_RATE_FB_RATE0_H 0x40000000 1239#define WLAN_RTS_RATE_FB_RATE1 0x003FF010 1240#define WLAN_RTS_RATE_FB_RATE1_H 0x40000000 1241#define WLAN_RTS_RATE_FB_RATE4 0x0600F010 1242#define WLAN_RTS_RATE_FB_RATE4_H 0x400003E0 1243#define WLAN_RTS_RATE_FB_RATE5 0x0600F015 1244#define WLAN_RTS_RATE_FB_RATE5_H 0x000000E0 1245#define WLAN_MULTI_ADDR 0xFFFFFFFF 1246 1247#define WLAN_TX_FUNC_CFG1 0x30 1248#define WLAN_TX_FUNC_CFG2 0x30 1249#define WLAN_MAC_OPT_NORM_FUNC1 0x98 1250#define WLAN_MAC_OPT_LB_FUNC1 0x80 1251#define WLAN_MAC_OPT_FUNC2 0xb0810041 1252#define WLAN_MAC_INT_MIG_CFG 0x33330000 1253 1254#define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \ 1255 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \ 1256 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \ 1257 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX)) 1258 1259#define WLAN_SIFS_DUR_TUNE (WLAN_SIFS_CCK_DUR_TUNE | \ 1260 (WLAN_SIFS_OFDM_DUR_TUNE << 8)) 1261 1262#define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\ 1263 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP)) 1264 1265#define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16)) 1266#define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8) 1267 1268#define MAC_CLK_SPEED 80 /* 80M */ 1269#define EFUSE_PCB_INFO_OFFSET 0xCA 1270 1271static int rtw8822c_mac_init(struct rtw_dev *rtwdev) 1272{ 1273 u8 value8; 1274 u16 value16; 1275 u32 value32; 1276 u16 pre_txcnt; 1277 1278 /* txq control */ 1279 value8 = rtw_read8(rtwdev, REG_FWHW_TXQ_CTRL); 1280 value8 |= (BIT(7) & ~BIT(1) & ~BIT(2)); 1281 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL, value8); 1282 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN); 1283 /* sifs control */ 1284 rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SIFS_DUR_TUNE); 1285 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG); 1286 rtw_write16(rtwdev, REG_RESP_SIFS_CCK, 1287 WLAN_SIFS_CCK_CTX | WLAN_SIFS_CCK_IRX << 8); 1288 rtw_write16(rtwdev, REG_RESP_SIFS_OFDM, 1289 WLAN_SIFS_OFDM_CTX | WLAN_SIFS_OFDM_IRX << 8); 1290 /* rate fallback control */ 1291 rtw_write32(rtwdev, REG_DARFRC, WLAN_DATA_RATE_FB_CNT_1_4); 1292 rtw_write32(rtwdev, REG_DARFRCH, WLAN_DATA_RATE_FB_CNT_5_8); 1293 rtw_write32(rtwdev, REG_RARFRCH, WLAN_RTS_RATE_FB_CNT_5_8); 1294 rtw_write32(rtwdev, REG_ARFR0, WLAN_DATA_RATE_FB_RATE0); 1295 rtw_write32(rtwdev, REG_ARFRH0, WLAN_DATA_RATE_FB_RATE0_H); 1296 rtw_write32(rtwdev, REG_ARFR1_V1, WLAN_RTS_RATE_FB_RATE1); 1297 rtw_write32(rtwdev, REG_ARFRH1_V1, WLAN_RTS_RATE_FB_RATE1_H); 1298 rtw_write32(rtwdev, REG_ARFR4, WLAN_RTS_RATE_FB_RATE4); 1299 rtw_write32(rtwdev, REG_ARFRH4, WLAN_RTS_RATE_FB_RATE4_H); 1300 rtw_write32(rtwdev, REG_ARFR5, WLAN_RTS_RATE_FB_RATE5); 1301 rtw_write32(rtwdev, REG_ARFRH5, WLAN_RTS_RATE_FB_RATE5_H); 1302 /* protocol configuration */ 1303 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); 1304 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); 1305 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT; 1306 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); 1307 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8)); 1308 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | 1309 (WLAN_MAX_AGG_PKT_LIMIT << 16) | 1310 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); 1311 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32); 1312 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2, 1313 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); 1314 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH); 1315 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH); 1316 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH); 1317 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH); 1318 /* close BA parser */ 1319 rtw_write8_clr(rtwdev, REG_LIFETIME_EN, BIT_BA_PARSER_EN); 1320 rtw_write32_clr(rtwdev, REG_RRSR, BITS_RRSR_RSC); 1321 1322 /* EDCA configuration */ 1323 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, WLAN_EDCA_VO_PARAM); 1324 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, WLAN_EDCA_VI_PARAM); 1325 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, WLAN_EDCA_BE_PARAM); 1326 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, WLAN_EDCA_BK_PARAM); 1327 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME); 1328 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8); 1329 rtw_write8_set(rtwdev, REG_RD_CTRL + 1, 1330 (BIT_DIS_TXOP_CFE | BIT_DIS_LSIG_CFE | 1331 BIT_DIS_STBC_CFE) >> 8); 1332 1333 /* MAC clock configuration */ 1334 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BIT_MAC_CLK_SEL); 1335 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED); 1336 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED); 1337 1338 rtw_write8_set(rtwdev, REG_MISC_CTRL, 1339 BIT_EN_FREE_CNT | BIT_DIS_SECOND_CCA); 1340 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0); 1341 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000); 1342 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 1343 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG); 1344 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); 1345 /* Set beacon cotnrol - enable TSF and other related functions */ 1346 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 1347 /* Set send beacon related registers */ 1348 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); 1349 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT); 1350 rtw_write8(rtwdev, REG_BCN_CTRL_CLINT0, WLAN_BCN_CTRL_CLT0); 1351 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 1352 rtw_write8(rtwdev, REG_BCN_MAX_ERR, WLAN_BCN_MAX_ERR); 1353 1354 /* WMAC configuration */ 1355 rtw_write32(rtwdev, REG_MAR, WLAN_MULTI_ADDR); 1356 rtw_write32(rtwdev, REG_MAR + 4, WLAN_MULTI_ADDR); 1357 rtw_write8(rtwdev, REG_BBPSF_CTRL + 2, WLAN_RESP_TXRATE); 1358 rtw_write8(rtwdev, REG_ACKTO, WLAN_ACK_TO); 1359 rtw_write8(rtwdev, REG_ACKTO_CCK, WLAN_ACK_TO_CCK); 1360 rtw_write16(rtwdev, REG_EIFS, WLAN_EIFS_DUR_TUNE); 1361 rtw_write8(rtwdev, REG_NAV_CTRL + 2, WLAN_NAV_MAX); 1362 rtw_write8(rtwdev, REG_WMAC_TRXPTCL_CTL_H + 2, WLAN_BAR_ACK_TYPE); 1363 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 1364 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 1365 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 1366 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); 1367 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2); 1368 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1); 1369 rtw_write32_set(rtwdev, REG_GENERAL_OPTION, BIT_DUMMY_FCS_READY_MASK_EN); 1370 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); 1371 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION_1, WLAN_MAC_OPT_NORM_FUNC1); 1372 1373 /* init low power */ 1374 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL + 2) & 0xF00F; 1375 value16 |= (BIT_RXGCK_VHT_FIFOTHR(1) | BIT_RXGCK_HT_FIFOTHR(1) | 1376 BIT_RXGCK_OFDM_FIFOTHR(1) | BIT_RXGCK_CCK_FIFOTHR(1)) >> 16; 1377 rtw_write16(rtwdev, REG_RXPSF_CTRL + 2, value16); 1378 value16 = 0; 1379 value16 = BIT_SET_RXPSF_PKTLENTHR(value16, 1); 1380 value16 |= BIT_RXPSF_CTRLEN | BIT_RXPSF_VHTCHKEN | BIT_RXPSF_HTCHKEN 1381 | BIT_RXPSF_OFDMCHKEN | BIT_RXPSF_CCKCHKEN 1382 | BIT_RXPSF_OFDMRST; 1383 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16); 1384 rtw_write32(rtwdev, REG_RXPSF_TYPE_CTRL, 0xFFFFFFFF); 1385 /* rx ignore configuration */ 1386 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL); 1387 value16 &= ~(BIT_RXPSF_MHCHKEN | BIT_RXPSF_CCKRST | 1388 BIT_RXPSF_CONT_ERRCHKEN); 1389 value16 = BIT_SET_RXPSF_ERRTHR(value16, 0x07); 1390 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16); 1391 1392 /* Interrupt migration configuration */ 1393 rtw_write32(rtwdev, REG_INT_MIG, WLAN_MAC_INT_MIG_CFG); 1394 1395 return 0; 1396} 1397 1398static void rtw8822c_rstb_3wire(struct rtw_dev *rtwdev, bool enable) 1399{ 1400 if (enable) { 1401 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x1); 1402 rtw_write32_mask(rtwdev, REG_ANAPAR_A, BIT_ANAPAR_UPDATE, 0x1); 1403 rtw_write32_mask(rtwdev, REG_ANAPAR_B, BIT_ANAPAR_UPDATE, 0x1); 1404 } else { 1405 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x0); 1406 } 1407} 1408 1409static void rtw8822c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 1410{ 1411#define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8)) 1412#define RF18_BAND_2G (0) 1413#define RF18_BAND_5G (BIT(16) | BIT(8)) 1414#define RF18_CHANNEL_MASK (MASKBYTE0) 1415#define RF18_RFSI_MASK (BIT(18) | BIT(17)) 1416#define RF18_RFSI_GE_CH80 (BIT(17)) 1417#define RF18_RFSI_GT_CH140 (BIT(18)) 1418#define RF18_BW_MASK (BIT(13) | BIT(12)) 1419#define RF18_BW_20M (BIT(13) | BIT(12)) 1420#define RF18_BW_40M (BIT(13)) 1421#define RF18_BW_80M (BIT(12)) 1422 1423 u32 rf_reg18 = 0; 1424 u32 rf_rxbb = 0; 1425 1426 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 1427 1428 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK | 1429 RF18_BW_MASK); 1430 1431 rf_reg18 |= (IS_CH_2G_BAND(channel) ? RF18_BAND_2G : RF18_BAND_5G); 1432 rf_reg18 |= (channel & RF18_CHANNEL_MASK); 1433 if (IS_CH_5G_BAND_4(channel)) 1434 rf_reg18 |= RF18_RFSI_GT_CH140; 1435 else if (IS_CH_5G_BAND_3(channel)) 1436 rf_reg18 |= RF18_RFSI_GE_CH80; 1437 1438 switch (bw) { 1439 case RTW_CHANNEL_WIDTH_5: 1440 case RTW_CHANNEL_WIDTH_10: 1441 case RTW_CHANNEL_WIDTH_20: 1442 default: 1443 rf_reg18 |= RF18_BW_20M; 1444 rf_rxbb = 0x18; 1445 break; 1446 case RTW_CHANNEL_WIDTH_40: 1447 /* RF bandwidth */ 1448 rf_reg18 |= RF18_BW_40M; 1449 rf_rxbb = 0x10; 1450 break; 1451 case RTW_CHANNEL_WIDTH_80: 1452 rf_reg18 |= RF18_BW_80M; 1453 rf_rxbb = 0x8; 1454 break; 1455 } 1456 1457 rtw8822c_rstb_3wire(rtwdev, false); 1458 1459 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x01); 1460 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, 0x1f, 0x12); 1461 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, 0xfffff, rf_rxbb); 1462 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x00); 1463 1464 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x01); 1465 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWA, 0x1f, 0x12); 1466 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWD0, 0xfffff, rf_rxbb); 1467 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x00); 1468 1469 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_reg18); 1470 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_reg18); 1471 1472 rtw8822c_rstb_3wire(rtwdev, true); 1473} 1474 1475static void rtw8822c_toggle_igi(struct rtw_dev *rtwdev) 1476{ 1477 u32 igi; 1478 1479 igi = rtw_read32_mask(rtwdev, REG_RXIGI, 0x7f); 1480 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi - 2); 1481 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi - 2); 1482 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi); 1483 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi); 1484} 1485 1486static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 1487 u8 primary_ch_idx) 1488{ 1489 if (IS_CH_2G_BAND(channel)) { 1490 rtw_write32_clr(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT); 1491 rtw_write32_set(rtwdev, REG_TXF4, BIT(20)); 1492 rtw_write32_clr(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN); 1493 rtw_write32_clr(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN); 1494 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0xF); 1495 1496 switch (bw) { 1497 case RTW_CHANNEL_WIDTH_20: 1498 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK, 1499 0x5); 1500 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK, 1501 0x5); 1502 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1503 0x6); 1504 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1505 0x6); 1506 break; 1507 case RTW_CHANNEL_WIDTH_40: 1508 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK, 1509 0x4); 1510 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK, 1511 0x4); 1512 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1513 0x0); 1514 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1515 0x0); 1516 break; 1517 } 1518 if (channel == 13 || channel == 14) 1519 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x969); 1520 else if (channel == 11 || channel == 12) 1521 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x96a); 1522 else 1523 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x9aa); 1524 if (channel == 14) { 1525 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x3da0); 1526 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD, 1527 0x4962c931); 1528 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x6aa3); 1529 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xaa7b); 1530 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xf3d7); 1531 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 0x0); 1532 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD, 1533 0xff012455); 1534 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 0xffff); 1535 } else { 1536 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x5284); 1537 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD, 1538 0x3e18fec8); 1539 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x0a88); 1540 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xacc4); 1541 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xc8b2); 1542 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 1543 0x00faf0de); 1544 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD, 1545 0x00122344); 1546 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 1547 0x0fffffff); 1548 } 1549 if (channel == 13) 1550 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3); 1551 else 1552 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x1); 1553 } else if (IS_CH_5G_BAND(channel)) { 1554 rtw_write32_set(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN); 1555 rtw_write32_set(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN); 1556 rtw_write32_set(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT); 1557 rtw_write32_clr(rtwdev, REG_TXF4, BIT(20)); 1558 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0x22); 1559 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3); 1560 if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) { 1561 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1562 0x1); 1563 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1564 0x1); 1565 } else if (IS_CH_5G_BAND_3(channel)) { 1566 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1567 0x2); 1568 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1569 0x2); 1570 } else if (IS_CH_5G_BAND_4(channel)) { 1571 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1572 0x3); 1573 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1574 0x3); 1575 } 1576 1577 if (channel >= 36 && channel <= 51) 1578 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x494); 1579 else if (channel >= 52 && channel <= 55) 1580 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x493); 1581 else if (channel >= 56 && channel <= 111) 1582 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x453); 1583 else if (channel >= 112 && channel <= 119) 1584 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x452); 1585 else if (channel >= 120 && channel <= 172) 1586 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x412); 1587 else if (channel >= 173 && channel <= 177) 1588 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x411); 1589 } 1590 1591 switch (bw) { 1592 case RTW_CHANNEL_WIDTH_20: 1593 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x19B); 1594 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 1595 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x0); 1596 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x7); 1597 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x6); 1598 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 1599 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1600 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 1601 break; 1602 case RTW_CHANNEL_WIDTH_40: 1603 rtw_write32_mask(rtwdev, REG_CCKSB, BIT(4), 1604 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0)); 1605 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x5); 1606 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0); 1607 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00, 1608 (primary_ch_idx | (primary_ch_idx << 4))); 1609 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x1); 1610 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1611 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1); 1612 break; 1613 case RTW_CHANNEL_WIDTH_80: 1614 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0xa); 1615 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0); 1616 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00, 1617 (primary_ch_idx | (primary_ch_idx << 4))); 1618 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x6); 1619 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1); 1620 break; 1621 case RTW_CHANNEL_WIDTH_5: 1622 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB); 1623 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 1624 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x1); 1625 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x4); 1626 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x4); 1627 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 1628 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1629 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 1630 break; 1631 case RTW_CHANNEL_WIDTH_10: 1632 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB); 1633 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 1634 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x2); 1635 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x6); 1636 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x5); 1637 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 1638 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1639 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 1640 break; 1641 } 1642} 1643 1644static void rtw8822c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 1645 u8 primary_chan_idx) 1646{ 1647 rtw8822c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 1648 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 1649 rtw8822c_set_channel_rf(rtwdev, channel, bw); 1650 rtw8822c_toggle_igi(rtwdev); 1651} 1652 1653static void rtw8822c_config_cck_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 1654{ 1655 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { 1656 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x0); 1657 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x0); 1658 } else if (rx_path == BB_PATH_AB) { 1659 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x1); 1660 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x1); 1661 } 1662 1663 if (rx_path == BB_PATH_A) 1664 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x0); 1665 else if (rx_path == BB_PATH_B) 1666 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x5); 1667 else if (rx_path == BB_PATH_AB) 1668 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x1); 1669} 1670 1671static void rtw8822c_config_ofdm_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 1672{ 1673 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { 1674 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x0); 1675 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x0); 1676 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x0); 1677 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x0); 1678 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x0); 1679 } else if (rx_path == BB_PATH_AB) { 1680 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x1); 1681 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x1); 1682 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x1); 1683 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x1); 1684 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x1); 1685 } 1686 1687 rtw_write32_mask(rtwdev, 0x824, 0x0f000000, rx_path); 1688 rtw_write32_mask(rtwdev, 0x824, 0x000f0000, rx_path); 1689} 1690 1691static void rtw8822c_config_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 1692{ 1693 rtw8822c_config_cck_rx_path(rtwdev, rx_path); 1694 rtw8822c_config_ofdm_rx_path(rtwdev, rx_path); 1695} 1696 1697static void rtw8822c_config_cck_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 1698 bool is_tx2_path) 1699{ 1700 if (tx_path == BB_PATH_A) { 1701 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); 1702 } else if (tx_path == BB_PATH_B) { 1703 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x4); 1704 } else { 1705 if (is_tx2_path) 1706 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0xc); 1707 else 1708 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); 1709 } 1710} 1711 1712static void rtw8822c_config_ofdm_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 1713 bool is_tx2_path) 1714{ 1715 if (tx_path == BB_PATH_A) { 1716 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x11); 1717 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0); 1718 } else if (tx_path == BB_PATH_B) { 1719 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x12); 1720 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0); 1721 } else { 1722 if (is_tx2_path) { 1723 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x33); 1724 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0404); 1725 } else { 1726 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x31); 1727 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400); 1728 } 1729 } 1730} 1731 1732static void rtw8822c_config_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 1733 bool is_tx2_path) 1734{ 1735 rtw8822c_config_cck_tx_path(rtwdev, tx_path, is_tx2_path); 1736 rtw8822c_config_ofdm_tx_path(rtwdev, tx_path, is_tx2_path); 1737} 1738 1739static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 1740 u8 rx_path, bool is_tx2_path) 1741{ 1742 if ((tx_path | rx_path) & BB_PATH_A) 1743 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x33312); 1744 else 1745 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x11111); 1746 if ((tx_path | rx_path) & BB_PATH_B) 1747 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x33312); 1748 else 1749 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x11111); 1750 1751 rtw8822c_config_rx_path(rtwdev, rx_path); 1752 rtw8822c_config_tx_path(rtwdev, tx_path, is_tx2_path); 1753 1754 rtw8822c_toggle_igi(rtwdev); 1755} 1756 1757static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 1758 struct rtw_rx_pkt_stat *pkt_stat) 1759{ 1760 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1761 u8 l_bnd, u_bnd; 1762 u8 gain_a, gain_b; 1763 s8 rx_power[RTW_RF_PATH_MAX]; 1764 s8 min_rx_power = -120; 1765 u8 rssi; 1766 int path; 1767 1768 rx_power[RF_PATH_A] = GET_PHY_STAT_P0_PWDB_A(phy_status); 1769 rx_power[RF_PATH_B] = GET_PHY_STAT_P0_PWDB_B(phy_status); 1770 l_bnd = dm_info->cck_gi_l_bnd; 1771 u_bnd = dm_info->cck_gi_u_bnd; 1772 gain_a = GET_PHY_STAT_P0_GAIN_A(phy_status); 1773 gain_b = GET_PHY_STAT_P0_GAIN_B(phy_status); 1774 if (gain_a < l_bnd) 1775 rx_power[RF_PATH_A] += (l_bnd - gain_a) << 1; 1776 else if (gain_a > u_bnd) 1777 rx_power[RF_PATH_A] -= (gain_a - u_bnd) << 1; 1778 if (gain_b < l_bnd) 1779 rx_power[RF_PATH_B] += (l_bnd - gain_b) << 1; 1780 else if (gain_b > u_bnd) 1781 rx_power[RF_PATH_B] -= (gain_b - u_bnd) << 1; 1782 1783 rx_power[RF_PATH_A] -= 110; 1784 rx_power[RF_PATH_B] -= 110; 1785 1786 pkt_stat->rx_power[RF_PATH_A] = rx_power[RF_PATH_A]; 1787 pkt_stat->rx_power[RF_PATH_B] = rx_power[RF_PATH_B]; 1788 1789 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { 1790 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1); 1791 dm_info->rssi[path] = rssi; 1792 } 1793 1794 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 1795 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 1796 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 1797 min_rx_power); 1798} 1799 1800static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 1801 struct rtw_rx_pkt_stat *pkt_stat) 1802{ 1803 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1804 u8 rxsc, bw; 1805 s8 min_rx_power = -120; 1806 s8 rx_evm; 1807 u8 evm_dbm = 0; 1808 u8 rssi; 1809 int path; 1810 1811 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 1812 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 1813 else 1814 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 1815 1816 if (rxsc >= 9 && rxsc <= 12) 1817 bw = RTW_CHANNEL_WIDTH_40; 1818 else if (rxsc >= 13) 1819 bw = RTW_CHANNEL_WIDTH_80; 1820 else 1821 bw = RTW_CHANNEL_WIDTH_20; 1822 1823 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 1824 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110; 1825 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2); 1826 pkt_stat->bw = bw; 1827 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A], 1828 pkt_stat->rx_power[RF_PATH_B], 1829 min_rx_power); 1830 1831 dm_info->curr_rx_rate = pkt_stat->rate; 1832 1833 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status); 1834 pkt_stat->rx_evm[RF_PATH_B] = GET_PHY_STAT_P1_RXEVM_B(phy_status); 1835 1836 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status); 1837 pkt_stat->rx_snr[RF_PATH_B] = GET_PHY_STAT_P1_RXSNR_B(phy_status); 1838 1839 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status); 1840 pkt_stat->cfo_tail[RF_PATH_B] = GET_PHY_STAT_P1_CFO_TAIL_B(phy_status); 1841 1842 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { 1843 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1); 1844 dm_info->rssi[path] = rssi; 1845 dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1; 1846 dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1; 1847 1848 rx_evm = pkt_stat->rx_evm[path]; 1849 1850 if (rx_evm < 0) { 1851 if (rx_evm == S8_MIN) 1852 evm_dbm = 0; 1853 else 1854 evm_dbm = ((u8)-rx_evm >> 1); 1855 } 1856 dm_info->rx_evm_dbm[path] = evm_dbm; 1857 } 1858} 1859 1860static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 1861 struct rtw_rx_pkt_stat *pkt_stat) 1862{ 1863 u8 page; 1864 1865 page = *phy_status & 0xf; 1866 1867 switch (page) { 1868 case 0: 1869 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 1870 break; 1871 case 1: 1872 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 1873 break; 1874 default: 1875 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 1876 return; 1877 } 1878} 1879 1880static void rtw8822c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 1881 struct rtw_rx_pkt_stat *pkt_stat, 1882 struct ieee80211_rx_status *rx_status) 1883{ 1884 struct ieee80211_hdr *hdr; 1885 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 1886 u8 *phy_status = NULL; 1887 1888 memset(pkt_stat, 0, sizeof(*pkt_stat)); 1889 1890 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 1891 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 1892 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 1893 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && 1894 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE; 1895 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 1896 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 1897 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 1898 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 1899 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 1900 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 1901 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); 1902 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 1903 1904 /* drv_info_sz is in unit of 8-bytes */ 1905 pkt_stat->drv_info_sz *= 8; 1906 1907 /* c2h cmd pkt's rx/phy status is not interested */ 1908 if (pkt_stat->is_c2h) 1909 return; 1910 1911 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 1912 pkt_stat->drv_info_sz); 1913 if (pkt_stat->phy_status) { 1914 phy_status = rx_desc + desc_sz + pkt_stat->shift; 1915 query_phy_status(rtwdev, phy_status, pkt_stat); 1916 } 1917 1918 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 1919} 1920 1921static void 1922rtw8822c_set_write_tx_power_ref(struct rtw_dev *rtwdev, u8 *tx_pwr_ref_cck, 1923 u8 *tx_pwr_ref_ofdm) 1924{ 1925 struct rtw_hal *hal = &rtwdev->hal; 1926 u32 txref_cck[2] = {0x18a0, 0x41a0}; 1927 u32 txref_ofdm[2] = {0x18e8, 0x41e8}; 1928 u8 path; 1929 1930 for (path = 0; path < hal->rf_path_num; path++) { 1931 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); 1932 rtw_write32_mask(rtwdev, txref_cck[path], 0x7f0000, 1933 tx_pwr_ref_cck[path]); 1934 } 1935 for (path = 0; path < hal->rf_path_num; path++) { 1936 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); 1937 rtw_write32_mask(rtwdev, txref_ofdm[path], 0x1fc00, 1938 tx_pwr_ref_ofdm[path]); 1939 } 1940} 1941 1942static void rtw8822c_set_tx_power_diff(struct rtw_dev *rtwdev, u8 rate, 1943 s8 *diff_idx) 1944{ 1945 u32 offset_txagc = 0x3a00; 1946 u8 rate_idx = rate & 0xfc; 1947 u8 pwr_idx[4]; 1948 u32 phy_pwr_idx; 1949 int i; 1950 1951 for (i = 0; i < 4; i++) 1952 pwr_idx[i] = diff_idx[i] & 0x7f; 1953 1954 phy_pwr_idx = pwr_idx[0] | 1955 (pwr_idx[1] << 8) | 1956 (pwr_idx[2] << 16) | 1957 (pwr_idx[3] << 24); 1958 1959 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0x0); 1960 rtw_write32_mask(rtwdev, offset_txagc + rate_idx, MASKDWORD, 1961 phy_pwr_idx); 1962} 1963 1964static void rtw8822c_set_tx_power_index(struct rtw_dev *rtwdev) 1965{ 1966 struct rtw_hal *hal = &rtwdev->hal; 1967 u8 rs, rate, j; 1968 u8 pwr_ref_cck[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATE11M], 1969 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATE11M]}; 1970 u8 pwr_ref_ofdm[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATEMCS7], 1971 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATEMCS7]}; 1972 s8 diff_a, diff_b; 1973 u8 pwr_a, pwr_b; 1974 s8 diff_idx[4]; 1975 1976 rtw8822c_set_write_tx_power_ref(rtwdev, pwr_ref_cck, pwr_ref_ofdm); 1977 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) { 1978 for (j = 0; j < rtw_rate_size[rs]; j++) { 1979 rate = rtw_rate_section[rs][j]; 1980 pwr_a = hal->tx_pwr_tbl[RF_PATH_A][rate]; 1981 pwr_b = hal->tx_pwr_tbl[RF_PATH_B][rate]; 1982 if (rs == 0) { 1983 diff_a = (s8)pwr_a - (s8)pwr_ref_cck[0]; 1984 diff_b = (s8)pwr_b - (s8)pwr_ref_cck[1]; 1985 } else { 1986 diff_a = (s8)pwr_a - (s8)pwr_ref_ofdm[0]; 1987 diff_b = (s8)pwr_b - (s8)pwr_ref_ofdm[1]; 1988 } 1989 diff_idx[rate % 4] = min(diff_a, diff_b); 1990 if (rate % 4 == 3) 1991 rtw8822c_set_tx_power_diff(rtwdev, rate - 3, 1992 diff_idx); 1993 } 1994 } 1995} 1996 1997static int rtw8822c_set_antenna(struct rtw_dev *rtwdev, 1998 u32 antenna_tx, 1999 u32 antenna_rx) 2000{ 2001 struct rtw_hal *hal = &rtwdev->hal; 2002 2003 switch (antenna_tx) { 2004 case BB_PATH_A: 2005 case BB_PATH_B: 2006 case BB_PATH_AB: 2007 break; 2008 default: 2009 rtw_info(rtwdev, "unsupported tx path 0x%x\n", antenna_tx); 2010 return -EINVAL; 2011 } 2012 2013 /* path B only is not available for RX */ 2014 switch (antenna_rx) { 2015 case BB_PATH_A: 2016 case BB_PATH_AB: 2017 break; 2018 default: 2019 rtw_info(rtwdev, "unsupported rx path 0x%x\n", antenna_rx); 2020 return -EINVAL; 2021 } 2022 2023 hal->antenna_tx = antenna_tx; 2024 hal->antenna_rx = antenna_rx; 2025 2026 rtw8822c_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false); 2027 2028 return 0; 2029} 2030 2031static void rtw8822c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 2032{ 2033 u8 ldo_pwr; 2034 2035 ldo_pwr = rtw_read8(rtwdev, REG_ANAPARLDO_POW_MAC); 2036 ldo_pwr = enable ? ldo_pwr | BIT_LDOE25_PON : ldo_pwr & ~BIT_LDOE25_PON; 2037 rtw_write8(rtwdev, REG_ANAPARLDO_POW_MAC, ldo_pwr); 2038} 2039 2040static void rtw8822c_false_alarm_statistics(struct rtw_dev *rtwdev) 2041{ 2042 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2043 u32 cck_enable; 2044 u32 cck_fa_cnt; 2045 u32 crc32_cnt; 2046 u32 cca32_cnt; 2047 u32 ofdm_fa_cnt; 2048 u32 ofdm_fa_cnt1, ofdm_fa_cnt2, ofdm_fa_cnt3, ofdm_fa_cnt4, ofdm_fa_cnt5; 2049 u16 parity_fail, rate_illegal, crc8_fail, mcs_fail, sb_search_fail, 2050 fast_fsync, crc8_fail_vhta, mcs_fail_vht; 2051 2052 cck_enable = rtw_read32(rtwdev, REG_ENCCK) & BIT_CCK_BLK_EN; 2053 cck_fa_cnt = rtw_read16(rtwdev, REG_CCK_FACNT); 2054 2055 ofdm_fa_cnt1 = rtw_read32(rtwdev, REG_OFDM_FACNT1); 2056 ofdm_fa_cnt2 = rtw_read32(rtwdev, REG_OFDM_FACNT2); 2057 ofdm_fa_cnt3 = rtw_read32(rtwdev, REG_OFDM_FACNT3); 2058 ofdm_fa_cnt4 = rtw_read32(rtwdev, REG_OFDM_FACNT4); 2059 ofdm_fa_cnt5 = rtw_read32(rtwdev, REG_OFDM_FACNT5); 2060 2061 parity_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt1); 2062 rate_illegal = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt2); 2063 crc8_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt2); 2064 crc8_fail_vhta = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt3); 2065 mcs_fail = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt4); 2066 mcs_fail_vht = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt4); 2067 fast_fsync = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt5); 2068 sb_search_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt5); 2069 2070 ofdm_fa_cnt = parity_fail + rate_illegal + crc8_fail + crc8_fail_vhta + 2071 mcs_fail + mcs_fail_vht + fast_fsync + sb_search_fail; 2072 2073 dm_info->cck_fa_cnt = cck_fa_cnt; 2074 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 2075 dm_info->total_fa_cnt = ofdm_fa_cnt; 2076 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0; 2077 2078 crc32_cnt = rtw_read32(rtwdev, 0x2c04); 2079 dm_info->cck_ok_cnt = crc32_cnt & 0xffff; 2080 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2081 crc32_cnt = rtw_read32(rtwdev, 0x2c14); 2082 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff; 2083 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2084 crc32_cnt = rtw_read32(rtwdev, 0x2c10); 2085 dm_info->ht_ok_cnt = crc32_cnt & 0xffff; 2086 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2087 crc32_cnt = rtw_read32(rtwdev, 0x2c0c); 2088 dm_info->vht_ok_cnt = crc32_cnt & 0xffff; 2089 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2090 2091 cca32_cnt = rtw_read32(rtwdev, 0x2c08); 2092 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16); 2093 dm_info->cck_cca_cnt = cca32_cnt & 0xffff; 2094 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; 2095 if (cck_enable) 2096 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; 2097 2098 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 0); 2099 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 2); 2100 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 0); 2101 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 2); 2102 2103 /* disable rx clk gating to reset counters */ 2104 rtw_write32_clr(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN); 2105 rtw_write32_set(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST); 2106 rtw_write32_clr(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST); 2107 rtw_write32_set(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN); 2108} 2109 2110static void rtw8822c_do_lck(struct rtw_dev *rtwdev) 2111{ 2112 u32 val; 2113 2114 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_CTRL, RFREG_MASK, 0x80010); 2115 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_PFD, RFREG_MASK, 0x1F0FA); 2116 fsleep(1); 2117 rtw_write_rf(rtwdev, RF_PATH_A, RF_AAC_CTRL, RFREG_MASK, 0x80000); 2118 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_AAC, RFREG_MASK, 0x80001); 2119 read_poll_timeout(rtw_read_rf, val, val != 0x1, 1000, 100000, 2120 true, rtwdev, RF_PATH_A, RF_AAC_CTRL, 0x1000); 2121 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_PFD, RFREG_MASK, 0x1F0F8); 2122 rtw_write_rf(rtwdev, RF_PATH_B, RF_SYN_CTRL, RFREG_MASK, 0x80010); 2123 2124 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x0f000); 2125 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x4f000); 2126 fsleep(1); 2127 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x0f000); 2128} 2129 2130static void rtw8822c_do_iqk(struct rtw_dev *rtwdev) 2131{ 2132 struct rtw_iqk_para para = {0}; 2133 u8 iqk_chk; 2134 int counter; 2135 2136 para.clear = 1; 2137 rtw_fw_do_iqk(rtwdev, ¶); 2138 2139 for (counter = 0; counter < 300; counter++) { 2140 iqk_chk = rtw_read8(rtwdev, REG_RPT_CIP); 2141 if (iqk_chk == 0xaa) 2142 break; 2143 msleep(20); 2144 } 2145 rtw_write8(rtwdev, REG_IQKSTAT, 0x0); 2146 2147 rtw_dbg(rtwdev, RTW_DBG_RFK, "iqk counter=%d\n", counter); 2148} 2149 2150/* for coex */ 2151static void rtw8822c_coex_cfg_init(struct rtw_dev *rtwdev) 2152{ 2153 /* enable TBTT nterrupt */ 2154 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 2155 2156 /* BT report packet sample rate */ 2157 /* 0x790[5:0]=0x5 */ 2158 rtw_write8_set(rtwdev, REG_BT_TDMA_TIME, 0x05); 2159 2160 /* enable BT counter statistics */ 2161 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); 2162 2163 /* enable PTA (3-wire function form BT side) */ 2164 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 2165 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3); 2166 2167 /* enable PTA (tx/rx signal form WiFi side) */ 2168 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 2169 /* wl tx signal to PTA not case EDCCA */ 2170 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN); 2171 /* GNT_BT=1 while select both */ 2172 rtw_write8_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY); 2173 /* BT_CCA = ~GNT_WL_BB, (not or GNT_BT_BB, LTE_Rx */ 2174 rtw_write8_clr(rtwdev, REG_DUMMY_PAGE4_V1, BIT_BTCCA_CTRL); 2175 2176 /* to avoid RF parameter error */ 2177 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, 0x40000); 2178} 2179 2180static void rtw8822c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 2181{ 2182 struct rtw_coex *coex = &rtwdev->coex; 2183 struct rtw_coex_stat *coex_stat = &coex->stat; 2184 struct rtw_efuse *efuse = &rtwdev->efuse; 2185 u32 rf_0x1; 2186 2187 if (coex_stat->gnt_workaround_state == coex_stat->wl_coex_mode) 2188 return; 2189 2190 coex_stat->gnt_workaround_state = coex_stat->wl_coex_mode; 2191 2192 if ((coex_stat->kt_ver == 0 && coex->under_5g) || coex->freerun) 2193 rf_0x1 = 0x40021; 2194 else 2195 rf_0x1 = 0x40000; 2196 2197 /* BT at S1 for Shared-Ant */ 2198 if (efuse->share_ant) 2199 rf_0x1 |= BIT(13); 2200 2201 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, rf_0x1); 2202 2203 /* WL-S0 2G RF TRX cannot be masked by GNT_BT 2204 * enable "WLS0 BB chage RF mode if GNT_BT = 1" for shared-antenna type 2205 * disable:0x1860[3] = 1, enable:0x1860[3] = 0 2206 * 2207 * enable "DAC off if GNT_WL = 0" for non-shared-antenna 2208 * disable 0x1c30[22] = 0, 2209 * enable: 0x1c30[22] = 1, 0x1c38[12] = 0, 0x1c38[28] = 1 2210 * 2211 * disable WL-S1 BB chage RF mode if GNT_BT 2212 * since RF TRx mask can do it 2213 */ 2214 rtw_write8_mask(rtwdev, 0x1c32, BIT(6), 1); 2215 rtw_write8_mask(rtwdev, 0x1c39, BIT(4), 0); 2216 rtw_write8_mask(rtwdev, 0x1c3b, BIT(4), 1); 2217 rtw_write8_mask(rtwdev, 0x4160, BIT(3), 1); 2218 2219 /* disable WL-S0 BB chage RF mode if wifi is at 5G, 2220 * or antenna path is separated 2221 */ 2222 if (coex_stat->wl_coex_mode == COEX_WLINK_5G || 2223 coex->under_5g || !efuse->share_ant) { 2224 if (coex_stat->kt_ver >= 3) { 2225 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0); 2226 rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 1); 2227 } else { 2228 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 1); 2229 } 2230 } else { 2231 /* shared-antenna */ 2232 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0); 2233 if (coex_stat->kt_ver >= 3) 2234 rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 0); 2235 } 2236} 2237 2238static void rtw8822c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 2239{ 2240 rtw_write8_mask(rtwdev, 0x66, BIT(4), 0); 2241 rtw_write8_mask(rtwdev, 0x67, BIT(0), 0); 2242 rtw_write8_mask(rtwdev, 0x42, BIT(3), 0); 2243 rtw_write8_mask(rtwdev, 0x65, BIT(7), 0); 2244 rtw_write8_mask(rtwdev, 0x73, BIT(3), 0); 2245} 2246 2247static void rtw8822c_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 2248{ 2249 struct rtw_coex *coex = &rtwdev->coex; 2250 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 2251 struct rtw_efuse *efuse = &rtwdev->efuse; 2252 2253 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; 2254 coex_rfe->ant_switch_polarity = 0; 2255 coex_rfe->ant_switch_exist = false; 2256 coex_rfe->ant_switch_with_bt = false; 2257 coex_rfe->ant_switch_diversity = false; 2258 2259 if (efuse->share_ant) 2260 coex_rfe->wlg_at_btg = true; 2261 else 2262 coex_rfe->wlg_at_btg = false; 2263 2264 /* disable LTE coex in wifi side */ 2265 rtw_coex_write_indirect_reg(rtwdev, 0x38, BIT_LTE_COEX_EN, 0x0); 2266 rtw_coex_write_indirect_reg(rtwdev, 0xa0, MASKLWORD, 0xffff); 2267 rtw_coex_write_indirect_reg(rtwdev, 0xa4, MASKLWORD, 0xffff); 2268} 2269 2270static void rtw8822c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 2271{ 2272 struct rtw_coex *coex = &rtwdev->coex; 2273 struct rtw_coex_dm *coex_dm = &coex->dm; 2274 2275 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 2276 return; 2277 2278 coex_dm->cur_wl_pwr_lvl = wl_pwr; 2279} 2280 2281static void rtw8822c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 2282{ 2283 struct rtw_coex *coex = &rtwdev->coex; 2284 struct rtw_coex_dm *coex_dm = &coex->dm; 2285 2286 if (low_gain == coex_dm->cur_wl_rx_low_gain_en) 2287 return; 2288 2289 coex_dm->cur_wl_rx_low_gain_en = low_gain; 2290 2291 if (coex_dm->cur_wl_rx_low_gain_en) { 2292 /* set Rx filter corner RCK offset */ 2293 rtw_write_rf(rtwdev, RF_PATH_A, 0xde, 0xfffff, 0x22); 2294 rtw_write_rf(rtwdev, RF_PATH_A, 0x1d, 0xfffff, 0x36); 2295 rtw_write_rf(rtwdev, RF_PATH_B, 0xde, 0xfffff, 0x22); 2296 rtw_write_rf(rtwdev, RF_PATH_B, 0x1d, 0xfffff, 0x36); 2297 } else { 2298 /* set Rx filter corner RCK offset */ 2299 rtw_write_rf(rtwdev, RF_PATH_A, 0xde, 0xfffff, 0x20); 2300 rtw_write_rf(rtwdev, RF_PATH_A, 0x1d, 0xfffff, 0x0); 2301 rtw_write_rf(rtwdev, RF_PATH_B, 0x1d, 0xfffff, 0x0); 2302 } 2303} 2304 2305static void rtw8822c_bf_enable_bfee_su(struct rtw_dev *rtwdev, 2306 struct rtw_vif *vif, 2307 struct rtw_bfee *bfee) 2308{ 2309 u8 csi_rsc = 0; 2310 u32 tmp6dc; 2311 2312 rtw_bf_enable_bfee_su(rtwdev, vif, bfee); 2313 2314 tmp6dc = rtw_read32(rtwdev, REG_BBPSF_CTRL) | 2315 BIT_WMAC_USE_NDPARATE | 2316 (csi_rsc << 13); 2317 if (vif->net_type == RTW_NET_AP_MODE) 2318 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc | BIT(12)); 2319 else 2320 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc & ~BIT(12)); 2321 2322 rtw_write32(rtwdev, REG_CSI_RRSR, 0x550); 2323} 2324 2325static void rtw8822c_bf_config_bfee_su(struct rtw_dev *rtwdev, 2326 struct rtw_vif *vif, 2327 struct rtw_bfee *bfee, bool enable) 2328{ 2329 if (enable) 2330 rtw8822c_bf_enable_bfee_su(rtwdev, vif, bfee); 2331 else 2332 rtw_bf_remove_bfee_su(rtwdev, bfee); 2333} 2334 2335static void rtw8822c_bf_config_bfee_mu(struct rtw_dev *rtwdev, 2336 struct rtw_vif *vif, 2337 struct rtw_bfee *bfee, bool enable) 2338{ 2339 if (enable) 2340 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee); 2341 else 2342 rtw_bf_remove_bfee_mu(rtwdev, bfee); 2343} 2344 2345static void rtw8822c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif, 2346 struct rtw_bfee *bfee, bool enable) 2347{ 2348 if (bfee->role == RTW_BFEE_SU) 2349 rtw8822c_bf_config_bfee_su(rtwdev, vif, bfee, enable); 2350 else if (bfee->role == RTW_BFEE_MU) 2351 rtw8822c_bf_config_bfee_mu(rtwdev, vif, bfee, enable); 2352 else 2353 rtw_warn(rtwdev, "wrong bfee role\n"); 2354} 2355 2356struct dpk_cfg_pair { 2357 u32 addr; 2358 u32 bitmask; 2359 u32 data; 2360}; 2361 2362void rtw8822c_parse_tbl_dpk(struct rtw_dev *rtwdev, 2363 const struct rtw_table *tbl) 2364{ 2365 const struct dpk_cfg_pair *p = tbl->data; 2366 const struct dpk_cfg_pair *end = p + tbl->size / 3; 2367 2368 BUILD_BUG_ON(sizeof(struct dpk_cfg_pair) != sizeof(u32) * 3); 2369 2370 for (; p < end; p++) 2371 rtw_write32_mask(rtwdev, p->addr, p->bitmask, p->data); 2372} 2373 2374static void rtw8822c_dpk_set_gnt_wl(struct rtw_dev *rtwdev, bool is_before_k) 2375{ 2376 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2377 2378 if (is_before_k) { 2379 dpk_info->gnt_control = rtw_read32(rtwdev, 0x70); 2380 dpk_info->gnt_value = rtw_coex_read_indirect_reg(rtwdev, 0x38); 2381 rtw_write32_mask(rtwdev, 0x70, BIT(26), 0x1); 2382 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKBYTE1, 0x77); 2383 } else { 2384 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKDWORD, 2385 dpk_info->gnt_value); 2386 rtw_write32(rtwdev, 0x70, dpk_info->gnt_control); 2387 } 2388} 2389 2390static void 2391rtw8822c_dpk_restore_registers(struct rtw_dev *rtwdev, u32 reg_num, 2392 struct rtw_backup_info *bckp) 2393{ 2394 rtw_restore_reg(rtwdev, bckp, reg_num); 2395 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 2396 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0x4); 2397} 2398 2399static void 2400rtw8822c_dpk_backup_registers(struct rtw_dev *rtwdev, u32 *reg, 2401 u32 reg_num, struct rtw_backup_info *bckp) 2402{ 2403 u32 i; 2404 2405 for (i = 0; i < reg_num; i++) { 2406 bckp[i].len = 4; 2407 bckp[i].reg = reg[i]; 2408 bckp[i].val = rtw_read32(rtwdev, reg[i]); 2409 } 2410} 2411 2412static void rtw8822c_dpk_backup_rf_registers(struct rtw_dev *rtwdev, 2413 u32 *rf_reg, 2414 u32 rf_reg_bak[][2]) 2415{ 2416 u32 i; 2417 2418 for (i = 0; i < DPK_RF_REG_NUM; i++) { 2419 rf_reg_bak[i][RF_PATH_A] = rtw_read_rf(rtwdev, RF_PATH_A, 2420 rf_reg[i], RFREG_MASK); 2421 rf_reg_bak[i][RF_PATH_B] = rtw_read_rf(rtwdev, RF_PATH_B, 2422 rf_reg[i], RFREG_MASK); 2423 } 2424} 2425 2426static void rtw8822c_dpk_reload_rf_registers(struct rtw_dev *rtwdev, 2427 u32 *rf_reg, 2428 u32 rf_reg_bak[][2]) 2429{ 2430 u32 i; 2431 2432 for (i = 0; i < DPK_RF_REG_NUM; i++) { 2433 rtw_write_rf(rtwdev, RF_PATH_A, rf_reg[i], RFREG_MASK, 2434 rf_reg_bak[i][RF_PATH_A]); 2435 rtw_write_rf(rtwdev, RF_PATH_B, rf_reg[i], RFREG_MASK, 2436 rf_reg_bak[i][RF_PATH_B]); 2437 } 2438} 2439 2440static void rtw8822c_dpk_information(struct rtw_dev *rtwdev) 2441{ 2442 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2443 u32 reg; 2444 u8 band_shift; 2445 2446 reg = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 2447 2448 band_shift = FIELD_GET(BIT(16), reg); 2449 dpk_info->dpk_band = 1 << band_shift; 2450 dpk_info->dpk_ch = FIELD_GET(0xff, reg); 2451 dpk_info->dpk_bw = FIELD_GET(0x3000, reg); 2452} 2453 2454static void rtw8822c_dpk_rxbb_dc_cal(struct rtw_dev *rtwdev, u8 path) 2455{ 2456 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800); 2457 udelay(5); 2458 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84801); 2459 usleep_range(600, 610); 2460 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800); 2461} 2462 2463static u8 rtw8822c_dpk_dc_corr_check(struct rtw_dev *rtwdev, u8 path) 2464{ 2465 u16 dc_i, dc_q; 2466 u8 corr_val, corr_idx; 2467 2468 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000900f0); 2469 dc_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16)); 2470 dc_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(11, 0)); 2471 2472 if (dc_i & BIT(11)) 2473 dc_i = 0x1000 - dc_i; 2474 if (dc_q & BIT(11)) 2475 dc_q = 0x1000 - dc_q; 2476 2477 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); 2478 corr_idx = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(7, 0)); 2479 corr_val = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(15, 8)); 2480 2481 if (dc_i > 200 || dc_q > 200 || corr_idx < 40 || corr_idx > 65) 2482 return 1; 2483 else 2484 return 0; 2485 2486} 2487 2488static void rtw8822c_dpk_tx_pause(struct rtw_dev *rtwdev) 2489{ 2490 u8 reg_a, reg_b; 2491 u16 count = 0; 2492 2493 rtw_write8(rtwdev, 0x522, 0xff); 2494 rtw_write32_mask(rtwdev, 0x1e70, 0xf, 0x2); 2495 2496 do { 2497 reg_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A, 0x00, 0xf0000); 2498 reg_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B, 0x00, 0xf0000); 2499 udelay(2); 2500 count++; 2501 } while ((reg_a == 2 || reg_b == 2) && count < 2500); 2502} 2503 2504static void rtw8822c_dpk_mac_bb_setting(struct rtw_dev *rtwdev) 2505{ 2506 rtw8822c_dpk_tx_pause(rtwdev); 2507 rtw_load_table(rtwdev, &rtw8822c_dpk_mac_bb_tbl); 2508} 2509 2510static void rtw8822c_dpk_afe_setting(struct rtw_dev *rtwdev, bool is_do_dpk) 2511{ 2512 if (is_do_dpk) 2513 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_is_dpk_tbl); 2514 else 2515 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_no_dpk_tbl); 2516} 2517 2518static void rtw8822c_dpk_pre_setting(struct rtw_dev *rtwdev) 2519{ 2520 u8 path; 2521 2522 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 2523 rtw_write_rf(rtwdev, path, RF_RXAGC_OFFSET, RFREG_MASK, 0x0); 2524 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1)); 2525 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) 2526 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f100000); 2527 else 2528 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f0d0000); 2529 rtw_write32_mask(rtwdev, REG_DPD_LUT0, BIT_GLOSS_DB, 0x4); 2530 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x3); 2531 } 2532 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 2533 rtw_write32(rtwdev, REG_DPD_CTL11, 0x3b23170b); 2534 rtw_write32(rtwdev, REG_DPD_CTL12, 0x775f5347); 2535} 2536 2537static u32 rtw8822c_dpk_rf_setting(struct rtw_dev *rtwdev, u8 path) 2538{ 2539 u32 ori_txbb; 2540 2541 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50017); 2542 ori_txbb = rtw_read_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK); 2543 2544 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1); 2545 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_PWR_TRIM, 0x1); 2546 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_TX_OFFSET_VAL, 0x0); 2547 rtw_write_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK, ori_txbb); 2548 2549 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) { 2550 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_LB_ATT, 0x1); 2551 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x0); 2552 } else { 2553 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x0); 2554 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x6); 2555 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1); 2556 rtw_write_rf(rtwdev, path, RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0); 2557 } 2558 2559 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf); 2560 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1); 2561 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0); 2562 2563 if (rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80) 2564 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x2); 2565 else 2566 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1); 2567 2568 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT(1), 0x1); 2569 2570 usleep_range(100, 110); 2571 2572 return ori_txbb & 0x1f; 2573} 2574 2575static u16 rtw8822c_dpk_get_cmd(struct rtw_dev *rtwdev, u8 action, u8 path) 2576{ 2577 u16 cmd; 2578 u8 bw = rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80 ? 2 : 0; 2579 2580 switch (action) { 2581 case RTW_DPK_GAIN_LOSS: 2582 cmd = 0x14 + path; 2583 break; 2584 case RTW_DPK_DO_DPK: 2585 cmd = 0x16 + path + bw; 2586 break; 2587 case RTW_DPK_DPK_ON: 2588 cmd = 0x1a + path; 2589 break; 2590 case RTW_DPK_DAGC: 2591 cmd = 0x1c + path + bw; 2592 break; 2593 default: 2594 return 0; 2595 } 2596 2597 return (cmd << 8) | 0x48; 2598} 2599 2600static u8 rtw8822c_dpk_one_shot(struct rtw_dev *rtwdev, u8 path, u8 action) 2601{ 2602 u16 dpk_cmd; 2603 u8 result = 0; 2604 2605 rtw8822c_dpk_set_gnt_wl(rtwdev, true); 2606 2607 if (action == RTW_DPK_CAL_PWR) { 2608 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x1); 2609 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x0); 2610 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0); 2611 msleep(10); 2612 if (!check_hw_ready(rtwdev, REG_STAT_RPT, BIT(31), 0x1)) { 2613 result = 1; 2614 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n"); 2615 } 2616 } else { 2617 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 2618 0x8 | (path << 1)); 2619 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9); 2620 2621 dpk_cmd = rtw8822c_dpk_get_cmd(rtwdev, action, path); 2622 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd); 2623 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd + 1); 2624 msleep(10); 2625 if (!check_hw_ready(rtwdev, 0x2d9c, 0xff, 0x55)) { 2626 result = 1; 2627 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n"); 2628 } 2629 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 2630 0x8 | (path << 1)); 2631 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0); 2632 } 2633 2634 rtw8822c_dpk_set_gnt_wl(rtwdev, false); 2635 2636 rtw_write8(rtwdev, 0x1b10, 0x0); 2637 2638 return result; 2639} 2640 2641static u16 rtw8822c_dpk_dgain_read(struct rtw_dev *rtwdev, u8 path) 2642{ 2643 u16 dgain; 2644 2645 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 2646 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, 0x00ff0000, 0x0); 2647 2648 dgain = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16)); 2649 2650 return dgain; 2651} 2652 2653static u8 rtw8822c_dpk_thermal_read(struct rtw_dev *rtwdev, u8 path) 2654{ 2655 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1); 2656 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x0); 2657 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1); 2658 udelay(15); 2659 2660 return (u8)rtw_read_rf(rtwdev, path, RF_T_METER, 0x0007e); 2661} 2662 2663static u32 rtw8822c_dpk_pas_read(struct rtw_dev *rtwdev, u8 path) 2664{ 2665 u32 i_val, q_val; 2666 2667 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1)); 2668 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0); 2669 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060001); 2670 rtw_write32(rtwdev, 0x1b4c, 0x00000000); 2671 rtw_write32(rtwdev, 0x1b4c, 0x00080000); 2672 2673 q_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD); 2674 i_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD); 2675 2676 if (i_val & BIT(15)) 2677 i_val = 0x10000 - i_val; 2678 if (q_val & BIT(15)) 2679 q_val = 0x10000 - q_val; 2680 2681 rtw_write32(rtwdev, 0x1b4c, 0x00000000); 2682 2683 return i_val * i_val + q_val * q_val; 2684} 2685 2686static u32 rtw8822c_psd_log2base(u32 val) 2687{ 2688 u32 tmp, val_integerd_b, tindex; 2689 u32 result, val_fractiond_b; 2690 u32 table_fraction[21] = {0, 432, 332, 274, 232, 200, 174, 2691 151, 132, 115, 100, 86, 74, 62, 51, 2692 42, 32, 23, 15, 7, 0}; 2693 2694 if (val == 0) 2695 return 0; 2696 2697 val_integerd_b = __fls(val) + 1; 2698 2699 tmp = (val * 100) / (1 << val_integerd_b); 2700 tindex = tmp / 5; 2701 2702 if (tindex >= ARRAY_SIZE(table_fraction)) 2703 tindex = ARRAY_SIZE(table_fraction) - 1; 2704 2705 val_fractiond_b = table_fraction[tindex]; 2706 2707 result = val_integerd_b * 100 - val_fractiond_b; 2708 2709 return result; 2710} 2711 2712static u8 rtw8822c_dpk_gainloss_result(struct rtw_dev *rtwdev, u8 path) 2713{ 2714 u8 result; 2715 2716 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 2717 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x1); 2718 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060000); 2719 2720 result = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, 0x000000f0); 2721 2722 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0); 2723 2724 return result; 2725} 2726 2727static u8 rtw8822c_dpk_agc_gain_chk(struct rtw_dev *rtwdev, u8 path, 2728 u8 limited_pga) 2729{ 2730 u8 result = 0; 2731 u16 dgain; 2732 2733 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC); 2734 dgain = rtw8822c_dpk_dgain_read(rtwdev, path); 2735 2736 if (dgain > 1535 && !limited_pga) 2737 return RTW_DPK_GAIN_LESS; 2738 else if (dgain < 768 && !limited_pga) 2739 return RTW_DPK_GAIN_LARGE; 2740 else 2741 return result; 2742} 2743 2744static u8 rtw8822c_dpk_agc_loss_chk(struct rtw_dev *rtwdev, u8 path) 2745{ 2746 u32 loss, loss_db; 2747 2748 loss = rtw8822c_dpk_pas_read(rtwdev, path); 2749 if (loss < 0x4000000) 2750 return RTW_DPK_GL_LESS; 2751 loss_db = 3 * rtw8822c_psd_log2base(loss >> 13) - 3870; 2752 2753 if (loss_db > 1000) 2754 return RTW_DPK_GL_LARGE; 2755 else if (loss_db < 250) 2756 return RTW_DPK_GL_LESS; 2757 else 2758 return RTW_DPK_AGC_OUT; 2759} 2760 2761struct rtw8822c_dpk_data { 2762 u8 txbb; 2763 u8 pga; 2764 u8 limited_pga; 2765 u8 agc_cnt; 2766 bool loss_only; 2767 bool gain_only; 2768 u8 path; 2769}; 2770 2771static u8 rtw8822c_gain_check_state(struct rtw_dev *rtwdev, 2772 struct rtw8822c_dpk_data *data) 2773{ 2774 u8 state; 2775 2776 data->txbb = (u8)rtw_read_rf(rtwdev, data->path, RF_TX_GAIN, 2777 BIT_GAIN_TXBB); 2778 data->pga = (u8)rtw_read_rf(rtwdev, data->path, RF_MODE_TRXAGC, 2779 BIT_RXAGC); 2780 2781 if (data->loss_only) { 2782 state = RTW_DPK_LOSS_CHECK; 2783 goto check_end; 2784 } 2785 2786 state = rtw8822c_dpk_agc_gain_chk(rtwdev, data->path, 2787 data->limited_pga); 2788 if (state == RTW_DPK_GAIN_CHECK && data->gain_only) 2789 state = RTW_DPK_AGC_OUT; 2790 else if (state == RTW_DPK_GAIN_CHECK) 2791 state = RTW_DPK_LOSS_CHECK; 2792 2793check_end: 2794 data->agc_cnt++; 2795 if (data->agc_cnt >= 6) 2796 state = RTW_DPK_AGC_OUT; 2797 2798 return state; 2799} 2800 2801static u8 rtw8822c_gain_large_state(struct rtw_dev *rtwdev, 2802 struct rtw8822c_dpk_data *data) 2803{ 2804 u8 pga = data->pga; 2805 2806 if (pga > 0xe) 2807 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc); 2808 else if (pga > 0xb && pga < 0xf) 2809 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0); 2810 else if (pga < 0xc) 2811 data->limited_pga = 1; 2812 2813 return RTW_DPK_GAIN_CHECK; 2814} 2815 2816static u8 rtw8822c_gain_less_state(struct rtw_dev *rtwdev, 2817 struct rtw8822c_dpk_data *data) 2818{ 2819 u8 pga = data->pga; 2820 2821 if (pga < 0xc) 2822 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc); 2823 else if (pga > 0xb && pga < 0xf) 2824 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf); 2825 else if (pga > 0xe) 2826 data->limited_pga = 1; 2827 2828 return RTW_DPK_GAIN_CHECK; 2829} 2830 2831static u8 rtw8822c_gl_state(struct rtw_dev *rtwdev, 2832 struct rtw8822c_dpk_data *data, u8 is_large) 2833{ 2834 u8 txbb_bound[] = {0x1f, 0}; 2835 2836 if (data->txbb == txbb_bound[is_large]) 2837 return RTW_DPK_AGC_OUT; 2838 2839 if (is_large == 1) 2840 data->txbb -= 2; 2841 else 2842 data->txbb += 3; 2843 2844 rtw_write_rf(rtwdev, data->path, RF_TX_GAIN, BIT_GAIN_TXBB, data->txbb); 2845 data->limited_pga = 0; 2846 2847 return RTW_DPK_GAIN_CHECK; 2848} 2849 2850static u8 rtw8822c_gl_large_state(struct rtw_dev *rtwdev, 2851 struct rtw8822c_dpk_data *data) 2852{ 2853 return rtw8822c_gl_state(rtwdev, data, 1); 2854} 2855 2856static u8 rtw8822c_gl_less_state(struct rtw_dev *rtwdev, 2857 struct rtw8822c_dpk_data *data) 2858{ 2859 return rtw8822c_gl_state(rtwdev, data, 0); 2860} 2861 2862static u8 rtw8822c_loss_check_state(struct rtw_dev *rtwdev, 2863 struct rtw8822c_dpk_data *data) 2864{ 2865 u8 path = data->path; 2866 u8 state; 2867 2868 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_GAIN_LOSS); 2869 state = rtw8822c_dpk_agc_loss_chk(rtwdev, path); 2870 2871 return state; 2872} 2873 2874static u8 (*dpk_state[])(struct rtw_dev *rtwdev, 2875 struct rtw8822c_dpk_data *data) = { 2876 rtw8822c_gain_check_state, rtw8822c_gain_large_state, 2877 rtw8822c_gain_less_state, rtw8822c_gl_large_state, 2878 rtw8822c_gl_less_state, rtw8822c_loss_check_state }; 2879 2880static u8 rtw8822c_dpk_pas_agc(struct rtw_dev *rtwdev, u8 path, 2881 bool gain_only, bool loss_only) 2882{ 2883 struct rtw8822c_dpk_data data = {0}; 2884 u8 (*func)(struct rtw_dev *rtwdev, struct rtw8822c_dpk_data *data); 2885 u8 state = RTW_DPK_GAIN_CHECK; 2886 2887 data.loss_only = loss_only; 2888 data.gain_only = gain_only; 2889 data.path = path; 2890 2891 for (;;) { 2892 func = dpk_state[state]; 2893 state = func(rtwdev, &data); 2894 if (state == RTW_DPK_AGC_OUT) 2895 break; 2896 } 2897 2898 return data.txbb; 2899} 2900 2901static bool rtw8822c_dpk_coef_iq_check(struct rtw_dev *rtwdev, 2902 u16 coef_i, u16 coef_q) 2903{ 2904 if (coef_i == 0x1000 || coef_i == 0x0fff || 2905 coef_q == 0x1000 || coef_q == 0x0fff) 2906 return true; 2907 2908 return false; 2909} 2910 2911static u32 rtw8822c_dpk_coef_transfer(struct rtw_dev *rtwdev) 2912{ 2913 u32 reg = 0; 2914 u16 coef_i = 0, coef_q = 0; 2915 2916 reg = rtw_read32(rtwdev, REG_STAT_RPT); 2917 2918 coef_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD) & 0x1fff; 2919 coef_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD) & 0x1fff; 2920 2921 coef_q = ((0x2000 - coef_q) & 0x1fff) - 1; 2922 2923 reg = (coef_i << 16) | coef_q; 2924 2925 return reg; 2926} 2927 2928static const u32 rtw8822c_dpk_get_coef_tbl[] = { 2929 0x000400f0, 0x040400f0, 0x080400f0, 0x010400f0, 0x050400f0, 2930 0x090400f0, 0x020400f0, 0x060400f0, 0x0a0400f0, 0x030400f0, 2931 0x070400f0, 0x0b0400f0, 0x0c0400f0, 0x100400f0, 0x0d0400f0, 2932 0x110400f0, 0x0e0400f0, 0x120400f0, 0x0f0400f0, 0x130400f0, 2933}; 2934 2935static void rtw8822c_dpk_coef_tbl_apply(struct rtw_dev *rtwdev, u8 path) 2936{ 2937 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2938 int i; 2939 2940 for (i = 0; i < 20; i++) { 2941 rtw_write32(rtwdev, REG_RXSRAM_CTL, 2942 rtw8822c_dpk_get_coef_tbl[i]); 2943 dpk_info->coef[path][i] = rtw8822c_dpk_coef_transfer(rtwdev); 2944 } 2945} 2946 2947static void rtw8822c_dpk_get_coef(struct rtw_dev *rtwdev, u8 path) 2948{ 2949 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c); 2950 2951 if (path == RF_PATH_A) { 2952 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x0); 2953 rtw_write32(rtwdev, REG_DPD_CTL0_S0, 0x30000080); 2954 } else if (path == RF_PATH_B) { 2955 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x1); 2956 rtw_write32(rtwdev, REG_DPD_CTL0_S1, 0x30000080); 2957 } 2958 2959 rtw8822c_dpk_coef_tbl_apply(rtwdev, path); 2960} 2961 2962static u8 rtw8822c_dpk_coef_read(struct rtw_dev *rtwdev, u8 path) 2963{ 2964 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2965 u8 addr, result = 1; 2966 u16 coef_i, coef_q; 2967 2968 for (addr = 0; addr < 20; addr++) { 2969 coef_i = FIELD_GET(0x1fff0000, dpk_info->coef[path][addr]); 2970 coef_q = FIELD_GET(0x1fff, dpk_info->coef[path][addr]); 2971 2972 if (rtw8822c_dpk_coef_iq_check(rtwdev, coef_i, coef_q)) { 2973 result = 0; 2974 break; 2975 } 2976 } 2977 return result; 2978} 2979 2980static void rtw8822c_dpk_coef_write(struct rtw_dev *rtwdev, u8 path, u8 result) 2981{ 2982 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2983 u16 reg[DPK_RF_PATH_NUM] = {0x1b0c, 0x1b64}; 2984 u32 coef; 2985 u8 addr; 2986 2987 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c); 2988 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); 2989 2990 for (addr = 0; addr < 20; addr++) { 2991 if (result == 0) { 2992 if (addr == 3) 2993 coef = 0x04001fff; 2994 else 2995 coef = 0x00001fff; 2996 } else { 2997 coef = dpk_info->coef[path][addr]; 2998 } 2999 rtw_write32(rtwdev, reg[path] + addr * 4, coef); 3000 } 3001} 3002 3003static void rtw8822c_dpk_fill_result(struct rtw_dev *rtwdev, u32 dpk_txagc, 3004 u8 path, u8 result) 3005{ 3006 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3007 3008 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3009 3010 if (result) 3011 rtw_write8(rtwdev, REG_DPD_AGC, (u8)(dpk_txagc - 6)); 3012 else 3013 rtw_write8(rtwdev, REG_DPD_AGC, 0x00); 3014 3015 dpk_info->result[path] = result; 3016 dpk_info->dpk_txagc[path] = rtw_read8(rtwdev, REG_DPD_AGC); 3017 3018 rtw8822c_dpk_coef_write(rtwdev, path, result); 3019} 3020 3021static u32 rtw8822c_dpk_gainloss(struct rtw_dev *rtwdev, u8 path) 3022{ 3023 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3024 u8 tx_agc, tx_bb, ori_txbb, ori_txagc, tx_agc_search, t1, t2; 3025 3026 ori_txbb = rtw8822c_dpk_rf_setting(rtwdev, path); 3027 ori_txagc = (u8)rtw_read_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_TXAGC); 3028 3029 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path); 3030 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC); 3031 rtw8822c_dpk_dgain_read(rtwdev, path); 3032 3033 if (rtw8822c_dpk_dc_corr_check(rtwdev, path)) { 3034 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path); 3035 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC); 3036 rtw8822c_dpk_dc_corr_check(rtwdev, path); 3037 } 3038 3039 t1 = rtw8822c_dpk_thermal_read(rtwdev, path); 3040 tx_bb = rtw8822c_dpk_pas_agc(rtwdev, path, false, true); 3041 tx_agc_search = rtw8822c_dpk_gainloss_result(rtwdev, path); 3042 3043 if (tx_bb < tx_agc_search) 3044 tx_bb = 0; 3045 else 3046 tx_bb = tx_bb - tx_agc_search; 3047 3048 rtw_write_rf(rtwdev, path, RF_TX_GAIN, BIT_GAIN_TXBB, tx_bb); 3049 3050 tx_agc = ori_txagc - (ori_txbb - tx_bb); 3051 3052 t2 = rtw8822c_dpk_thermal_read(rtwdev, path); 3053 3054 dpk_info->thermal_dpk_delta[path] = abs(t2 - t1); 3055 3056 return tx_agc; 3057} 3058 3059static u8 rtw8822c_dpk_by_path(struct rtw_dev *rtwdev, u32 tx_agc, u8 path) 3060{ 3061 u8 result; 3062 3063 result = rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DO_DPK); 3064 3065 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3066 3067 result = result | (u8)rtw_read32_mask(rtwdev, REG_DPD_CTL1_S0, BIT(26)); 3068 3069 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x33e14); 3070 3071 rtw8822c_dpk_get_coef(rtwdev, path); 3072 3073 return result; 3074} 3075 3076static void rtw8822c_dpk_cal_gs(struct rtw_dev *rtwdev, u8 path) 3077{ 3078 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3079 u32 tmp_gs = 0; 3080 3081 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3082 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_BYPASS_DPD, 0x0); 3083 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 3084 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9); 3085 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x1); 3086 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3087 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0xf); 3088 3089 if (path == RF_PATH_A) { 3090 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 3091 0x1066680); 3092 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 0x1); 3093 } else { 3094 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 3095 0x1066680); 3096 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 0x1); 3097 } 3098 3099 if (dpk_info->dpk_bw == DPK_CHANNEL_WIDTH_80) { 3100 rtw_write32(rtwdev, REG_DPD_CTL16, 0x80001310); 3101 rtw_write32(rtwdev, REG_DPD_CTL16, 0x00001310); 3102 rtw_write32(rtwdev, REG_DPD_CTL16, 0x810000db); 3103 rtw_write32(rtwdev, REG_DPD_CTL16, 0x010000db); 3104 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428); 3105 rtw_write32(rtwdev, REG_DPD_CTL15, 3106 0x05020000 | (BIT(path) << 28)); 3107 } else { 3108 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8200190c); 3109 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0200190c); 3110 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8301ee14); 3111 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0301ee14); 3112 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428); 3113 rtw_write32(rtwdev, REG_DPD_CTL15, 3114 0x05020008 | (BIT(path) << 28)); 3115 } 3116 3117 rtw_write32_mask(rtwdev, REG_DPD_CTL0, MASKBYTE3, 0x8 | path); 3118 3119 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_CAL_PWR); 3120 3121 rtw_write32_mask(rtwdev, REG_DPD_CTL15, MASKBYTE3, 0x0); 3122 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3123 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0); 3124 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x0); 3125 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3126 3127 if (path == RF_PATH_A) 3128 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 0x5b); 3129 else 3130 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 0x5b); 3131 3132 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0); 3133 3134 tmp_gs = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, BIT_RPT_DGAIN); 3135 tmp_gs = (tmp_gs * 910) >> 10; 3136 tmp_gs = DIV_ROUND_CLOSEST(tmp_gs, 10); 3137 3138 if (path == RF_PATH_A) 3139 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, tmp_gs); 3140 else 3141 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, tmp_gs); 3142 3143 dpk_info->dpk_gs[path] = tmp_gs; 3144} 3145 3146static void rtw8822c_dpk_cal_coef1(struct rtw_dev *rtwdev) 3147{ 3148 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3149 u32 offset[DPK_RF_PATH_NUM] = {0, 0x58}; 3150 u32 i_scaling; 3151 u8 path; 3152 3153 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c); 3154 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); 3155 rtw_write32(rtwdev, REG_NCTL0, 0x00001148); 3156 rtw_write32(rtwdev, REG_NCTL0, 0x00001149); 3157 3158 check_hw_ready(rtwdev, 0x2d9c, MASKBYTE0, 0x55); 3159 3160 rtw_write8(rtwdev, 0x1b10, 0x0); 3161 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c); 3162 3163 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 3164 i_scaling = 0x16c00 / dpk_info->dpk_gs[path]; 3165 3166 rtw_write32_mask(rtwdev, 0x1b18 + offset[path], MASKHWORD, 3167 i_scaling); 3168 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path], 3169 GENMASK(31, 28), 0x9); 3170 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path], 3171 GENMASK(31, 28), 0x1); 3172 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path], 3173 GENMASK(31, 28), 0x0); 3174 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0 + offset[path], 3175 BIT(14), 0x0); 3176 } 3177} 3178 3179static void rtw8822c_dpk_on(struct rtw_dev *rtwdev, u8 path) 3180{ 3181 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3182 3183 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON); 3184 3185 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3186 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 3187 3188 if (test_bit(path, dpk_info->dpk_path_ok)) 3189 rtw8822c_dpk_cal_gs(rtwdev, path); 3190} 3191 3192static bool rtw8822c_dpk_check_pass(struct rtw_dev *rtwdev, bool is_fail, 3193 u32 dpk_txagc, u8 path) 3194{ 3195 bool result; 3196 3197 if (!is_fail) { 3198 if (rtw8822c_dpk_coef_read(rtwdev, path)) 3199 result = true; 3200 else 3201 result = false; 3202 } else { 3203 result = false; 3204 } 3205 3206 rtw8822c_dpk_fill_result(rtwdev, dpk_txagc, path, result); 3207 3208 return result; 3209} 3210 3211static void rtw8822c_dpk_result_reset(struct rtw_dev *rtwdev) 3212{ 3213 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3214 u8 path; 3215 3216 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 3217 clear_bit(path, dpk_info->dpk_path_ok); 3218 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 3219 0x8 | (path << 1)); 3220 rtw_write32_mask(rtwdev, 0x1b58, 0x0000007f, 0x0); 3221 3222 dpk_info->dpk_txagc[path] = 0; 3223 dpk_info->result[path] = 0; 3224 dpk_info->dpk_gs[path] = 0x5b; 3225 dpk_info->pre_pwsf[path] = 0; 3226 dpk_info->thermal_dpk[path] = rtw8822c_dpk_thermal_read(rtwdev, 3227 path); 3228 } 3229} 3230 3231static void rtw8822c_dpk_calibrate(struct rtw_dev *rtwdev, u8 path) 3232{ 3233 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3234 u32 dpk_txagc; 3235 u8 dpk_fail; 3236 3237 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk start\n", path); 3238 3239 dpk_txagc = rtw8822c_dpk_gainloss(rtwdev, path); 3240 3241 dpk_fail = rtw8822c_dpk_by_path(rtwdev, dpk_txagc, path); 3242 3243 if (!rtw8822c_dpk_check_pass(rtwdev, dpk_fail, dpk_txagc, path)) 3244 rtw_err(rtwdev, "failed to do dpk calibration\n"); 3245 3246 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk finish\n", path); 3247 3248 if (dpk_info->result[path]) 3249 set_bit(path, dpk_info->dpk_path_ok); 3250} 3251 3252static void rtw8822c_dpk_path_select(struct rtw_dev *rtwdev) 3253{ 3254 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_A); 3255 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_B); 3256 rtw8822c_dpk_on(rtwdev, RF_PATH_A); 3257 rtw8822c_dpk_on(rtwdev, RF_PATH_B); 3258 rtw8822c_dpk_cal_coef1(rtwdev); 3259} 3260 3261static void rtw8822c_dpk_enable_disable(struct rtw_dev *rtwdev) 3262{ 3263 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3264 u32 mask = BIT(15) | BIT(14); 3265 3266 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3267 3268 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 3269 dpk_info->is_dpk_pwr_on); 3270 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 3271 dpk_info->is_dpk_pwr_on); 3272 3273 if (test_bit(RF_PATH_A, dpk_info->dpk_path_ok)) { 3274 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, mask, 0x0); 3275 rtw_write8(rtwdev, REG_DPD_CTL0_S0, dpk_info->dpk_gs[RF_PATH_A]); 3276 } 3277 if (test_bit(RF_PATH_B, dpk_info->dpk_path_ok)) { 3278 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, mask, 0x0); 3279 rtw_write8(rtwdev, REG_DPD_CTL0_S1, dpk_info->dpk_gs[RF_PATH_B]); 3280 } 3281} 3282 3283static void rtw8822c_dpk_reload_data(struct rtw_dev *rtwdev) 3284{ 3285 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3286 u8 path; 3287 3288 if (!test_bit(RF_PATH_A, dpk_info->dpk_path_ok) && 3289 !test_bit(RF_PATH_B, dpk_info->dpk_path_ok) && 3290 dpk_info->dpk_ch == 0) 3291 return; 3292 3293 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 3294 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 3295 0x8 | (path << 1)); 3296 if (dpk_info->dpk_band == RTW_BAND_2G) 3297 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f100000); 3298 else 3299 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f0d0000); 3300 3301 rtw_write8(rtwdev, REG_DPD_AGC, dpk_info->dpk_txagc[path]); 3302 3303 rtw8822c_dpk_coef_write(rtwdev, path, 3304 test_bit(path, dpk_info->dpk_path_ok)); 3305 3306 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON); 3307 3308 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3309 3310 if (path == RF_PATH_A) 3311 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 3312 dpk_info->dpk_gs[path]); 3313 else 3314 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 3315 dpk_info->dpk_gs[path]); 3316 } 3317 rtw8822c_dpk_cal_coef1(rtwdev); 3318} 3319 3320static bool rtw8822c_dpk_reload(struct rtw_dev *rtwdev) 3321{ 3322 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3323 u8 channel; 3324 3325 dpk_info->is_reload = false; 3326 3327 channel = (u8)(rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK) & 0xff); 3328 3329 if (channel == dpk_info->dpk_ch) { 3330 rtw_dbg(rtwdev, RTW_DBG_RFK, 3331 "[DPK] DPK reload for CH%d!!\n", dpk_info->dpk_ch); 3332 rtw8822c_dpk_reload_data(rtwdev); 3333 dpk_info->is_reload = true; 3334 } 3335 3336 return dpk_info->is_reload; 3337} 3338 3339static void rtw8822c_do_dpk(struct rtw_dev *rtwdev) 3340{ 3341 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3342 struct rtw_backup_info bckp[DPK_BB_REG_NUM]; 3343 u32 rf_reg_backup[DPK_RF_REG_NUM][DPK_RF_PATH_NUM]; 3344 u32 bb_reg[DPK_BB_REG_NUM] = { 3345 0x520, 0x820, 0x824, 0x1c3c, 0x1d58, 0x1864, 3346 0x4164, 0x180c, 0x410c, 0x186c, 0x416c, 3347 0x1a14, 0x1e70, 0x80c, 0x1d70, 0x1e7c, 0x18a4, 0x41a4}; 3348 u32 rf_reg[DPK_RF_REG_NUM] = { 3349 0x0, 0x1a, 0x55, 0x63, 0x87, 0x8f, 0xde}; 3350 u8 path; 3351 3352 if (!dpk_info->is_dpk_pwr_on) { 3353 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] Skip DPK due to DPD PWR off\n"); 3354 return; 3355 } else if (rtw8822c_dpk_reload(rtwdev)) { 3356 return; 3357 } 3358 3359 for (path = RF_PATH_A; path < DPK_RF_PATH_NUM; path++) 3360 ewma_thermal_init(&dpk_info->avg_thermal[path]); 3361 3362 rtw8822c_dpk_information(rtwdev); 3363 3364 rtw8822c_dpk_backup_registers(rtwdev, bb_reg, DPK_BB_REG_NUM, bckp); 3365 rtw8822c_dpk_backup_rf_registers(rtwdev, rf_reg, rf_reg_backup); 3366 3367 rtw8822c_dpk_mac_bb_setting(rtwdev); 3368 rtw8822c_dpk_afe_setting(rtwdev, true); 3369 rtw8822c_dpk_pre_setting(rtwdev); 3370 rtw8822c_dpk_result_reset(rtwdev); 3371 rtw8822c_dpk_path_select(rtwdev); 3372 rtw8822c_dpk_afe_setting(rtwdev, false); 3373 rtw8822c_dpk_enable_disable(rtwdev); 3374 3375 rtw8822c_dpk_reload_rf_registers(rtwdev, rf_reg, rf_reg_backup); 3376 for (path = 0; path < rtwdev->hal.rf_path_num; path++) 3377 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path); 3378 rtw8822c_dpk_restore_registers(rtwdev, DPK_BB_REG_NUM, bckp); 3379} 3380 3381static void rtw8822c_phy_calibration(struct rtw_dev *rtwdev) 3382{ 3383 rtw8822c_do_iqk(rtwdev); 3384 rtw8822c_do_dpk(rtwdev); 3385} 3386 3387static void rtw8822c_dpk_track(struct rtw_dev *rtwdev) 3388{ 3389 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3390 u8 path; 3391 u8 thermal_value[DPK_RF_PATH_NUM] = {0}; 3392 s8 offset[DPK_RF_PATH_NUM], delta_dpk[DPK_RF_PATH_NUM]; 3393 3394 if (dpk_info->thermal_dpk[0] == 0 && dpk_info->thermal_dpk[1] == 0) 3395 return; 3396 3397 for (path = 0; path < DPK_RF_PATH_NUM; path++) { 3398 thermal_value[path] = rtw8822c_dpk_thermal_read(rtwdev, path); 3399 ewma_thermal_add(&dpk_info->avg_thermal[path], 3400 thermal_value[path]); 3401 thermal_value[path] = 3402 ewma_thermal_read(&dpk_info->avg_thermal[path]); 3403 delta_dpk[path] = dpk_info->thermal_dpk[path] - 3404 thermal_value[path]; 3405 offset[path] = delta_dpk[path] - 3406 dpk_info->thermal_dpk_delta[path]; 3407 offset[path] &= 0x7f; 3408 3409 if (offset[path] != dpk_info->pre_pwsf[path]) { 3410 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 3411 0x8 | (path << 1)); 3412 rtw_write32_mask(rtwdev, 0x1b58, GENMASK(6, 0), 3413 offset[path]); 3414 dpk_info->pre_pwsf[path] = offset[path]; 3415 } 3416 } 3417} 3418 3419static const struct rtw_phy_cck_pd_reg 3420rtw8822c_cck_pd_reg[RTW_CHANNEL_WIDTH_40 + 1][RTW_RF_PATH_MAX] = { 3421 { 3422 {0x1ac8, 0x00ff, 0x1ad0, 0x01f}, 3423 {0x1ac8, 0xff00, 0x1ad0, 0x3e0} 3424 }, 3425 { 3426 {0x1acc, 0x00ff, 0x1ad0, 0x01F00000}, 3427 {0x1acc, 0xff00, 0x1ad0, 0x3E000000} 3428 }, 3429}; 3430 3431#define RTW_CCK_PD_MAX 255 3432#define RTW_CCK_CS_MAX 31 3433#define RTW_CCK_CS_ERR1 27 3434#define RTW_CCK_CS_ERR2 29 3435static void 3436rtw8822c_phy_cck_pd_set_reg(struct rtw_dev *rtwdev, 3437 s8 pd_diff, s8 cs_diff, u8 bw, u8 nrx) 3438{ 3439 u32 pd, cs; 3440 3441 if (WARN_ON(bw > RTW_CHANNEL_WIDTH_40 || nrx >= RTW_RF_PATH_MAX)) 3442 return; 3443 3444 pd = rtw_read32_mask(rtwdev, 3445 rtw8822c_cck_pd_reg[bw][nrx].reg_pd, 3446 rtw8822c_cck_pd_reg[bw][nrx].mask_pd); 3447 cs = rtw_read32_mask(rtwdev, 3448 rtw8822c_cck_pd_reg[bw][nrx].reg_cs, 3449 rtw8822c_cck_pd_reg[bw][nrx].mask_cs); 3450 pd += pd_diff; 3451 cs += cs_diff; 3452 if (pd > RTW_CCK_PD_MAX) 3453 pd = RTW_CCK_PD_MAX; 3454 if (cs == RTW_CCK_CS_ERR1 || cs == RTW_CCK_CS_ERR2) 3455 cs++; 3456 else if (cs > RTW_CCK_CS_MAX) 3457 cs = RTW_CCK_CS_MAX; 3458 rtw_write32_mask(rtwdev, 3459 rtw8822c_cck_pd_reg[bw][nrx].reg_pd, 3460 rtw8822c_cck_pd_reg[bw][nrx].mask_pd, 3461 pd); 3462 rtw_write32_mask(rtwdev, 3463 rtw8822c_cck_pd_reg[bw][nrx].reg_cs, 3464 rtw8822c_cck_pd_reg[bw][nrx].mask_cs, 3465 cs); 3466} 3467 3468static void rtw8822c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl) 3469{ 3470 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 3471 s8 pd_lvl[CCK_PD_LV_MAX] = {0, 2, 4, 6, 8}; 3472 s8 cs_lvl[CCK_PD_LV_MAX] = {0, 2, 2, 2, 4}; 3473 u8 cur_lvl; 3474 u8 nrx, bw; 3475 3476 nrx = (u8)rtw_read32_mask(rtwdev, 0x1a2c, 0x60000); 3477 bw = (u8)rtw_read32_mask(rtwdev, 0x9b0, 0xc); 3478 3479 if (dm_info->cck_pd_lv[bw][nrx] == new_lvl) 3480 return; 3481 3482 cur_lvl = dm_info->cck_pd_lv[bw][nrx]; 3483 3484 /* update cck pd info */ 3485 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; 3486 3487 rtw8822c_phy_cck_pd_set_reg(rtwdev, 3488 pd_lvl[new_lvl] - pd_lvl[cur_lvl], 3489 cs_lvl[new_lvl] - cs_lvl[cur_lvl], 3490 bw, nrx); 3491 dm_info->cck_pd_lv[bw][nrx] = new_lvl; 3492} 3493 3494#define PWR_TRACK_MASK 0x7f 3495static void rtw8822c_pwrtrack_set(struct rtw_dev *rtwdev, u8 rf_path) 3496{ 3497 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 3498 3499 switch (rf_path) { 3500 case RF_PATH_A: 3501 rtw_write32_mask(rtwdev, 0x18a0, PWR_TRACK_MASK, 3502 dm_info->delta_power_index[rf_path]); 3503 break; 3504 case RF_PATH_B: 3505 rtw_write32_mask(rtwdev, 0x41a0, PWR_TRACK_MASK, 3506 dm_info->delta_power_index[rf_path]); 3507 break; 3508 default: 3509 break; 3510 } 3511} 3512 3513static void rtw8822c_pwr_track_stats(struct rtw_dev *rtwdev, u8 path) 3514{ 3515 u8 thermal_value; 3516 3517 if (rtwdev->efuse.thermal_meter[path] == 0xff) 3518 return; 3519 3520 thermal_value = rtw_read_rf(rtwdev, path, RF_T_METER, 0x7e); 3521 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, path); 3522} 3523 3524static void rtw8822c_pwr_track_path(struct rtw_dev *rtwdev, 3525 struct rtw_swing_table *swing_table, 3526 u8 path) 3527{ 3528 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 3529 u8 delta; 3530 3531 delta = rtw_phy_pwrtrack_get_delta(rtwdev, path); 3532 dm_info->delta_power_index[path] = 3533 rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table, path, path, 3534 delta); 3535 rtw8822c_pwrtrack_set(rtwdev, path); 3536} 3537 3538static void __rtw8822c_pwr_track(struct rtw_dev *rtwdev) 3539{ 3540 struct rtw_swing_table swing_table; 3541 u8 i; 3542 3543 rtw_phy_config_swing_table(rtwdev, &swing_table); 3544 3545 for (i = 0; i < rtwdev->hal.rf_path_num; i++) 3546 rtw8822c_pwr_track_stats(rtwdev, i); 3547 if (rtw_phy_pwrtrack_need_lck(rtwdev)) 3548 rtw8822c_do_lck(rtwdev); 3549 for (i = 0; i < rtwdev->hal.rf_path_num; i++) 3550 rtw8822c_pwr_track_path(rtwdev, &swing_table, i); 3551} 3552 3553static void rtw8822c_pwr_track(struct rtw_dev *rtwdev) 3554{ 3555 struct rtw_efuse *efuse = &rtwdev->efuse; 3556 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 3557 3558 if (efuse->power_track_type != 0) 3559 return; 3560 3561 if (!dm_info->pwr_trk_triggered) { 3562 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01); 3563 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x00); 3564 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01); 3565 3566 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01); 3567 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x00); 3568 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01); 3569 3570 dm_info->pwr_trk_triggered = true; 3571 return; 3572 } 3573 3574 __rtw8822c_pwr_track(rtwdev); 3575 dm_info->pwr_trk_triggered = false; 3576} 3577 3578static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822c[] = { 3579 {0x0086, 3580 RTW_PWR_CUT_ALL_MSK, 3581 RTW_PWR_INTF_SDIO_MSK, 3582 RTW_PWR_ADDR_SDIO, 3583 RTW_PWR_CMD_WRITE, BIT(0), 0}, 3584 {0x0086, 3585 RTW_PWR_CUT_ALL_MSK, 3586 RTW_PWR_INTF_SDIO_MSK, 3587 RTW_PWR_ADDR_SDIO, 3588 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 3589 {0x002E, 3590 RTW_PWR_CUT_ALL_MSK, 3591 RTW_PWR_INTF_ALL_MSK, 3592 RTW_PWR_ADDR_MAC, 3593 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 3594 {0x002D, 3595 RTW_PWR_CUT_ALL_MSK, 3596 RTW_PWR_INTF_ALL_MSK, 3597 RTW_PWR_ADDR_MAC, 3598 RTW_PWR_CMD_WRITE, BIT(0), 0}, 3599 {0x007F, 3600 RTW_PWR_CUT_ALL_MSK, 3601 RTW_PWR_INTF_ALL_MSK, 3602 RTW_PWR_ADDR_MAC, 3603 RTW_PWR_CMD_WRITE, BIT(7), 0}, 3604 {0x004A, 3605 RTW_PWR_CUT_ALL_MSK, 3606 RTW_PWR_INTF_USB_MSK, 3607 RTW_PWR_ADDR_MAC, 3608 RTW_PWR_CMD_WRITE, BIT(0), 0}, 3609 {0x0005, 3610 RTW_PWR_CUT_ALL_MSK, 3611 RTW_PWR_INTF_ALL_MSK, 3612 RTW_PWR_ADDR_MAC, 3613 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, 3614 {0xFFFF, 3615 RTW_PWR_CUT_ALL_MSK, 3616 RTW_PWR_INTF_ALL_MSK, 3617 0, 3618 RTW_PWR_CMD_END, 0, 0}, 3619}; 3620 3621static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822c[] = { 3622 {0x0000, 3623 RTW_PWR_CUT_ALL_MSK, 3624 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 3625 RTW_PWR_ADDR_MAC, 3626 RTW_PWR_CMD_WRITE, BIT(5), 0}, 3627 {0x0005, 3628 RTW_PWR_CUT_ALL_MSK, 3629 RTW_PWR_INTF_ALL_MSK, 3630 RTW_PWR_ADDR_MAC, 3631 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 3632 {0x0075, 3633 RTW_PWR_CUT_ALL_MSK, 3634 RTW_PWR_INTF_PCI_MSK, 3635 RTW_PWR_ADDR_MAC, 3636 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 3637 {0x0006, 3638 RTW_PWR_CUT_ALL_MSK, 3639 RTW_PWR_INTF_ALL_MSK, 3640 RTW_PWR_ADDR_MAC, 3641 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 3642 {0x0075, 3643 RTW_PWR_CUT_ALL_MSK, 3644 RTW_PWR_INTF_PCI_MSK, 3645 RTW_PWR_ADDR_MAC, 3646 RTW_PWR_CMD_WRITE, BIT(0), 0}, 3647 {0xFF1A, 3648 RTW_PWR_CUT_ALL_MSK, 3649 RTW_PWR_INTF_USB_MSK, 3650 RTW_PWR_ADDR_MAC, 3651 RTW_PWR_CMD_WRITE, 0xFF, 0}, 3652 {0x002E, 3653 RTW_PWR_CUT_ALL_MSK, 3654 RTW_PWR_INTF_ALL_MSK, 3655 RTW_PWR_ADDR_MAC, 3656 RTW_PWR_CMD_WRITE, BIT(3), 0}, 3657 {0x0006, 3658 RTW_PWR_CUT_ALL_MSK, 3659 RTW_PWR_INTF_ALL_MSK, 3660 RTW_PWR_ADDR_MAC, 3661 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 3662 {0x0005, 3663 RTW_PWR_CUT_ALL_MSK, 3664 RTW_PWR_INTF_ALL_MSK, 3665 RTW_PWR_ADDR_MAC, 3666 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 3667 {0x1018, 3668 RTW_PWR_CUT_ALL_MSK, 3669 RTW_PWR_INTF_ALL_MSK, 3670 RTW_PWR_ADDR_MAC, 3671 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 3672 {0x0005, 3673 RTW_PWR_CUT_ALL_MSK, 3674 RTW_PWR_INTF_ALL_MSK, 3675 RTW_PWR_ADDR_MAC, 3676 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 3677 {0x0005, 3678 RTW_PWR_CUT_ALL_MSK, 3679 RTW_PWR_INTF_ALL_MSK, 3680 RTW_PWR_ADDR_MAC, 3681 RTW_PWR_CMD_POLLING, BIT(0), 0}, 3682 {0x0074, 3683 RTW_PWR_CUT_ALL_MSK, 3684 RTW_PWR_INTF_PCI_MSK, 3685 RTW_PWR_ADDR_MAC, 3686 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 3687 {0x0071, 3688 RTW_PWR_CUT_ALL_MSK, 3689 RTW_PWR_INTF_PCI_MSK, 3690 RTW_PWR_ADDR_MAC, 3691 RTW_PWR_CMD_WRITE, BIT(4), 0}, 3692 {0x0062, 3693 RTW_PWR_CUT_ALL_MSK, 3694 RTW_PWR_INTF_PCI_MSK, 3695 RTW_PWR_ADDR_MAC, 3696 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 3697 (BIT(7) | BIT(6) | BIT(5))}, 3698 {0x0061, 3699 RTW_PWR_CUT_ALL_MSK, 3700 RTW_PWR_INTF_PCI_MSK, 3701 RTW_PWR_ADDR_MAC, 3702 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0}, 3703 {0x001F, 3704 RTW_PWR_CUT_ALL_MSK, 3705 RTW_PWR_INTF_ALL_MSK, 3706 RTW_PWR_ADDR_MAC, 3707 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)}, 3708 {0x00EF, 3709 RTW_PWR_CUT_ALL_MSK, 3710 RTW_PWR_INTF_ALL_MSK, 3711 RTW_PWR_ADDR_MAC, 3712 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)}, 3713 {0x1045, 3714 RTW_PWR_CUT_ALL_MSK, 3715 RTW_PWR_INTF_ALL_MSK, 3716 RTW_PWR_ADDR_MAC, 3717 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 3718 {0x0010, 3719 RTW_PWR_CUT_ALL_MSK, 3720 RTW_PWR_INTF_ALL_MSK, 3721 RTW_PWR_ADDR_MAC, 3722 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 3723 {0x1064, 3724 RTW_PWR_CUT_ALL_MSK, 3725 RTW_PWR_INTF_ALL_MSK, 3726 RTW_PWR_ADDR_MAC, 3727 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 3728 {0xFFFF, 3729 RTW_PWR_CUT_ALL_MSK, 3730 RTW_PWR_INTF_ALL_MSK, 3731 0, 3732 RTW_PWR_CMD_END, 0, 0}, 3733}; 3734 3735static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822c[] = { 3736 {0x0093, 3737 RTW_PWR_CUT_ALL_MSK, 3738 RTW_PWR_INTF_ALL_MSK, 3739 RTW_PWR_ADDR_MAC, 3740 RTW_PWR_CMD_WRITE, BIT(3), 0}, 3741 {0x001F, 3742 RTW_PWR_CUT_ALL_MSK, 3743 RTW_PWR_INTF_ALL_MSK, 3744 RTW_PWR_ADDR_MAC, 3745 RTW_PWR_CMD_WRITE, 0xFF, 0}, 3746 {0x00EF, 3747 RTW_PWR_CUT_ALL_MSK, 3748 RTW_PWR_INTF_ALL_MSK, 3749 RTW_PWR_ADDR_MAC, 3750 RTW_PWR_CMD_WRITE, 0xFF, 0}, 3751 {0x1045, 3752 RTW_PWR_CUT_ALL_MSK, 3753 RTW_PWR_INTF_ALL_MSK, 3754 RTW_PWR_ADDR_MAC, 3755 RTW_PWR_CMD_WRITE, BIT(4), 0}, 3756 {0xFF1A, 3757 RTW_PWR_CUT_ALL_MSK, 3758 RTW_PWR_INTF_USB_MSK, 3759 RTW_PWR_ADDR_MAC, 3760 RTW_PWR_CMD_WRITE, 0xFF, 0x30}, 3761 {0x0049, 3762 RTW_PWR_CUT_ALL_MSK, 3763 RTW_PWR_INTF_ALL_MSK, 3764 RTW_PWR_ADDR_MAC, 3765 RTW_PWR_CMD_WRITE, BIT(1), 0}, 3766 {0x0006, 3767 RTW_PWR_CUT_ALL_MSK, 3768 RTW_PWR_INTF_ALL_MSK, 3769 RTW_PWR_ADDR_MAC, 3770 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 3771 {0x0002, 3772 RTW_PWR_CUT_ALL_MSK, 3773 RTW_PWR_INTF_ALL_MSK, 3774 RTW_PWR_ADDR_MAC, 3775 RTW_PWR_CMD_WRITE, BIT(1), 0}, 3776 {0x0005, 3777 RTW_PWR_CUT_ALL_MSK, 3778 RTW_PWR_INTF_ALL_MSK, 3779 RTW_PWR_ADDR_MAC, 3780 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 3781 {0x0005, 3782 RTW_PWR_CUT_ALL_MSK, 3783 RTW_PWR_INTF_ALL_MSK, 3784 RTW_PWR_ADDR_MAC, 3785 RTW_PWR_CMD_POLLING, BIT(1), 0}, 3786 {0x0000, 3787 RTW_PWR_CUT_ALL_MSK, 3788 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 3789 RTW_PWR_ADDR_MAC, 3790 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 3791 {0xFFFF, 3792 RTW_PWR_CUT_ALL_MSK, 3793 RTW_PWR_INTF_ALL_MSK, 3794 0, 3795 RTW_PWR_CMD_END, 0, 0}, 3796}; 3797 3798static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822c[] = { 3799 {0x0005, 3800 RTW_PWR_CUT_ALL_MSK, 3801 RTW_PWR_INTF_SDIO_MSK, 3802 RTW_PWR_ADDR_MAC, 3803 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 3804 {0x0007, 3805 RTW_PWR_CUT_ALL_MSK, 3806 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 3807 RTW_PWR_ADDR_MAC, 3808 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 3809 {0x0067, 3810 RTW_PWR_CUT_ALL_MSK, 3811 RTW_PWR_INTF_ALL_MSK, 3812 RTW_PWR_ADDR_MAC, 3813 RTW_PWR_CMD_WRITE, BIT(5), 0}, 3814 {0x004A, 3815 RTW_PWR_CUT_ALL_MSK, 3816 RTW_PWR_INTF_USB_MSK, 3817 RTW_PWR_ADDR_MAC, 3818 RTW_PWR_CMD_WRITE, BIT(0), 0}, 3819 {0x0081, 3820 RTW_PWR_CUT_ALL_MSK, 3821 RTW_PWR_INTF_ALL_MSK, 3822 RTW_PWR_ADDR_MAC, 3823 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 3824 {0x0090, 3825 RTW_PWR_CUT_ALL_MSK, 3826 RTW_PWR_INTF_ALL_MSK, 3827 RTW_PWR_ADDR_MAC, 3828 RTW_PWR_CMD_WRITE, BIT(1), 0}, 3829 {0x0092, 3830 RTW_PWR_CUT_ALL_MSK, 3831 RTW_PWR_INTF_PCI_MSK, 3832 RTW_PWR_ADDR_MAC, 3833 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 3834 {0x0093, 3835 RTW_PWR_CUT_ALL_MSK, 3836 RTW_PWR_INTF_PCI_MSK, 3837 RTW_PWR_ADDR_MAC, 3838 RTW_PWR_CMD_WRITE, 0xFF, 0x04}, 3839 {0x0005, 3840 RTW_PWR_CUT_ALL_MSK, 3841 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 3842 RTW_PWR_ADDR_MAC, 3843 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 3844 {0x0005, 3845 RTW_PWR_CUT_ALL_MSK, 3846 RTW_PWR_INTF_PCI_MSK, 3847 RTW_PWR_ADDR_MAC, 3848 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 3849 {0x0086, 3850 RTW_PWR_CUT_ALL_MSK, 3851 RTW_PWR_INTF_SDIO_MSK, 3852 RTW_PWR_ADDR_SDIO, 3853 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 3854 {0xFFFF, 3855 RTW_PWR_CUT_ALL_MSK, 3856 RTW_PWR_INTF_ALL_MSK, 3857 0, 3858 RTW_PWR_CMD_END, 0, 0}, 3859}; 3860 3861static const struct rtw_pwr_seq_cmd *card_enable_flow_8822c[] = { 3862 trans_carddis_to_cardemu_8822c, 3863 trans_cardemu_to_act_8822c, 3864 NULL 3865}; 3866 3867static const struct rtw_pwr_seq_cmd *card_disable_flow_8822c[] = { 3868 trans_act_to_cardemu_8822c, 3869 trans_cardemu_to_carddis_8822c, 3870 NULL 3871}; 3872 3873static const struct rtw_intf_phy_para usb2_param_8822c[] = { 3874 {0xFFFF, 0x00, 3875 RTW_IP_SEL_PHY, 3876 RTW_INTF_PHY_CUT_ALL, 3877 RTW_INTF_PHY_PLATFORM_ALL}, 3878}; 3879 3880static const struct rtw_intf_phy_para usb3_param_8822c[] = { 3881 {0xFFFF, 0x0000, 3882 RTW_IP_SEL_PHY, 3883 RTW_INTF_PHY_CUT_ALL, 3884 RTW_INTF_PHY_PLATFORM_ALL}, 3885}; 3886 3887static const struct rtw_intf_phy_para pcie_gen1_param_8822c[] = { 3888 {0xFFFF, 0x0000, 3889 RTW_IP_SEL_PHY, 3890 RTW_INTF_PHY_CUT_ALL, 3891 RTW_INTF_PHY_PLATFORM_ALL}, 3892}; 3893 3894static const struct rtw_intf_phy_para pcie_gen2_param_8822c[] = { 3895 {0xFFFF, 0x0000, 3896 RTW_IP_SEL_PHY, 3897 RTW_INTF_PHY_CUT_ALL, 3898 RTW_INTF_PHY_PLATFORM_ALL}, 3899}; 3900 3901static const struct rtw_intf_phy_para_table phy_para_table_8822c = { 3902 .usb2_para = usb2_param_8822c, 3903 .usb3_para = usb3_param_8822c, 3904 .gen1_para = pcie_gen1_param_8822c, 3905 .gen2_para = pcie_gen2_param_8822c, 3906 .n_usb2_para = ARRAY_SIZE(usb2_param_8822c), 3907 .n_usb3_para = ARRAY_SIZE(usb2_param_8822c), 3908 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822c), 3909 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822c), 3910}; 3911 3912static const struct rtw_rfe_def rtw8822c_rfe_defs[] = { 3913 [0] = RTW_DEF_RFE(8822c, 0, 0), 3914 [1] = RTW_DEF_RFE(8822c, 0, 0), 3915 [2] = RTW_DEF_RFE(8822c, 0, 0), 3916 [5] = RTW_DEF_RFE(8822c, 0, 5), 3917 [6] = RTW_DEF_RFE(8822c, 0, 0), 3918}; 3919 3920static const struct rtw_hw_reg rtw8822c_dig[] = { 3921 [0] = { .addr = 0x1d70, .mask = 0x7f }, 3922 [1] = { .addr = 0x1d70, .mask = 0x7f00 }, 3923}; 3924 3925static const struct rtw_ltecoex_addr rtw8822c_ltecoex_addr = { 3926 .ctrl = LTECOEX_ACCESS_CTRL, 3927 .wdata = LTECOEX_WRITE_DATA, 3928 .rdata = LTECOEX_READ_DATA, 3929}; 3930 3931static const struct rtw_page_table page_table_8822c[] = { 3932 {64, 64, 64, 64, 1}, 3933 {64, 64, 64, 64, 1}, 3934 {64, 64, 0, 0, 1}, 3935 {64, 64, 64, 0, 1}, 3936 {64, 64, 64, 64, 1}, 3937}; 3938 3939static const struct rtw_rqpn rqpn_table_8822c[] = { 3940 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 3941 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 3942 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 3943 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 3944 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 3945 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 3946 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 3947 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 3948 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 3949 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 3950 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 3951 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 3952 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 3953 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 3954 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 3955}; 3956 3957static struct rtw_prioq_addrs prioq_addrs_8822c = { 3958 .prio[RTW_DMA_MAPPING_EXTRA] = { 3959 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2, 3960 }, 3961 .prio[RTW_DMA_MAPPING_LOW] = { 3962 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2, 3963 }, 3964 .prio[RTW_DMA_MAPPING_NORMAL] = { 3965 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2, 3966 }, 3967 .prio[RTW_DMA_MAPPING_HIGH] = { 3968 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2, 3969 }, 3970 .wsize = true, 3971}; 3972 3973static struct rtw_chip_ops rtw8822c_ops = { 3974 .phy_set_param = rtw8822c_phy_set_param, 3975 .read_efuse = rtw8822c_read_efuse, 3976 .query_rx_desc = rtw8822c_query_rx_desc, 3977 .set_channel = rtw8822c_set_channel, 3978 .mac_init = rtw8822c_mac_init, 3979 .read_rf = rtw_phy_read_rf, 3980 .write_rf = rtw_phy_write_rf_reg_mix, 3981 .set_tx_power_index = rtw8822c_set_tx_power_index, 3982 .set_antenna = rtw8822c_set_antenna, 3983 .cfg_ldo25 = rtw8822c_cfg_ldo25, 3984 .false_alarm_statistics = rtw8822c_false_alarm_statistics, 3985 .dpk_track = rtw8822c_dpk_track, 3986 .phy_calibration = rtw8822c_phy_calibration, 3987 .cck_pd_set = rtw8822c_phy_cck_pd_set, 3988 .pwr_track = rtw8822c_pwr_track, 3989 .config_bfee = rtw8822c_bf_config_bfee, 3990 .set_gid_table = rtw_bf_set_gid_table, 3991 .cfg_csi_rate = rtw_bf_cfg_csi_rate, 3992 3993 .coex_set_init = rtw8822c_coex_cfg_init, 3994 .coex_set_ant_switch = NULL, 3995 .coex_set_gnt_fix = rtw8822c_coex_cfg_gnt_fix, 3996 .coex_set_gnt_debug = rtw8822c_coex_cfg_gnt_debug, 3997 .coex_set_rfe_type = rtw8822c_coex_cfg_rfe_type, 3998 .coex_set_wl_tx_power = rtw8822c_coex_cfg_wl_tx_power, 3999 .coex_set_wl_rx_gain = rtw8822c_coex_cfg_wl_rx_gain, 4000}; 4001 4002/* Shared-Antenna Coex Table */ 4003static const struct coex_table_para table_sant_8822c[] = { 4004 {0xffffffff, 0xffffffff}, /* case-0 */ 4005 {0x55555555, 0x55555555}, 4006 {0x66555555, 0x66555555}, 4007 {0xaaaaaaaa, 0xaaaaaaaa}, 4008 {0x5a5a5a5a, 0x5a5a5a5a}, 4009 {0xfafafafa, 0xfafafafa}, /* case-5 */ 4010 {0x6a5a6a5a, 0xaaaaaaaa}, 4011 {0x6a5a56aa, 0x6a5a56aa}, 4012 {0x6a5a5a5a, 0x6a5a5a5a}, 4013 {0x66555555, 0x5a5a5a5a}, 4014 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 4015 {0x66555555, 0xfafafafa}, 4016 {0x66555555, 0x5a5a5aaa}, 4017 {0x66555555, 0x5aaa5aaa}, 4018 {0x66555555, 0xaaaa5aaa}, 4019 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 4020 {0xffff55ff, 0xfafafafa}, 4021 {0xffff55ff, 0x6afa5afa}, 4022 {0xaaffffaa, 0xfafafafa}, 4023 {0xaa5555aa, 0x5a5a5a5a}, 4024 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 4025 {0xaa5555aa, 0xaaaaaaaa}, 4026 {0xffffffff, 0x5a5a5a5a}, 4027 {0xffffffff, 0x6a5a5a5a}, 4028 {0xffffffff, 0x55555555}, 4029 {0xffffffff, 0x6a5a5aaa}, /* case-25 */ 4030 {0x55555555, 0x5a5a5a5a}, 4031 {0x55555555, 0xaaaaaaaa}, 4032 {0x55555555, 0x6a5a6a5a}, 4033 {0x66556655, 0x66556655} 4034}; 4035 4036/* Non-Shared-Antenna Coex Table */ 4037static const struct coex_table_para table_nsant_8822c[] = { 4038 {0xffffffff, 0xffffffff}, /* case-100 */ 4039 {0x55555555, 0x55555555}, 4040 {0x66555555, 0x66555555}, 4041 {0xaaaaaaaa, 0xaaaaaaaa}, 4042 {0x5a5a5a5a, 0x5a5a5a5a}, 4043 {0xfafafafa, 0xfafafafa}, /* case-105 */ 4044 {0x5afa5afa, 0x5afa5afa}, 4045 {0x55555555, 0xfafafafa}, 4046 {0x66555555, 0xfafafafa}, 4047 {0x66555555, 0x5a5a5a5a}, 4048 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 4049 {0x66555555, 0xaaaaaaaa}, 4050 {0xffff55ff, 0xfafafafa}, 4051 {0xffff55ff, 0x5afa5afa}, 4052 {0xffff55ff, 0xaaaaaaaa}, 4053 {0xaaffffaa, 0xfafafafa}, /* case-115 */ 4054 {0xaaffffaa, 0x5afa5afa}, 4055 {0xaaffffaa, 0xaaaaaaaa}, 4056 {0xffffffff, 0xfafafafa}, 4057 {0xffffffff, 0x5afa5afa}, 4058 {0xffffffff, 0xaaaaaaaa},/* case-120 */ 4059 {0x55ff55ff, 0x5afa5afa}, 4060 {0x55ff55ff, 0xaaaaaaaa}, 4061 {0x55ff55ff, 0x55ff55ff} 4062}; 4063 4064/* Shared-Antenna TDMA */ 4065static const struct coex_tdma_para tdma_sant_8822c[] = { 4066 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 4067 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 4068 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 4069 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 4070 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 4071 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */ 4072 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 4073 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 4074 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 4075 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 4076 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 4077 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 4078 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 4079 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 4080 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 4081 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 4082 { {0x51, 0x45, 0x03, 0x10, 0x10} }, 4083 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 4084 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 4085 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 4086 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 4087 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 4088 { {0x51, 0x0c, 0x03, 0x10, 0x54} }, 4089 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 4090 { {0x65, 0x10, 0x03, 0x11, 0x11} }, 4091 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 4092 { {0x51, 0x08, 0x03, 0x10, 0x50} }, 4093 { {0x61, 0x08, 0x03, 0x11, 0x11} } 4094}; 4095 4096/* Non-Shared-Antenna TDMA */ 4097static const struct coex_tdma_para tdma_nsant_8822c[] = { 4098 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */ 4099 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 4100 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 4101 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 4102 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 4103 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 4104 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 4105 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 4106 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 4107 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 4108 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 4109 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 4110 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 4111 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 4112 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 4113 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 4114 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 4115 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 4116 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 4117 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 4118 { {0x51, 0x10, 0x03, 0x10, 0x50} } /* case-120 */ 4119}; 4120 4121/* rssi in percentage % (dbm = % - 100) */ 4122static const u8 wl_rssi_step_8822c[] = {60, 50, 44, 30}; 4123static const u8 bt_rssi_step_8822c[] = {8, 15, 20, 25}; 4124static const struct coex_5g_afh_map afh_5g_8822c[] = { {0, 0, 0} }; 4125 4126/* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 4127static const struct coex_rf_para rf_para_tx_8822c[] = { 4128 {0, 0, false, 7}, /* for normal */ 4129 {0, 16, false, 7}, /* for WL-CPT */ 4130 {8, 17, true, 4}, 4131 {7, 18, true, 4}, 4132 {6, 19, true, 4}, 4133 {5, 20, true, 4} 4134}; 4135 4136static const struct coex_rf_para rf_para_rx_8822c[] = { 4137 {0, 0, false, 7}, /* for normal */ 4138 {0, 16, false, 7}, /* for WL-CPT */ 4139 {3, 24, true, 5}, 4140 {2, 26, true, 5}, 4141 {1, 27, true, 5}, 4142 {0, 28, true, 5} 4143}; 4144 4145static_assert(ARRAY_SIZE(rf_para_tx_8822c) == ARRAY_SIZE(rf_para_rx_8822c)); 4146 4147static const u8 4148rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 4149 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 4150 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 4151 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 }, 4152 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 4153 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 4154 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 }, 4155 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 4156 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 4157 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 }, 4158}; 4159 4160static const u8 4161rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 4162 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4163 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 4164 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 }, 4165 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4166 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 4167 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 }, 4168 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4169 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 4170 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 }, 4171}; 4172 4173static const u8 4174rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 4175 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 4176 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 4177 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 }, 4178 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 4179 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 4180 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 }, 4181 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 4182 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 4183 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 }, 4184}; 4185 4186static const u8 4187rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 4188 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4189 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 4190 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 }, 4191 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4192 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 4193 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 }, 4194 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4195 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 4196 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 }, 4197}; 4198 4199static const u8 rtw8822c_pwrtrk_2gb_n[RTW_PWR_TRK_TBL_SZ] = { 4200 0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 4201 9, 9, 10, 11, 12, 13, 14, 15, 15, 16, 4202 17, 18, 19, 20, 20, 21, 22, 23, 24, 25 4203}; 4204 4205static const u8 rtw8822c_pwrtrk_2gb_p[RTW_PWR_TRK_TBL_SZ] = { 4206 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4207 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 4208 19, 20, 21, 22, 23, 24, 25, 26, 27, 28 4209}; 4210 4211static const u8 rtw8822c_pwrtrk_2ga_n[RTW_PWR_TRK_TBL_SZ] = { 4212 0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 4213 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 4214 13, 14, 15, 15, 16, 17, 17, 18, 19, 19 4215}; 4216 4217static const u8 rtw8822c_pwrtrk_2ga_p[RTW_PWR_TRK_TBL_SZ] = { 4218 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4219 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 4220 19, 20, 21, 22, 23, 24, 25, 25, 26, 27 4221}; 4222 4223static const u8 rtw8822c_pwrtrk_2g_cck_b_n[RTW_PWR_TRK_TBL_SZ] = { 4224 0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 4225 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 4226 17, 18, 19, 20, 21, 22, 23, 23, 24, 25 4227}; 4228 4229static const u8 rtw8822c_pwrtrk_2g_cck_b_p[RTW_PWR_TRK_TBL_SZ] = { 4230 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4231 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 4232 20, 21, 22, 23, 24, 25, 26, 27, 28, 29 4233}; 4234 4235static const u8 rtw8822c_pwrtrk_2g_cck_a_n[RTW_PWR_TRK_TBL_SZ] = { 4236 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 4237 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 4238 15, 16, 17, 18, 18, 19, 20, 21, 21, 22 4239}; 4240 4241static const u8 rtw8822c_pwrtrk_2g_cck_a_p[RTW_PWR_TRK_TBL_SZ] = { 4242 0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 4243 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 4244 18, 18, 19, 20, 21, 22, 23, 24, 24, 25 4245}; 4246 4247static const struct rtw_pwr_track_tbl rtw8822c_rtw_pwr_track_tbl = { 4248 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_1], 4249 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_2], 4250 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_3], 4251 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_1], 4252 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_2], 4253 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_3], 4254 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_1], 4255 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_2], 4256 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_3], 4257 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_1], 4258 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_2], 4259 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_3], 4260 .pwrtrk_2gb_n = rtw8822c_pwrtrk_2gb_n, 4261 .pwrtrk_2gb_p = rtw8822c_pwrtrk_2gb_p, 4262 .pwrtrk_2ga_n = rtw8822c_pwrtrk_2ga_n, 4263 .pwrtrk_2ga_p = rtw8822c_pwrtrk_2ga_p, 4264 .pwrtrk_2g_cckb_n = rtw8822c_pwrtrk_2g_cck_b_n, 4265 .pwrtrk_2g_cckb_p = rtw8822c_pwrtrk_2g_cck_b_p, 4266 .pwrtrk_2g_ccka_n = rtw8822c_pwrtrk_2g_cck_a_n, 4267 .pwrtrk_2g_ccka_p = rtw8822c_pwrtrk_2g_cck_a_p, 4268}; 4269 4270#ifdef CONFIG_PM 4271static const struct wiphy_wowlan_support rtw_wowlan_stub_8822c = { 4272 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_GTK_REKEY_FAILURE | 4273 WIPHY_WOWLAN_DISCONNECT | WIPHY_WOWLAN_SUPPORTS_GTK_REKEY | 4274 WIPHY_WOWLAN_NET_DETECT, 4275 .n_patterns = RTW_MAX_PATTERN_NUM, 4276 .pattern_max_len = RTW_MAX_PATTERN_SIZE, 4277 .pattern_min_len = 1, 4278 .max_nd_match_sets = 4, 4279}; 4280#endif 4281 4282static const struct rtw_reg_domain coex_info_hw_regs_8822c[] = { 4283 {0x1860, BIT(3), RTW_REG_DOMAIN_MAC8}, 4284 {0x4160, BIT(3), RTW_REG_DOMAIN_MAC8}, 4285 {0x1c32, BIT(6), RTW_REG_DOMAIN_MAC8}, 4286 {0x1c38, BIT(28), RTW_REG_DOMAIN_MAC32}, 4287 {0, 0, RTW_REG_DOMAIN_NL}, 4288 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 4289 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 4290 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 4291 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 4292 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8}, 4293 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 4294 {0, 0, RTW_REG_DOMAIN_NL}, 4295 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32}, 4296 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8}, 4297 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8}, 4298 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8}, 4299 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_B}, 4300 {0, 0, RTW_REG_DOMAIN_NL}, 4301 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 4302 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 4303 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8}, 4304 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 4305}; 4306 4307struct rtw_chip_info rtw8822c_hw_spec = { 4308 .ops = &rtw8822c_ops, 4309 .id = RTW_CHIP_TYPE_8822C, 4310 .fw_name = "rtw88/rtw8822c_fw.bin", 4311 .wlan_cpu = RTW_WCPU_11AC, 4312 .tx_pkt_desc_sz = 48, 4313 .tx_buf_desc_sz = 16, 4314 .rx_pkt_desc_sz = 24, 4315 .rx_buf_desc_sz = 8, 4316 .phy_efuse_size = 512, 4317 .log_efuse_size = 768, 4318 .ptct_efuse_size = 124, 4319 .txff_size = 262144, 4320 .rxff_size = 24576, 4321 .fw_rxff_size = 12288, 4322 .txgi_factor = 2, 4323 .is_pwr_by_rate_dec = false, 4324 .max_power_index = 0x7f, 4325 .csi_buf_pg_num = 50, 4326 .band = RTW_BAND_2G | RTW_BAND_5G, 4327 .page_size = 128, 4328 .dig_min = 0x20, 4329 .ht_supported = true, 4330 .vht_supported = true, 4331 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK) | BIT(LPS_DEEP_MODE_PG), 4332 .sys_func_en = 0xD8, 4333 .pwr_on_seq = card_enable_flow_8822c, 4334 .pwr_off_seq = card_disable_flow_8822c, 4335 .page_table = page_table_8822c, 4336 .rqpn_table = rqpn_table_8822c, 4337 .prioq_addrs = &prioq_addrs_8822c, 4338 .intf_table = &phy_para_table_8822c, 4339 .dig = rtw8822c_dig, 4340 .dig_cck = NULL, 4341 .rf_base_addr = {0x3c00, 0x4c00}, 4342 .rf_sipi_addr = {0x1808, 0x4108}, 4343 .ltecoex_addr = &rtw8822c_ltecoex_addr, 4344 .mac_tbl = &rtw8822c_mac_tbl, 4345 .agc_tbl = &rtw8822c_agc_tbl, 4346 .bb_tbl = &rtw8822c_bb_tbl, 4347 .rfk_init_tbl = &rtw8822c_array_mp_cal_init_tbl, 4348 .rf_tbl = {&rtw8822c_rf_b_tbl, &rtw8822c_rf_a_tbl}, 4349 .rfe_defs = rtw8822c_rfe_defs, 4350 .rfe_defs_size = ARRAY_SIZE(rtw8822c_rfe_defs), 4351 .en_dis_dpd = true, 4352 .dpd_ratemask = DIS_DPD_RATEALL, 4353 .pwr_track_tbl = &rtw8822c_rtw_pwr_track_tbl, 4354 .iqk_threshold = 8, 4355 .lck_threshold = 8, 4356 .bfer_su_max_num = 2, 4357 .bfer_mu_max_num = 1, 4358 .rx_ldpc = true, 4359 4360#ifdef CONFIG_PM 4361 .wow_fw_name = "rtw88/rtw8822c_wow_fw.bin", 4362 .wowlan_stub = &rtw_wowlan_stub_8822c, 4363 .max_sched_scan_ssids = 4, 4364#endif 4365 .coex_para_ver = 0x20070217, 4366 .bt_desired_ver = 0x17, 4367 .scbd_support = true, 4368 .new_scbd10_def = true, 4369 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 4370 .bt_rssi_type = COEX_BTRSSI_DBM, 4371 .ant_isolation = 15, 4372 .rssi_tolerance = 2, 4373 .wl_rssi_step = wl_rssi_step_8822c, 4374 .bt_rssi_step = bt_rssi_step_8822c, 4375 .table_sant_num = ARRAY_SIZE(table_sant_8822c), 4376 .table_sant = table_sant_8822c, 4377 .table_nsant_num = ARRAY_SIZE(table_nsant_8822c), 4378 .table_nsant = table_nsant_8822c, 4379 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8822c), 4380 .tdma_sant = tdma_sant_8822c, 4381 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822c), 4382 .tdma_nsant = tdma_nsant_8822c, 4383 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822c), 4384 .wl_rf_para_tx = rf_para_tx_8822c, 4385 .wl_rf_para_rx = rf_para_rx_8822c, 4386 .bt_afh_span_bw20 = 0x24, 4387 .bt_afh_span_bw40 = 0x36, 4388 .afh_5g_num = ARRAY_SIZE(afh_5g_8822c), 4389 .afh_5g = afh_5g_8822c, 4390 4391 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8822c), 4392 .coex_info_hw_regs = coex_info_hw_regs_8822c, 4393 4394 .fw_fifo_addr = {0x780, 0x700, 0x780, 0x660, 0x650, 0x680}, 4395}; 4396EXPORT_SYMBOL(rtw8822c_hw_spec); 4397 4398MODULE_FIRMWARE("rtw88/rtw8822c_fw.bin"); 4399MODULE_FIRMWARE("rtw88/rtw8822c_wow_fw.bin"); 4400 4401MODULE_AUTHOR("Realtek Corporation"); 4402MODULE_DESCRIPTION("Realtek 802.11ac wireless 8822c driver"); 4403MODULE_LICENSE("Dual BSD/GPL"); 4404