1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2/* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5#ifndef __RTW_PHY_H_ 6#define __RTW_PHY_H_ 7 8#include "debug.h" 9 10extern u8 rtw_cck_rates[]; 11extern u8 rtw_ofdm_rates[]; 12extern u8 rtw_ht_1s_rates[]; 13extern u8 rtw_ht_2s_rates[]; 14extern u8 rtw_vht_1s_rates[]; 15extern u8 rtw_vht_2s_rates[]; 16extern u8 *rtw_rate_section[]; 17extern u8 rtw_rate_size[]; 18 19void rtw_phy_init(struct rtw_dev *rtwdev); 20void rtw_phy_dynamic_mechanism(struct rtw_dev *rtwdev); 21u8 rtw_phy_rf_power_2_rssi(s8 *rf_power, u8 path_num); 22u32 rtw_phy_read_rf(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 23 u32 addr, u32 mask); 24u32 rtw_phy_read_rf_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 25 u32 addr, u32 mask); 26bool rtw_phy_write_rf_reg_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 27 u32 addr, u32 mask, u32 data); 28bool rtw_phy_write_rf_reg(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 29 u32 addr, u32 mask, u32 data); 30bool rtw_phy_write_rf_reg_mix(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 31 u32 addr, u32 mask, u32 data); 32void rtw_phy_setup_phy_cond(struct rtw_dev *rtwdev, u32 pkg); 33void rtw_parse_tbl_phy_cond(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 34void rtw_parse_tbl_bb_pg(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 35void rtw_parse_tbl_txpwr_lmt(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 36void rtw_phy_cfg_mac(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 37 u32 addr, u32 data); 38void rtw_phy_cfg_agc(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 39 u32 addr, u32 data); 40void rtw_phy_cfg_bb(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 41 u32 addr, u32 data); 42void rtw_phy_cfg_rf(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 43 u32 addr, u32 data); 44void rtw_phy_init_tx_power(struct rtw_dev *rtwdev); 45void rtw_phy_load_tables(struct rtw_dev *rtwdev); 46u8 rtw_phy_get_tx_power_index(struct rtw_dev *rtwdev, u8 rf_path, u8 rate, 47 enum rtw_bandwidth bw, u8 channel, u8 regd); 48void rtw_phy_set_tx_power_level(struct rtw_dev *rtwdev, u8 channel); 49void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal); 50void rtw_phy_tx_power_limit_config(struct rtw_hal *hal); 51void rtw_phy_pwrtrack_avg(struct rtw_dev *rtwdev, u8 thermal, u8 path); 52bool rtw_phy_pwrtrack_thermal_changed(struct rtw_dev *rtwdev, u8 thermal, 53 u8 path); 54u8 rtw_phy_pwrtrack_get_delta(struct rtw_dev *rtwdev, u8 path); 55s8 rtw_phy_pwrtrack_get_pwridx(struct rtw_dev *rtwdev, 56 struct rtw_swing_table *swing_table, 57 u8 tbl_path, u8 therm_path, u8 delta); 58bool rtw_phy_pwrtrack_need_lck(struct rtw_dev *rtwdev); 59bool rtw_phy_pwrtrack_need_iqk(struct rtw_dev *rtwdev); 60void rtw_phy_config_swing_table(struct rtw_dev *rtwdev, 61 struct rtw_swing_table *swing_table); 62 63struct rtw_txpwr_lmt_cfg_pair { 64 u8 regd; 65 u8 band; 66 u8 bw; 67 u8 rs; 68 u8 ch; 69 s8 txpwr_lmt; 70}; 71 72struct rtw_phy_pg_cfg_pair { 73 u32 band; 74 u32 rf_path; 75 u32 tx_num; 76 u32 addr; 77 u32 bitmask; 78 u32 data; 79}; 80 81#define RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, path) \ 82const struct rtw_table name ## _tbl = { \ 83 .data = name, \ 84 .size = ARRAY_SIZE(name), \ 85 .parse = rtw_parse_tbl_phy_cond, \ 86 .do_cfg = cfg, \ 87 .rf_path = path, \ 88} 89 90#define RTW_DECL_TABLE_PHY_COND(name, cfg) \ 91 RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, 0) 92 93#define RTW_DECL_TABLE_RF_RADIO(name, path) \ 94 RTW_DECL_TABLE_PHY_COND_CORE(name, rtw_phy_cfg_rf, RF_PATH_ ## path) 95 96#define RTW_DECL_TABLE_BB_PG(name) \ 97const struct rtw_table name ## _tbl = { \ 98 .data = name, \ 99 .size = ARRAY_SIZE(name), \ 100 .parse = rtw_parse_tbl_bb_pg, \ 101} 102 103#define RTW_DECL_TABLE_TXPWR_LMT(name) \ 104const struct rtw_table name ## _tbl = { \ 105 .data = name, \ 106 .size = ARRAY_SIZE(name), \ 107 .parse = rtw_parse_tbl_txpwr_lmt, \ 108} 109 110static inline const struct rtw_rfe_def *rtw_get_rfe_def(struct rtw_dev *rtwdev) 111{ 112 struct rtw_chip_info *chip = rtwdev->chip; 113 struct rtw_efuse *efuse = &rtwdev->efuse; 114 const struct rtw_rfe_def *rfe_def = NULL; 115 116 if (chip->rfe_defs_size == 0) 117 return NULL; 118 119 if (efuse->rfe_option < chip->rfe_defs_size) 120 rfe_def = &chip->rfe_defs[efuse->rfe_option]; 121 122 rtw_dbg(rtwdev, RTW_DBG_PHY, "use rfe_def[%d]\n", efuse->rfe_option); 123 return rfe_def; 124} 125 126static inline int rtw_check_supported_rfe(struct rtw_dev *rtwdev) 127{ 128 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); 129 130 if (!rfe_def || !rfe_def->phy_pg_tbl || !rfe_def->txpwr_lmt_tbl) { 131 rtw_err(rtwdev, "rfe %d isn't supported\n", 132 rtwdev->efuse.rfe_option); 133 return -ENODEV; 134 } 135 136 return 0; 137} 138 139void rtw_phy_dig_write(struct rtw_dev *rtwdev, u8 igi); 140 141struct rtw_power_params { 142 u8 pwr_base; 143 s8 pwr_offset; 144 s8 pwr_limit; 145 s8 pwr_remnant; 146}; 147 148void 149rtw_get_tx_power_params(struct rtw_dev *rtwdev, u8 path, 150 u8 rate, u8 bw, u8 ch, u8 regd, 151 struct rtw_power_params *pwr_param); 152 153enum rtw_phy_cck_pd_lv { 154 CCK_PD_LV0, 155 CCK_PD_LV1, 156 CCK_PD_LV2, 157 CCK_PD_LV3, 158 CCK_PD_LV4, 159 CCK_PD_LV_MAX, 160}; 161 162#define MASKBYTE0 0xff 163#define MASKBYTE1 0xff00 164#define MASKBYTE2 0xff0000 165#define MASKBYTE3 0xff000000 166#define MASKHWORD 0xffff0000 167#define MASKLWORD 0x0000ffff 168#define MASKDWORD 0xffffffff 169#define RFREG_MASK 0xfffff 170 171#define MASK7BITS 0x7f 172#define MASK12BITS 0xfff 173#define MASKH4BITS 0xf0000000 174#define MASK20BITS 0xfffff 175#define MASK24BITS 0xffffff 176 177#define MASKH3BYTES 0xffffff00 178#define MASKL3BYTES 0x00ffffff 179#define MASKBYTE2HIGHNIBBLE 0x00f00000 180#define MASKBYTE3LOWNIBBLE 0x0f000000 181#define MASKL3BYTES 0x00ffffff 182 183#define CCK_FA_AVG_RESET 0xffffffff 184 185#define LSSI_READ_ADDR_MASK 0x7f800000 186#define LSSI_READ_EDGE_MASK 0x80000000 187#define LSSI_READ_DATA_MASK 0xfffff 188 189#endif 190