1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2/* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5#ifndef __RTK_MAIN_H_ 6#define __RTK_MAIN_H_ 7 8#include <net/mac80211.h> 9#include <linux/vmalloc.h> 10#include <linux/firmware.h> 11#include <linux/average.h> 12#include <linux/bitops.h> 13#include <linux/bitfield.h> 14#include <linux/iopoll.h> 15#include <linux/interrupt.h> 16 17#include "util.h" 18 19#define RTW_MAX_MAC_ID_NUM 32 20#define RTW_MAX_SEC_CAM_NUM 32 21#define MAX_PG_CAM_BACKUP_NUM 8 22 23#define RTW_MAX_PATTERN_NUM 12 24#define RTW_MAX_PATTERN_MASK_SIZE 16 25#define RTW_MAX_PATTERN_SIZE 128 26 27#define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2) 28 29#define RFREG_MASK 0xfffff 30#define INV_RF_DATA 0xffffffff 31#define TX_PAGE_SIZE_SHIFT 7 32 33#define RTW_CHANNEL_WIDTH_MAX 3 34#define RTW_RF_PATH_MAX 4 35#define HW_FEATURE_LEN 13 36 37#define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */ 38 39extern bool rtw_bf_support; 40extern unsigned int rtw_fw_lps_deep_mode; 41extern unsigned int rtw_debug_mask; 42extern const struct ieee80211_ops rtw_ops; 43 44#define RTW_MAX_CHANNEL_NUM_2G 14 45#define RTW_MAX_CHANNEL_NUM_5G 49 46 47struct rtw_dev; 48 49enum rtw_hci_type { 50 RTW_HCI_TYPE_PCIE, 51 RTW_HCI_TYPE_USB, 52 RTW_HCI_TYPE_SDIO, 53 54 RTW_HCI_TYPE_UNDEFINE, 55}; 56 57struct rtw_hci { 58 struct rtw_hci_ops *ops; 59 enum rtw_hci_type type; 60 61 u32 rpwm_addr; 62 u32 cpwm_addr; 63 64 u8 bulkout_num; 65}; 66 67#define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48)) 68#define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64)) 69#define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144)) 70#define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177)) 71 72#define IS_CH_5G_BAND_MID(channel) \ 73 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel)) 74 75#define IS_CH_2G_BAND(channel) ((channel) <= 14) 76#define IS_CH_5G_BAND(channel) \ 77 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \ 78 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel)) 79 80enum rtw_supported_band { 81 RTW_BAND_2G = 1 << 0, 82 RTW_BAND_5G = 1 << 1, 83 RTW_BAND_60G = 1 << 2, 84 85 RTW_BAND_MAX, 86}; 87 88/* now, support upto 80M bw */ 89#define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80 90 91enum rtw_bandwidth { 92 RTW_CHANNEL_WIDTH_20 = 0, 93 RTW_CHANNEL_WIDTH_40 = 1, 94 RTW_CHANNEL_WIDTH_80 = 2, 95 RTW_CHANNEL_WIDTH_160 = 3, 96 RTW_CHANNEL_WIDTH_80_80 = 4, 97 RTW_CHANNEL_WIDTH_5 = 5, 98 RTW_CHANNEL_WIDTH_10 = 6, 99}; 100 101enum rtw_sc_offset { 102 RTW_SC_DONT_CARE = 0, 103 RTW_SC_20_UPPER = 1, 104 RTW_SC_20_LOWER = 2, 105 RTW_SC_20_UPMOST = 3, 106 RTW_SC_20_LOWEST = 4, 107 RTW_SC_40_UPPER = 9, 108 RTW_SC_40_LOWER = 10, 109}; 110 111enum rtw_net_type { 112 RTW_NET_NO_LINK = 0, 113 RTW_NET_AD_HOC = 1, 114 RTW_NET_MGD_LINKED = 2, 115 RTW_NET_AP_MODE = 3, 116}; 117 118enum rtw_rf_type { 119 RF_1T1R = 0, 120 RF_1T2R = 1, 121 RF_2T2R = 2, 122 RF_2T3R = 3, 123 RF_2T4R = 4, 124 RF_3T3R = 5, 125 RF_3T4R = 6, 126 RF_4T4R = 7, 127 RF_TYPE_MAX, 128}; 129 130enum rtw_rf_path { 131 RF_PATH_A = 0, 132 RF_PATH_B = 1, 133 RF_PATH_C = 2, 134 RF_PATH_D = 3, 135}; 136 137enum rtw_bb_path { 138 BB_PATH_A = BIT(0), 139 BB_PATH_B = BIT(1), 140 BB_PATH_C = BIT(2), 141 BB_PATH_D = BIT(3), 142 143 BB_PATH_AB = (BB_PATH_A | BB_PATH_B), 144 BB_PATH_AC = (BB_PATH_A | BB_PATH_C), 145 BB_PATH_AD = (BB_PATH_A | BB_PATH_D), 146 BB_PATH_BC = (BB_PATH_B | BB_PATH_C), 147 BB_PATH_BD = (BB_PATH_B | BB_PATH_D), 148 BB_PATH_CD = (BB_PATH_C | BB_PATH_D), 149 150 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C), 151 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D), 152 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D), 153 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D), 154 155 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D), 156}; 157 158enum rtw_rate_section { 159 RTW_RATE_SECTION_CCK = 0, 160 RTW_RATE_SECTION_OFDM, 161 RTW_RATE_SECTION_HT_1S, 162 RTW_RATE_SECTION_HT_2S, 163 RTW_RATE_SECTION_VHT_1S, 164 RTW_RATE_SECTION_VHT_2S, 165 166 /* keep last */ 167 RTW_RATE_SECTION_MAX, 168}; 169 170enum rtw_wireless_set { 171 WIRELESS_CCK = 0x00000001, 172 WIRELESS_OFDM = 0x00000002, 173 WIRELESS_HT = 0x00000004, 174 WIRELESS_VHT = 0x00000008, 175}; 176 177#define HT_STBC_EN BIT(0) 178#define VHT_STBC_EN BIT(1) 179#define HT_LDPC_EN BIT(0) 180#define VHT_LDPC_EN BIT(1) 181 182enum rtw_chip_type { 183 RTW_CHIP_TYPE_8822B, 184 RTW_CHIP_TYPE_8822C, 185 RTW_CHIP_TYPE_8723D, 186 RTW_CHIP_TYPE_8821C, 187}; 188 189enum rtw_tx_queue_type { 190 /* the order of AC queues matters */ 191 RTW_TX_QUEUE_BK = 0x0, 192 RTW_TX_QUEUE_BE = 0x1, 193 RTW_TX_QUEUE_VI = 0x2, 194 RTW_TX_QUEUE_VO = 0x3, 195 196 RTW_TX_QUEUE_BCN = 0x4, 197 RTW_TX_QUEUE_MGMT = 0x5, 198 RTW_TX_QUEUE_HI0 = 0x6, 199 RTW_TX_QUEUE_H2C = 0x7, 200 /* keep it last */ 201 RTK_MAX_TX_QUEUE_NUM 202}; 203 204enum rtw_rx_queue_type { 205 RTW_RX_QUEUE_MPDU = 0x0, 206 RTW_RX_QUEUE_C2H = 0x1, 207 /* keep it last */ 208 RTK_MAX_RX_QUEUE_NUM 209}; 210 211enum rtw_fw_type { 212 RTW_NORMAL_FW = 0x0, 213 RTW_WOWLAN_FW = 0x1, 214}; 215 216enum rtw_rate_index { 217 RTW_RATEID_BGN_40M_2SS = 0, 218 RTW_RATEID_BGN_40M_1SS = 1, 219 RTW_RATEID_BGN_20M_2SS = 2, 220 RTW_RATEID_BGN_20M_1SS = 3, 221 RTW_RATEID_GN_N2SS = 4, 222 RTW_RATEID_GN_N1SS = 5, 223 RTW_RATEID_BG = 6, 224 RTW_RATEID_G = 7, 225 RTW_RATEID_B_20M = 8, 226 RTW_RATEID_ARFR0_AC_2SS = 9, 227 RTW_RATEID_ARFR1_AC_1SS = 10, 228 RTW_RATEID_ARFR2_AC_2G_1SS = 11, 229 RTW_RATEID_ARFR3_AC_2G_2SS = 12, 230 RTW_RATEID_ARFR4_AC_3SS = 13, 231 RTW_RATEID_ARFR5_N_3SS = 14, 232 RTW_RATEID_ARFR7_N_4SS = 15, 233 RTW_RATEID_ARFR6_AC_4SS = 16 234}; 235 236enum rtw_trx_desc_rate { 237 DESC_RATE1M = 0x00, 238 DESC_RATE2M = 0x01, 239 DESC_RATE5_5M = 0x02, 240 DESC_RATE11M = 0x03, 241 242 DESC_RATE6M = 0x04, 243 DESC_RATE9M = 0x05, 244 DESC_RATE12M = 0x06, 245 DESC_RATE18M = 0x07, 246 DESC_RATE24M = 0x08, 247 DESC_RATE36M = 0x09, 248 DESC_RATE48M = 0x0a, 249 DESC_RATE54M = 0x0b, 250 251 DESC_RATEMCS0 = 0x0c, 252 DESC_RATEMCS1 = 0x0d, 253 DESC_RATEMCS2 = 0x0e, 254 DESC_RATEMCS3 = 0x0f, 255 DESC_RATEMCS4 = 0x10, 256 DESC_RATEMCS5 = 0x11, 257 DESC_RATEMCS6 = 0x12, 258 DESC_RATEMCS7 = 0x13, 259 DESC_RATEMCS8 = 0x14, 260 DESC_RATEMCS9 = 0x15, 261 DESC_RATEMCS10 = 0x16, 262 DESC_RATEMCS11 = 0x17, 263 DESC_RATEMCS12 = 0x18, 264 DESC_RATEMCS13 = 0x19, 265 DESC_RATEMCS14 = 0x1a, 266 DESC_RATEMCS15 = 0x1b, 267 DESC_RATEMCS16 = 0x1c, 268 DESC_RATEMCS17 = 0x1d, 269 DESC_RATEMCS18 = 0x1e, 270 DESC_RATEMCS19 = 0x1f, 271 DESC_RATEMCS20 = 0x20, 272 DESC_RATEMCS21 = 0x21, 273 DESC_RATEMCS22 = 0x22, 274 DESC_RATEMCS23 = 0x23, 275 DESC_RATEMCS24 = 0x24, 276 DESC_RATEMCS25 = 0x25, 277 DESC_RATEMCS26 = 0x26, 278 DESC_RATEMCS27 = 0x27, 279 DESC_RATEMCS28 = 0x28, 280 DESC_RATEMCS29 = 0x29, 281 DESC_RATEMCS30 = 0x2a, 282 DESC_RATEMCS31 = 0x2b, 283 284 DESC_RATEVHT1SS_MCS0 = 0x2c, 285 DESC_RATEVHT1SS_MCS1 = 0x2d, 286 DESC_RATEVHT1SS_MCS2 = 0x2e, 287 DESC_RATEVHT1SS_MCS3 = 0x2f, 288 DESC_RATEVHT1SS_MCS4 = 0x30, 289 DESC_RATEVHT1SS_MCS5 = 0x31, 290 DESC_RATEVHT1SS_MCS6 = 0x32, 291 DESC_RATEVHT1SS_MCS7 = 0x33, 292 DESC_RATEVHT1SS_MCS8 = 0x34, 293 DESC_RATEVHT1SS_MCS9 = 0x35, 294 295 DESC_RATEVHT2SS_MCS0 = 0x36, 296 DESC_RATEVHT2SS_MCS1 = 0x37, 297 DESC_RATEVHT2SS_MCS2 = 0x38, 298 DESC_RATEVHT2SS_MCS3 = 0x39, 299 DESC_RATEVHT2SS_MCS4 = 0x3a, 300 DESC_RATEVHT2SS_MCS5 = 0x3b, 301 DESC_RATEVHT2SS_MCS6 = 0x3c, 302 DESC_RATEVHT2SS_MCS7 = 0x3d, 303 DESC_RATEVHT2SS_MCS8 = 0x3e, 304 DESC_RATEVHT2SS_MCS9 = 0x3f, 305 306 DESC_RATEVHT3SS_MCS0 = 0x40, 307 DESC_RATEVHT3SS_MCS1 = 0x41, 308 DESC_RATEVHT3SS_MCS2 = 0x42, 309 DESC_RATEVHT3SS_MCS3 = 0x43, 310 DESC_RATEVHT3SS_MCS4 = 0x44, 311 DESC_RATEVHT3SS_MCS5 = 0x45, 312 DESC_RATEVHT3SS_MCS6 = 0x46, 313 DESC_RATEVHT3SS_MCS7 = 0x47, 314 DESC_RATEVHT3SS_MCS8 = 0x48, 315 DESC_RATEVHT3SS_MCS9 = 0x49, 316 317 DESC_RATEVHT4SS_MCS0 = 0x4a, 318 DESC_RATEVHT4SS_MCS1 = 0x4b, 319 DESC_RATEVHT4SS_MCS2 = 0x4c, 320 DESC_RATEVHT4SS_MCS3 = 0x4d, 321 DESC_RATEVHT4SS_MCS4 = 0x4e, 322 DESC_RATEVHT4SS_MCS5 = 0x4f, 323 DESC_RATEVHT4SS_MCS6 = 0x50, 324 DESC_RATEVHT4SS_MCS7 = 0x51, 325 DESC_RATEVHT4SS_MCS8 = 0x52, 326 DESC_RATEVHT4SS_MCS9 = 0x53, 327 328 DESC_RATE_MAX, 329}; 330 331enum rtw_regulatory_domains { 332 RTW_REGD_FCC = 0, 333 RTW_REGD_MKK = 1, 334 RTW_REGD_ETSI = 2, 335 RTW_REGD_IC = 3, 336 RTW_REGD_KCC = 4, 337 RTW_REGD_ACMA = 5, 338 RTW_REGD_CHILE = 6, 339 RTW_REGD_UKRAINE = 7, 340 RTW_REGD_MEXICO = 8, 341 RTW_REGD_CN = 9, 342 RTW_REGD_WW, 343 344 RTW_REGD_MAX 345}; 346 347enum rtw_txq_flags { 348 RTW_TXQ_AMPDU, 349 RTW_TXQ_BLOCK_BA, 350}; 351 352enum rtw_flags { 353 RTW_FLAG_RUNNING, 354 RTW_FLAG_FW_RUNNING, 355 RTW_FLAG_SCANNING, 356 RTW_FLAG_INACTIVE_PS, 357 RTW_FLAG_LEISURE_PS, 358 RTW_FLAG_LEISURE_PS_DEEP, 359 RTW_FLAG_DIG_DISABLE, 360 RTW_FLAG_BUSY_TRAFFIC, 361 RTW_FLAG_WOWLAN, 362 RTW_FLAG_RESTARTING, 363 364 NUM_OF_RTW_FLAGS, 365}; 366 367enum rtw_evm { 368 RTW_EVM_OFDM = 0, 369 RTW_EVM_1SS, 370 RTW_EVM_2SS_A, 371 RTW_EVM_2SS_B, 372 /* keep it last */ 373 RTW_EVM_NUM 374}; 375 376enum rtw_snr { 377 RTW_SNR_OFDM_A = 0, 378 RTW_SNR_OFDM_B, 379 RTW_SNR_OFDM_C, 380 RTW_SNR_OFDM_D, 381 RTW_SNR_1SS_A, 382 RTW_SNR_1SS_B, 383 RTW_SNR_1SS_C, 384 RTW_SNR_1SS_D, 385 RTW_SNR_2SS_A, 386 RTW_SNR_2SS_B, 387 RTW_SNR_2SS_C, 388 RTW_SNR_2SS_D, 389 /* keep it last */ 390 RTW_SNR_NUM 391}; 392 393enum rtw_wow_flags { 394 RTW_WOW_FLAG_EN_MAGIC_PKT, 395 RTW_WOW_FLAG_EN_REKEY_PKT, 396 RTW_WOW_FLAG_EN_DISCONNECT, 397 398 /* keep it last */ 399 RTW_WOW_FLAG_MAX, 400}; 401 402/* the power index is represented by differences, which cck-1s & ht40-1s are 403 * the base values, so for 1s's differences, there are only ht20 & ofdm 404 */ 405struct rtw_2g_1s_pwr_idx_diff { 406#ifdef __LITTLE_ENDIAN 407 s8 ofdm:4; 408 s8 bw20:4; 409#else 410 s8 bw20:4; 411 s8 ofdm:4; 412#endif 413} __packed; 414 415struct rtw_2g_ns_pwr_idx_diff { 416#ifdef __LITTLE_ENDIAN 417 s8 bw20:4; 418 s8 bw40:4; 419 s8 cck:4; 420 s8 ofdm:4; 421#else 422 s8 ofdm:4; 423 s8 cck:4; 424 s8 bw40:4; 425 s8 bw20:4; 426#endif 427} __packed; 428 429struct rtw_2g_txpwr_idx { 430 u8 cck_base[6]; 431 u8 bw40_base[5]; 432 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff; 433 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff; 434 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff; 435 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff; 436}; 437 438struct rtw_5g_ht_1s_pwr_idx_diff { 439#ifdef __LITTLE_ENDIAN 440 s8 ofdm:4; 441 s8 bw20:4; 442#else 443 s8 bw20:4; 444 s8 ofdm:4; 445#endif 446} __packed; 447 448struct rtw_5g_ht_ns_pwr_idx_diff { 449#ifdef __LITTLE_ENDIAN 450 s8 bw20:4; 451 s8 bw40:4; 452#else 453 s8 bw40:4; 454 s8 bw20:4; 455#endif 456} __packed; 457 458struct rtw_5g_ofdm_ns_pwr_idx_diff { 459#ifdef __LITTLE_ENDIAN 460 s8 ofdm_3s:4; 461 s8 ofdm_2s:4; 462 s8 ofdm_4s:4; 463 s8 res:4; 464#else 465 s8 res:4; 466 s8 ofdm_4s:4; 467 s8 ofdm_2s:4; 468 s8 ofdm_3s:4; 469#endif 470} __packed; 471 472struct rtw_5g_vht_ns_pwr_idx_diff { 473#ifdef __LITTLE_ENDIAN 474 s8 bw160:4; 475 s8 bw80:4; 476#else 477 s8 bw80:4; 478 s8 bw160:4; 479#endif 480} __packed; 481 482struct rtw_5g_txpwr_idx { 483 u8 bw40_base[14]; 484 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff; 485 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff; 486 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff; 487 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff; 488 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff; 489 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff; 490 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff; 491 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff; 492 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff; 493}; 494 495struct rtw_txpwr_idx { 496 struct rtw_2g_txpwr_idx pwr_idx_2g; 497 struct rtw_5g_txpwr_idx pwr_idx_5g; 498}; 499 500struct rtw_timer_list { 501 struct timer_list timer; 502 void (*function)(void *data); 503 void *args; 504}; 505 506struct rtw_channel_params { 507 u8 center_chan; 508 u8 bandwidth; 509 u8 primary_chan_idx; 510 /* center channel by different available bandwidth, 511 * val of (bw > current bandwidth) is invalid 512 */ 513 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 514}; 515 516struct rtw_hw_reg { 517 u32 addr; 518 u32 mask; 519}; 520 521struct rtw_ltecoex_addr { 522 u32 ctrl; 523 u32 wdata; 524 u32 rdata; 525}; 526 527struct rtw_reg_domain { 528 u32 addr; 529 u32 mask; 530#define RTW_REG_DOMAIN_MAC32 0 531#define RTW_REG_DOMAIN_MAC16 1 532#define RTW_REG_DOMAIN_MAC8 2 533#define RTW_REG_DOMAIN_RF_A 3 534#define RTW_REG_DOMAIN_RF_B 4 535#define RTW_REG_DOMAIN_NL 0xFF 536 u8 domain; 537}; 538 539struct rtw_rf_sipi_addr { 540 u32 hssi_1; 541 u32 hssi_2; 542 u32 lssi_read; 543 u32 lssi_read_pi; 544}; 545 546struct rtw_backup_info { 547 u8 len; 548 u32 reg; 549 u32 val; 550}; 551 552enum rtw_vif_port_set { 553 PORT_SET_MAC_ADDR = BIT(0), 554 PORT_SET_BSSID = BIT(1), 555 PORT_SET_NET_TYPE = BIT(2), 556 PORT_SET_AID = BIT(3), 557 PORT_SET_BCN_CTRL = BIT(4), 558}; 559 560struct rtw_vif_port { 561 struct rtw_hw_reg mac_addr; 562 struct rtw_hw_reg bssid; 563 struct rtw_hw_reg net_type; 564 struct rtw_hw_reg aid; 565 struct rtw_hw_reg bcn_ctrl; 566}; 567 568struct rtw_tx_pkt_info { 569 u32 tx_pkt_size; 570 u8 offset; 571 u8 pkt_offset; 572 u8 mac_id; 573 u8 rate_id; 574 u8 rate; 575 u8 qsel; 576 u8 bw; 577 u8 sec_type; 578 u8 sn; 579 bool ampdu_en; 580 u8 ampdu_factor; 581 u8 ampdu_density; 582 u16 seq; 583 bool stbc; 584 bool ldpc; 585 bool dis_rate_fallback; 586 bool bmc; 587 bool use_rate; 588 bool ls; 589 bool fs; 590 bool short_gi; 591 bool report; 592 bool rts; 593 bool dis_qselseq; 594 bool en_hwseq; 595 u8 hw_ssn_sel; 596 bool nav_use_hdr; 597 bool bt_null; 598}; 599 600struct rtw_rx_pkt_stat { 601 bool phy_status; 602 bool icv_err; 603 bool crc_err; 604 bool decrypted; 605 bool is_c2h; 606 607 s32 signal_power; 608 u16 pkt_len; 609 u8 bw; 610 u8 drv_info_sz; 611 u8 shift; 612 u8 rate; 613 u8 mac_id; 614 u8 cam_id; 615 u8 ppdu_cnt; 616 u32 tsf_low; 617 s8 rx_power[RTW_RF_PATH_MAX]; 618 u8 rssi; 619 u8 rxsc; 620 s8 rx_snr[RTW_RF_PATH_MAX]; 621 u8 rx_evm[RTW_RF_PATH_MAX]; 622 s8 cfo_tail[RTW_RF_PATH_MAX]; 623 624 struct rtw_sta_info *si; 625 struct ieee80211_vif *vif; 626}; 627 628DECLARE_EWMA(tp, 10, 2); 629 630struct rtw_traffic_stats { 631 /* units in bytes */ 632 u64 tx_unicast; 633 u64 rx_unicast; 634 635 /* count for packets */ 636 u64 tx_cnt; 637 u64 rx_cnt; 638 639 /* units in Mbps */ 640 u32 tx_throughput; 641 u32 rx_throughput; 642 struct ewma_tp tx_ewma_tp; 643 struct ewma_tp rx_ewma_tp; 644}; 645 646enum rtw_lps_mode { 647 RTW_MODE_ACTIVE = 0, 648 RTW_MODE_LPS = 1, 649 RTW_MODE_WMM_PS = 2, 650}; 651 652enum rtw_lps_deep_mode { 653 LPS_DEEP_MODE_NONE = 0, 654 LPS_DEEP_MODE_LCLK = 1, 655 LPS_DEEP_MODE_PG = 2, 656}; 657 658enum rtw_pwr_state { 659 RTW_RF_OFF = 0x0, 660 RTW_RF_ON = 0x4, 661 RTW_ALL_ON = 0xc, 662}; 663 664struct rtw_lps_conf { 665 enum rtw_lps_mode mode; 666 enum rtw_lps_deep_mode deep_mode; 667 enum rtw_pwr_state state; 668 u8 awake_interval; 669 u8 rlbm; 670 u8 smart_ps; 671 u8 port_id; 672 bool sec_cam_backup; 673 bool pattern_cam_backup; 674}; 675 676enum rtw_hw_key_type { 677 RTW_CAM_NONE = 0, 678 RTW_CAM_WEP40 = 1, 679 RTW_CAM_TKIP = 2, 680 RTW_CAM_AES = 4, 681 RTW_CAM_WEP104 = 5, 682}; 683 684struct rtw_cam_entry { 685 bool valid; 686 bool group; 687 u8 addr[ETH_ALEN]; 688 u8 hw_key_type; 689 struct ieee80211_key_conf *key; 690}; 691 692struct rtw_sec_desc { 693 /* search strategy */ 694 bool default_key_search; 695 696 u32 total_cam_num; 697 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM]; 698 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM); 699}; 700 701struct rtw_tx_report { 702 /* protect the tx report queue */ 703 spinlock_t q_lock; 704 struct sk_buff_head queue; 705 atomic_t sn; 706 struct timer_list purge_timer; 707}; 708 709struct rtw_ra_report { 710 struct rate_info txrate; 711 u32 bit_rate; 712 u8 desc_rate; 713}; 714 715struct rtw_txq { 716 struct list_head list; 717 718 unsigned long flags; 719 unsigned long last_push; 720}; 721 722#define RTW_BC_MC_MACID 1 723DECLARE_EWMA(rssi, 10, 16); 724 725struct rtw_sta_info { 726 struct ieee80211_sta *sta; 727 struct ieee80211_vif *vif; 728 729 struct ewma_rssi avg_rssi; 730 u8 rssi_level; 731 732 u8 mac_id; 733 u8 rate_id; 734 enum rtw_bandwidth bw_mode; 735 enum rtw_rf_type rf_type; 736 enum rtw_wireless_set wireless_set; 737 u8 stbc_en:2; 738 u8 ldpc_en:2; 739 bool sgi_enable; 740 bool vht_enable; 741 bool updated; 742 u8 init_ra_lv; 743 u64 ra_mask; 744 745 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS); 746 747 struct rtw_ra_report ra_report; 748 749 bool use_cfg_mask; 750 struct cfg80211_bitrate_mask *mask; 751}; 752 753enum rtw_bfee_role { 754 RTW_BFEE_NONE, 755 RTW_BFEE_SU, 756 RTW_BFEE_MU 757}; 758 759struct rtw_bfee { 760 enum rtw_bfee_role role; 761 762 u16 p_aid; 763 u8 g_id; 764 u8 mac_addr[ETH_ALEN]; 765 u8 sound_dim; 766 767 /* SU-MIMO */ 768 u8 su_reg_index; 769 770 /* MU-MIMO */ 771 u16 aid; 772}; 773 774struct rtw_bf_info { 775 u8 bfer_mu_cnt; 776 u8 bfer_su_cnt; 777 DECLARE_BITMAP(bfer_su_reg_maping, 2); 778 u8 cur_csi_rpt_rate; 779}; 780 781struct rtw_vif { 782 enum rtw_net_type net_type; 783 u16 aid; 784 u8 mac_addr[ETH_ALEN]; 785 u8 bssid[ETH_ALEN]; 786 u8 port; 787 u8 bcn_ctrl; 788 struct list_head rsvd_page_list; 789 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 790 const struct rtw_vif_port *conf; 791 792 struct rtw_traffic_stats stats; 793 794 struct rtw_bfee bfee; 795}; 796 797struct rtw_regulatory { 798 char alpha2[2]; 799 u8 chplan; 800 u8 txpwr_regd; 801}; 802 803struct rtw_chip_ops { 804 int (*mac_init)(struct rtw_dev *rtwdev); 805 void (*shutdown)(struct rtw_dev *rtwdev); 806 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map); 807 void (*phy_set_param)(struct rtw_dev *rtwdev); 808 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel, 809 u8 bandwidth, u8 primary_chan_idx); 810 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc, 811 struct rtw_rx_pkt_stat *pkt_stat, 812 struct ieee80211_rx_status *rx_status); 813 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 814 u32 addr, u32 mask); 815 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 816 u32 addr, u32 mask, u32 data); 817 void (*set_tx_power_index)(struct rtw_dev *rtwdev); 818 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset, 819 u32 size); 820 int (*set_antenna)(struct rtw_dev *rtwdev, 821 u32 antenna_tx, 822 u32 antenna_rx); 823 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable); 824 void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable); 825 void (*false_alarm_statistics)(struct rtw_dev *rtwdev); 826 void (*phy_calibration)(struct rtw_dev *rtwdev); 827 void (*dpk_track)(struct rtw_dev *rtwdev); 828 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level); 829 void (*pwr_track)(struct rtw_dev *rtwdev); 830 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif, 831 struct rtw_bfee *bfee, bool enable); 832 void (*set_gid_table)(struct rtw_dev *rtwdev, 833 struct ieee80211_vif *vif, 834 struct ieee80211_bss_conf *conf); 835 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate, 836 u8 fixrate_en, u8 *new_rate); 837 838 /* for coex */ 839 void (*coex_set_init)(struct rtw_dev *rtwdev); 840 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev, 841 u8 ctrl_type, u8 pos_type); 842 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev); 843 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev); 844 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev); 845 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr); 846 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain); 847}; 848 849#define RTW_PWR_POLLING_CNT 20000 850 851#define RTW_PWR_CMD_READ 0x00 852#define RTW_PWR_CMD_WRITE 0x01 853#define RTW_PWR_CMD_POLLING 0x02 854#define RTW_PWR_CMD_DELAY 0x03 855#define RTW_PWR_CMD_END 0x04 856 857/* define the base address of each block */ 858#define RTW_PWR_ADDR_MAC 0x00 859#define RTW_PWR_ADDR_USB 0x01 860#define RTW_PWR_ADDR_PCIE 0x02 861#define RTW_PWR_ADDR_SDIO 0x03 862 863#define RTW_PWR_INTF_SDIO_MSK BIT(0) 864#define RTW_PWR_INTF_USB_MSK BIT(1) 865#define RTW_PWR_INTF_PCI_MSK BIT(2) 866#define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 867 868#define RTW_PWR_CUT_TEST_MSK BIT(0) 869#define RTW_PWR_CUT_A_MSK BIT(1) 870#define RTW_PWR_CUT_B_MSK BIT(2) 871#define RTW_PWR_CUT_C_MSK BIT(3) 872#define RTW_PWR_CUT_D_MSK BIT(4) 873#define RTW_PWR_CUT_E_MSK BIT(5) 874#define RTW_PWR_CUT_F_MSK BIT(6) 875#define RTW_PWR_CUT_G_MSK BIT(7) 876#define RTW_PWR_CUT_ALL_MSK 0xFF 877 878enum rtw_pwr_seq_cmd_delay_unit { 879 RTW_PWR_DELAY_US, 880 RTW_PWR_DELAY_MS, 881}; 882 883struct rtw_pwr_seq_cmd { 884 u16 offset; 885 u8 cut_mask; 886 u8 intf_mask; 887 u8 base:4; 888 u8 cmd:4; 889 u8 mask; 890 u8 value; 891}; 892 893enum rtw_chip_ver { 894 RTW_CHIP_VER_CUT_A = 0x00, 895 RTW_CHIP_VER_CUT_B = 0x01, 896 RTW_CHIP_VER_CUT_C = 0x02, 897 RTW_CHIP_VER_CUT_D = 0x03, 898 RTW_CHIP_VER_CUT_E = 0x04, 899 RTW_CHIP_VER_CUT_F = 0x05, 900 RTW_CHIP_VER_CUT_G = 0x06, 901}; 902 903#define RTW_INTF_PHY_PLATFORM_ALL 0 904 905enum rtw_intf_phy_cut { 906 RTW_INTF_PHY_CUT_A = BIT(0), 907 RTW_INTF_PHY_CUT_B = BIT(1), 908 RTW_INTF_PHY_CUT_C = BIT(2), 909 RTW_INTF_PHY_CUT_D = BIT(3), 910 RTW_INTF_PHY_CUT_E = BIT(4), 911 RTW_INTF_PHY_CUT_F = BIT(5), 912 RTW_INTF_PHY_CUT_G = BIT(6), 913 RTW_INTF_PHY_CUT_ALL = 0xFFFF, 914}; 915 916enum rtw_ip_sel { 917 RTW_IP_SEL_PHY = 0, 918 RTW_IP_SEL_MAC = 1, 919 RTW_IP_SEL_DBI = 2, 920 921 RTW_IP_SEL_UNDEF = 0xFFFF 922}; 923 924enum rtw_pq_map_id { 925 RTW_PQ_MAP_VO = 0x0, 926 RTW_PQ_MAP_VI = 0x1, 927 RTW_PQ_MAP_BE = 0x2, 928 RTW_PQ_MAP_BK = 0x3, 929 RTW_PQ_MAP_MG = 0x4, 930 RTW_PQ_MAP_HI = 0x5, 931 RTW_PQ_MAP_NUM = 0x6, 932 933 RTW_PQ_MAP_UNDEF, 934}; 935 936enum rtw_dma_mapping { 937 RTW_DMA_MAPPING_EXTRA = 0, 938 RTW_DMA_MAPPING_LOW = 1, 939 RTW_DMA_MAPPING_NORMAL = 2, 940 RTW_DMA_MAPPING_HIGH = 3, 941 942 RTW_DMA_MAPPING_MAX, 943 RTW_DMA_MAPPING_UNDEF, 944}; 945 946struct rtw_rqpn { 947 enum rtw_dma_mapping dma_map_vo; 948 enum rtw_dma_mapping dma_map_vi; 949 enum rtw_dma_mapping dma_map_be; 950 enum rtw_dma_mapping dma_map_bk; 951 enum rtw_dma_mapping dma_map_mg; 952 enum rtw_dma_mapping dma_map_hi; 953}; 954 955struct rtw_prioq_addr { 956 u32 rsvd; 957 u32 avail; 958}; 959 960struct rtw_prioq_addrs { 961 struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX]; 962 bool wsize; 963}; 964 965struct rtw_page_table { 966 u16 hq_num; 967 u16 nq_num; 968 u16 lq_num; 969 u16 exq_num; 970 u16 gapq_num; 971}; 972 973struct rtw_intf_phy_para { 974 u16 offset; 975 u16 value; 976 u16 ip_sel; 977 u16 cut_mask; 978 u16 platform; 979}; 980 981struct rtw_wow_pattern { 982 u16 crc; 983 u8 type; 984 u8 valid; 985 u8 mask[RTW_MAX_PATTERN_MASK_SIZE]; 986}; 987 988struct rtw_pno_request { 989 bool inited; 990 u32 match_set_cnt; 991 struct cfg80211_match_set *match_sets; 992 u8 channel_cnt; 993 struct ieee80211_channel *channels; 994 struct cfg80211_sched_scan_plan scan_plan; 995}; 996 997struct rtw_wow_param { 998 struct ieee80211_vif *wow_vif; 999 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX); 1000 u8 txpause; 1001 u8 pattern_cnt; 1002 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM]; 1003 1004 bool ips_enabled; 1005 struct rtw_pno_request pno_req; 1006}; 1007 1008struct rtw_intf_phy_para_table { 1009 const struct rtw_intf_phy_para *usb2_para; 1010 const struct rtw_intf_phy_para *usb3_para; 1011 const struct rtw_intf_phy_para *gen1_para; 1012 const struct rtw_intf_phy_para *gen2_para; 1013 u8 n_usb2_para; 1014 u8 n_usb3_para; 1015 u8 n_gen1_para; 1016 u8 n_gen2_para; 1017}; 1018 1019struct rtw_table { 1020 const void *data; 1021 const u32 size; 1022 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 1023 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1024 u32 addr, u32 data); 1025 enum rtw_rf_path rf_path; 1026}; 1027 1028static inline void rtw_load_table(struct rtw_dev *rtwdev, 1029 const struct rtw_table *tbl) 1030{ 1031 (*tbl->parse)(rtwdev, tbl); 1032} 1033 1034enum rtw_rfe_fem { 1035 RTW_RFE_IFEM, 1036 RTW_RFE_EFEM, 1037 RTW_RFE_IFEM2G_EFEM5G, 1038 RTW_RFE_NUM, 1039}; 1040 1041struct rtw_rfe_def { 1042 const struct rtw_table *phy_pg_tbl; 1043 const struct rtw_table *txpwr_lmt_tbl; 1044}; 1045 1046#define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \ 1047 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1048 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1049 } 1050 1051#define RTW_PWR_TRK_5G_1 0 1052#define RTW_PWR_TRK_5G_2 1 1053#define RTW_PWR_TRK_5G_3 2 1054#define RTW_PWR_TRK_5G_NUM 3 1055 1056#define RTW_PWR_TRK_TBL_SZ 30 1057 1058/* This table stores the values of TX power that will be adjusted by power 1059 * tracking. 1060 * 1061 * For 5G bands, there are 3 different settings. 1062 * For 2G there are cck rate and ofdm rate with different settings. 1063 */ 1064struct rtw_pwr_track_tbl { 1065 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM]; 1066 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM]; 1067 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM]; 1068 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM]; 1069 const u8 *pwrtrk_2gb_n; 1070 const u8 *pwrtrk_2gb_p; 1071 const u8 *pwrtrk_2ga_n; 1072 const u8 *pwrtrk_2ga_p; 1073 const u8 *pwrtrk_2g_cckb_n; 1074 const u8 *pwrtrk_2g_cckb_p; 1075 const u8 *pwrtrk_2g_ccka_n; 1076 const u8 *pwrtrk_2g_ccka_p; 1077 const s8 *pwrtrk_xtal_n; 1078 const s8 *pwrtrk_xtal_p; 1079}; 1080 1081enum rtw_wlan_cpu { 1082 RTW_WCPU_11AC, 1083 RTW_WCPU_11N, 1084}; 1085 1086enum rtw_fw_fifo_sel { 1087 RTW_FW_FIFO_SEL_TX, 1088 RTW_FW_FIFO_SEL_RX, 1089 RTW_FW_FIFO_SEL_RSVD_PAGE, 1090 RTW_FW_FIFO_SEL_REPORT, 1091 RTW_FW_FIFO_SEL_LLT, 1092 RTW_FW_FIFO_SEL_RXBUF_FW, 1093 1094 RTW_FW_FIFO_MAX, 1095}; 1096 1097/* hardware configuration for each IC */ 1098struct rtw_chip_info { 1099 struct rtw_chip_ops *ops; 1100 u8 id; 1101 1102 const char *fw_name; 1103 enum rtw_wlan_cpu wlan_cpu; 1104 u8 tx_pkt_desc_sz; 1105 u8 tx_buf_desc_sz; 1106 u8 rx_pkt_desc_sz; 1107 u8 rx_buf_desc_sz; 1108 u32 phy_efuse_size; 1109 u32 log_efuse_size; 1110 u32 ptct_efuse_size; 1111 u32 txff_size; 1112 u32 rxff_size; 1113 u32 fw_rxff_size; 1114 u8 band; 1115 u8 page_size; 1116 u8 csi_buf_pg_num; 1117 u8 dig_max; 1118 u8 dig_min; 1119 u8 txgi_factor; 1120 bool is_pwr_by_rate_dec; 1121 bool rx_ldpc; 1122 u8 max_power_index; 1123 1124 u16 fw_fifo_addr[RTW_FW_FIFO_MAX]; 1125 1126 bool ht_supported; 1127 bool vht_supported; 1128 u8 lps_deep_mode_supported; 1129 1130 /* init values */ 1131 u8 sys_func_en; 1132 const struct rtw_pwr_seq_cmd **pwr_on_seq; 1133 const struct rtw_pwr_seq_cmd **pwr_off_seq; 1134 const struct rtw_rqpn *rqpn_table; 1135 const struct rtw_prioq_addrs *prioq_addrs; 1136 const struct rtw_page_table *page_table; 1137 const struct rtw_intf_phy_para_table *intf_table; 1138 1139 const struct rtw_hw_reg *dig; 1140 const struct rtw_hw_reg *dig_cck; 1141 u32 rf_base_addr[2]; 1142 u32 rf_sipi_addr[2]; 1143 const struct rtw_rf_sipi_addr *rf_sipi_read_addr; 1144 u8 fix_rf_phy_num; 1145 const struct rtw_ltecoex_addr *ltecoex_addr; 1146 1147 const struct rtw_table *mac_tbl; 1148 const struct rtw_table *agc_tbl; 1149 const struct rtw_table *bb_tbl; 1150 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX]; 1151 const struct rtw_table *rfk_init_tbl; 1152 1153 const struct rtw_rfe_def *rfe_defs; 1154 u32 rfe_defs_size; 1155 1156 bool en_dis_dpd; 1157 u16 dpd_ratemask; 1158 u8 iqk_threshold; 1159 u8 lck_threshold; 1160 const struct rtw_pwr_track_tbl *pwr_track_tbl; 1161 1162 u8 bfer_su_max_num; 1163 u8 bfer_mu_max_num; 1164 1165 const char *wow_fw_name; 1166 const struct wiphy_wowlan_support *wowlan_stub; 1167 const u8 max_sched_scan_ssids; 1168 1169 /* for 8821c set channel */ 1170 u32 ch_param[3]; 1171 1172 /* coex paras */ 1173 u32 coex_para_ver; 1174 u8 bt_desired_ver; 1175 bool scbd_support; 1176 bool new_scbd10_def; /* true: fix 2M(8822c) */ 1177 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */ 1178 u8 bt_rssi_type; 1179 u8 ant_isolation; 1180 u8 rssi_tolerance; 1181 u8 table_sant_num; 1182 u8 table_nsant_num; 1183 u8 tdma_sant_num; 1184 u8 tdma_nsant_num; 1185 u8 bt_afh_span_bw20; 1186 u8 bt_afh_span_bw40; 1187 u8 afh_5g_num; 1188 u8 wl_rf_para_num; 1189 u8 coex_info_hw_regs_num; 1190 const u8 *bt_rssi_step; 1191 const u8 *wl_rssi_step; 1192 const struct coex_table_para *table_nsant; 1193 const struct coex_table_para *table_sant; 1194 const struct coex_tdma_para *tdma_sant; 1195 const struct coex_tdma_para *tdma_nsant; 1196 const struct coex_rf_para *wl_rf_para_tx; 1197 const struct coex_rf_para *wl_rf_para_rx; 1198 const struct coex_5g_afh_map *afh_5g; 1199 const struct rtw_hw_reg *btg_reg; 1200 const struct rtw_reg_domain *coex_info_hw_regs; 1201}; 1202 1203enum rtw_coex_bt_state_cnt { 1204 COEX_CNT_BT_RETRY, 1205 COEX_CNT_BT_REINIT, 1206 COEX_CNT_BT_REENABLE, 1207 COEX_CNT_BT_POPEVENT, 1208 COEX_CNT_BT_SETUPLINK, 1209 COEX_CNT_BT_IGNWLANACT, 1210 COEX_CNT_BT_INQ, 1211 COEX_CNT_BT_PAGE, 1212 COEX_CNT_BT_ROLESWITCH, 1213 COEX_CNT_BT_AFHUPDATE, 1214 COEX_CNT_BT_INFOUPDATE, 1215 COEX_CNT_BT_IQK, 1216 COEX_CNT_BT_IQKFAIL, 1217 1218 COEX_CNT_BT_MAX 1219}; 1220 1221enum rtw_coex_wl_state_cnt { 1222 COEX_CNT_WL_CONNPKT, 1223 COEX_CNT_WL_COEXRUN, 1224 COEX_CNT_WL_NOISY0, 1225 COEX_CNT_WL_NOISY1, 1226 COEX_CNT_WL_NOISY2, 1227 COEX_CNT_WL_5MS_NOEXTEND, 1228 COEX_CNT_WL_FW_NOTIFY, 1229 1230 COEX_CNT_WL_MAX 1231}; 1232 1233struct rtw_coex_rfe { 1234 bool ant_switch_exist; 1235 bool ant_switch_diversity; 1236 bool ant_switch_with_bt; 1237 u8 rfe_module_type; 1238 u8 ant_switch_polarity; 1239 1240 /* true if WLG at BTG, else at WLAG */ 1241 bool wlg_at_btg; 1242}; 1243 1244struct rtw_coex_dm { 1245 bool cur_ps_tdma_on; 1246 bool cur_wl_rx_low_gain_en; 1247 bool ignore_wl_act; 1248 1249 u8 reason; 1250 u8 bt_rssi_state[4]; 1251 u8 wl_rssi_state[4]; 1252 u8 wl_ch_info[3]; 1253 u8 cur_ps_tdma; 1254 u8 cur_table; 1255 u8 ps_tdma_para[5]; 1256 u8 cur_bt_pwr_lvl; 1257 u8 cur_bt_lna_lvl; 1258 u8 cur_wl_pwr_lvl; 1259 u8 bt_status; 1260 u32 cur_ant_pos_type; 1261 u32 cur_switch_status; 1262 u32 setting_tdma; 1263}; 1264 1265#define COEX_BTINFO_SRC_WL_FW 0x0 1266#define COEX_BTINFO_SRC_BT_RSP 0x1 1267#define COEX_BTINFO_SRC_BT_ACT 0x2 1268#define COEX_BTINFO_SRC_BT_IQK 0x3 1269#define COEX_BTINFO_SRC_BT_SCBD 0x4 1270#define COEX_BTINFO_SRC_MAX 0x5 1271 1272#define COEX_INFO_FTP BIT(7) 1273#define COEX_INFO_A2DP BIT(6) 1274#define COEX_INFO_HID BIT(5) 1275#define COEX_INFO_SCO_BUSY BIT(4) 1276#define COEX_INFO_ACL_BUSY BIT(3) 1277#define COEX_INFO_INQ_PAGE BIT(2) 1278#define COEX_INFO_SCO_ESCO BIT(1) 1279#define COEX_INFO_CONNECTION BIT(0) 1280#define COEX_BTINFO_LENGTH_MAX 10 1281 1282struct rtw_coex_stat { 1283 bool bt_disabled; 1284 bool bt_disabled_pre; 1285 bool bt_link_exist; 1286 bool bt_whck_test; 1287 bool bt_inq_page; 1288 bool bt_inq_remain; 1289 bool bt_inq; 1290 bool bt_page; 1291 bool bt_ble_voice; 1292 bool bt_ble_exist; 1293 bool bt_hfp_exist; 1294 bool bt_a2dp_exist; 1295 bool bt_hid_exist; 1296 bool bt_pan_exist; /* PAN or OPP */ 1297 bool bt_opp_exist; /* OPP only */ 1298 bool bt_acl_busy; 1299 bool bt_fix_2M; 1300 bool bt_setup_link; 1301 bool bt_multi_link; 1302 bool bt_a2dp_sink; 1303 bool bt_a2dp_active; 1304 bool bt_reenable; 1305 bool bt_ble_scan_en; 1306 bool bt_init_scan; 1307 bool bt_slave; 1308 bool bt_418_hid_exist; 1309 bool bt_mailbox_reply; 1310 1311 bool wl_under_lps; 1312 bool wl_under_ips; 1313 bool wl_hi_pri_task1; 1314 bool wl_hi_pri_task2; 1315 bool wl_force_lps_ctrl; 1316 bool wl_gl_busy; 1317 bool wl_linkscan_proc; 1318 bool wl_ps_state_fail; 1319 bool wl_tx_limit_en; 1320 bool wl_ampdu_limit_en; 1321 bool wl_connected; 1322 bool wl_slot_extend; 1323 bool wl_cck_lock; 1324 bool wl_cck_lock_pre; 1325 bool wl_cck_lock_ever; 1326 1327 u32 bt_supported_version; 1328 u32 bt_supported_feature; 1329 u32 patch_ver; 1330 u16 bt_reg_vendor_ae; 1331 u16 bt_reg_vendor_ac; 1332 s8 bt_rssi; 1333 u8 kt_ver; 1334 u8 gnt_workaround_state; 1335 u8 tdma_timer_base; 1336 u8 bt_profile_num; 1337 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX]; 1338 u8 bt_info_lb2; 1339 u8 bt_info_lb3; 1340 u8 bt_info_hb0; 1341 u8 bt_info_hb1; 1342 u8 bt_info_hb2; 1343 u8 bt_info_hb3; 1344 u8 bt_ble_scan_type; 1345 u8 bt_hid_pair_num; 1346 u8 bt_hid_slot; 1347 u8 bt_a2dp_bitpool; 1348 u8 bt_iqk_state; 1349 1350 u8 wl_noisy_level; 1351 u8 wl_fw_dbg_info[10]; 1352 u8 wl_fw_dbg_info_pre[10]; 1353 u8 wl_coex_mode; 1354 u8 ampdu_max_time; 1355 u8 wl_tput_dir; 1356 1357 u16 score_board; 1358 u16 retry_limit; 1359 1360 /* counters to record bt states */ 1361 u32 cnt_bt[COEX_CNT_BT_MAX]; 1362 1363 /* counters to record wifi states */ 1364 u32 cnt_wl[COEX_CNT_WL_MAX]; 1365 1366 u32 darfrc; 1367 u32 darfrch; 1368}; 1369 1370struct rtw_coex { 1371 /* protects coex info request section */ 1372 struct mutex mutex; 1373 struct sk_buff_head queue; 1374 wait_queue_head_t wait; 1375 1376 bool under_5g; 1377 bool stop_dm; 1378 bool freeze; 1379 bool freerun; 1380 bool wl_rf_off; 1381 1382 struct rtw_coex_stat stat; 1383 struct rtw_coex_dm dm; 1384 struct rtw_coex_rfe rfe; 1385 1386 struct delayed_work bt_relink_work; 1387 struct delayed_work bt_reenable_work; 1388 struct delayed_work defreeze_work; 1389 struct delayed_work wl_remain_work; 1390 struct delayed_work bt_remain_work; 1391}; 1392 1393#define DPK_RF_REG_NUM 7 1394#define DPK_RF_PATH_NUM 2 1395#define DPK_BB_REG_NUM 18 1396#define DPK_CHANNEL_WIDTH_80 1 1397 1398DECLARE_EWMA(thermal, 10, 4); 1399 1400struct rtw_dpk_info { 1401 bool is_dpk_pwr_on; 1402 bool is_reload; 1403 1404 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM); 1405 1406 u8 thermal_dpk[DPK_RF_PATH_NUM]; 1407 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM]; 1408 1409 u32 gnt_control; 1410 u32 gnt_value; 1411 1412 u8 result[RTW_RF_PATH_MAX]; 1413 u8 dpk_txagc[RTW_RF_PATH_MAX]; 1414 u32 coef[RTW_RF_PATH_MAX][20]; 1415 u16 dpk_gs[RTW_RF_PATH_MAX]; 1416 u8 thermal_dpk_delta[RTW_RF_PATH_MAX]; 1417 u8 pre_pwsf[RTW_RF_PATH_MAX]; 1418 1419 u8 dpk_band; 1420 u8 dpk_ch; 1421 u8 dpk_bw; 1422}; 1423 1424struct rtw_phy_cck_pd_reg { 1425 u32 reg_pd; 1426 u32 mask_pd; 1427 u32 reg_cs; 1428 u32 mask_cs; 1429}; 1430 1431#define DACK_MSBK_BACKUP_NUM 0xf 1432#define DACK_DCK_BACKUP_NUM 0x2 1433 1434struct rtw_swing_table { 1435 const u8 *p[RTW_RF_PATH_MAX]; 1436 const u8 *n[RTW_RF_PATH_MAX]; 1437}; 1438 1439struct rtw_pkt_count { 1440 u16 num_bcn_pkt; 1441 u16 num_qry_pkt[DESC_RATE_MAX]; 1442}; 1443 1444DECLARE_EWMA(evm, 10, 4); 1445DECLARE_EWMA(snr, 10, 4); 1446 1447struct rtw_iqk_info { 1448 bool done; 1449 struct { 1450 u32 s1_x; 1451 u32 s1_y; 1452 u32 s0_x; 1453 u32 s0_y; 1454 } result; 1455}; 1456 1457struct rtw_dm_info { 1458 u32 cck_fa_cnt; 1459 u32 ofdm_fa_cnt; 1460 u32 total_fa_cnt; 1461 u32 cck_cca_cnt; 1462 u32 ofdm_cca_cnt; 1463 u32 total_cca_cnt; 1464 1465 u32 cck_ok_cnt; 1466 u32 cck_err_cnt; 1467 u32 ofdm_ok_cnt; 1468 u32 ofdm_err_cnt; 1469 u32 ht_ok_cnt; 1470 u32 ht_err_cnt; 1471 u32 vht_ok_cnt; 1472 u32 vht_err_cnt; 1473 1474 u8 min_rssi; 1475 u8 pre_min_rssi; 1476 u16 fa_history[4]; 1477 u8 igi_history[4]; 1478 u8 igi_bitmap; 1479 bool damping; 1480 u8 damping_cnt; 1481 u8 damping_rssi; 1482 1483 u8 cck_gi_u_bnd; 1484 u8 cck_gi_l_bnd; 1485 1486 u8 tx_rate; 1487 u8 thermal_avg[RTW_RF_PATH_MAX]; 1488 u8 thermal_meter_k; 1489 u8 thermal_meter_lck; 1490 s8 delta_power_index[RTW_RF_PATH_MAX]; 1491 s8 delta_power_index_last[RTW_RF_PATH_MAX]; 1492 u8 default_ofdm_index; 1493 bool pwr_trk_triggered; 1494 bool pwr_trk_init_trigger; 1495 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX]; 1496 s8 txagc_remnant_cck; 1497 s8 txagc_remnant_ofdm; 1498 1499 /* backup dack results for each path and I/Q */ 1500 u32 dack_adck[RTW_RF_PATH_MAX]; 1501 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM]; 1502 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM]; 1503 1504 struct rtw_dpk_info dpk_info; 1505 1506 /* [bandwidth 0:20M/1:40M][number of path] */ 1507 u8 cck_pd_lv[2][RTW_RF_PATH_MAX]; 1508 u32 cck_fa_avg; 1509 u8 cck_pd_default; 1510 1511 /* save the last rx phy status for debug */ 1512 s8 rx_snr[RTW_RF_PATH_MAX]; 1513 u8 rx_evm_dbm[RTW_RF_PATH_MAX]; 1514 s16 cfo_tail[RTW_RF_PATH_MAX]; 1515 u8 rssi[RTW_RF_PATH_MAX]; 1516 u8 curr_rx_rate; 1517 struct rtw_pkt_count cur_pkt_count; 1518 struct rtw_pkt_count last_pkt_count; 1519 struct ewma_evm ewma_evm[RTW_EVM_NUM]; 1520 struct ewma_snr ewma_snr[RTW_SNR_NUM]; 1521 1522 struct rtw_iqk_info iqk; 1523}; 1524 1525struct rtw_efuse { 1526 u32 size; 1527 u32 physical_size; 1528 u32 logical_size; 1529 u32 protect_size; 1530 1531 u8 addr[ETH_ALEN]; 1532 u8 channel_plan; 1533 u8 country_code[2]; 1534 u8 rf_board_option; 1535 u8 rfe_option; 1536 u8 power_track_type; 1537 u8 thermal_meter[RTW_RF_PATH_MAX]; 1538 u8 thermal_meter_k; 1539 u8 crystal_cap; 1540 u8 ant_div_cfg; 1541 u8 ant_div_type; 1542 u8 regd; 1543 u8 afe; 1544 1545 u8 lna_type_2g; 1546 u8 lna_type_5g; 1547 u8 glna_type; 1548 u8 alna_type; 1549 bool ext_lna_2g; 1550 bool ext_lna_5g; 1551 u8 pa_type_2g; 1552 u8 pa_type_5g; 1553 u8 gpa_type; 1554 u8 apa_type; 1555 bool ext_pa_2g; 1556 bool ext_pa_5g; 1557 u8 tx_bb_swing_setting_2g; 1558 u8 tx_bb_swing_setting_5g; 1559 1560 bool btcoex; 1561 /* bt share antenna with wifi */ 1562 bool share_ant; 1563 u8 bt_setting; 1564 1565 struct { 1566 u8 hci; 1567 u8 bw; 1568 u8 ptcl; 1569 u8 nss; 1570 u8 ant_num; 1571 } hw_cap; 1572 1573 struct rtw_txpwr_idx txpwr_idx_table[4]; 1574}; 1575 1576struct rtw_phy_cond { 1577#ifdef __LITTLE_ENDIAN 1578 u32 rfe:8; 1579 u32 intf:4; 1580 u32 pkg:4; 1581 u32 plat:4; 1582 u32 intf_rsvd:4; 1583 u32 cut:4; 1584 u32 branch:2; 1585 u32 neg:1; 1586 u32 pos:1; 1587#else 1588 u32 pos:1; 1589 u32 neg:1; 1590 u32 branch:2; 1591 u32 cut:4; 1592 u32 intf_rsvd:4; 1593 u32 plat:4; 1594 u32 pkg:4; 1595 u32 intf:4; 1596 u32 rfe:8; 1597#endif 1598 /* for intf:4 */ 1599 #define INTF_PCIE BIT(0) 1600 #define INTF_USB BIT(1) 1601 #define INTF_SDIO BIT(2) 1602 /* for branch:2 */ 1603 #define BRANCH_IF 0 1604 #define BRANCH_ELIF 1 1605 #define BRANCH_ELSE 2 1606 #define BRANCH_ENDIF 3 1607}; 1608 1609struct rtw_fifo_conf { 1610 /* tx fifo information */ 1611 u16 rsvd_boundary; 1612 u16 rsvd_pg_num; 1613 u16 rsvd_drv_pg_num; 1614 u16 txff_pg_num; 1615 u16 acq_pg_num; 1616 u16 rsvd_drv_addr; 1617 u16 rsvd_h2c_info_addr; 1618 u16 rsvd_h2c_sta_info_addr; 1619 u16 rsvd_h2cq_addr; 1620 u16 rsvd_cpu_instr_addr; 1621 u16 rsvd_fw_txbuf_addr; 1622 u16 rsvd_csibuf_addr; 1623 const struct rtw_rqpn *rqpn; 1624}; 1625 1626#define FW_CD_TYPE 0xffff 1627#define FW_CD_LEN 4 1628#define FW_CD_VAL 0xaabbccdd 1629struct rtw_fw_state { 1630 const struct firmware *firmware; 1631 struct rtw_dev *rtwdev; 1632 struct completion completion; 1633 u16 version; 1634 u8 sub_version; 1635 u8 sub_index; 1636 u16 h2c_version; 1637 u8 prev_dump_seq; 1638}; 1639 1640struct rtw_hal { 1641 u32 rcr; 1642 1643 u32 chip_version; 1644 u8 cut_version; 1645 u8 mp_chip; 1646 u8 oem_id; 1647 struct rtw_phy_cond phy_cond; 1648 1649 u8 ps_mode; 1650 u8 current_channel; 1651 u8 current_band_width; 1652 u8 current_band_type; 1653 1654 /* center channel for different available bandwidth, 1655 * val of (bw > current_band_width) is invalid 1656 */ 1657 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 1658 1659 u8 sec_ch_offset; 1660 u8 rf_type; 1661 u8 rf_path_num; 1662 u8 rf_phy_num; 1663 u32 antenna_tx; 1664 u32 antenna_rx; 1665 u8 bfee_sts_cap; 1666 1667 /* protect tx power section */ 1668 struct mutex tx_power_mutex; 1669 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX] 1670 [DESC_RATE_MAX]; 1671 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX] 1672 [DESC_RATE_MAX]; 1673 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX] 1674 [RTW_RATE_SECTION_MAX]; 1675 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX] 1676 [RTW_RATE_SECTION_MAX]; 1677 s8 tx_pwr_limit_2g[RTW_REGD_MAX] 1678 [RTW_CHANNEL_WIDTH_MAX] 1679 [RTW_RATE_SECTION_MAX] 1680 [RTW_MAX_CHANNEL_NUM_2G]; 1681 s8 tx_pwr_limit_5g[RTW_REGD_MAX] 1682 [RTW_CHANNEL_WIDTH_MAX] 1683 [RTW_RATE_SECTION_MAX] 1684 [RTW_MAX_CHANNEL_NUM_5G]; 1685 s8 tx_pwr_tbl[RTW_RF_PATH_MAX] 1686 [DESC_RATE_MAX]; 1687}; 1688 1689struct rtw_dev { 1690 struct ieee80211_hw *hw; 1691 struct device *dev; 1692 1693 struct rtw_hci hci; 1694 1695 struct rtw_chip_info *chip; 1696 struct rtw_hal hal; 1697 struct rtw_fifo_conf fifo; 1698 struct rtw_fw_state fw; 1699 struct rtw_efuse efuse; 1700 struct rtw_sec_desc sec; 1701 struct rtw_traffic_stats stats; 1702 struct rtw_regulatory regd; 1703 struct rtw_bf_info bf_info; 1704 1705 struct rtw_dm_info dm_info; 1706 struct rtw_coex coex; 1707 1708 /* ensures exclusive access from mac80211 callbacks */ 1709 struct mutex mutex; 1710 1711 /* read/write rf register */ 1712 spinlock_t rf_lock; 1713 1714 /* watch dog every 2 sec */ 1715 struct delayed_work watch_dog_work; 1716 u32 watch_dog_cnt; 1717 1718 struct list_head rsvd_page_list; 1719 1720 /* c2h cmd queue & handler work */ 1721 struct sk_buff_head c2h_queue; 1722 struct work_struct c2h_work; 1723 struct work_struct fw_recovery_work; 1724 1725 /* used to protect txqs list */ 1726 spinlock_t txq_lock; 1727 struct list_head txqs; 1728 struct tasklet_struct tx_tasklet; 1729 struct work_struct ba_work; 1730 1731 struct rtw_tx_report tx_report; 1732 1733 struct { 1734 /* incicate the mail box to use with fw */ 1735 u8 last_box_num; 1736 /* protect to send h2c to fw */ 1737 spinlock_t lock; 1738 u32 seq; 1739 } h2c; 1740 1741 /* lps power state & handler work */ 1742 struct rtw_lps_conf lps_conf; 1743 bool ps_enabled; 1744 1745 struct dentry *debugfs; 1746 1747 u8 sta_cnt; 1748 u32 rts_threshold; 1749 1750 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM); 1751 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS); 1752 1753 u8 mp_mode; 1754 1755 struct rtw_fw_state wow_fw; 1756 struct rtw_wow_param wow; 1757 1758 bool need_rfk; 1759 1760 /* hci related data, must be last */ 1761 u8 priv[] __aligned(sizeof(void *)); 1762}; 1763 1764#include "hci.h" 1765 1766static inline bool rtw_is_assoc(struct rtw_dev *rtwdev) 1767{ 1768 return !!rtwdev->sta_cnt; 1769} 1770 1771static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq) 1772{ 1773 void *p = rtwtxq; 1774 1775 return container_of(p, struct ieee80211_txq, drv_priv); 1776} 1777 1778static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif) 1779{ 1780 void *p = rtwvif; 1781 1782 return container_of(p, struct ieee80211_vif, drv_priv); 1783} 1784 1785static inline bool rtw_ssid_equal(struct cfg80211_ssid *a, 1786 struct cfg80211_ssid *b) 1787{ 1788 if (!a || !b || a->ssid_len != b->ssid_len) 1789 return false; 1790 1791 if (memcmp(a->ssid, b->ssid, a->ssid_len)) 1792 return false; 1793 1794 return true; 1795} 1796 1797static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev) 1798{ 1799 if (rtwdev->chip->ops->efuse_grant) 1800 rtwdev->chip->ops->efuse_grant(rtwdev, true); 1801} 1802 1803static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev) 1804{ 1805 if (rtwdev->chip->ops->efuse_grant) 1806 rtwdev->chip->ops->efuse_grant(rtwdev, false); 1807} 1808 1809static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev) 1810{ 1811 return rtwdev->chip->wlan_cpu == RTW_WCPU_11N; 1812} 1813 1814static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev) 1815{ 1816 return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC; 1817} 1818 1819static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev) 1820{ 1821 return rtwdev->chip->rx_ldpc; 1822} 1823 1824static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id) 1825{ 1826 clear_bit(mac_id, rtwdev->mac_id_map); 1827} 1828 1829void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 1830 struct rtw_channel_params *ch_param); 1831bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target); 1832bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val); 1833bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value); 1834void rtw_restore_reg(struct rtw_dev *rtwdev, 1835 struct rtw_backup_info *bckp, u32 num); 1836void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss); 1837void rtw_set_channel(struct rtw_dev *rtwdev); 1838void rtw_chip_prepare_tx(struct rtw_dev *rtwdev); 1839void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 1840 u32 config); 1841void rtw_tx_report_purge_timer(struct timer_list *t); 1842void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 1843int rtw_core_start(struct rtw_dev *rtwdev); 1844void rtw_core_stop(struct rtw_dev *rtwdev); 1845int rtw_chip_info_setup(struct rtw_dev *rtwdev); 1846int rtw_core_init(struct rtw_dev *rtwdev); 1847void rtw_core_deinit(struct rtw_dev *rtwdev); 1848int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 1849void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 1850u16 rtw_desc_to_bitrate(u8 desc_rate); 1851void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 1852 struct ieee80211_bss_conf *conf); 1853int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 1854 struct ieee80211_vif *vif); 1855void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 1856 bool fw_exist); 1857void rtw_fw_recovery(struct rtw_dev *rtwdev); 1858 1859#endif 1860