1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2/* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5#include "main.h" 6#include "mac.h" 7#include "reg.h" 8#include "fw.h" 9#include "debug.h" 10 11void rtw_set_channel_mac(struct rtw_dev *rtwdev, u8 channel, u8 bw, 12 u8 primary_ch_idx) 13{ 14 u8 txsc40 = 0, txsc20 = 0; 15 u32 value32; 16 u8 value8; 17 18 txsc20 = primary_ch_idx; 19 if (bw == RTW_CHANNEL_WIDTH_80) { 20 if (txsc20 == RTW_SC_20_UPPER || txsc20 == RTW_SC_20_UPMOST) 21 txsc40 = RTW_SC_40_UPPER; 22 else 23 txsc40 = RTW_SC_40_LOWER; 24 } 25 rtw_write8(rtwdev, REG_DATA_SC, 26 BIT_TXSC_20M(txsc20) | BIT_TXSC_40M(txsc40)); 27 28 value32 = rtw_read32(rtwdev, REG_WMAC_TRXPTCL_CTL); 29 value32 &= ~BIT_RFMOD; 30 switch (bw) { 31 case RTW_CHANNEL_WIDTH_80: 32 value32 |= BIT_RFMOD_80M; 33 break; 34 case RTW_CHANNEL_WIDTH_40: 35 value32 |= BIT_RFMOD_40M; 36 break; 37 case RTW_CHANNEL_WIDTH_20: 38 default: 39 break; 40 } 41 rtw_write32(rtwdev, REG_WMAC_TRXPTCL_CTL, value32); 42 43 if (rtw_chip_wcpu_11n(rtwdev)) 44 return; 45 46 value32 = rtw_read32(rtwdev, REG_AFE_CTRL1) & ~(BIT_MAC_CLK_SEL); 47 value32 |= (MAC_CLK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL); 48 rtw_write32(rtwdev, REG_AFE_CTRL1, value32); 49 50 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED); 51 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED); 52 53 value8 = rtw_read8(rtwdev, REG_CCK_CHECK); 54 value8 = value8 & ~BIT_CHECK_CCK_EN; 55 if (IS_CH_5G_BAND(channel)) 56 value8 |= BIT_CHECK_CCK_EN; 57 rtw_write8(rtwdev, REG_CCK_CHECK, value8); 58} 59EXPORT_SYMBOL(rtw_set_channel_mac); 60 61static int rtw_mac_pre_system_cfg(struct rtw_dev *rtwdev) 62{ 63 u32 value32; 64 u8 value8; 65 66 rtw_write8(rtwdev, REG_RSV_CTRL, 0); 67 68 if (rtw_chip_wcpu_11n(rtwdev)) { 69 if (rtw_read32(rtwdev, REG_SYS_CFG1) & BIT_LDO) 70 rtw_write8(rtwdev, REG_LDO_SWR_CTRL, LDO_SEL); 71 else 72 rtw_write8(rtwdev, REG_LDO_SWR_CTRL, SPS_SEL); 73 return 0; 74 } 75 76 switch (rtw_hci_type(rtwdev)) { 77 case RTW_HCI_TYPE_PCIE: 78 rtw_write32_set(rtwdev, REG_HCI_OPT_CTRL, BIT_BT_DIG_CLK_EN); 79 break; 80 case RTW_HCI_TYPE_USB: 81 break; 82 default: 83 return -EINVAL; 84 } 85 86 /* config PIN Mux */ 87 value32 = rtw_read32(rtwdev, REG_PAD_CTRL1); 88 value32 |= BIT_PAPE_WLBT_SEL | BIT_LNAON_WLBT_SEL; 89 rtw_write32(rtwdev, REG_PAD_CTRL1, value32); 90 91 value32 = rtw_read32(rtwdev, REG_LED_CFG); 92 value32 &= ~(BIT_PAPE_SEL_EN | BIT_LNAON_SEL_EN); 93 rtw_write32(rtwdev, REG_LED_CFG, value32); 94 95 value32 = rtw_read32(rtwdev, REG_GPIO_MUXCFG); 96 value32 |= BIT_WLRFE_4_5_EN; 97 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value32); 98 99 /* disable BB/RF */ 100 value8 = rtw_read8(rtwdev, REG_SYS_FUNC_EN); 101 value8 &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST); 102 rtw_write8(rtwdev, REG_SYS_FUNC_EN, value8); 103 104 value8 = rtw_read8(rtwdev, REG_RF_CTRL); 105 value8 &= ~(BIT_RF_SDM_RSTB | BIT_RF_RSTB | BIT_RF_EN); 106 rtw_write8(rtwdev, REG_RF_CTRL, value8); 107 108 value32 = rtw_read32(rtwdev, REG_WLRF1); 109 value32 &= ~BIT_WLRF1_BBRF_EN; 110 rtw_write32(rtwdev, REG_WLRF1, value32); 111 112 return 0; 113} 114 115static bool do_pwr_poll_cmd(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target) 116{ 117 u32 val; 118 119 target &= mask; 120 121 return read_poll_timeout_atomic(rtw_read8, val, (val & mask) == target, 122 50, 50 * RTW_PWR_POLLING_CNT, false, 123 rtwdev, addr) == 0; 124} 125 126static int rtw_pwr_cmd_polling(struct rtw_dev *rtwdev, 127 const struct rtw_pwr_seq_cmd *cmd) 128{ 129 u8 value; 130 u32 offset; 131 132 if (cmd->base == RTW_PWR_ADDR_SDIO) 133 offset = cmd->offset | SDIO_LOCAL_OFFSET; 134 else 135 offset = cmd->offset; 136 137 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value)) 138 return 0; 139 140 if (rtw_hci_type(rtwdev) != RTW_HCI_TYPE_PCIE) 141 goto err; 142 143 /* if PCIE, toggle BIT_PFM_WOWL and try again */ 144 value = rtw_read8(rtwdev, REG_SYS_PW_CTRL); 145 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D) 146 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL); 147 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL); 148 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL); 149 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D) 150 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL); 151 152 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value)) 153 return 0; 154 155err: 156 rtw_err(rtwdev, "failed to poll offset=0x%x mask=0x%x value=0x%x\n", 157 offset, cmd->mask, cmd->value); 158 return -EBUSY; 159} 160 161static int rtw_sub_pwr_seq_parser(struct rtw_dev *rtwdev, u8 intf_mask, 162 u8 cut_mask, 163 const struct rtw_pwr_seq_cmd *cmd) 164{ 165 const struct rtw_pwr_seq_cmd *cur_cmd; 166 u32 offset; 167 u8 value; 168 169 for (cur_cmd = cmd; cur_cmd->cmd != RTW_PWR_CMD_END; cur_cmd++) { 170 if (!(cur_cmd->intf_mask & intf_mask) || 171 !(cur_cmd->cut_mask & cut_mask)) 172 continue; 173 174 switch (cur_cmd->cmd) { 175 case RTW_PWR_CMD_WRITE: 176 offset = cur_cmd->offset; 177 178 if (cur_cmd->base == RTW_PWR_ADDR_SDIO) 179 offset |= SDIO_LOCAL_OFFSET; 180 181 value = rtw_read8(rtwdev, offset); 182 value &= ~cur_cmd->mask; 183 value |= (cur_cmd->value & cur_cmd->mask); 184 rtw_write8(rtwdev, offset, value); 185 break; 186 case RTW_PWR_CMD_POLLING: 187 if (rtw_pwr_cmd_polling(rtwdev, cur_cmd)) 188 return -EBUSY; 189 break; 190 case RTW_PWR_CMD_DELAY: 191 if (cur_cmd->value == RTW_PWR_DELAY_US) 192 udelay(cur_cmd->offset); 193 else 194 mdelay(cur_cmd->offset); 195 break; 196 case RTW_PWR_CMD_READ: 197 break; 198 default: 199 return -EINVAL; 200 } 201 } 202 203 return 0; 204} 205 206static int rtw_pwr_seq_parser(struct rtw_dev *rtwdev, 207 const struct rtw_pwr_seq_cmd **cmd_seq) 208{ 209 u8 cut_mask; 210 u8 intf_mask; 211 u8 cut; 212 u32 idx = 0; 213 const struct rtw_pwr_seq_cmd *cmd; 214 int ret; 215 216 cut = rtwdev->hal.cut_version; 217 cut_mask = cut_version_to_mask(cut); 218 switch (rtw_hci_type(rtwdev)) { 219 case RTW_HCI_TYPE_PCIE: 220 intf_mask = BIT(2); 221 break; 222 case RTW_HCI_TYPE_USB: 223 intf_mask = BIT(1); 224 break; 225 default: 226 return -EINVAL; 227 } 228 229 do { 230 cmd = cmd_seq[idx]; 231 if (!cmd) 232 break; 233 234 ret = rtw_sub_pwr_seq_parser(rtwdev, intf_mask, cut_mask, cmd); 235 if (ret) 236 return ret; 237 238 idx++; 239 } while (1); 240 241 return 0; 242} 243 244static int rtw_mac_power_switch(struct rtw_dev *rtwdev, bool pwr_on) 245{ 246 struct rtw_chip_info *chip = rtwdev->chip; 247 const struct rtw_pwr_seq_cmd **pwr_seq; 248 u8 rpwm; 249 bool cur_pwr; 250 int ret; 251 252 if (rtw_chip_wcpu_11ac(rtwdev)) { 253 rpwm = rtw_read8(rtwdev, rtwdev->hci.rpwm_addr); 254 255 /* Check FW still exist or not */ 256 if (rtw_read16(rtwdev, REG_MCUFW_CTRL) == 0xC078) { 257 rpwm = (rpwm ^ BIT_RPWM_TOGGLE) & BIT_RPWM_TOGGLE; 258 rtw_write8(rtwdev, rtwdev->hci.rpwm_addr, rpwm); 259 } 260 } 261 262 if (rtw_read8(rtwdev, REG_CR) == 0xea) 263 cur_pwr = false; 264 else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB && 265 (rtw_read8(rtwdev, REG_SYS_STATUS1 + 1) & BIT(0))) 266 cur_pwr = false; 267 else 268 cur_pwr = true; 269 270 if (pwr_on == cur_pwr) 271 return -EALREADY; 272 273 pwr_seq = pwr_on ? chip->pwr_on_seq : chip->pwr_off_seq; 274 ret = rtw_pwr_seq_parser(rtwdev, pwr_seq); 275 if (ret) 276 return ret; 277 278 return 0; 279} 280 281static int __rtw_mac_init_system_cfg(struct rtw_dev *rtwdev) 282{ 283 u8 sys_func_en = rtwdev->chip->sys_func_en; 284 u8 value8; 285 u32 value, tmp; 286 287 value = rtw_read32(rtwdev, REG_CPU_DMEM_CON); 288 value |= BIT_WL_PLATFORM_RST | BIT_DDMA_EN; 289 rtw_write32(rtwdev, REG_CPU_DMEM_CON, value); 290 291 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, sys_func_en); 292 value8 = (rtw_read8(rtwdev, REG_CR_EXT + 3) & 0xF0) | 0x0C; 293 rtw_write8(rtwdev, REG_CR_EXT + 3, value8); 294 295 /* disable boot-from-flash for driver's DL FW */ 296 tmp = rtw_read32(rtwdev, REG_MCUFW_CTRL); 297 if (tmp & BIT_BOOT_FSPI_EN) { 298 rtw_write32(rtwdev, REG_MCUFW_CTRL, tmp & (~BIT_BOOT_FSPI_EN)); 299 value = rtw_read32(rtwdev, REG_GPIO_MUXCFG) & (~BIT_FSPI_EN); 300 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value); 301 } 302 303 return 0; 304} 305 306static int __rtw_mac_init_system_cfg_legacy(struct rtw_dev *rtwdev) 307{ 308 rtw_write8(rtwdev, REG_CR, 0xff); 309 mdelay(2); 310 rtw_write8(rtwdev, REG_HWSEQ_CTRL, 0x7f); 311 mdelay(2); 312 313 rtw_write8_set(rtwdev, REG_SYS_CLKR, BIT_WAKEPAD_EN); 314 rtw_write16_clr(rtwdev, REG_GPIO_MUXCFG, BIT_EN_SIC); 315 316 rtw_write16(rtwdev, REG_CR, 0x2ff); 317 318 return 0; 319} 320 321static int rtw_mac_init_system_cfg(struct rtw_dev *rtwdev) 322{ 323 if (rtw_chip_wcpu_11n(rtwdev)) 324 return __rtw_mac_init_system_cfg_legacy(rtwdev); 325 326 return __rtw_mac_init_system_cfg(rtwdev); 327} 328 329int rtw_mac_power_on(struct rtw_dev *rtwdev) 330{ 331 int ret = 0; 332 333 ret = rtw_mac_pre_system_cfg(rtwdev); 334 if (ret) 335 goto err; 336 337 ret = rtw_mac_power_switch(rtwdev, true); 338 if (ret == -EALREADY) { 339 rtw_mac_power_switch(rtwdev, false); 340 ret = rtw_mac_power_switch(rtwdev, true); 341 if (ret) 342 goto err; 343 } else if (ret) { 344 goto err; 345 } 346 347 ret = rtw_mac_init_system_cfg(rtwdev); 348 if (ret) 349 goto err; 350 351 return 0; 352 353err: 354 rtw_err(rtwdev, "mac power on failed"); 355 return ret; 356} 357 358void rtw_mac_power_off(struct rtw_dev *rtwdev) 359{ 360 rtw_mac_power_switch(rtwdev, false); 361} 362 363static bool check_firmware_size(const u8 *data, u32 size) 364{ 365 const struct rtw_fw_hdr *fw_hdr = (const struct rtw_fw_hdr *)data; 366 u32 dmem_size; 367 u32 imem_size; 368 u32 emem_size; 369 u32 real_size; 370 371 dmem_size = le32_to_cpu(fw_hdr->dmem_size); 372 imem_size = le32_to_cpu(fw_hdr->imem_size); 373 emem_size = (fw_hdr->mem_usage & BIT(4)) ? 374 le32_to_cpu(fw_hdr->emem_size) : 0; 375 376 dmem_size += FW_HDR_CHKSUM_SIZE; 377 imem_size += FW_HDR_CHKSUM_SIZE; 378 emem_size += emem_size ? FW_HDR_CHKSUM_SIZE : 0; 379 real_size = FW_HDR_SIZE + dmem_size + imem_size + emem_size; 380 if (real_size != size) 381 return false; 382 383 return true; 384} 385 386static void wlan_cpu_enable(struct rtw_dev *rtwdev, bool enable) 387{ 388 if (enable) { 389 /* cpu io interface enable */ 390 rtw_write8_set(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF); 391 392 /* cpu enable */ 393 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN); 394 } else { 395 /* cpu io interface disable */ 396 rtw_write8_clr(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN); 397 398 /* cpu disable */ 399 rtw_write8_clr(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF); 400 } 401} 402 403#define DLFW_RESTORE_REG_NUM 6 404 405static void download_firmware_reg_backup(struct rtw_dev *rtwdev, 406 struct rtw_backup_info *bckp) 407{ 408 u8 tmp; 409 u8 bckp_idx = 0; 410 411 /* set HIQ to hi priority */ 412 bckp[bckp_idx].len = 1; 413 bckp[bckp_idx].reg = REG_TXDMA_PQ_MAP + 1; 414 bckp[bckp_idx].val = rtw_read8(rtwdev, REG_TXDMA_PQ_MAP + 1); 415 bckp_idx++; 416 tmp = RTW_DMA_MAPPING_HIGH << 6; 417 rtw_write8(rtwdev, REG_TXDMA_PQ_MAP + 1, tmp); 418 419 /* DLFW only use HIQ, map HIQ to hi priority */ 420 bckp[bckp_idx].len = 1; 421 bckp[bckp_idx].reg = REG_CR; 422 bckp[bckp_idx].val = rtw_read8(rtwdev, REG_CR); 423 bckp_idx++; 424 bckp[bckp_idx].len = 4; 425 bckp[bckp_idx].reg = REG_H2CQ_CSR; 426 bckp[bckp_idx].val = BIT_H2CQ_FULL; 427 bckp_idx++; 428 tmp = BIT_HCI_TXDMA_EN | BIT_TXDMA_EN; 429 rtw_write8(rtwdev, REG_CR, tmp); 430 rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL); 431 432 /* Config hi priority queue and public priority queue page number */ 433 bckp[bckp_idx].len = 2; 434 bckp[bckp_idx].reg = REG_FIFOPAGE_INFO_1; 435 bckp[bckp_idx].val = rtw_read16(rtwdev, REG_FIFOPAGE_INFO_1); 436 bckp_idx++; 437 bckp[bckp_idx].len = 4; 438 bckp[bckp_idx].reg = REG_RQPN_CTRL_2; 439 bckp[bckp_idx].val = rtw_read32(rtwdev, REG_RQPN_CTRL_2) | BIT_LD_RQPN; 440 bckp_idx++; 441 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, 0x200); 442 rtw_write32(rtwdev, REG_RQPN_CTRL_2, bckp[bckp_idx - 1].val); 443 444 /* Disable beacon related functions */ 445 tmp = rtw_read8(rtwdev, REG_BCN_CTRL); 446 bckp[bckp_idx].len = 1; 447 bckp[bckp_idx].reg = REG_BCN_CTRL; 448 bckp[bckp_idx].val = tmp; 449 bckp_idx++; 450 tmp = (u8)((tmp & (~BIT_EN_BCN_FUNCTION)) | BIT_DIS_TSF_UDT); 451 rtw_write8(rtwdev, REG_BCN_CTRL, tmp); 452 453 WARN(bckp_idx != DLFW_RESTORE_REG_NUM, "wrong backup number\n"); 454} 455 456static void download_firmware_reset_platform(struct rtw_dev *rtwdev) 457{ 458 rtw_write8_clr(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16); 459 rtw_write8_clr(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8); 460 rtw_write8_set(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16); 461 rtw_write8_set(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8); 462} 463 464static void download_firmware_reg_restore(struct rtw_dev *rtwdev, 465 struct rtw_backup_info *bckp, 466 u8 bckp_num) 467{ 468 rtw_restore_reg(rtwdev, bckp, bckp_num); 469} 470 471#define TX_DESC_SIZE 48 472 473static int send_firmware_pkt_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr, 474 const u8 *data, u32 size) 475{ 476 u8 *buf; 477 int ret; 478 479 buf = kmemdup(data, size, GFP_KERNEL); 480 if (!buf) 481 return -ENOMEM; 482 483 ret = rtw_fw_write_data_rsvd_page(rtwdev, pg_addr, buf, size); 484 kfree(buf); 485 return ret; 486} 487 488static int 489send_firmware_pkt(struct rtw_dev *rtwdev, u16 pg_addr, const u8 *data, u32 size) 490{ 491 int ret; 492 493 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB && 494 !((size + TX_DESC_SIZE) & (512 - 1))) 495 size += 1; 496 497 ret = send_firmware_pkt_rsvd_page(rtwdev, pg_addr, data, size); 498 if (ret) 499 rtw_err(rtwdev, "failed to download rsvd page\n"); 500 501 return ret; 502} 503 504static int 505iddma_enable(struct rtw_dev *rtwdev, u32 src, u32 dst, u32 ctrl) 506{ 507 rtw_write32(rtwdev, REG_DDMA_CH0SA, src); 508 rtw_write32(rtwdev, REG_DDMA_CH0DA, dst); 509 rtw_write32(rtwdev, REG_DDMA_CH0CTRL, ctrl); 510 511 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) 512 return -EBUSY; 513 514 return 0; 515} 516 517static int iddma_download_firmware(struct rtw_dev *rtwdev, u32 src, u32 dst, 518 u32 len, u8 first) 519{ 520 u32 ch0_ctrl = BIT_DDMACH0_CHKSUM_EN | BIT_DDMACH0_OWN; 521 522 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) 523 return -EBUSY; 524 525 ch0_ctrl |= len & BIT_MASK_DDMACH0_DLEN; 526 if (!first) 527 ch0_ctrl |= BIT_DDMACH0_CHKSUM_CONT; 528 529 if (iddma_enable(rtwdev, src, dst, ch0_ctrl)) 530 return -EBUSY; 531 532 return 0; 533} 534 535static bool 536check_fw_checksum(struct rtw_dev *rtwdev, u32 addr) 537{ 538 u8 fw_ctrl; 539 540 fw_ctrl = rtw_read8(rtwdev, REG_MCUFW_CTRL); 541 542 if (rtw_read32(rtwdev, REG_DDMA_CH0CTRL) & BIT_DDMACH0_CHKSUM_STS) { 543 if (addr < OCPBASE_DMEM_88XX) { 544 fw_ctrl |= BIT_IMEM_DW_OK; 545 fw_ctrl &= ~BIT_IMEM_CHKSUM_OK; 546 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 547 } else { 548 fw_ctrl |= BIT_DMEM_DW_OK; 549 fw_ctrl &= ~BIT_DMEM_CHKSUM_OK; 550 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 551 } 552 553 rtw_err(rtwdev, "invalid fw checksum\n"); 554 555 return false; 556 } 557 558 if (addr < OCPBASE_DMEM_88XX) { 559 fw_ctrl |= (BIT_IMEM_DW_OK | BIT_IMEM_CHKSUM_OK); 560 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 561 } else { 562 fw_ctrl |= (BIT_DMEM_DW_OK | BIT_DMEM_CHKSUM_OK); 563 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 564 } 565 566 return true; 567} 568 569static int 570download_firmware_to_mem(struct rtw_dev *rtwdev, const u8 *data, 571 u32 src, u32 dst, u32 size) 572{ 573 struct rtw_chip_info *chip = rtwdev->chip; 574 u32 desc_size = chip->tx_pkt_desc_sz; 575 u8 first_part; 576 u32 mem_offset; 577 u32 residue_size; 578 u32 pkt_size; 579 u32 max_size = 0x1000; 580 u32 val; 581 int ret; 582 583 mem_offset = 0; 584 first_part = 1; 585 residue_size = size; 586 587 val = rtw_read32(rtwdev, REG_DDMA_CH0CTRL); 588 val |= BIT_DDMACH0_RESET_CHKSUM_STS; 589 rtw_write32(rtwdev, REG_DDMA_CH0CTRL, val); 590 591 while (residue_size) { 592 if (residue_size >= max_size) 593 pkt_size = max_size; 594 else 595 pkt_size = residue_size; 596 597 ret = send_firmware_pkt(rtwdev, (u16)(src >> 7), 598 data + mem_offset, pkt_size); 599 if (ret) 600 return ret; 601 602 ret = iddma_download_firmware(rtwdev, OCPBASE_TXBUF_88XX + 603 src + desc_size, 604 dst + mem_offset, pkt_size, 605 first_part); 606 if (ret) 607 return ret; 608 609 first_part = 0; 610 mem_offset += pkt_size; 611 residue_size -= pkt_size; 612 } 613 614 if (!check_fw_checksum(rtwdev, dst)) 615 return -EINVAL; 616 617 return 0; 618} 619 620static int 621start_download_firmware(struct rtw_dev *rtwdev, const u8 *data, u32 size) 622{ 623 const struct rtw_fw_hdr *fw_hdr = (const struct rtw_fw_hdr *)data; 624 const u8 *cur_fw; 625 u16 val; 626 u32 imem_size; 627 u32 dmem_size; 628 u32 emem_size; 629 u32 addr; 630 int ret; 631 632 dmem_size = le32_to_cpu(fw_hdr->dmem_size); 633 imem_size = le32_to_cpu(fw_hdr->imem_size); 634 emem_size = (fw_hdr->mem_usage & BIT(4)) ? 635 le32_to_cpu(fw_hdr->emem_size) : 0; 636 dmem_size += FW_HDR_CHKSUM_SIZE; 637 imem_size += FW_HDR_CHKSUM_SIZE; 638 emem_size += emem_size ? FW_HDR_CHKSUM_SIZE : 0; 639 640 val = (u16)(rtw_read16(rtwdev, REG_MCUFW_CTRL) & 0x3800); 641 val |= BIT_MCUFWDL_EN; 642 rtw_write16(rtwdev, REG_MCUFW_CTRL, val); 643 644 cur_fw = data + FW_HDR_SIZE; 645 addr = le32_to_cpu(fw_hdr->dmem_addr); 646 addr &= ~BIT(31); 647 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, dmem_size); 648 if (ret) 649 return ret; 650 651 cur_fw = data + FW_HDR_SIZE + dmem_size; 652 addr = le32_to_cpu(fw_hdr->imem_addr); 653 addr &= ~BIT(31); 654 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, imem_size); 655 if (ret) 656 return ret; 657 658 if (emem_size) { 659 cur_fw = data + FW_HDR_SIZE + dmem_size + imem_size; 660 addr = le32_to_cpu(fw_hdr->emem_addr); 661 addr &= ~BIT(31); 662 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, 663 emem_size); 664 if (ret) 665 return ret; 666 } 667 668 return 0; 669} 670 671static int download_firmware_validate(struct rtw_dev *rtwdev) 672{ 673 u32 fw_key; 674 675 if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, FW_READY_MASK, FW_READY)) { 676 fw_key = rtw_read32(rtwdev, REG_FW_DBG7) & FW_KEY_MASK; 677 if (fw_key == ILLEGAL_KEY_GROUP) 678 rtw_err(rtwdev, "invalid fw key\n"); 679 return -EINVAL; 680 } 681 682 return 0; 683} 684 685static void download_firmware_end_flow(struct rtw_dev *rtwdev) 686{ 687 u16 fw_ctrl; 688 689 rtw_write32(rtwdev, REG_TXDMA_STATUS, BTI_PAGE_OVF); 690 691 /* Check IMEM & DMEM checksum is OK or not */ 692 fw_ctrl = rtw_read16(rtwdev, REG_MCUFW_CTRL); 693 if ((fw_ctrl & BIT_CHECK_SUM_OK) != BIT_CHECK_SUM_OK) 694 return; 695 696 fw_ctrl = (fw_ctrl | BIT_FW_DW_RDY) & ~BIT_MCUFWDL_EN; 697 rtw_write16(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 698} 699 700static int __rtw_download_firmware(struct rtw_dev *rtwdev, 701 struct rtw_fw_state *fw) 702{ 703 struct rtw_backup_info bckp[DLFW_RESTORE_REG_NUM]; 704 const u8 *data = fw->firmware->data; 705 u32 size = fw->firmware->size; 706 u32 ltecoex_bckp; 707 int ret; 708 709 if (!check_firmware_size(data, size)) 710 return -EINVAL; 711 712 if (!ltecoex_read_reg(rtwdev, 0x38, <ecoex_bckp)) 713 return -EBUSY; 714 715 wlan_cpu_enable(rtwdev, false); 716 717 download_firmware_reg_backup(rtwdev, bckp); 718 download_firmware_reset_platform(rtwdev); 719 720 ret = start_download_firmware(rtwdev, data, size); 721 if (ret) 722 goto dlfw_fail; 723 724 download_firmware_reg_restore(rtwdev, bckp, DLFW_RESTORE_REG_NUM); 725 726 download_firmware_end_flow(rtwdev); 727 728 wlan_cpu_enable(rtwdev, true); 729 730 if (!ltecoex_reg_write(rtwdev, 0x38, ltecoex_bckp)) 731 return -EBUSY; 732 733 ret = download_firmware_validate(rtwdev); 734 if (ret) 735 goto dlfw_fail; 736 737 /* reset desc and index */ 738 rtw_hci_setup(rtwdev); 739 740 rtwdev->h2c.last_box_num = 0; 741 rtwdev->h2c.seq = 0; 742 743 set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 744 745 return 0; 746 747dlfw_fail: 748 /* Disable FWDL_EN */ 749 rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN); 750 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN); 751 752 return ret; 753} 754 755static void en_download_firmware_legacy(struct rtw_dev *rtwdev, bool en) 756{ 757 int try; 758 759 if (en) { 760 wlan_cpu_enable(rtwdev, false); 761 wlan_cpu_enable(rtwdev, true); 762 763 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN); 764 765 for (try = 0; try < 10; try++) { 766 if (rtw_read8(rtwdev, REG_MCUFW_CTRL) & BIT_MCUFWDL_EN) 767 goto fwdl_ready; 768 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN); 769 msleep(20); 770 } 771 rtw_err(rtwdev, "failed to check fw download ready\n"); 772fwdl_ready: 773 rtw_write32_clr(rtwdev, REG_MCUFW_CTRL, BIT_ROM_DLEN); 774 } else { 775 rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN); 776 } 777} 778 779static void 780write_firmware_page(struct rtw_dev *rtwdev, u32 page, const u8 *data, u32 size) 781{ 782 u32 val32; 783 u32 block_nr; 784 u32 remain_size; 785 u32 write_addr = FW_START_ADDR_LEGACY; 786 const __le32 *ptr = (const __le32 *)data; 787 u32 block; 788 __le32 remain_data = 0; 789 790 block_nr = size >> DLFW_BLK_SIZE_SHIFT_LEGACY; 791 remain_size = size & (DLFW_BLK_SIZE_LEGACY - 1); 792 793 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL); 794 val32 &= ~BIT_ROM_PGE; 795 val32 |= (page << BIT_SHIFT_ROM_PGE) & BIT_ROM_PGE; 796 rtw_write32(rtwdev, REG_MCUFW_CTRL, val32); 797 798 for (block = 0; block < block_nr; block++) { 799 rtw_write32(rtwdev, write_addr, le32_to_cpu(*ptr)); 800 801 write_addr += DLFW_BLK_SIZE_LEGACY; 802 ptr++; 803 } 804 805 if (remain_size) { 806 memcpy(&remain_data, ptr, remain_size); 807 rtw_write32(rtwdev, write_addr, le32_to_cpu(remain_data)); 808 } 809} 810 811static int 812download_firmware_legacy(struct rtw_dev *rtwdev, const u8 *data, u32 size) 813{ 814 u32 page; 815 u32 total_page; 816 u32 last_page_size; 817 818 data += sizeof(struct rtw_fw_hdr_legacy); 819 size -= sizeof(struct rtw_fw_hdr_legacy); 820 821 total_page = size >> DLFW_PAGE_SIZE_SHIFT_LEGACY; 822 last_page_size = size & (DLFW_PAGE_SIZE_LEGACY - 1); 823 824 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_FWDL_CHK_RPT); 825 826 for (page = 0; page < total_page; page++) { 827 write_firmware_page(rtwdev, page, data, DLFW_PAGE_SIZE_LEGACY); 828 data += DLFW_PAGE_SIZE_LEGACY; 829 } 830 if (last_page_size) 831 write_firmware_page(rtwdev, page, data, last_page_size); 832 833 if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, BIT_FWDL_CHK_RPT, 1)) { 834 rtw_err(rtwdev, "failed to check download firmware report\n"); 835 return -EINVAL; 836 } 837 838 return 0; 839} 840 841static int download_firmware_validate_legacy(struct rtw_dev *rtwdev) 842{ 843 u32 val32; 844 int try; 845 846 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL); 847 val32 |= BIT_MCUFWDL_RDY; 848 val32 &= ~BIT_WINTINI_RDY; 849 rtw_write32(rtwdev, REG_MCUFW_CTRL, val32); 850 851 wlan_cpu_enable(rtwdev, false); 852 wlan_cpu_enable(rtwdev, true); 853 854 for (try = 0; try < 10; try++) { 855 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL); 856 if ((val32 & FW_READY_LEGACY) == FW_READY_LEGACY) 857 return 0; 858 msleep(20); 859 } 860 861 rtw_err(rtwdev, "failed to validate firmware\n"); 862 return -EINVAL; 863} 864 865static int __rtw_download_firmware_legacy(struct rtw_dev *rtwdev, 866 struct rtw_fw_state *fw) 867{ 868 int ret = 0; 869 870 en_download_firmware_legacy(rtwdev, true); 871 ret = download_firmware_legacy(rtwdev, fw->firmware->data, fw->firmware->size); 872 en_download_firmware_legacy(rtwdev, false); 873 if (ret) 874 goto out; 875 876 ret = download_firmware_validate_legacy(rtwdev); 877 if (ret) 878 goto out; 879 880 /* reset desc and index */ 881 rtw_hci_setup(rtwdev); 882 883 rtwdev->h2c.last_box_num = 0; 884 rtwdev->h2c.seq = 0; 885 886 set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 887 888out: 889 return ret; 890} 891 892int rtw_download_firmware(struct rtw_dev *rtwdev, struct rtw_fw_state *fw) 893{ 894 if (rtw_chip_wcpu_11n(rtwdev)) 895 return __rtw_download_firmware_legacy(rtwdev, fw); 896 897 return __rtw_download_firmware(rtwdev, fw); 898} 899 900static u32 get_priority_queues(struct rtw_dev *rtwdev, u32 queues) 901{ 902 const struct rtw_rqpn *rqpn = rtwdev->fifo.rqpn; 903 u32 prio_queues = 0; 904 905 if (queues & BIT(IEEE80211_AC_VO)) 906 prio_queues |= BIT(rqpn->dma_map_vo); 907 if (queues & BIT(IEEE80211_AC_VI)) 908 prio_queues |= BIT(rqpn->dma_map_vi); 909 if (queues & BIT(IEEE80211_AC_BE)) 910 prio_queues |= BIT(rqpn->dma_map_be); 911 if (queues & BIT(IEEE80211_AC_BK)) 912 prio_queues |= BIT(rqpn->dma_map_bk); 913 914 return prio_queues; 915} 916 917static void __rtw_mac_flush_prio_queue(struct rtw_dev *rtwdev, 918 u32 prio_queue, bool drop) 919{ 920 struct rtw_chip_info *chip = rtwdev->chip; 921 const struct rtw_prioq_addr *addr; 922 bool wsize; 923 u16 avail_page, rsvd_page; 924 int i; 925 926 if (prio_queue >= RTW_DMA_MAPPING_MAX) 927 return; 928 929 addr = &chip->prioq_addrs->prio[prio_queue]; 930 wsize = chip->prioq_addrs->wsize; 931 932 /* check if all of the reserved pages are available for 100 msecs */ 933 for (i = 0; i < 5; i++) { 934 rsvd_page = wsize ? rtw_read16(rtwdev, addr->rsvd) : 935 rtw_read8(rtwdev, addr->rsvd); 936 avail_page = wsize ? rtw_read16(rtwdev, addr->avail) : 937 rtw_read8(rtwdev, addr->avail); 938 if (rsvd_page == avail_page) 939 return; 940 941 msleep(20); 942 } 943 944 /* priority queue is still not empty, throw a warning, 945 * 946 * Note that if we want to flush the tx queue when having a lot of 947 * traffic (ex, 100Mbps up), some of the packets could be dropped. 948 * And it requires like ~2secs to flush the full priority queue. 949 */ 950 if (!drop) 951 rtw_warn(rtwdev, "timed out to flush queue %d\n", prio_queue); 952} 953 954static void rtw_mac_flush_prio_queues(struct rtw_dev *rtwdev, 955 u32 prio_queues, bool drop) 956{ 957 u32 q; 958 959 for (q = 0; q < RTW_DMA_MAPPING_MAX; q++) 960 if (prio_queues & BIT(q)) 961 __rtw_mac_flush_prio_queue(rtwdev, q, drop); 962} 963 964void rtw_mac_flush_queues(struct rtw_dev *rtwdev, u32 queues, bool drop) 965{ 966 u32 prio_queues = 0; 967 968 /* If all of the hardware queues are requested to flush, 969 * or the priority queues are not mapped yet, 970 * flush all of the priority queues 971 */ 972 if (queues == BIT(rtwdev->hw->queues) - 1 || !rtwdev->fifo.rqpn) 973 prio_queues = BIT(RTW_DMA_MAPPING_MAX) - 1; 974 else 975 prio_queues = get_priority_queues(rtwdev, queues); 976 977 rtw_mac_flush_prio_queues(rtwdev, prio_queues, drop); 978} 979 980static int txdma_queue_mapping(struct rtw_dev *rtwdev) 981{ 982 struct rtw_chip_info *chip = rtwdev->chip; 983 const struct rtw_rqpn *rqpn = NULL; 984 u16 txdma_pq_map = 0; 985 986 switch (rtw_hci_type(rtwdev)) { 987 case RTW_HCI_TYPE_PCIE: 988 rqpn = &chip->rqpn_table[1]; 989 break; 990 case RTW_HCI_TYPE_USB: 991 if (rtwdev->hci.bulkout_num == 2) 992 rqpn = &chip->rqpn_table[2]; 993 else if (rtwdev->hci.bulkout_num == 3) 994 rqpn = &chip->rqpn_table[3]; 995 else if (rtwdev->hci.bulkout_num == 4) 996 rqpn = &chip->rqpn_table[4]; 997 else 998 return -EINVAL; 999 break; 1000 default: 1001 return -EINVAL; 1002 } 1003 1004 rtwdev->fifo.rqpn = rqpn; 1005 txdma_pq_map |= BIT_TXDMA_HIQ_MAP(rqpn->dma_map_hi); 1006 txdma_pq_map |= BIT_TXDMA_MGQ_MAP(rqpn->dma_map_mg); 1007 txdma_pq_map |= BIT_TXDMA_BKQ_MAP(rqpn->dma_map_bk); 1008 txdma_pq_map |= BIT_TXDMA_BEQ_MAP(rqpn->dma_map_be); 1009 txdma_pq_map |= BIT_TXDMA_VIQ_MAP(rqpn->dma_map_vi); 1010 txdma_pq_map |= BIT_TXDMA_VOQ_MAP(rqpn->dma_map_vo); 1011 rtw_write16(rtwdev, REG_TXDMA_PQ_MAP, txdma_pq_map); 1012 1013 rtw_write8(rtwdev, REG_CR, 0); 1014 rtw_write8(rtwdev, REG_CR, MAC_TRX_ENABLE); 1015 if (rtw_chip_wcpu_11ac(rtwdev)) 1016 rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL); 1017 1018 return 0; 1019} 1020 1021static int set_trx_fifo_info(struct rtw_dev *rtwdev) 1022{ 1023 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1024 struct rtw_chip_info *chip = rtwdev->chip; 1025 u16 cur_pg_addr; 1026 u8 csi_buf_pg_num = chip->csi_buf_pg_num; 1027 1028 /* config rsvd page num */ 1029 fifo->rsvd_drv_pg_num = 8; 1030 fifo->txff_pg_num = chip->txff_size >> 7; 1031 if (rtw_chip_wcpu_11n(rtwdev)) 1032 fifo->rsvd_pg_num = fifo->rsvd_drv_pg_num; 1033 else 1034 fifo->rsvd_pg_num = fifo->rsvd_drv_pg_num + 1035 RSVD_PG_H2C_EXTRAINFO_NUM + 1036 RSVD_PG_H2C_STATICINFO_NUM + 1037 RSVD_PG_H2CQ_NUM + 1038 RSVD_PG_CPU_INSTRUCTION_NUM + 1039 RSVD_PG_FW_TXBUF_NUM + 1040 csi_buf_pg_num; 1041 1042 if (fifo->rsvd_pg_num > fifo->txff_pg_num) 1043 return -ENOMEM; 1044 1045 fifo->acq_pg_num = fifo->txff_pg_num - fifo->rsvd_pg_num; 1046 fifo->rsvd_boundary = fifo->txff_pg_num - fifo->rsvd_pg_num; 1047 1048 cur_pg_addr = fifo->txff_pg_num; 1049 if (rtw_chip_wcpu_11ac(rtwdev)) { 1050 cur_pg_addr -= csi_buf_pg_num; 1051 fifo->rsvd_csibuf_addr = cur_pg_addr; 1052 cur_pg_addr -= RSVD_PG_FW_TXBUF_NUM; 1053 fifo->rsvd_fw_txbuf_addr = cur_pg_addr; 1054 cur_pg_addr -= RSVD_PG_CPU_INSTRUCTION_NUM; 1055 fifo->rsvd_cpu_instr_addr = cur_pg_addr; 1056 cur_pg_addr -= RSVD_PG_H2CQ_NUM; 1057 fifo->rsvd_h2cq_addr = cur_pg_addr; 1058 cur_pg_addr -= RSVD_PG_H2C_STATICINFO_NUM; 1059 fifo->rsvd_h2c_sta_info_addr = cur_pg_addr; 1060 cur_pg_addr -= RSVD_PG_H2C_EXTRAINFO_NUM; 1061 fifo->rsvd_h2c_info_addr = cur_pg_addr; 1062 } 1063 cur_pg_addr -= fifo->rsvd_drv_pg_num; 1064 fifo->rsvd_drv_addr = cur_pg_addr; 1065 1066 if (fifo->rsvd_boundary != fifo->rsvd_drv_addr) { 1067 rtw_err(rtwdev, "wrong rsvd driver address\n"); 1068 return -EINVAL; 1069 } 1070 1071 return 0; 1072} 1073 1074static int __priority_queue_cfg(struct rtw_dev *rtwdev, 1075 const struct rtw_page_table *pg_tbl, 1076 u16 pubq_num) 1077{ 1078 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1079 struct rtw_chip_info *chip = rtwdev->chip; 1080 1081 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, pg_tbl->hq_num); 1082 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_2, pg_tbl->lq_num); 1083 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_3, pg_tbl->nq_num); 1084 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_4, pg_tbl->exq_num); 1085 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_5, pubq_num); 1086 rtw_write32_set(rtwdev, REG_RQPN_CTRL_2, BIT_LD_RQPN); 1087 1088 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2, fifo->rsvd_boundary); 1089 rtw_write8_set(rtwdev, REG_FWHW_TXQ_CTRL + 2, BIT_EN_WR_FREE_TAIL >> 16); 1090 1091 rtw_write16(rtwdev, REG_BCNQ_BDNY_V1, fifo->rsvd_boundary); 1092 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2 + 2, fifo->rsvd_boundary); 1093 rtw_write16(rtwdev, REG_BCNQ1_BDNY_V1, fifo->rsvd_boundary); 1094 rtw_write32(rtwdev, REG_RXFF_BNDY, chip->rxff_size - C2H_PKT_BUF - 1); 1095 rtw_write8_set(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1); 1096 1097 if (!check_hw_ready(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1, 0)) 1098 return -EBUSY; 1099 1100 rtw_write8(rtwdev, REG_CR + 3, 0); 1101 1102 return 0; 1103} 1104 1105static int __priority_queue_cfg_legacy(struct rtw_dev *rtwdev, 1106 const struct rtw_page_table *pg_tbl, 1107 u16 pubq_num) 1108{ 1109 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1110 struct rtw_chip_info *chip = rtwdev->chip; 1111 u32 val32; 1112 1113 val32 = BIT_RQPN_NE(pg_tbl->nq_num, pg_tbl->exq_num); 1114 rtw_write32(rtwdev, REG_RQPN_NPQ, val32); 1115 val32 = BIT_RQPN_HLP(pg_tbl->hq_num, pg_tbl->lq_num, pubq_num); 1116 rtw_write32(rtwdev, REG_RQPN, val32); 1117 1118 rtw_write8(rtwdev, REG_TRXFF_BNDY, fifo->rsvd_boundary); 1119 rtw_write16(rtwdev, REG_TRXFF_BNDY + 2, chip->rxff_size - REPORT_BUF - 1); 1120 rtw_write8(rtwdev, REG_DWBCN0_CTRL + 1, fifo->rsvd_boundary); 1121 rtw_write8(rtwdev, REG_BCNQ_BDNY, fifo->rsvd_boundary); 1122 rtw_write8(rtwdev, REG_MGQ_BDNY, fifo->rsvd_boundary); 1123 rtw_write8(rtwdev, REG_WMAC_LBK_BF_HD, fifo->rsvd_boundary); 1124 1125 rtw_write32_set(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT); 1126 1127 if (!check_hw_ready(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT, 0)) 1128 return -EBUSY; 1129 1130 return 0; 1131} 1132 1133static int priority_queue_cfg(struct rtw_dev *rtwdev) 1134{ 1135 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1136 struct rtw_chip_info *chip = rtwdev->chip; 1137 const struct rtw_page_table *pg_tbl = NULL; 1138 u16 pubq_num; 1139 int ret; 1140 1141 ret = set_trx_fifo_info(rtwdev); 1142 if (ret) 1143 return ret; 1144 1145 switch (rtw_hci_type(rtwdev)) { 1146 case RTW_HCI_TYPE_PCIE: 1147 pg_tbl = &chip->page_table[1]; 1148 break; 1149 case RTW_HCI_TYPE_USB: 1150 if (rtwdev->hci.bulkout_num == 2) 1151 pg_tbl = &chip->page_table[2]; 1152 else if (rtwdev->hci.bulkout_num == 3) 1153 pg_tbl = &chip->page_table[3]; 1154 else if (rtwdev->hci.bulkout_num == 4) 1155 pg_tbl = &chip->page_table[4]; 1156 else 1157 return -EINVAL; 1158 break; 1159 default: 1160 return -EINVAL; 1161 } 1162 1163 pubq_num = fifo->acq_pg_num - pg_tbl->hq_num - pg_tbl->lq_num - 1164 pg_tbl->nq_num - pg_tbl->exq_num - pg_tbl->gapq_num; 1165 if (rtw_chip_wcpu_11n(rtwdev)) 1166 return __priority_queue_cfg_legacy(rtwdev, pg_tbl, pubq_num); 1167 else 1168 return __priority_queue_cfg(rtwdev, pg_tbl, pubq_num); 1169} 1170 1171static int init_h2c(struct rtw_dev *rtwdev) 1172{ 1173 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1174 u8 value8; 1175 u32 value32; 1176 u32 h2cq_addr; 1177 u32 h2cq_size; 1178 u32 h2cq_free; 1179 u32 wp, rp; 1180 1181 if (rtw_chip_wcpu_11n(rtwdev)) 1182 return 0; 1183 1184 h2cq_addr = fifo->rsvd_h2cq_addr << TX_PAGE_SIZE_SHIFT; 1185 h2cq_size = RSVD_PG_H2CQ_NUM << TX_PAGE_SIZE_SHIFT; 1186 1187 value32 = rtw_read32(rtwdev, REG_H2C_HEAD); 1188 value32 = (value32 & 0xFFFC0000) | h2cq_addr; 1189 rtw_write32(rtwdev, REG_H2C_HEAD, value32); 1190 1191 value32 = rtw_read32(rtwdev, REG_H2C_READ_ADDR); 1192 value32 = (value32 & 0xFFFC0000) | h2cq_addr; 1193 rtw_write32(rtwdev, REG_H2C_READ_ADDR, value32); 1194 1195 value32 = rtw_read32(rtwdev, REG_H2C_TAIL); 1196 value32 &= 0xFFFC0000; 1197 value32 |= (h2cq_addr + h2cq_size); 1198 rtw_write32(rtwdev, REG_H2C_TAIL, value32); 1199 1200 value8 = rtw_read8(rtwdev, REG_H2C_INFO); 1201 value8 = (u8)((value8 & 0xFC) | 0x01); 1202 rtw_write8(rtwdev, REG_H2C_INFO, value8); 1203 1204 value8 = rtw_read8(rtwdev, REG_H2C_INFO); 1205 value8 = (u8)((value8 & 0xFB) | 0x04); 1206 rtw_write8(rtwdev, REG_H2C_INFO, value8); 1207 1208 value8 = rtw_read8(rtwdev, REG_TXDMA_OFFSET_CHK + 1); 1209 value8 = (u8)((value8 & 0x7f) | 0x80); 1210 rtw_write8(rtwdev, REG_TXDMA_OFFSET_CHK + 1, value8); 1211 1212 wp = rtw_read32(rtwdev, REG_H2C_PKT_WRITEADDR) & 0x3FFFF; 1213 rp = rtw_read32(rtwdev, REG_H2C_PKT_READADDR) & 0x3FFFF; 1214 h2cq_free = wp >= rp ? h2cq_size - (wp - rp) : rp - wp; 1215 1216 if (h2cq_size != h2cq_free) { 1217 rtw_err(rtwdev, "H2C queue mismatch\n"); 1218 return -EINVAL; 1219 } 1220 1221 return 0; 1222} 1223 1224static int rtw_init_trx_cfg(struct rtw_dev *rtwdev) 1225{ 1226 int ret; 1227 1228 ret = txdma_queue_mapping(rtwdev); 1229 if (ret) 1230 return ret; 1231 1232 ret = priority_queue_cfg(rtwdev); 1233 if (ret) 1234 return ret; 1235 1236 ret = init_h2c(rtwdev); 1237 if (ret) 1238 return ret; 1239 1240 return 0; 1241} 1242 1243static int rtw_drv_info_cfg(struct rtw_dev *rtwdev) 1244{ 1245 u8 value8; 1246 1247 rtw_write8(rtwdev, REG_RX_DRVINFO_SZ, PHY_STATUS_SIZE); 1248 if (rtw_chip_wcpu_11ac(rtwdev)) { 1249 value8 = rtw_read8(rtwdev, REG_TRXFF_BNDY + 1); 1250 value8 &= 0xF0; 1251 /* For rxdesc len = 0 issue */ 1252 value8 |= 0xF; 1253 rtw_write8(rtwdev, REG_TRXFF_BNDY + 1, value8); 1254 } 1255 rtw_write32_set(rtwdev, REG_RCR, BIT_APP_PHYSTS); 1256 rtw_write32_clr(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, BIT(8) | BIT(9)); 1257 1258 return 0; 1259} 1260 1261int rtw_mac_init(struct rtw_dev *rtwdev) 1262{ 1263 struct rtw_chip_info *chip = rtwdev->chip; 1264 int ret; 1265 1266 ret = rtw_init_trx_cfg(rtwdev); 1267 if (ret) 1268 return ret; 1269 1270 ret = chip->ops->mac_init(rtwdev); 1271 if (ret) 1272 return ret; 1273 1274 ret = rtw_drv_info_cfg(rtwdev); 1275 if (ret) 1276 return ret; 1277 1278 rtw_hci_interface_cfg(rtwdev); 1279 1280 return 0; 1281} 1282