1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/* Copyright(c) 2018-2019  Realtek Corporation
3 */
4
5#ifndef __RTW_COEX_H__
6#define __RTW_COEX_H__
7
8/* BT profile map bit definition */
9#define BPM_HFP		BIT(0)
10#define BPM_HID		BIT(1)
11#define BPM_A2DP		BIT(2)
12#define BPM_PAN		BIT(3)
13
14#define COEX_RESP_ACK_BY_WL_FW	0x1
15#define COEX_REQUEST_TIMEOUT	msecs_to_jiffies(10)
16
17#define COEX_MIN_DELAY		10 /* delay unit in ms */
18#define COEX_RFK_TIMEOUT	600 /* RFK timeout in ms */
19
20#define COEX_RF_OFF	0x0
21#define COEX_RF_ON	0x1
22
23#define COEX_H2C69_WL_LEAKAP	0xc
24#define PARA1_H2C69_DIS_5MS	0x1
25#define PARA1_H2C69_EN_5MS	0x0
26
27#define COEX_H2C69_TDMA_SLOT	0xb
28#define PARA1_H2C69_TDMA_4SLOT	0xc1
29#define PARA1_H2C69_TDMA_2SLOT	0x1
30
31#define TDMA_4SLOT	BIT(8)
32
33#define COEX_RSSI_STEP		4
34#define COEX_RSSI_HIGH(rssi) \
35	({ typeof(rssi) __rssi__ = rssi; \
36	   (__rssi__ == COEX_RSSI_STATE_HIGH || \
37	    __rssi__ == COEX_RSSI_STATE_STAY_HIGH ? true : false); })
38
39#define COEX_RSSI_MEDIUM(rssi) \
40	({ typeof(rssi) __rssi__ = rssi; \
41	   (__rssi__ == COEX_RSSI_STATE_MEDIUM || \
42	    __rssi__ == COEX_RSSI_STATE_STAY_MEDIUM ? true : false); })
43
44#define COEX_RSSI_LOW(rssi) \
45	({ typeof(rssi) __rssi__ = rssi; \
46	   (__rssi__ == COEX_RSSI_STATE_LOW || \
47	    __rssi__ == COEX_RSSI_STATE_STAY_LOW ? true : false); })
48
49#define GET_COEX_RESP_BT_SUPP_VER(payload)				\
50	le64_get_bits(*((__le64 *)(payload)), GENMASK_ULL(39, 32))
51#define GET_COEX_RESP_BT_SUPP_FEAT(payload)				\
52	le64_get_bits(*((__le64 *)(payload)), GENMASK_ULL(39, 24))
53#define GET_COEX_RESP_BT_PATCH_VER(payload)				\
54	le64_get_bits(*((__le64 *)(payload)), GENMASK_ULL(55, 24))
55#define GET_COEX_RESP_BT_REG_VAL(payload)				\
56	le64_get_bits(*((__le64 *)(payload)), GENMASK_ULL(39, 24))
57#define GET_COEX_RESP_BT_SCAN_TYPE(payload)				\
58	le64_get_bits(*((__le64 *)(payload)), GENMASK(31, 24))
59
60enum coex_mp_info_op {
61	BT_MP_INFO_OP_PATCH_VER	= 0x00,
62	BT_MP_INFO_OP_READ_REG	= 0x11,
63	BT_MP_INFO_OP_SUPP_FEAT	= 0x2a,
64	BT_MP_INFO_OP_SUPP_VER	= 0x2b,
65	BT_MP_INFO_OP_SCAN_TYPE	= 0x2d,
66	BT_MP_INFO_OP_LNA_CONSTRAINT	= 0x32,
67};
68
69enum coex_set_ant_phase {
70	COEX_SET_ANT_INIT,
71	COEX_SET_ANT_WONLY,
72	COEX_SET_ANT_WOFF,
73	COEX_SET_ANT_2G,
74	COEX_SET_ANT_5G,
75	COEX_SET_ANT_POWERON,
76	COEX_SET_ANT_2G_WLBT,
77	COEX_SET_ANT_2G_FREERUN,
78
79	COEX_SET_ANT_MAX
80};
81
82enum coex_runreason {
83	COEX_RSN_2GSCANSTART	= 0,
84	COEX_RSN_5GSCANSTART	= 1,
85	COEX_RSN_SCANFINISH	= 2,
86	COEX_RSN_2GSWITCHBAND	= 3,
87	COEX_RSN_5GSWITCHBAND	= 4,
88	COEX_RSN_2GCONSTART	= 5,
89	COEX_RSN_5GCONSTART	= 6,
90	COEX_RSN_2GCONFINISH	= 7,
91	COEX_RSN_5GCONFINISH	= 8,
92	COEX_RSN_2GMEDIA	= 9,
93	COEX_RSN_5GMEDIA	= 10,
94	COEX_RSN_MEDIADISCON	= 11,
95	COEX_RSN_BTINFO		= 12,
96	COEX_RSN_LPS		= 13,
97	COEX_RSN_WLSTATUS	= 14,
98	COEX_RSN_BTSTATUS	= 15,
99
100	COEX_RSN_MAX
101};
102
103enum coex_lte_coex_table_type {
104	COEX_CTT_WL_VS_LTE,
105	COEX_CTT_BT_VS_LTE,
106};
107
108enum coex_gnt_setup_state {
109	COEX_GNT_SET_HW_PTA	= 0x0,
110	COEX_GNT_SET_SW_LOW	= 0x1,
111	COEX_GNT_SET_SW_HIGH	= 0x3,
112};
113
114enum coex_ext_ant_switch_pos_type {
115	COEX_SWITCH_TO_BT,
116	COEX_SWITCH_TO_WLG,
117	COEX_SWITCH_TO_WLA,
118	COEX_SWITCH_TO_NOCARE,
119	COEX_SWITCH_TO_WLG_BT,
120
121	COEX_SWITCH_TO_MAX
122};
123
124enum coex_ext_ant_switch_ctrl_type {
125	COEX_SWITCH_CTRL_BY_BBSW,
126	COEX_SWITCH_CTRL_BY_PTA,
127	COEX_SWITCH_CTRL_BY_ANTDIV,
128	COEX_SWITCH_CTRL_BY_MAC,
129	COEX_SWITCH_CTRL_BY_BT,
130	COEX_SWITCH_CTRL_BY_FW,
131
132	COEX_SWITCH_CTRL_MAX
133};
134
135enum coex_algorithm {
136	COEX_ALGO_NOPROFILE	= 0,
137	COEX_ALGO_HFP		= 1,
138	COEX_ALGO_HID		= 2,
139	COEX_ALGO_A2DP		= 3,
140	COEX_ALGO_PAN		= 4,
141	COEX_ALGO_A2DP_HID	= 5,
142	COEX_ALGO_A2DP_PAN	= 6,
143	COEX_ALGO_PAN_HID	= 7,
144	COEX_ALGO_A2DP_PAN_HID	= 8,
145
146	COEX_ALGO_MAX
147};
148
149enum coex_wl_link_mode {
150	COEX_WLINK_2G1PORT	= 0x0,
151	COEX_WLINK_5G		= 0x3,
152	COEX_WLINK_MAX
153};
154
155enum coex_wl2bt_scoreboard {
156	COEX_SCBD_ACTIVE	= BIT(0),
157	COEX_SCBD_ONOFF		= BIT(1),
158	COEX_SCBD_SCAN		= BIT(2),
159	COEX_SCBD_UNDERTEST	= BIT(3),
160	COEX_SCBD_RXGAIN	= BIT(4),
161	COEX_SCBD_BT_RFK	= BIT(5),
162	COEX_SCBD_WLBUSY	= BIT(6),
163	COEX_SCBD_EXTFEM	= BIT(8),
164	COEX_SCBD_TDMA		= BIT(9),
165	COEX_SCBD_FIX2M		= BIT(10),
166	COEX_SCBD_ALL		= GENMASK(15, 0),
167};
168
169enum coex_power_save_type {
170	COEX_PS_WIFI_NATIVE	= 0,
171	COEX_PS_LPS_ON		= 1,
172	COEX_PS_LPS_OFF		= 2,
173};
174
175enum coex_rssi_state {
176	COEX_RSSI_STATE_HIGH,
177	COEX_RSSI_STATE_MEDIUM,
178	COEX_RSSI_STATE_LOW,
179	COEX_RSSI_STATE_STAY_HIGH,
180	COEX_RSSI_STATE_STAY_MEDIUM,
181	COEX_RSSI_STATE_STAY_LOW,
182};
183
184enum coex_notify_type_ips {
185	COEX_IPS_LEAVE		= 0x0,
186	COEX_IPS_ENTER		= 0x1,
187};
188
189enum coex_notify_type_lps {
190	COEX_LPS_DISABLE	= 0x0,
191	COEX_LPS_ENABLE		= 0x1,
192};
193
194enum coex_notify_type_scan {
195	COEX_SCAN_FINISH,
196	COEX_SCAN_START,
197	COEX_SCAN_START_2G,
198	COEX_SCAN_START_5G,
199};
200
201enum coex_notify_type_switchband {
202	COEX_NOT_SWITCH,
203	COEX_SWITCH_TO_24G,
204	COEX_SWITCH_TO_5G,
205	COEX_SWITCH_TO_24G_NOFORSCAN,
206};
207
208enum coex_notify_type_associate {
209	COEX_ASSOCIATE_FINISH,
210	COEX_ASSOCIATE_START,
211	COEX_ASSOCIATE_5G_FINISH,
212	COEX_ASSOCIATE_5G_START,
213};
214
215enum coex_notify_type_media_status {
216	COEX_MEDIA_DISCONNECT,
217	COEX_MEDIA_CONNECT,
218	COEX_MEDIA_CONNECT_5G,
219};
220
221enum coex_bt_status {
222	COEX_BTSTATUS_NCON_IDLE		= 0,
223	COEX_BTSTATUS_CON_IDLE		= 1,
224	COEX_BTSTATUS_INQ_PAGE		= 2,
225	COEX_BTSTATUS_ACL_BUSY		= 3,
226	COEX_BTSTATUS_SCO_BUSY		= 4,
227	COEX_BTSTATUS_ACL_SCO_BUSY	= 5,
228
229	COEX_BTSTATUS_MAX
230};
231
232enum coex_wl_tput_dir {
233	COEX_WL_TPUT_TX			= 0x0,
234	COEX_WL_TPUT_RX			= 0x1,
235	COEX_WL_TPUT_MAX
236};
237
238enum coex_wl_priority_mask {
239	COEX_WLPRI_RX_RSP	= 2,
240	COEX_WLPRI_TX_RSP	= 3,
241	COEX_WLPRI_TX_BEACON	= 4,
242	COEX_WLPRI_TX_OFDM	= 11,
243	COEX_WLPRI_TX_CCK	= 12,
244	COEX_WLPRI_TX_BEACONQ	= 27,
245	COEX_WLPRI_RX_CCK	= 28,
246	COEX_WLPRI_RX_OFDM	= 29,
247	COEX_WLPRI_MAX
248};
249
250enum coex_commom_chip_setup {
251	COEX_CSETUP_INIT_HW		= 0x0,
252	COEX_CSETUP_ANT_SWITCH		= 0x1,
253	COEX_CSETUP_GNT_FIX		= 0x2,
254	COEX_CSETUP_GNT_DEBUG		= 0x3,
255	COEX_CSETUP_RFE_TYPE		= 0x4,
256	COEX_CSETUP_COEXINFO_HW		= 0x5,
257	COEX_CSETUP_WL_TX_POWER		= 0x6,
258	COEX_CSETUP_WL_RX_GAIN		= 0x7,
259	COEX_CSETUP_WLAN_ACT_IPS	= 0x8,
260	COEX_CSETUP_MAX
261};
262
263enum coex_indirect_reg_type {
264	COEX_INDIRECT_1700		= 0x0,
265	COEX_INDIRECT_7C0		= 0x1,
266	COEX_INDIRECT_MAX
267};
268
269enum coex_pstdma_type {
270	COEX_PSTDMA_FORCE_LPSOFF	= 0x0,
271	COEX_PSTDMA_FORCE_LPSON		= 0x1,
272	COEX_PSTDMA_MAX
273};
274
275enum coex_btrssi_type {
276	COEX_BTRSSI_RATIO		= 0x0,
277	COEX_BTRSSI_DBM			= 0x1,
278	COEX_BTRSSI_MAX
279};
280
281struct coex_table_para {
282	u32 bt;
283	u32 wl;
284};
285
286struct coex_tdma_para {
287	u8 para[5];
288};
289
290struct coex_5g_afh_map {
291	u32 wl_5g_ch;
292	u8 bt_skip_ch;
293	u8 bt_skip_span;
294};
295
296struct coex_rf_para {
297	u8 wl_pwr_dec_lvl;
298	u8 bt_pwr_dec_lvl;
299	bool wl_low_gain_en;
300	u8 bt_lna_lvl;
301};
302
303static inline void rtw_coex_set_init(struct rtw_dev *rtwdev)
304{
305	struct rtw_chip_info *chip = rtwdev->chip;
306
307	chip->ops->coex_set_init(rtwdev);
308}
309
310static inline
311void rtw_coex_set_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type, u8 pos_type)
312{
313	struct rtw_chip_info *chip = rtwdev->chip;
314
315	if (!chip->ops->coex_set_ant_switch)
316		return;
317
318	chip->ops->coex_set_ant_switch(rtwdev, ctrl_type, pos_type);
319}
320
321static inline void rtw_coex_set_gnt_fix(struct rtw_dev *rtwdev)
322{
323	struct rtw_chip_info *chip = rtwdev->chip;
324
325	chip->ops->coex_set_gnt_fix(rtwdev);
326}
327
328static inline void rtw_coex_set_gnt_debug(struct rtw_dev *rtwdev)
329{
330	struct rtw_chip_info *chip = rtwdev->chip;
331
332	chip->ops->coex_set_gnt_debug(rtwdev);
333}
334
335static inline  void rtw_coex_set_rfe_type(struct rtw_dev *rtwdev)
336{
337	struct rtw_chip_info *chip = rtwdev->chip;
338
339	chip->ops->coex_set_rfe_type(rtwdev);
340}
341
342static inline void rtw_coex_set_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
343{
344	struct rtw_chip_info *chip = rtwdev->chip;
345
346	chip->ops->coex_set_wl_tx_power(rtwdev, wl_pwr);
347}
348
349static inline
350void rtw_coex_set_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
351{
352	struct rtw_chip_info *chip = rtwdev->chip;
353
354	chip->ops->coex_set_wl_rx_gain(rtwdev, low_gain);
355}
356
357void rtw_coex_info_response(struct rtw_dev *rtwdev, struct sk_buff *skb);
358u32 rtw_coex_read_indirect_reg(struct rtw_dev *rtwdev, u16 addr);
359void rtw_coex_write_indirect_reg(struct rtw_dev *rtwdev, u16 addr,
360				 u32 mask, u32 val);
361void rtw_coex_write_scbd(struct rtw_dev *rtwdev, u16 bitpos, bool set);
362
363void rtw_coex_bt_relink_work(struct work_struct *work);
364void rtw_coex_bt_reenable_work(struct work_struct *work);
365void rtw_coex_defreeze_work(struct work_struct *work);
366void rtw_coex_wl_remain_work(struct work_struct *work);
367void rtw_coex_bt_remain_work(struct work_struct *work);
368
369void rtw_coex_power_on_setting(struct rtw_dev *rtwdev);
370void rtw_coex_init_hw_config(struct rtw_dev *rtwdev, bool wifi_only);
371void rtw_coex_ips_notify(struct rtw_dev *rtwdev, u8 type);
372void rtw_coex_lps_notify(struct rtw_dev *rtwdev, u8 type);
373void rtw_coex_scan_notify(struct rtw_dev *rtwdev, u8 type);
374void rtw_coex_connect_notify(struct rtw_dev *rtwdev, u8 action);
375void rtw_coex_media_status_notify(struct rtw_dev *rtwdev, u8 status);
376void rtw_coex_bt_info_notify(struct rtw_dev *rtwdev, u8 *buf, u8 len);
377void rtw_coex_wl_fwdbginfo_notify(struct rtw_dev *rtwdev, u8 *buf, u8 length);
378void rtw_coex_switchband_notify(struct rtw_dev *rtwdev, u8 type);
379void rtw_coex_wl_status_change_notify(struct rtw_dev *rtwdev);
380
381void rtw_coex_display_coex_info(struct rtw_dev *rtwdev, struct seq_file *m);
382
383#endif
384