1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright(c) 2009-2012  Realtek Corporation.*/
3
4#ifndef __RTL8723E_PWRSEQ_H__
5#define __RTL8723E_PWRSEQ_H__
6
7#include "../pwrseqcmd.h"
8/*
9 *	Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd
10 *	There are 6 HW Power States:
11 *	0: POFF--Power Off
12 *	1: PDN--Power Down
13 *	2: CARDEMU--Card Emulation
14 *	3: ACT--Active Mode
15 *	4: LPS--Low Power State
16 *	5: SUS--Suspend
17 *
18 *	The transision from different states are defined below
19 *	TRANS_CARDEMU_TO_ACT
20 *	TRANS_ACT_TO_CARDEMU
21 *	TRANS_CARDEMU_TO_SUS
22 *	TRANS_SUS_TO_CARDEMU
23 *	TRANS_CARDEMU_TO_PDN
24 *	TRANS_ACT_TO_LPS
25 *	TRANS_LPS_TO_ACT
26 *
27 *	TRANS_END
28 */
29
30#define	RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS	10
31#define	RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS	10
32#define	RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS	10
33#define	RTL8723A_TRANS_SUS_TO_CARDEMU_STEPS	10
34#define	RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS	10
35#define	RTL8723A_TRANS_PDN_TO_CARDEMU_STEPS	10
36#define	RTL8723A_TRANS_ACT_TO_LPS_STEPS		15
37#define	RTL8723A_TRANS_LPS_TO_ACT_STEPS		15
38#define	RTL8723A_TRANS_END_STEPS		1
39
40/* format */
41/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }*/
42
43#define RTL8723A_TRANS_CARDEMU_TO_ACT	\
44	/* disable SW LPS 0x04[10]=0*/	\
45	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
46		PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), 0},\
47	/* wait till 0x04[17] = 1    power ready*/	\
48	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
49		PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},\
50	/* release WLON reset  0x04[16]=1*/	\
51	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
52		PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
53	/* disable HWPDN 0x04[15]=0*/ \
54	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
55		PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
56	/* disable WL suspend*/ \
57	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
58		PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},\
59	/* polling until return 0*/ \
60	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
61		PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
62	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
63		PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},
64
65/* format */
66/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
67
68#define RTL8723A_TRANS_ACT_TO_CARDEMU	\
69	/*0x1F[7:0] = 0 turn off RF*/ \
70	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
71		PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},	\
72	{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
73		PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
74	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
75		PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
76	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
77		PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0},
78
79/* format */
80/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/
81#define RTL8723A_TRANS_CARDEMU_TO_SUS			\
82		/*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
83	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
84		PWR_BASEADDR_MAC, PWR_CMD_WRITE, \
85		BIT(4)|BIT(3), (BIT(4)|BIT(3))},\
86/*0x04[12:11] = 2b'01 enable WL suspend*/	\
87	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK| \
88		PWR_INTF_SDIO_MSK,\
89		PWR_BASEADDR_MAC, \
90		PWR_CMD_WRITE, \
91		BIT(3)|BIT(4), BIT(3)}, \
92/*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
93	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
94		PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, \
95		PWR_CMD_WRITE, BIT(3)|BIT(4), \
96		BIT(3)|BIT(4)}, \
97/*Set SDIO suspend local register*/	\
98	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
99		PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
100		PWR_CMD_WRITE, BIT(0), BIT(0)}, \
101/*wait power state to suspend*/ \
102	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
103		PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
104		PWR_CMD_POLLING, BIT(1), 0},
105
106/* format */
107/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
108
109#define RTL8723A_TRANS_SUS_TO_CARDEMU	\
110 /*Set SDIO suspend local register*/	\
111	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
112		PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},\
113 /*wait power state to suspend*/ \
114	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
115		PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},\
116 /*0x04[12:11] = 2b'00 disable WL suspend*/ \
117	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
118		PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
119
120/* format */
121/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
122
123#define RTL8723A_TRANS_CARDEMU_TO_CARDDIS \
124 /*0x04[12:11] = 2b'01 enable WL suspend*/	 \
125	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
126		PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, \
127		PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
128/*0x04[10] = 1, enable SW LPS*/	\
129	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
130		PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC,\
131		PWR_CMD_WRITE, BIT(2), BIT(2)}, \
132/*Set SDIO suspend local register*/ \
133	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
134		PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
135		PWR_CMD_WRITE, BIT(0), BIT(0)}, \
136 /*wait power state to suspend*/ \
137	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
138		PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
139		PWR_CMD_POLLING, BIT(1), 0},
140
141/* format */
142/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
143
144#define RTL8723A_TRANS_CARDDIS_TO_CARDEMU\
145/*Set SDIO suspend local register*/	\
146	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
147		PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
148		PWR_CMD_WRITE, BIT(0), 0}, \
149 /*wait power state to suspend*/ \
150	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
151		PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
152		PWR_CMD_POLLING, BIT(1), BIT(1)},\
153 /*0x04[12:11] = 2b'00 disable WL suspend*/ \
154	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
155		PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
156		PWR_CMD_WRITE, BIT(3)|BIT(4), 0},\
157/*PCIe DMA start*/ \
158	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
159		PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
160		PWR_CMD_WRITE, 0xFF, 0},
161
162/* format */
163/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
164#define RTL8723A_TRANS_CARDEMU_TO_PDN	\
165	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
166		PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
167		PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/\
168	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
169		PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
170		PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/
171
172/* format */
173/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
174#define RTL8723A_TRANS_PDN_TO_CARDEMU	\
175	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
176		PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
177		PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/
178
179/* format */
180/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
181
182#define RTL8723A_TRANS_ACT_TO_LPS	\
183	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
184		PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
185		PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
186	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
187		PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
188		PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/	\
189	/*Should be zero if no packet is transmitting*/	\
190	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
191		PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
192		PWR_CMD_POLLING, 0xFF, 0},\
193	/*Should be zero if no packet is transmitting*/	\
194	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
195		PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
196		PWR_CMD_POLLING, 0xFF, 0},\
197	/*Should be zero if no packet is transmitting*/	\
198	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
199		PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
200		PWR_CMD_POLLING, 0xFF, 0},\
201	/*Should be zero if no packet is transmitting*/	\
202	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
203		PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
204		PWR_CMD_POLLING, 0xFF, 0},\
205	/*CCK and OFDM are disabled,and clock are gated*/ \
206	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
207		PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
208		PWR_CMD_WRITE, BIT(0), 0},\
209	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
210		PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
211		PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\
212	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
213		PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
214		PWR_CMD_WRITE, BIT(1), 0},/*Whole BB is reset*/	\
215	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
216		PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
217		PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/	\
218	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
219		PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
220		PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/	\
221	/*Respond TxOK to scheduler*/	\
222	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
223		PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
224		PWR_CMD_WRITE, BIT(5), BIT(5)},\
225
226#define RTL8723A_TRANS_LPS_TO_ACT\
227/* format */	\
228/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */	\
229	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
230		PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
231		PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
232	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
233		PWR_INTF_USB_MSK, PWR_BASEADDR_MAC,\
234		PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
235	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
236		PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC,\
237		PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
238	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
239		PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
240		PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
241	/*.	0x08[4] = 0		 switch TSF to 40M*/\
242	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
243		PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
244		PWR_CMD_WRITE, BIT(4), 0},  \
245	/*Polling 0x109[7]=0  TSF in 40M*/\
246	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
247		PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
248		PWR_CMD_POLLING, BIT(7), 0}, \
249	/*.	0x29[7:6] = 2b'00	 enable BB clock*/\
250	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
251		PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
252		PWR_CMD_WRITE, BIT(6)|BIT(7), 0},\
253	 /*.	0x101[1] = 1*/\
254	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
255		PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
256		PWR_CMD_WRITE, BIT(1), BIT(1)},\
257	 /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
258	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
259		PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
260		PWR_CMD_WRITE, 0xFF, 0xFF},\
261	 /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
262	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
263		PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
264		PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)},\
265	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
266		PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
267		PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
268
269/* format */
270/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
271
272#define RTL8723A_TRANS_END \
273	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
274	0, PWR_CMD_END, 0, 0}
275
276extern struct wlan_pwr_cfg rtl8723A_power_on_flow
277		[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS +
278		 RTL8723A_TRANS_END_STEPS];
279extern struct wlan_pwr_cfg rtl8723A_radio_off_flow
280		[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
281		 RTL8723A_TRANS_END_STEPS];
282extern struct wlan_pwr_cfg rtl8723A_card_disable_flow
283		[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
284		 RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS +
285		 RTL8723A_TRANS_END_STEPS];
286extern struct wlan_pwr_cfg rtl8723A_card_enable_flow
287		[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
288		 RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS +
289		 RTL8723A_TRANS_END_STEPS];
290extern struct wlan_pwr_cfg rtl8723A_suspend_flow
291		[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
292		 RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS +
293		 RTL8723A_TRANS_END_STEPS];
294extern struct wlan_pwr_cfg rtl8723A_resume_flow
295		[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
296		 RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS +
297		 RTL8723A_TRANS_END_STEPS];
298extern struct wlan_pwr_cfg rtl8723A_hwpdn_flow
299		[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
300		 RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS +
301		 RTL8723A_TRANS_END_STEPS];
302extern struct wlan_pwr_cfg rtl8723A_enter_lps_flow
303		[RTL8723A_TRANS_ACT_TO_LPS_STEPS + RTL8723A_TRANS_END_STEPS];
304extern struct wlan_pwr_cfg rtl8723A_leave_lps_flow
305		[RTL8723A_TRANS_LPS_TO_ACT_STEPS + RTL8723A_TRANS_END_STEPS];
306
307/* RTL8723 Power Configuration CMDs for PCIe interface */
308#define RTL8723_NIC_PWR_ON_FLOW		rtl8723A_power_on_flow
309#define RTL8723_NIC_RF_OFF_FLOW		rtl8723A_radio_off_flow
310#define RTL8723_NIC_DISABLE_FLOW	rtl8723A_card_disable_flow
311#define RTL8723_NIC_ENABLE_FLOW		rtl8723A_card_enable_flow
312#define RTL8723_NIC_SUSPEND_FLOW	rtl8723A_suspend_flow
313#define RTL8723_NIC_RESUME_FLOW		rtl8723A_resume_flow
314#define RTL8723_NIC_PDN_FLOW		rtl8723A_hwpdn_flow
315#define RTL8723_NIC_LPS_ENTER_FLOW	rtl8723A_enter_lps_flow
316#define RTL8723_NIC_LPS_LEAVE_FLOW	rtl8723A_leave_lps_flow
317
318#endif
319