1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4#include "../wifi.h" 5#include "../pci.h" 6#include "../ps.h" 7#include "../core.h" 8#include "reg.h" 9#include "def.h" 10#include "phy.h" 11#include "rf.h" 12#include "dm.h" 13#include "fw.h" 14#include "hw.h" 15#include "table.h" 16 17u32 rtl92s_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) 18{ 19 struct rtl_priv *rtlpriv = rtl_priv(hw); 20 u32 returnvalue = 0, originalvalue, bitshift; 21 22 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n", 23 regaddr, bitmask); 24 25 originalvalue = rtl_read_dword(rtlpriv, regaddr); 26 bitshift = calculate_bit_shift(bitmask); 27 returnvalue = (originalvalue & bitmask) >> bitshift; 28 29 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "BBR MASK=0x%x Addr[0x%x]=0x%x\n", 30 bitmask, regaddr, originalvalue); 31 32 return returnvalue; 33 34} 35 36void rtl92s_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask, 37 u32 data) 38{ 39 struct rtl_priv *rtlpriv = rtl_priv(hw); 40 u32 originalvalue, bitshift; 41 42 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 43 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 44 regaddr, bitmask, data); 45 46 if (bitmask != MASKDWORD) { 47 originalvalue = rtl_read_dword(rtlpriv, regaddr); 48 bitshift = calculate_bit_shift(bitmask); 49 data = ((originalvalue & (~bitmask)) | (data << bitshift)); 50 } 51 52 rtl_write_dword(rtlpriv, regaddr, data); 53 54 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 55 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 56 regaddr, bitmask, data); 57 58} 59 60static u32 _rtl92s_phy_rf_serial_read(struct ieee80211_hw *hw, 61 enum radio_path rfpath, u32 offset) 62{ 63 64 struct rtl_priv *rtlpriv = rtl_priv(hw); 65 struct rtl_phy *rtlphy = &(rtlpriv->phy); 66 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 67 u32 newoffset; 68 u32 tmplong, tmplong2; 69 u8 rfpi_enable = 0; 70 u32 retvalue = 0; 71 72 offset &= 0x3f; 73 newoffset = offset; 74 75 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); 76 77 if (rfpath == RF90_PATH_A) 78 tmplong2 = tmplong; 79 else 80 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); 81 82 tmplong2 = (tmplong2 & (~BLSSI_READADDRESS)) | (newoffset << 23) | 83 BLSSI_READEDGE; 84 85 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, 86 tmplong & (~BLSSI_READEDGE)); 87 88 mdelay(1); 89 90 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); 91 mdelay(1); 92 93 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, tmplong | 94 BLSSI_READEDGE); 95 mdelay(1); 96 97 if (rfpath == RF90_PATH_A) 98 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, 99 BIT(8)); 100 else if (rfpath == RF90_PATH_B) 101 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, 102 BIT(8)); 103 104 if (rfpi_enable) 105 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi, 106 BLSSI_READBACK_DATA); 107 else 108 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, 109 BLSSI_READBACK_DATA); 110 111 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, 112 BLSSI_READBACK_DATA); 113 114 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n", 115 rfpath, pphyreg->rf_rb, retvalue); 116 117 return retvalue; 118 119} 120 121static void _rtl92s_phy_rf_serial_write(struct ieee80211_hw *hw, 122 enum radio_path rfpath, u32 offset, 123 u32 data) 124{ 125 struct rtl_priv *rtlpriv = rtl_priv(hw); 126 struct rtl_phy *rtlphy = &(rtlpriv->phy); 127 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 128 u32 data_and_addr = 0; 129 u32 newoffset; 130 131 offset &= 0x3f; 132 newoffset = offset; 133 134 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; 135 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); 136 137 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n", 138 rfpath, pphyreg->rf3wire_offset, data_and_addr); 139} 140 141 142u32 rtl92s_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, 143 u32 regaddr, u32 bitmask) 144{ 145 struct rtl_priv *rtlpriv = rtl_priv(hw); 146 u32 original_value, readback_value, bitshift; 147 148 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 149 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n", 150 regaddr, rfpath, bitmask); 151 152 spin_lock(&rtlpriv->locks.rf_lock); 153 154 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath, regaddr); 155 156 bitshift = calculate_bit_shift(bitmask); 157 readback_value = (original_value & bitmask) >> bitshift; 158 159 spin_unlock(&rtlpriv->locks.rf_lock); 160 161 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 162 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n", 163 regaddr, rfpath, bitmask, original_value); 164 165 return readback_value; 166} 167 168void rtl92s_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, 169 u32 regaddr, u32 bitmask, u32 data) 170{ 171 struct rtl_priv *rtlpriv = rtl_priv(hw); 172 struct rtl_phy *rtlphy = &(rtlpriv->phy); 173 u32 original_value, bitshift; 174 175 if (!((rtlphy->rf_pathmap >> rfpath) & 0x1)) 176 return; 177 178 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 179 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 180 regaddr, bitmask, data, rfpath); 181 182 spin_lock(&rtlpriv->locks.rf_lock); 183 184 if (bitmask != RFREG_OFFSET_MASK) { 185 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath, 186 regaddr); 187 bitshift = calculate_bit_shift(bitmask); 188 data = ((original_value & (~bitmask)) | (data << bitshift)); 189 } 190 191 _rtl92s_phy_rf_serial_write(hw, rfpath, regaddr, data); 192 193 spin_unlock(&rtlpriv->locks.rf_lock); 194 195 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 196 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 197 regaddr, bitmask, data, rfpath); 198 199} 200 201void rtl92s_phy_scan_operation_backup(struct ieee80211_hw *hw, 202 u8 operation) 203{ 204 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 205 206 if (!is_hal_stop(rtlhal)) { 207 switch (operation) { 208 case SCAN_OPT_BACKUP: 209 rtl92s_phy_set_fw_cmd(hw, FW_CMD_PAUSE_DM_BY_SCAN); 210 break; 211 case SCAN_OPT_RESTORE: 212 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RESUME_DM_BY_SCAN); 213 break; 214 default: 215 pr_err("Unknown operation\n"); 216 break; 217 } 218 } 219} 220 221void rtl92s_phy_set_bw_mode(struct ieee80211_hw *hw, 222 enum nl80211_channel_type ch_type) 223{ 224 struct rtl_priv *rtlpriv = rtl_priv(hw); 225 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 226 struct rtl_phy *rtlphy = &(rtlpriv->phy); 227 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 228 u8 reg_bw_opmode; 229 230 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n", 231 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? 232 "20MHz" : "40MHz"); 233 234 if (rtlphy->set_bwmode_inprogress) 235 return; 236 if (is_hal_stop(rtlhal)) 237 return; 238 239 rtlphy->set_bwmode_inprogress = true; 240 241 reg_bw_opmode = rtl_read_byte(rtlpriv, BW_OPMODE); 242 /* dummy read */ 243 rtl_read_byte(rtlpriv, RRSR + 2); 244 245 switch (rtlphy->current_chan_bw) { 246 case HT_CHANNEL_WIDTH_20: 247 reg_bw_opmode |= BW_OPMODE_20MHZ; 248 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode); 249 break; 250 case HT_CHANNEL_WIDTH_20_40: 251 reg_bw_opmode &= ~BW_OPMODE_20MHZ; 252 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode); 253 break; 254 default: 255 pr_err("unknown bandwidth: %#X\n", 256 rtlphy->current_chan_bw); 257 break; 258 } 259 260 switch (rtlphy->current_chan_bw) { 261 case HT_CHANNEL_WIDTH_20: 262 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); 263 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); 264 265 if (rtlhal->version >= VERSION_8192S_BCUT) 266 rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x58); 267 break; 268 case HT_CHANNEL_WIDTH_20_40: 269 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); 270 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); 271 272 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND, 273 (mac->cur_40_prime_sc >> 1)); 274 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); 275 276 if (rtlhal->version >= VERSION_8192S_BCUT) 277 rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x18); 278 break; 279 default: 280 pr_err("unknown bandwidth: %#X\n", 281 rtlphy->current_chan_bw); 282 break; 283 } 284 285 rtl92s_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); 286 rtlphy->set_bwmode_inprogress = false; 287 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); 288} 289 290static bool _rtl92s_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable, 291 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid, 292 u32 para1, u32 para2, u32 msdelay) 293{ 294 struct swchnlcmd *pcmd; 295 296 if (cmdtable == NULL) { 297 WARN_ONCE(true, "rtl8192se: cmdtable cannot be NULL\n"); 298 return false; 299 } 300 301 if (cmdtableidx >= cmdtablesz) 302 return false; 303 304 pcmd = cmdtable + cmdtableidx; 305 pcmd->cmdid = cmdid; 306 pcmd->para1 = para1; 307 pcmd->para2 = para2; 308 pcmd->msdelay = msdelay; 309 310 return true; 311} 312 313static bool _rtl92s_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, 314 u8 channel, u8 *stage, u8 *step, u32 *delay) 315{ 316 struct rtl_priv *rtlpriv = rtl_priv(hw); 317 struct rtl_phy *rtlphy = &(rtlpriv->phy); 318 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT]; 319 u32 precommoncmdcnt; 320 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT]; 321 u32 postcommoncmdcnt; 322 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT]; 323 u32 rfdependcmdcnt; 324 struct swchnlcmd *currentcmd = NULL; 325 u8 rfpath; 326 u8 num_total_rfpath = rtlphy->num_total_rfpath; 327 328 precommoncmdcnt = 0; 329 _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 330 MAX_PRECMD_CNT, CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0); 331 _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 332 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); 333 334 postcommoncmdcnt = 0; 335 336 _rtl92s_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++, 337 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); 338 339 rfdependcmdcnt = 0; 340 341 WARN_ONCE((channel < 1 || channel > 14), 342 "rtl8192se: invalid channel for Zebra: %d\n", channel); 343 344 _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 345 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG, 346 RF_CHNLBW, channel, 10); 347 348 _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 349 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 0); 350 351 do { 352 switch (*stage) { 353 case 0: 354 currentcmd = &precommoncmd[*step]; 355 break; 356 case 1: 357 currentcmd = &rfdependcmd[*step]; 358 break; 359 case 2: 360 currentcmd = &postcommoncmd[*step]; 361 break; 362 default: 363 return true; 364 } 365 366 if (currentcmd->cmdid == CMDID_END) { 367 if ((*stage) == 2) { 368 return true; 369 } else { 370 (*stage)++; 371 (*step) = 0; 372 continue; 373 } 374 } 375 376 switch (currentcmd->cmdid) { 377 case CMDID_SET_TXPOWEROWER_LEVEL: 378 rtl92s_phy_set_txpower(hw, channel); 379 break; 380 case CMDID_WRITEPORT_ULONG: 381 rtl_write_dword(rtlpriv, currentcmd->para1, 382 currentcmd->para2); 383 break; 384 case CMDID_WRITEPORT_USHORT: 385 rtl_write_word(rtlpriv, currentcmd->para1, 386 (u16)currentcmd->para2); 387 break; 388 case CMDID_WRITEPORT_UCHAR: 389 rtl_write_byte(rtlpriv, currentcmd->para1, 390 (u8)currentcmd->para2); 391 break; 392 case CMDID_RF_WRITEREG: 393 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { 394 rtlphy->rfreg_chnlval[rfpath] = 395 ((rtlphy->rfreg_chnlval[rfpath] & 396 0xfffffc00) | currentcmd->para2); 397 rtl_set_rfreg(hw, (enum radio_path)rfpath, 398 currentcmd->para1, 399 RFREG_OFFSET_MASK, 400 rtlphy->rfreg_chnlval[rfpath]); 401 } 402 break; 403 default: 404 pr_err("switch case %#x not processed\n", 405 currentcmd->cmdid); 406 break; 407 } 408 409 break; 410 } while (true); 411 412 (*delay) = currentcmd->msdelay; 413 (*step)++; 414 return false; 415} 416 417u8 rtl92s_phy_sw_chnl(struct ieee80211_hw *hw) 418{ 419 struct rtl_priv *rtlpriv = rtl_priv(hw); 420 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 421 struct rtl_phy *rtlphy = &(rtlpriv->phy); 422 u32 delay; 423 bool ret; 424 425 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "switch to channel%d\n", 426 rtlphy->current_channel); 427 428 if (rtlphy->sw_chnl_inprogress) 429 return 0; 430 431 if (rtlphy->set_bwmode_inprogress) 432 return 0; 433 434 if (is_hal_stop(rtlhal)) 435 return 0; 436 437 rtlphy->sw_chnl_inprogress = true; 438 rtlphy->sw_chnl_stage = 0; 439 rtlphy->sw_chnl_step = 0; 440 441 do { 442 if (!rtlphy->sw_chnl_inprogress) 443 break; 444 445 ret = _rtl92s_phy_sw_chnl_step_by_step(hw, 446 rtlphy->current_channel, 447 &rtlphy->sw_chnl_stage, 448 &rtlphy->sw_chnl_step, &delay); 449 if (!ret) { 450 if (delay > 0) 451 mdelay(delay); 452 else 453 continue; 454 } else { 455 rtlphy->sw_chnl_inprogress = false; 456 } 457 break; 458 } while (true); 459 460 rtlphy->sw_chnl_inprogress = false; 461 462 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); 463 464 return 1; 465} 466 467static void _rtl92se_phy_set_rf_sleep(struct ieee80211_hw *hw) 468{ 469 struct rtl_priv *rtlpriv = rtl_priv(hw); 470 u8 u1btmp; 471 472 u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL); 473 u1btmp |= BIT(0); 474 475 rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp); 476 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0); 477 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF); 478 rtl_write_word(rtlpriv, CMDR, 0x57FC); 479 udelay(100); 480 481 rtl_write_word(rtlpriv, CMDR, 0x77FC); 482 rtl_write_byte(rtlpriv, PHY_CCA, 0x0); 483 udelay(10); 484 485 rtl_write_word(rtlpriv, CMDR, 0x37FC); 486 udelay(10); 487 488 rtl_write_word(rtlpriv, CMDR, 0x77FC); 489 udelay(10); 490 491 rtl_write_word(rtlpriv, CMDR, 0x57FC); 492 493 /* we should chnge GPIO to input mode 494 * this will drop away current about 25mA*/ 495 rtl8192se_gpiobit3_cfg_inputmode(hw); 496} 497 498bool rtl92s_phy_set_rf_power_state(struct ieee80211_hw *hw, 499 enum rf_pwrstate rfpwr_state) 500{ 501 struct rtl_priv *rtlpriv = rtl_priv(hw); 502 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 503 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 504 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 505 bool bresult = true; 506 u8 i, queue_id; 507 struct rtl8192_tx_ring *ring = NULL; 508 509 if (rfpwr_state == ppsc->rfpwr_state) 510 return false; 511 512 switch (rfpwr_state) { 513 case ERFON:{ 514 if ((ppsc->rfpwr_state == ERFOFF) && 515 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { 516 517 bool rtstatus; 518 u32 initializecount = 0; 519 do { 520 initializecount++; 521 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 522 "IPS Set eRf nic enable\n"); 523 rtstatus = rtl_ps_enable_nic(hw); 524 } while (!rtstatus && (initializecount < 10)); 525 526 RT_CLEAR_PS_LEVEL(ppsc, 527 RT_RF_OFF_LEVL_HALT_NIC); 528 } else { 529 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, 530 "awake, slept:%d ms state_inap:%x\n", 531 jiffies_to_msecs(jiffies - 532 ppsc->last_sleep_jiffies), 533 rtlpriv->psc.state_inap); 534 ppsc->last_awake_jiffies = jiffies; 535 rtl_write_word(rtlpriv, CMDR, 0x37FC); 536 rtl_write_byte(rtlpriv, TXPAUSE, 0x00); 537 rtl_write_byte(rtlpriv, PHY_CCA, 0x3); 538 } 539 540 if (mac->link_state == MAC80211_LINKED) 541 rtlpriv->cfg->ops->led_control(hw, 542 LED_CTL_LINK); 543 else 544 rtlpriv->cfg->ops->led_control(hw, 545 LED_CTL_NO_LINK); 546 break; 547 } 548 case ERFOFF:{ 549 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) { 550 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 551 "IPS Set eRf nic disable\n"); 552 rtl_ps_disable_nic(hw); 553 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 554 } else { 555 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 556 rtlpriv->cfg->ops->led_control(hw, 557 LED_CTL_NO_LINK); 558 else 559 rtlpriv->cfg->ops->led_control(hw, 560 LED_CTL_POWER_OFF); 561 } 562 break; 563 } 564 case ERFSLEEP: 565 if (ppsc->rfpwr_state == ERFOFF) 566 return false; 567 568 for (queue_id = 0, i = 0; 569 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) { 570 ring = &pcipriv->dev.tx_ring[queue_id]; 571 if (skb_queue_len(&ring->queue) == 0 || 572 queue_id == BEACON_QUEUE) { 573 queue_id++; 574 continue; 575 } else { 576 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 577 "eRf Off/Sleep: %d times TcbBusyQueue[%d] = %d before doze!\n", 578 i + 1, queue_id, 579 skb_queue_len(&ring->queue)); 580 581 udelay(10); 582 i++; 583 } 584 585 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 586 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 587 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n", 588 MAX_DOZE_WAITING_TIMES_9x, 589 queue_id, 590 skb_queue_len(&ring->queue)); 591 break; 592 } 593 } 594 595 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, 596 "Set ERFSLEEP awaked:%d ms\n", 597 jiffies_to_msecs(jiffies - 598 ppsc->last_awake_jiffies)); 599 600 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, 601 "sleep awaked:%d ms state_inap:%x\n", 602 jiffies_to_msecs(jiffies - 603 ppsc->last_awake_jiffies), 604 rtlpriv->psc.state_inap); 605 ppsc->last_sleep_jiffies = jiffies; 606 _rtl92se_phy_set_rf_sleep(hw); 607 break; 608 default: 609 pr_err("switch case %#x not processed\n", 610 rfpwr_state); 611 bresult = false; 612 break; 613 } 614 615 if (bresult) 616 ppsc->rfpwr_state = rfpwr_state; 617 618 return bresult; 619} 620 621static bool _rtl92s_phy_config_rfpa_bias_current(struct ieee80211_hw *hw, 622 enum radio_path rfpath) 623{ 624 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 625 bool rtstatus = true; 626 u32 tmpval = 0; 627 628 /* If inferiority IC, we have to increase the PA bias current */ 629 if (rtlhal->ic_class != IC_INFERIORITY_A) { 630 tmpval = rtl92s_phy_query_rf_reg(hw, rfpath, RF_IPA, 0xf); 631 rtl92s_phy_set_rf_reg(hw, rfpath, RF_IPA, 0xf, tmpval + 1); 632 } 633 634 return rtstatus; 635} 636 637static void _rtl92s_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw, 638 u32 reg_addr, u32 bitmask, u32 data) 639{ 640 struct rtl_priv *rtlpriv = rtl_priv(hw); 641 struct rtl_phy *rtlphy = &(rtlpriv->phy); 642 int index; 643 644 if (reg_addr == RTXAGC_RATE18_06) 645 index = 0; 646 else if (reg_addr == RTXAGC_RATE54_24) 647 index = 1; 648 else if (reg_addr == RTXAGC_CCK_MCS32) 649 index = 6; 650 else if (reg_addr == RTXAGC_MCS03_MCS00) 651 index = 2; 652 else if (reg_addr == RTXAGC_MCS07_MCS04) 653 index = 3; 654 else if (reg_addr == RTXAGC_MCS11_MCS08) 655 index = 4; 656 else if (reg_addr == RTXAGC_MCS15_MCS12) 657 index = 5; 658 else 659 return; 660 661 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data; 662 if (index == 5) 663 rtlphy->pwrgroup_cnt++; 664} 665 666static void _rtl92s_phy_init_register_definition(struct ieee80211_hw *hw) 667{ 668 struct rtl_priv *rtlpriv = rtl_priv(hw); 669 struct rtl_phy *rtlphy = &(rtlpriv->phy); 670 671 /*RF Interface Sowrtware Control */ 672 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; 673 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW; 674 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW; 675 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; 676 677 /* RF Interface Readback Value */ 678 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB; 679 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB; 680 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB; 681 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; 682 683 /* RF Interface Output (and Enable) */ 684 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; 685 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE; 686 rtlphy->phyreg_def[RF90_PATH_C].rfintfo = RFPGA0_XC_RFINTERFACEOE; 687 rtlphy->phyreg_def[RF90_PATH_D].rfintfo = RFPGA0_XD_RFINTERFACEOE; 688 689 /* RF Interface (Output and) Enable */ 690 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; 691 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; 692 rtlphy->phyreg_def[RF90_PATH_C].rfintfe = RFPGA0_XC_RFINTERFACEOE; 693 rtlphy->phyreg_def[RF90_PATH_D].rfintfe = RFPGA0_XD_RFINTERFACEOE; 694 695 /* Addr of LSSI. Wirte RF register by driver */ 696 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = 697 RFPGA0_XA_LSSIPARAMETER; 698 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = 699 RFPGA0_XB_LSSIPARAMETER; 700 rtlphy->phyreg_def[RF90_PATH_C].rf3wire_offset = 701 RFPGA0_XC_LSSIPARAMETER; 702 rtlphy->phyreg_def[RF90_PATH_D].rf3wire_offset = 703 RFPGA0_XD_LSSIPARAMETER; 704 705 /* RF parameter */ 706 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER; 707 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER; 708 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER; 709 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; 710 711 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */ 712 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; 713 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; 714 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; 715 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; 716 717 /* Tranceiver A~D HSSI Parameter-1 */ 718 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1; 719 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1; 720 rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para1 = RFPGA0_XC_HSSIPARAMETER1; 721 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para1 = RFPGA0_XD_HSSIPARAMETER1; 722 723 /* Tranceiver A~D HSSI Parameter-2 */ 724 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2; 725 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2; 726 rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para2 = RFPGA0_XC_HSSIPARAMETER2; 727 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para2 = RFPGA0_XD_HSSIPARAMETER2; 728 729 /* RF switch Control */ 730 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; 731 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; 732 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; 733 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; 734 735 /* AGC control 1 */ 736 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1; 737 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1; 738 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1; 739 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; 740 741 /* AGC control 2 */ 742 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2; 743 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2; 744 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2; 745 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; 746 747 /* RX AFE control 1 */ 748 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE; 749 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE; 750 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE; 751 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE; 752 753 /* RX AFE control 1 */ 754 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE; 755 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE; 756 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE; 757 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; 758 759 /* Tx AFE control 1 */ 760 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE; 761 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE; 762 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE; 763 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE; 764 765 /* Tx AFE control 2 */ 766 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE; 767 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE; 768 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE; 769 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE; 770 771 /* Tranceiver LSSI Readback */ 772 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK; 773 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK; 774 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK; 775 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK; 776 777 /* Tranceiver LSSI Readback PI mode */ 778 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK; 779 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK; 780} 781 782 783static bool _rtl92s_phy_config_bb(struct ieee80211_hw *hw, u8 configtype) 784{ 785 int i; 786 u32 *phy_reg_table; 787 u32 *agc_table; 788 u16 phy_reg_len, agc_len; 789 790 agc_len = AGCTAB_ARRAYLENGTH; 791 agc_table = rtl8192seagctab_array; 792 /* Default RF_type: 2T2R */ 793 phy_reg_len = PHY_REG_2T2RARRAYLENGTH; 794 phy_reg_table = rtl8192sephy_reg_2t2rarray; 795 796 if (configtype == BASEBAND_CONFIG_PHY_REG) { 797 for (i = 0; i < phy_reg_len; i = i + 2) { 798 rtl_addr_delay(phy_reg_table[i]); 799 800 /* Add delay for ECS T20 & LG malow platform, */ 801 udelay(1); 802 803 rtl92s_phy_set_bb_reg(hw, phy_reg_table[i], MASKDWORD, 804 phy_reg_table[i + 1]); 805 } 806 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) { 807 for (i = 0; i < agc_len; i = i + 2) { 808 rtl92s_phy_set_bb_reg(hw, agc_table[i], MASKDWORD, 809 agc_table[i + 1]); 810 811 /* Add delay for ECS T20 & LG malow platform */ 812 udelay(1); 813 } 814 } 815 816 return true; 817} 818 819static bool _rtl92s_phy_set_bb_to_diff_rf(struct ieee80211_hw *hw, 820 u8 configtype) 821{ 822 struct rtl_priv *rtlpriv = rtl_priv(hw); 823 struct rtl_phy *rtlphy = &(rtlpriv->phy); 824 u32 *phy_regarray2xtxr_table; 825 u16 phy_regarray2xtxr_len; 826 int i; 827 828 if (rtlphy->rf_type == RF_1T1R) { 829 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t1rarray; 830 phy_regarray2xtxr_len = PHY_CHANGETO_1T1RARRAYLENGTH; 831 } else if (rtlphy->rf_type == RF_1T2R) { 832 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t2rarray; 833 phy_regarray2xtxr_len = PHY_CHANGETO_1T2RARRAYLENGTH; 834 } else { 835 return false; 836 } 837 838 if (configtype == BASEBAND_CONFIG_PHY_REG) { 839 for (i = 0; i < phy_regarray2xtxr_len; i = i + 3) { 840 rtl_addr_delay(phy_regarray2xtxr_table[i]); 841 842 rtl92s_phy_set_bb_reg(hw, phy_regarray2xtxr_table[i], 843 phy_regarray2xtxr_table[i + 1], 844 phy_regarray2xtxr_table[i + 2]); 845 } 846 } 847 848 return true; 849} 850 851static bool _rtl92s_phy_config_bb_with_pg(struct ieee80211_hw *hw, 852 u8 configtype) 853{ 854 int i; 855 u32 *phy_table_pg; 856 u16 phy_pg_len; 857 858 phy_pg_len = PHY_REG_ARRAY_PGLENGTH; 859 phy_table_pg = rtl8192sephy_reg_array_pg; 860 861 if (configtype == BASEBAND_CONFIG_PHY_REG) { 862 for (i = 0; i < phy_pg_len; i = i + 3) { 863 rtl_addr_delay(phy_table_pg[i]); 864 865 _rtl92s_store_pwrindex_diffrate_offset(hw, 866 phy_table_pg[i], 867 phy_table_pg[i + 1], 868 phy_table_pg[i + 2]); 869 rtl92s_phy_set_bb_reg(hw, phy_table_pg[i], 870 phy_table_pg[i + 1], 871 phy_table_pg[i + 2]); 872 } 873 } 874 875 return true; 876} 877 878static bool _rtl92s_phy_bb_config_parafile(struct ieee80211_hw *hw) 879{ 880 struct rtl_priv *rtlpriv = rtl_priv(hw); 881 struct rtl_phy *rtlphy = &(rtlpriv->phy); 882 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 883 bool rtstatus = true; 884 885 /* 1. Read PHY_REG.TXT BB INIT!! */ 886 /* We will separate as 1T1R/1T2R/1T2R_GREEN/2T2R */ 887 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_2T2R || 888 rtlphy->rf_type == RF_1T1R || rtlphy->rf_type == RF_2T2R_GREEN) { 889 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_PHY_REG); 890 891 if (rtlphy->rf_type != RF_2T2R && 892 rtlphy->rf_type != RF_2T2R_GREEN) 893 /* so we should reconfig BB reg with the right 894 * PHY parameters. */ 895 rtstatus = _rtl92s_phy_set_bb_to_diff_rf(hw, 896 BASEBAND_CONFIG_PHY_REG); 897 } else { 898 rtstatus = false; 899 } 900 901 if (!rtstatus) { 902 pr_err("Write BB Reg Fail!!\n"); 903 goto phy_bb8190_config_parafile_fail; 904 } 905 906 /* 2. If EEPROM or EFUSE autoload OK, We must config by 907 * PHY_REG_PG.txt */ 908 if (rtlefuse->autoload_failflag == false) { 909 rtlphy->pwrgroup_cnt = 0; 910 911 rtstatus = _rtl92s_phy_config_bb_with_pg(hw, 912 BASEBAND_CONFIG_PHY_REG); 913 } 914 if (!rtstatus) { 915 pr_err("_rtl92s_phy_bb_config_parafile(): BB_PG Reg Fail!!\n"); 916 goto phy_bb8190_config_parafile_fail; 917 } 918 919 /* 3. BB AGC table Initialization */ 920 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_AGC_TAB); 921 922 if (!rtstatus) { 923 pr_err("%s(): AGC Table Fail\n", __func__); 924 goto phy_bb8190_config_parafile_fail; 925 } 926 927 /* Check if the CCK HighPower is turned ON. */ 928 /* This is used to calculate PWDB. */ 929 rtlphy->cck_high_power = (bool)(rtl92s_phy_query_bb_reg(hw, 930 RFPGA0_XA_HSSIPARAMETER2, 0x200)); 931 932phy_bb8190_config_parafile_fail: 933 return rtstatus; 934} 935 936u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath) 937{ 938 struct rtl_priv *rtlpriv = rtl_priv(hw); 939 struct rtl_phy *rtlphy = &(rtlpriv->phy); 940 int i; 941 bool rtstatus = true; 942 u32 *radio_a_table; 943 u32 *radio_b_table; 944 u16 radio_a_tblen, radio_b_tblen; 945 946 radio_a_tblen = RADIOA_1T_ARRAYLENGTH; 947 radio_a_table = rtl8192seradioa_1t_array; 948 949 /* Using Green mode array table for RF_2T2R_GREEN */ 950 if (rtlphy->rf_type == RF_2T2R_GREEN) { 951 radio_b_table = rtl8192seradiob_gm_array; 952 radio_b_tblen = RADIOB_GM_ARRAYLENGTH; 953 } else { 954 radio_b_table = rtl8192seradiob_array; 955 radio_b_tblen = RADIOB_ARRAYLENGTH; 956 } 957 958 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath); 959 rtstatus = true; 960 961 switch (rfpath) { 962 case RF90_PATH_A: 963 for (i = 0; i < radio_a_tblen; i = i + 2) { 964 rtl_rfreg_delay(hw, rfpath, radio_a_table[i], 965 MASK20BITS, radio_a_table[i + 1]); 966 967 } 968 969 /* PA Bias current for inferiority IC */ 970 _rtl92s_phy_config_rfpa_bias_current(hw, rfpath); 971 break; 972 case RF90_PATH_B: 973 for (i = 0; i < radio_b_tblen; i = i + 2) { 974 rtl_rfreg_delay(hw, rfpath, radio_b_table[i], 975 MASK20BITS, radio_b_table[i + 1]); 976 } 977 break; 978 case RF90_PATH_C: 979 ; 980 break; 981 case RF90_PATH_D: 982 ; 983 break; 984 default: 985 break; 986 } 987 988 return rtstatus; 989} 990 991 992bool rtl92s_phy_mac_config(struct ieee80211_hw *hw) 993{ 994 struct rtl_priv *rtlpriv = rtl_priv(hw); 995 u32 i; 996 u32 arraylength; 997 u32 *ptrarray; 998 999 arraylength = MAC_2T_ARRAYLENGTH; 1000 ptrarray = rtl8192semac_2t_array; 1001 1002 for (i = 0; i < arraylength; i = i + 2) 1003 rtl_write_byte(rtlpriv, ptrarray[i], (u8)ptrarray[i + 1]); 1004 1005 return true; 1006} 1007 1008 1009bool rtl92s_phy_bb_config(struct ieee80211_hw *hw) 1010{ 1011 struct rtl_priv *rtlpriv = rtl_priv(hw); 1012 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1013 bool rtstatus = true; 1014 u8 pathmap, index, rf_num = 0; 1015 u8 path1, path2; 1016 1017 _rtl92s_phy_init_register_definition(hw); 1018 1019 /* Config BB and AGC */ 1020 rtstatus = _rtl92s_phy_bb_config_parafile(hw); 1021 1022 1023 /* Check BB/RF confiuration setting. */ 1024 /* We only need to configure RF which is turned on. */ 1025 path1 = (u8)(rtl92s_phy_query_bb_reg(hw, RFPGA0_TXINFO, 0xf)); 1026 mdelay(10); 1027 path2 = (u8)(rtl92s_phy_query_bb_reg(hw, ROFDM0_TRXPATHENABLE, 0xf)); 1028 pathmap = path1 | path2; 1029 1030 rtlphy->rf_pathmap = pathmap; 1031 for (index = 0; index < 4; index++) { 1032 if ((pathmap >> index) & 0x1) 1033 rf_num++; 1034 } 1035 1036 if ((rtlphy->rf_type == RF_1T1R && rf_num != 1) || 1037 (rtlphy->rf_type == RF_1T2R && rf_num != 2) || 1038 (rtlphy->rf_type == RF_2T2R && rf_num != 2) || 1039 (rtlphy->rf_type == RF_2T2R_GREEN && rf_num != 2)) { 1040 pr_err("RF_Type(%x) does not match RF_Num(%x)!!\n", 1041 rtlphy->rf_type, rf_num); 1042 pr_err("path1 0x%x, path2 0x%x, pathmap 0x%x\n", 1043 path1, path2, pathmap); 1044 } 1045 1046 return rtstatus; 1047} 1048 1049bool rtl92s_phy_rf_config(struct ieee80211_hw *hw) 1050{ 1051 struct rtl_priv *rtlpriv = rtl_priv(hw); 1052 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1053 1054 /* Initialize general global value */ 1055 if (rtlphy->rf_type == RF_1T1R) 1056 rtlphy->num_total_rfpath = 1; 1057 else 1058 rtlphy->num_total_rfpath = 2; 1059 1060 /* Config BB and RF */ 1061 return rtl92s_phy_rf6052_config(hw); 1062} 1063 1064void rtl92s_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) 1065{ 1066 struct rtl_priv *rtlpriv = rtl_priv(hw); 1067 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1068 1069 /* read rx initial gain */ 1070 rtlphy->default_initialgain[0] = rtl_get_bbreg(hw, 1071 ROFDM0_XAAGCCORE1, MASKBYTE0); 1072 rtlphy->default_initialgain[1] = rtl_get_bbreg(hw, 1073 ROFDM0_XBAGCCORE1, MASKBYTE0); 1074 rtlphy->default_initialgain[2] = rtl_get_bbreg(hw, 1075 ROFDM0_XCAGCCORE1, MASKBYTE0); 1076 rtlphy->default_initialgain[3] = rtl_get_bbreg(hw, 1077 ROFDM0_XDAGCCORE1, MASKBYTE0); 1078 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1079 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n", 1080 rtlphy->default_initialgain[0], 1081 rtlphy->default_initialgain[1], 1082 rtlphy->default_initialgain[2], 1083 rtlphy->default_initialgain[3]); 1084 1085 /* read framesync */ 1086 rtlphy->framesync = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, MASKBYTE0); 1087 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, 1088 MASKDWORD); 1089 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1090 "Default framesync (0x%x) = 0x%x\n", 1091 ROFDM0_RXDETECTOR3, rtlphy->framesync); 1092 1093} 1094 1095static void _rtl92s_phy_get_txpower_index(struct ieee80211_hw *hw, u8 channel, 1096 u8 *cckpowerlevel, u8 *ofdmpowerlevel) 1097{ 1098 struct rtl_priv *rtlpriv = rtl_priv(hw); 1099 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1100 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1101 u8 index = (channel - 1); 1102 1103 /* 1. CCK */ 1104 /* RF-A */ 1105 cckpowerlevel[0] = rtlefuse->txpwrlevel_cck[0][index]; 1106 /* RF-B */ 1107 cckpowerlevel[1] = rtlefuse->txpwrlevel_cck[1][index]; 1108 1109 /* 2. OFDM for 1T or 2T */ 1110 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) { 1111 /* Read HT 40 OFDM TX power */ 1112 ofdmpowerlevel[0] = rtlefuse->txpwrlevel_ht40_1s[0][index]; 1113 ofdmpowerlevel[1] = rtlefuse->txpwrlevel_ht40_1s[1][index]; 1114 } else if (rtlphy->rf_type == RF_2T2R) { 1115 /* Read HT 40 OFDM TX power */ 1116 ofdmpowerlevel[0] = rtlefuse->txpwrlevel_ht40_2s[0][index]; 1117 ofdmpowerlevel[1] = rtlefuse->txpwrlevel_ht40_2s[1][index]; 1118 } else { 1119 ofdmpowerlevel[0] = 0; 1120 ofdmpowerlevel[1] = 0; 1121 } 1122} 1123 1124static void _rtl92s_phy_ccxpower_indexcheck(struct ieee80211_hw *hw, 1125 u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel) 1126{ 1127 struct rtl_priv *rtlpriv = rtl_priv(hw); 1128 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1129 1130 rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; 1131 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; 1132} 1133 1134void rtl92s_phy_set_txpower(struct ieee80211_hw *hw, u8 channel) 1135{ 1136 struct rtl_priv *rtlpriv = rtl_priv(hw); 1137 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1138 /* [0]:RF-A, [1]:RF-B */ 1139 u8 cckpowerlevel[2], ofdmpowerlevel[2]; 1140 1141 if (!rtlefuse->txpwr_fromeprom) 1142 return; 1143 1144 /* Mainly we use RF-A Tx Power to write the Tx Power registers, 1145 * but the RF-B Tx Power must be calculated by the antenna diff. 1146 * So we have to rewrite Antenna gain offset register here. 1147 * Please refer to BB register 0x80c 1148 * 1. For CCK. 1149 * 2. For OFDM 1T or 2T */ 1150 _rtl92s_phy_get_txpower_index(hw, channel, &cckpowerlevel[0], 1151 &ofdmpowerlevel[0]); 1152 1153 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 1154 "Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n", 1155 channel, cckpowerlevel[0], cckpowerlevel[1], 1156 ofdmpowerlevel[0], ofdmpowerlevel[1]); 1157 1158 _rtl92s_phy_ccxpower_indexcheck(hw, channel, &cckpowerlevel[0], 1159 &ofdmpowerlevel[0]); 1160 1161 rtl92s_phy_rf6052_set_ccktxpower(hw, cckpowerlevel[0]); 1162 rtl92s_phy_rf6052_set_ofdmtxpower(hw, &ofdmpowerlevel[0], channel); 1163 1164} 1165 1166void rtl92s_phy_chk_fwcmd_iodone(struct ieee80211_hw *hw) 1167{ 1168 struct rtl_priv *rtlpriv = rtl_priv(hw); 1169 u16 pollingcnt = 10000; 1170 u32 tmpvalue; 1171 1172 /* Make sure that CMD IO has be accepted by FW. */ 1173 do { 1174 udelay(10); 1175 1176 tmpvalue = rtl_read_dword(rtlpriv, WFM5); 1177 if (tmpvalue == 0) 1178 break; 1179 } while (--pollingcnt); 1180 1181 if (pollingcnt == 0) 1182 pr_err("Set FW Cmd fail!!\n"); 1183} 1184 1185 1186static void _rtl92s_phy_set_fwcmd_io(struct ieee80211_hw *hw) 1187{ 1188 struct rtl_priv *rtlpriv = rtl_priv(hw); 1189 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1190 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1191 u32 input, current_aid = 0; 1192 1193 if (is_hal_stop(rtlhal)) 1194 return; 1195 1196 if (hal_get_firmwareversion(rtlpriv) < 0x34) 1197 goto skip; 1198 /* We re-map RA related CMD IO to combinational ones */ 1199 /* if FW version is v.52 or later. */ 1200 switch (rtlhal->current_fwcmd_io) { 1201 case FW_CMD_RA_REFRESH_N: 1202 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_N_COMB; 1203 break; 1204 case FW_CMD_RA_REFRESH_BG: 1205 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_BG_COMB; 1206 break; 1207 default: 1208 break; 1209 } 1210 1211skip: 1212 switch (rtlhal->current_fwcmd_io) { 1213 case FW_CMD_RA_RESET: 1214 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_RESET\n"); 1215 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET); 1216 rtl92s_phy_chk_fwcmd_iodone(hw); 1217 break; 1218 case FW_CMD_RA_ACTIVE: 1219 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_ACTIVE\n"); 1220 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE); 1221 rtl92s_phy_chk_fwcmd_iodone(hw); 1222 break; 1223 case FW_CMD_RA_REFRESH_N: 1224 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_REFRESH_N\n"); 1225 input = FW_RA_REFRESH; 1226 rtl_write_dword(rtlpriv, WFM5, input); 1227 rtl92s_phy_chk_fwcmd_iodone(hw); 1228 rtl_write_dword(rtlpriv, WFM5, FW_RA_ENABLE_RSSI_MASK); 1229 rtl92s_phy_chk_fwcmd_iodone(hw); 1230 break; 1231 case FW_CMD_RA_REFRESH_BG: 1232 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, 1233 "FW_CMD_RA_REFRESH_BG\n"); 1234 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH); 1235 rtl92s_phy_chk_fwcmd_iodone(hw); 1236 rtl_write_dword(rtlpriv, WFM5, FW_RA_DISABLE_RSSI_MASK); 1237 rtl92s_phy_chk_fwcmd_iodone(hw); 1238 break; 1239 case FW_CMD_RA_REFRESH_N_COMB: 1240 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, 1241 "FW_CMD_RA_REFRESH_N_COMB\n"); 1242 input = FW_RA_IOT_N_COMB; 1243 rtl_write_dword(rtlpriv, WFM5, input); 1244 rtl92s_phy_chk_fwcmd_iodone(hw); 1245 break; 1246 case FW_CMD_RA_REFRESH_BG_COMB: 1247 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, 1248 "FW_CMD_RA_REFRESH_BG_COMB\n"); 1249 input = FW_RA_IOT_BG_COMB; 1250 rtl_write_dword(rtlpriv, WFM5, input); 1251 rtl92s_phy_chk_fwcmd_iodone(hw); 1252 break; 1253 case FW_CMD_IQK_ENABLE: 1254 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_IQK_ENABLE\n"); 1255 rtl_write_dword(rtlpriv, WFM5, FW_IQK_ENABLE); 1256 rtl92s_phy_chk_fwcmd_iodone(hw); 1257 break; 1258 case FW_CMD_PAUSE_DM_BY_SCAN: 1259 /* Lower initial gain */ 1260 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17); 1261 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17); 1262 /* CCA threshold */ 1263 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40); 1264 break; 1265 case FW_CMD_RESUME_DM_BY_SCAN: 1266 /* CCA threshold */ 1267 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd); 1268 rtl92s_phy_set_txpower(hw, rtlphy->current_channel); 1269 break; 1270 case FW_CMD_HIGH_PWR_DISABLE: 1271 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) 1272 break; 1273 1274 /* Lower initial gain */ 1275 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17); 1276 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17); 1277 /* CCA threshold */ 1278 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40); 1279 break; 1280 case FW_CMD_HIGH_PWR_ENABLE: 1281 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) || 1282 rtlpriv->dm.dynamic_txpower_enable) 1283 break; 1284 1285 /* CCA threshold */ 1286 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd); 1287 break; 1288 case FW_CMD_LPS_ENTER: 1289 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_ENTER\n"); 1290 current_aid = rtlpriv->mac80211.assoc_id; 1291 rtl_write_dword(rtlpriv, WFM5, (FW_LPS_ENTER | 1292 ((current_aid | 0xc000) << 8))); 1293 rtl92s_phy_chk_fwcmd_iodone(hw); 1294 /* FW set TXOP disable here, so disable EDCA 1295 * turbo mode until driver leave LPS */ 1296 break; 1297 case FW_CMD_LPS_LEAVE: 1298 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_LEAVE\n"); 1299 rtl_write_dword(rtlpriv, WFM5, FW_LPS_LEAVE); 1300 rtl92s_phy_chk_fwcmd_iodone(hw); 1301 break; 1302 case FW_CMD_ADD_A2_ENTRY: 1303 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_ADD_A2_ENTRY\n"); 1304 rtl_write_dword(rtlpriv, WFM5, FW_ADD_A2_ENTRY); 1305 rtl92s_phy_chk_fwcmd_iodone(hw); 1306 break; 1307 case FW_CMD_CTRL_DM_BY_DRIVER: 1308 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, 1309 "FW_CMD_CTRL_DM_BY_DRIVER\n"); 1310 rtl_write_dword(rtlpriv, WFM5, FW_CTRL_DM_BY_DRIVER); 1311 rtl92s_phy_chk_fwcmd_iodone(hw); 1312 break; 1313 1314 default: 1315 break; 1316 } 1317 1318 rtl92s_phy_chk_fwcmd_iodone(hw); 1319 1320 /* Clear FW CMD operation flag. */ 1321 rtlhal->set_fwcmd_inprogress = false; 1322} 1323 1324bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fw_cmdio) 1325{ 1326 struct rtl_priv *rtlpriv = rtl_priv(hw); 1327 struct dig_t *digtable = &rtlpriv->dm_digtable; 1328 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1329 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1330 u32 fw_param = FW_CMD_IO_PARA_QUERY(rtlpriv); 1331 u16 fw_cmdmap = FW_CMD_IO_QUERY(rtlpriv); 1332 bool postprocessing = false; 1333 1334 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, 1335 "Set FW Cmd(%#x), set_fwcmd_inprogress(%d)\n", 1336 fw_cmdio, rtlhal->set_fwcmd_inprogress); 1337 1338 do { 1339 /* We re-map to combined FW CMD ones if firmware version */ 1340 /* is v.53 or later. */ 1341 if (hal_get_firmwareversion(rtlpriv) >= 0x35) { 1342 switch (fw_cmdio) { 1343 case FW_CMD_RA_REFRESH_N: 1344 fw_cmdio = FW_CMD_RA_REFRESH_N_COMB; 1345 break; 1346 case FW_CMD_RA_REFRESH_BG: 1347 fw_cmdio = FW_CMD_RA_REFRESH_BG_COMB; 1348 break; 1349 default: 1350 break; 1351 } 1352 } else { 1353 if ((fw_cmdio == FW_CMD_IQK_ENABLE) || 1354 (fw_cmdio == FW_CMD_RA_REFRESH_N) || 1355 (fw_cmdio == FW_CMD_RA_REFRESH_BG)) { 1356 postprocessing = true; 1357 break; 1358 } 1359 } 1360 1361 /* If firmware version is v.62 or later, 1362 * use FW_CMD_IO_SET for FW_CMD_CTRL_DM_BY_DRIVER */ 1363 if (hal_get_firmwareversion(rtlpriv) >= 0x3E) { 1364 if (fw_cmdio == FW_CMD_CTRL_DM_BY_DRIVER) 1365 fw_cmdio = FW_CMD_CTRL_DM_BY_DRIVER_NEW; 1366 } 1367 1368 1369 /* We shall revise all FW Cmd IO into Reg0x364 1370 * DM map table in the future. */ 1371 switch (fw_cmdio) { 1372 case FW_CMD_RA_INIT: 1373 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "RA init!!\n"); 1374 fw_cmdmap |= FW_RA_INIT_CTL; 1375 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1376 /* Clear control flag to sync with FW. */ 1377 FW_CMD_IO_CLR(rtlpriv, FW_RA_INIT_CTL); 1378 break; 1379 case FW_CMD_DIG_DISABLE: 1380 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, 1381 "Set DIG disable!!\n"); 1382 fw_cmdmap &= ~FW_DIG_ENABLE_CTL; 1383 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1384 break; 1385 case FW_CMD_DIG_ENABLE: 1386 case FW_CMD_DIG_RESUME: 1387 if (!(rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE)) { 1388 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, 1389 "Set DIG enable or resume!!\n"); 1390 fw_cmdmap |= (FW_DIG_ENABLE_CTL | FW_SS_CTL); 1391 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1392 } 1393 break; 1394 case FW_CMD_DIG_HALT: 1395 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, 1396 "Set DIG halt!!\n"); 1397 fw_cmdmap &= ~(FW_DIG_ENABLE_CTL | FW_SS_CTL); 1398 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1399 break; 1400 case FW_CMD_TXPWR_TRACK_THERMAL: { 1401 u8 thermalval = 0; 1402 fw_cmdmap |= FW_PWR_TRK_CTL; 1403 1404 /* Clear FW parameter in terms of thermal parts. */ 1405 fw_param &= FW_PWR_TRK_PARAM_CLR; 1406 1407 thermalval = rtlpriv->dm.thermalvalue; 1408 fw_param |= ((thermalval << 24) | 1409 (rtlefuse->thermalmeter[0] << 16)); 1410 1411 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, 1412 "Set TxPwr tracking!! FwCmdMap(%#x), FwParam(%#x)\n", 1413 fw_cmdmap, fw_param); 1414 1415 FW_CMD_PARA_SET(rtlpriv, fw_param); 1416 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1417 1418 /* Clear control flag to sync with FW. */ 1419 FW_CMD_IO_CLR(rtlpriv, FW_PWR_TRK_CTL); 1420 } 1421 break; 1422 /* The following FW CMDs are only compatible to 1423 * v.53 or later. */ 1424 case FW_CMD_RA_REFRESH_N_COMB: 1425 fw_cmdmap |= FW_RA_N_CTL; 1426 1427 /* Clear RA BG mode control. */ 1428 fw_cmdmap &= ~(FW_RA_BG_CTL | FW_RA_INIT_CTL); 1429 1430 /* Clear FW parameter in terms of RA parts. */ 1431 fw_param &= FW_RA_PARAM_CLR; 1432 1433 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, 1434 "[FW CMD] [New Version] Set RA/IOT Comb in n mode!! FwCmdMap(%#x), FwParam(%#x)\n", 1435 fw_cmdmap, fw_param); 1436 1437 FW_CMD_PARA_SET(rtlpriv, fw_param); 1438 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1439 1440 /* Clear control flag to sync with FW. */ 1441 FW_CMD_IO_CLR(rtlpriv, FW_RA_N_CTL); 1442 break; 1443 case FW_CMD_RA_REFRESH_BG_COMB: 1444 fw_cmdmap |= FW_RA_BG_CTL; 1445 1446 /* Clear RA n-mode control. */ 1447 fw_cmdmap &= ~(FW_RA_N_CTL | FW_RA_INIT_CTL); 1448 /* Clear FW parameter in terms of RA parts. */ 1449 fw_param &= FW_RA_PARAM_CLR; 1450 1451 FW_CMD_PARA_SET(rtlpriv, fw_param); 1452 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1453 1454 /* Clear control flag to sync with FW. */ 1455 FW_CMD_IO_CLR(rtlpriv, FW_RA_BG_CTL); 1456 break; 1457 case FW_CMD_IQK_ENABLE: 1458 fw_cmdmap |= FW_IQK_CTL; 1459 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1460 /* Clear control flag to sync with FW. */ 1461 FW_CMD_IO_CLR(rtlpriv, FW_IQK_CTL); 1462 break; 1463 /* The following FW CMD is compatible to v.62 or later. */ 1464 case FW_CMD_CTRL_DM_BY_DRIVER_NEW: 1465 fw_cmdmap |= FW_DRIVER_CTRL_DM_CTL; 1466 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1467 break; 1468 /* The followed FW Cmds needs post-processing later. */ 1469 case FW_CMD_RESUME_DM_BY_SCAN: 1470 fw_cmdmap |= (FW_DIG_ENABLE_CTL | 1471 FW_HIGH_PWR_ENABLE_CTL | 1472 FW_SS_CTL); 1473 1474 if (rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE || 1475 !digtable->dig_enable_flag) 1476 fw_cmdmap &= ~FW_DIG_ENABLE_CTL; 1477 1478 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) || 1479 rtlpriv->dm.dynamic_txpower_enable) 1480 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL; 1481 1482 if ((digtable->dig_ext_port_stage == 1483 DIG_EXT_PORT_STAGE_0) || 1484 (digtable->dig_ext_port_stage == 1485 DIG_EXT_PORT_STAGE_1)) 1486 fw_cmdmap &= ~FW_DIG_ENABLE_CTL; 1487 1488 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1489 postprocessing = true; 1490 break; 1491 case FW_CMD_PAUSE_DM_BY_SCAN: 1492 fw_cmdmap &= ~(FW_DIG_ENABLE_CTL | 1493 FW_HIGH_PWR_ENABLE_CTL | 1494 FW_SS_CTL); 1495 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1496 postprocessing = true; 1497 break; 1498 case FW_CMD_HIGH_PWR_DISABLE: 1499 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL; 1500 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1501 postprocessing = true; 1502 break; 1503 case FW_CMD_HIGH_PWR_ENABLE: 1504 if (!(rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) && 1505 !rtlpriv->dm.dynamic_txpower_enable) { 1506 fw_cmdmap |= (FW_HIGH_PWR_ENABLE_CTL | 1507 FW_SS_CTL); 1508 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1509 postprocessing = true; 1510 } 1511 break; 1512 case FW_CMD_DIG_MODE_FA: 1513 fw_cmdmap |= FW_FA_CTL; 1514 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1515 break; 1516 case FW_CMD_DIG_MODE_SS: 1517 fw_cmdmap &= ~FW_FA_CTL; 1518 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1519 break; 1520 case FW_CMD_PAPE_CONTROL: 1521 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, 1522 "[FW CMD] Set PAPE Control\n"); 1523 fw_cmdmap &= ~FW_PAPE_CTL_BY_SW_HW; 1524 1525 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1526 break; 1527 default: 1528 /* Pass to original FW CMD processing callback 1529 * routine. */ 1530 postprocessing = true; 1531 break; 1532 } 1533 } while (false); 1534 1535 /* We shall post processing these FW CMD if 1536 * variable postprocessing is set. 1537 */ 1538 if (postprocessing && !rtlhal->set_fwcmd_inprogress) { 1539 rtlhal->set_fwcmd_inprogress = true; 1540 /* Update current FW Cmd for callback use. */ 1541 rtlhal->current_fwcmd_io = fw_cmdio; 1542 } else { 1543 return false; 1544 } 1545 1546 _rtl92s_phy_set_fwcmd_io(hw); 1547 return true; 1548} 1549 1550static void _rtl92s_phy_check_ephy_switchready(struct ieee80211_hw *hw) 1551{ 1552 struct rtl_priv *rtlpriv = rtl_priv(hw); 1553 u32 delay = 100; 1554 u8 regu1; 1555 1556 regu1 = rtl_read_byte(rtlpriv, 0x554); 1557 while ((regu1 & BIT(5)) && (delay > 0)) { 1558 regu1 = rtl_read_byte(rtlpriv, 0x554); 1559 delay--; 1560 /* We delay only 50us to prevent 1561 * being scheduled out. */ 1562 udelay(50); 1563 } 1564} 1565 1566void rtl92s_phy_switch_ephy_parameter(struct ieee80211_hw *hw) 1567{ 1568 struct rtl_priv *rtlpriv = rtl_priv(hw); 1569 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1570 1571 /* The way to be capable to switch clock request 1572 * when the PG setting does not support clock request. 1573 * This is the backdoor solution to switch clock 1574 * request before ASPM or D3. */ 1575 rtl_write_dword(rtlpriv, 0x540, 0x73c11); 1576 rtl_write_dword(rtlpriv, 0x548, 0x2407c); 1577 1578 /* Switch EPHY parameter!!!! */ 1579 rtl_write_word(rtlpriv, 0x550, 0x1000); 1580 rtl_write_byte(rtlpriv, 0x554, 0x20); 1581 _rtl92s_phy_check_ephy_switchready(hw); 1582 1583 rtl_write_word(rtlpriv, 0x550, 0xa0eb); 1584 rtl_write_byte(rtlpriv, 0x554, 0x3e); 1585 _rtl92s_phy_check_ephy_switchready(hw); 1586 1587 rtl_write_word(rtlpriv, 0x550, 0xff80); 1588 rtl_write_byte(rtlpriv, 0x554, 0x39); 1589 _rtl92s_phy_check_ephy_switchready(hw); 1590 1591 /* Delay L1 enter time */ 1592 if (ppsc->support_aspm && !ppsc->support_backdoor) 1593 rtl_write_byte(rtlpriv, 0x560, 0x40); 1594 else 1595 rtl_write_byte(rtlpriv, 0x560, 0x00); 1596 1597} 1598 1599void rtl92s_phy_set_beacon_hwreg(struct ieee80211_hw *hw, u16 beaconinterval) 1600{ 1601 struct rtl_priv *rtlpriv = rtl_priv(hw); 1602 u32 new_bcn_num = 0; 1603 1604 if (hal_get_firmwareversion(rtlpriv) >= 0x33) { 1605 /* Fw v.51 and later. */ 1606 rtl_write_dword(rtlpriv, WFM5, 0xF1000000 | 1607 (beaconinterval << 8)); 1608 } else { 1609 new_bcn_num = beaconinterval * 32 - 64; 1610 rtl_write_dword(rtlpriv, WFM3 + 4, new_bcn_num); 1611 rtl_write_dword(rtlpriv, WFM3, 0xB026007C); 1612 } 1613} 1614