1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4#include "../wifi.h" 5#include "../base.h" 6#include "../core.h" 7#include "reg.h" 8#include "def.h" 9#include "phy.h" 10#include "dm.h" 11#include "fw.h" 12 13#define UNDEC_SM_PWDB entry_min_undec_sm_pwdb 14 15static const u32 ofdmswing_table[OFDM_TABLE_SIZE_92D] = { 16 0x7f8001fe, /* 0, +6.0dB */ 17 0x788001e2, /* 1, +5.5dB */ 18 0x71c001c7, /* 2, +5.0dB */ 19 0x6b8001ae, /* 3, +4.5dB */ 20 0x65400195, /* 4, +4.0dB */ 21 0x5fc0017f, /* 5, +3.5dB */ 22 0x5a400169, /* 6, +3.0dB */ 23 0x55400155, /* 7, +2.5dB */ 24 0x50800142, /* 8, +2.0dB */ 25 0x4c000130, /* 9, +1.5dB */ 26 0x47c0011f, /* 10, +1.0dB */ 27 0x43c0010f, /* 11, +0.5dB */ 28 0x40000100, /* 12, +0dB */ 29 0x3c8000f2, /* 13, -0.5dB */ 30 0x390000e4, /* 14, -1.0dB */ 31 0x35c000d7, /* 15, -1.5dB */ 32 0x32c000cb, /* 16, -2.0dB */ 33 0x300000c0, /* 17, -2.5dB */ 34 0x2d4000b5, /* 18, -3.0dB */ 35 0x2ac000ab, /* 19, -3.5dB */ 36 0x288000a2, /* 20, -4.0dB */ 37 0x26000098, /* 21, -4.5dB */ 38 0x24000090, /* 22, -5.0dB */ 39 0x22000088, /* 23, -5.5dB */ 40 0x20000080, /* 24, -6.0dB */ 41 0x1e400079, /* 25, -6.5dB */ 42 0x1c800072, /* 26, -7.0dB */ 43 0x1b00006c, /* 27. -7.5dB */ 44 0x19800066, /* 28, -8.0dB */ 45 0x18000060, /* 29, -8.5dB */ 46 0x16c0005b, /* 30, -9.0dB */ 47 0x15800056, /* 31, -9.5dB */ 48 0x14400051, /* 32, -10.0dB */ 49 0x1300004c, /* 33, -10.5dB */ 50 0x12000048, /* 34, -11.0dB */ 51 0x11000044, /* 35, -11.5dB */ 52 0x10000040, /* 36, -12.0dB */ 53 0x0f00003c, /* 37, -12.5dB */ 54 0x0e400039, /* 38, -13.0dB */ 55 0x0d800036, /* 39, -13.5dB */ 56 0x0cc00033, /* 40, -14.0dB */ 57 0x0c000030, /* 41, -14.5dB */ 58 0x0b40002d, /* 42, -15.0dB */ 59}; 60 61static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = { 62 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ 63 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ 64 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */ 65 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */ 66 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ 67 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */ 68 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */ 69 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */ 70 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ 71 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */ 72 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ 73 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */ 74 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */ 75 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */ 76 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ 77 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */ 78 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ 79 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */ 80 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ 81 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */ 82 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */ 83 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */ 84 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */ 85 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */ 86 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */ 87 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */ 88 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */ 89 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */ 90 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */ 91 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */ 92 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */ 93 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */ 94 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */ 95}; 96 97static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = { 98 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */ 99 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */ 100 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */ 101 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */ 102 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */ 103 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */ 104 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */ 105 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */ 106 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */ 107 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */ 108 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */ 109 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */ 110 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */ 111 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */ 112 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */ 113 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */ 114 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ 115 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */ 116 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */ 117 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */ 118 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */ 119 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */ 120 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */ 121 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */ 122 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */ 123 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */ 124 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */ 125 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */ 126 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */ 127 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */ 128 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */ 129 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */ 130 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */ 131}; 132 133static void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) 134{ 135 u32 ret_value; 136 struct rtl_priv *rtlpriv = rtl_priv(hw); 137 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt); 138 unsigned long flag = 0; 139 140 /* hold ofdm counter */ 141 rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 1); /* hold page C counter */ 142 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1); /*hold page D counter */ 143 144 ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD); 145 falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff); 146 falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16); 147 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD); 148 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16); 149 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD); 150 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff); 151 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16); 152 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD); 153 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff); 154 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail + 155 falsealm_cnt->cnt_rate_illegal + 156 falsealm_cnt->cnt_crc8_fail + 157 falsealm_cnt->cnt_mcs_fail + 158 falsealm_cnt->cnt_fast_fsync_fail + 159 falsealm_cnt->cnt_sb_search_fail; 160 161 if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) { 162 /* hold cck counter */ 163 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); 164 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0); 165 falsealm_cnt->cnt_cck_fail = ret_value; 166 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3); 167 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8; 168 rtl92d_release_cckandrw_pagea_ctl(hw, &flag); 169 } else { 170 falsealm_cnt->cnt_cck_fail = 0; 171 } 172 173 /* reset false alarm counter registers */ 174 falsealm_cnt->cnt_all = falsealm_cnt->cnt_fast_fsync_fail + 175 falsealm_cnt->cnt_sb_search_fail + 176 falsealm_cnt->cnt_parity_fail + 177 falsealm_cnt->cnt_rate_illegal + 178 falsealm_cnt->cnt_crc8_fail + 179 falsealm_cnt->cnt_mcs_fail + 180 falsealm_cnt->cnt_cck_fail; 181 182 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1); 183 /* update ofdm counter */ 184 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0); 185 /* update page C counter */ 186 rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 0); 187 /* update page D counter */ 188 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 0); 189 if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) { 190 /* reset cck counter */ 191 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); 192 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0); 193 /* enable cck counter */ 194 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2); 195 rtl92d_release_cckandrw_pagea_ctl(hw, &flag); 196 } 197 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, 198 "Cnt_Fast_Fsync_fail = %x, Cnt_SB_Search_fail = %x\n", 199 falsealm_cnt->cnt_fast_fsync_fail, 200 falsealm_cnt->cnt_sb_search_fail); 201 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, 202 "Cnt_Parity_Fail = %x, Cnt_Rate_Illegal = %x, Cnt_Crc8_fail = %x, Cnt_Mcs_fail = %x\n", 203 falsealm_cnt->cnt_parity_fail, 204 falsealm_cnt->cnt_rate_illegal, 205 falsealm_cnt->cnt_crc8_fail, 206 falsealm_cnt->cnt_mcs_fail); 207 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, 208 "Cnt_Ofdm_fail = %x, Cnt_Cck_fail = %x, Cnt_all = %x\n", 209 falsealm_cnt->cnt_ofdm_fail, 210 falsealm_cnt->cnt_cck_fail, 211 falsealm_cnt->cnt_all); 212} 213 214static void rtl92d_dm_find_minimum_rssi(struct ieee80211_hw *hw) 215{ 216 struct rtl_priv *rtlpriv = rtl_priv(hw); 217 struct dig_t *de_digtable = &rtlpriv->dm_digtable; 218 struct rtl_mac *mac = rtl_mac(rtlpriv); 219 220 /* Determine the minimum RSSI */ 221 if ((mac->link_state < MAC80211_LINKED) && 222 (rtlpriv->dm.UNDEC_SM_PWDB == 0)) { 223 de_digtable->min_undec_pwdb_for_dm = 0; 224 rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, 225 "Not connected to any\n"); 226 } 227 if (mac->link_state >= MAC80211_LINKED) { 228 if (mac->opmode == NL80211_IFTYPE_AP || 229 mac->opmode == NL80211_IFTYPE_ADHOC) { 230 de_digtable->min_undec_pwdb_for_dm = 231 rtlpriv->dm.UNDEC_SM_PWDB; 232 rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, 233 "AP Client PWDB = 0x%lx\n", 234 rtlpriv->dm.UNDEC_SM_PWDB); 235 } else { 236 de_digtable->min_undec_pwdb_for_dm = 237 rtlpriv->dm.undec_sm_pwdb; 238 rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, 239 "STA Default Port PWDB = 0x%x\n", 240 de_digtable->min_undec_pwdb_for_dm); 241 } 242 } else { 243 de_digtable->min_undec_pwdb_for_dm = rtlpriv->dm.UNDEC_SM_PWDB; 244 rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, 245 "AP Ext Port or disconnect PWDB = 0x%x\n", 246 de_digtable->min_undec_pwdb_for_dm); 247 } 248 249 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "MinUndecoratedPWDBForDM =%d\n", 250 de_digtable->min_undec_pwdb_for_dm); 251} 252 253static void rtl92d_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw) 254{ 255 struct rtl_priv *rtlpriv = rtl_priv(hw); 256 struct dig_t *de_digtable = &rtlpriv->dm_digtable; 257 unsigned long flag = 0; 258 259 if (de_digtable->cursta_cstate == DIG_STA_CONNECT) { 260 if (de_digtable->pre_cck_pd_state == CCK_PD_STAGE_LOWRSSI) { 261 if (de_digtable->min_undec_pwdb_for_dm <= 25) 262 de_digtable->cur_cck_pd_state = 263 CCK_PD_STAGE_LOWRSSI; 264 else 265 de_digtable->cur_cck_pd_state = 266 CCK_PD_STAGE_HIGHRSSI; 267 } else { 268 if (de_digtable->min_undec_pwdb_for_dm <= 20) 269 de_digtable->cur_cck_pd_state = 270 CCK_PD_STAGE_LOWRSSI; 271 else 272 de_digtable->cur_cck_pd_state = 273 CCK_PD_STAGE_HIGHRSSI; 274 } 275 } else { 276 de_digtable->cur_cck_pd_state = CCK_PD_STAGE_LOWRSSI; 277 } 278 if (de_digtable->pre_cck_pd_state != de_digtable->cur_cck_pd_state) { 279 if (de_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI) { 280 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); 281 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x83); 282 rtl92d_release_cckandrw_pagea_ctl(hw, &flag); 283 } else { 284 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); 285 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd); 286 rtl92d_release_cckandrw_pagea_ctl(hw, &flag); 287 } 288 de_digtable->pre_cck_pd_state = de_digtable->cur_cck_pd_state; 289 } 290 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "CurSTAConnectState=%s\n", 291 de_digtable->cursta_cstate == DIG_STA_CONNECT ? 292 "DIG_STA_CONNECT " : "DIG_STA_DISCONNECT"); 293 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "CCKPDStage=%s\n", 294 de_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI ? 295 "Low RSSI " : "High RSSI "); 296 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "is92d single phy =%x\n", 297 IS_92D_SINGLEPHY(rtlpriv->rtlhal.version)); 298 299} 300 301void rtl92d_dm_write_dig(struct ieee80211_hw *hw) 302{ 303 struct rtl_priv *rtlpriv = rtl_priv(hw); 304 struct dig_t *de_digtable = &rtlpriv->dm_digtable; 305 306 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, 307 "cur_igvalue = 0x%x, pre_igvalue = 0x%x, back_val = %d\n", 308 de_digtable->cur_igvalue, de_digtable->pre_igvalue, 309 de_digtable->back_val); 310 if (de_digtable->dig_enable_flag == false) { 311 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "DIG is disabled\n"); 312 de_digtable->pre_igvalue = 0x17; 313 return; 314 } 315 if (de_digtable->pre_igvalue != de_digtable->cur_igvalue) { 316 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f, 317 de_digtable->cur_igvalue); 318 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f, 319 de_digtable->cur_igvalue); 320 de_digtable->pre_igvalue = de_digtable->cur_igvalue; 321 } 322} 323 324static void rtl92d_early_mode_enabled(struct rtl_priv *rtlpriv) 325{ 326 struct dig_t *de_digtable = &rtlpriv->dm_digtable; 327 328 if ((rtlpriv->mac80211.link_state >= MAC80211_LINKED) && 329 (rtlpriv->mac80211.vendor == PEER_CISCO)) { 330 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "IOT_PEER = CISCO\n"); 331 if (de_digtable->last_min_undec_pwdb_for_dm >= 50 332 && de_digtable->min_undec_pwdb_for_dm < 50) { 333 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x00); 334 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, 335 "Early Mode Off\n"); 336 } else if (de_digtable->last_min_undec_pwdb_for_dm <= 55 && 337 de_digtable->min_undec_pwdb_for_dm > 55) { 338 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x0f); 339 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, 340 "Early Mode On\n"); 341 } 342 } else if (!(rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL) & 0xf)) { 343 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x0f); 344 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "Early Mode On\n"); 345 } 346} 347 348static void rtl92d_dm_dig(struct ieee80211_hw *hw) 349{ 350 struct rtl_priv *rtlpriv = rtl_priv(hw); 351 struct dig_t *de_digtable = &rtlpriv->dm_digtable; 352 u8 value_igi = de_digtable->cur_igvalue; 353 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt); 354 355 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "==>\n"); 356 if (rtlpriv->rtlhal.earlymode_enable) { 357 rtl92d_early_mode_enabled(rtlpriv); 358 de_digtable->last_min_undec_pwdb_for_dm = 359 de_digtable->min_undec_pwdb_for_dm; 360 } 361 if (!rtlpriv->dm.dm_initialgain_enable) 362 return; 363 364 /* because we will send data pkt when scanning 365 * this will cause some ap like gear-3700 wep TP 366 * lower if we return here, this is the diff of 367 * mac80211 driver vs ieee80211 driver */ 368 /* if (rtlpriv->mac80211.act_scanning) 369 * return; */ 370 371 /* Not STA mode return tmp */ 372 if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION) 373 return; 374 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "progress\n"); 375 /* Decide the current status and if modify initial gain or not */ 376 if (rtlpriv->mac80211.link_state >= MAC80211_LINKED) 377 de_digtable->cursta_cstate = DIG_STA_CONNECT; 378 else 379 de_digtable->cursta_cstate = DIG_STA_DISCONNECT; 380 381 /* adjust initial gain according to false alarm counter */ 382 if (falsealm_cnt->cnt_all < DM_DIG_FA_TH0) 383 value_igi--; 384 else if (falsealm_cnt->cnt_all < DM_DIG_FA_TH1) 385 value_igi += 0; 386 else if (falsealm_cnt->cnt_all < DM_DIG_FA_TH2) 387 value_igi++; 388 else if (falsealm_cnt->cnt_all >= DM_DIG_FA_TH2) 389 value_igi += 2; 390 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, 391 "dm_DIG() Before: large_fa_hit=%d, forbidden_igi=%x\n", 392 de_digtable->large_fa_hit, de_digtable->forbidden_igi); 393 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, 394 "dm_DIG() Before: Recover_cnt=%d, rx_gain_min=%x\n", 395 de_digtable->recover_cnt, de_digtable->rx_gain_min); 396 397 /* deal with abnormally large false alarm */ 398 if (falsealm_cnt->cnt_all > 10000) { 399 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, 400 "dm_DIG(): Abnormally false alarm case\n"); 401 402 de_digtable->large_fa_hit++; 403 if (de_digtable->forbidden_igi < de_digtable->cur_igvalue) { 404 de_digtable->forbidden_igi = de_digtable->cur_igvalue; 405 de_digtable->large_fa_hit = 1; 406 } 407 if (de_digtable->large_fa_hit >= 3) { 408 if ((de_digtable->forbidden_igi + 1) > DM_DIG_MAX) 409 de_digtable->rx_gain_min = DM_DIG_MAX; 410 else 411 de_digtable->rx_gain_min = 412 (de_digtable->forbidden_igi + 1); 413 de_digtable->recover_cnt = 3600; /* 3600=2hr */ 414 } 415 } else { 416 /* Recovery mechanism for IGI lower bound */ 417 if (de_digtable->recover_cnt != 0) { 418 de_digtable->recover_cnt--; 419 } else { 420 if (de_digtable->large_fa_hit == 0) { 421 if ((de_digtable->forbidden_igi - 1) < 422 DM_DIG_FA_LOWER) { 423 de_digtable->forbidden_igi = 424 DM_DIG_FA_LOWER; 425 de_digtable->rx_gain_min = 426 DM_DIG_FA_LOWER; 427 428 } else { 429 de_digtable->forbidden_igi--; 430 de_digtable->rx_gain_min = 431 (de_digtable->forbidden_igi + 1); 432 } 433 } else if (de_digtable->large_fa_hit == 3) { 434 de_digtable->large_fa_hit = 0; 435 } 436 } 437 } 438 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, 439 "dm_DIG() After: large_fa_hit=%d, forbidden_igi=%x\n", 440 de_digtable->large_fa_hit, de_digtable->forbidden_igi); 441 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, 442 "dm_DIG() After: recover_cnt=%d, rx_gain_min=%x\n", 443 de_digtable->recover_cnt, de_digtable->rx_gain_min); 444 445 if (value_igi > DM_DIG_MAX) 446 value_igi = DM_DIG_MAX; 447 else if (value_igi < de_digtable->rx_gain_min) 448 value_igi = de_digtable->rx_gain_min; 449 de_digtable->cur_igvalue = value_igi; 450 rtl92d_dm_write_dig(hw); 451 if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) 452 rtl92d_dm_cck_packet_detection_thresh(hw); 453 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "<<==\n"); 454} 455 456static void rtl92d_dm_init_dynamic_txpower(struct ieee80211_hw *hw) 457{ 458 struct rtl_priv *rtlpriv = rtl_priv(hw); 459 460 rtlpriv->dm.dynamic_txpower_enable = true; 461 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL; 462 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL; 463} 464 465static void rtl92d_dm_dynamic_txpower(struct ieee80211_hw *hw) 466{ 467 struct rtl_priv *rtlpriv = rtl_priv(hw); 468 struct rtl_phy *rtlphy = &(rtlpriv->phy); 469 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 470 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 471 long undec_sm_pwdb; 472 473 if ((!rtlpriv->dm.dynamic_txpower_enable) 474 || rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) { 475 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL; 476 return; 477 } 478 if ((mac->link_state < MAC80211_LINKED) && 479 (rtlpriv->dm.UNDEC_SM_PWDB == 0)) { 480 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE, 481 "Not connected to any\n"); 482 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL; 483 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL; 484 return; 485 } 486 if (mac->link_state >= MAC80211_LINKED) { 487 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 488 undec_sm_pwdb = 489 rtlpriv->dm.UNDEC_SM_PWDB; 490 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 491 "IBSS Client PWDB = 0x%lx\n", 492 undec_sm_pwdb); 493 } else { 494 undec_sm_pwdb = 495 rtlpriv->dm.undec_sm_pwdb; 496 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 497 "STA Default Port PWDB = 0x%lx\n", 498 undec_sm_pwdb); 499 } 500 } else { 501 undec_sm_pwdb = 502 rtlpriv->dm.UNDEC_SM_PWDB; 503 504 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 505 "AP Ext Port PWDB = 0x%lx\n", 506 undec_sm_pwdb); 507 } 508 if (rtlhal->current_bandtype == BAND_ON_5G) { 509 if (undec_sm_pwdb >= 0x33) { 510 rtlpriv->dm.dynamic_txhighpower_lvl = 511 TXHIGHPWRLEVEL_LEVEL2; 512 rtl_dbg(rtlpriv, COMP_HIPWR, DBG_LOUD, 513 "5G:TxHighPwrLevel_Level2 (TxPwr=0x0)\n"); 514 } else if ((undec_sm_pwdb < 0x33) 515 && (undec_sm_pwdb >= 0x2b)) { 516 rtlpriv->dm.dynamic_txhighpower_lvl = 517 TXHIGHPWRLEVEL_LEVEL1; 518 rtl_dbg(rtlpriv, COMP_HIPWR, DBG_LOUD, 519 "5G:TxHighPwrLevel_Level1 (TxPwr=0x10)\n"); 520 } else if (undec_sm_pwdb < 0x2b) { 521 rtlpriv->dm.dynamic_txhighpower_lvl = 522 TXHIGHPWRLEVEL_NORMAL; 523 rtl_dbg(rtlpriv, COMP_HIPWR, DBG_LOUD, 524 "5G:TxHighPwrLevel_Normal\n"); 525 } 526 } else { 527 if (undec_sm_pwdb >= 528 TX_POWER_NEAR_FIELD_THRESH_LVL2) { 529 rtlpriv->dm.dynamic_txhighpower_lvl = 530 TXHIGHPWRLEVEL_LEVEL2; 531 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 532 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n"); 533 } else 534 if ((undec_sm_pwdb < 535 (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) 536 && (undec_sm_pwdb >= 537 TX_POWER_NEAR_FIELD_THRESH_LVL1)) { 538 539 rtlpriv->dm.dynamic_txhighpower_lvl = 540 TXHIGHPWRLEVEL_LEVEL1; 541 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 542 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n"); 543 } else if (undec_sm_pwdb < 544 (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) { 545 rtlpriv->dm.dynamic_txhighpower_lvl = 546 TXHIGHPWRLEVEL_NORMAL; 547 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 548 "TXHIGHPWRLEVEL_NORMAL\n"); 549 } 550 } 551 if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) { 552 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 553 "PHY_SetTxPowerLevel8192S() Channel = %d\n", 554 rtlphy->current_channel); 555 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel); 556 } 557 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl; 558} 559 560static void rtl92d_dm_pwdb_monitor(struct ieee80211_hw *hw) 561{ 562 struct rtl_priv *rtlpriv = rtl_priv(hw); 563 564 /* AP & ADHOC & MESH will return tmp */ 565 if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION) 566 return; 567 /* Indicate Rx signal strength to FW. */ 568 if (rtlpriv->dm.useramask) { 569 u32 temp = rtlpriv->dm.undec_sm_pwdb; 570 571 temp <<= 16; 572 temp |= 0x100; 573 /* fw v12 cmdid 5:use max macid ,for nic , 574 * default macid is 0 ,max macid is 1 */ 575 rtl92d_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, (u8 *) (&temp)); 576 } else { 577 rtl_write_byte(rtlpriv, 0x4fe, 578 (u8) rtlpriv->dm.undec_sm_pwdb); 579 } 580} 581 582void rtl92d_dm_init_edca_turbo(struct ieee80211_hw *hw) 583{ 584 struct rtl_priv *rtlpriv = rtl_priv(hw); 585 586 rtlpriv->dm.current_turbo_edca = false; 587 rtlpriv->dm.is_any_nonbepkts = false; 588 rtlpriv->dm.is_cur_rdlstate = false; 589} 590 591static void rtl92d_dm_check_edca_turbo(struct ieee80211_hw *hw) 592{ 593 struct rtl_priv *rtlpriv = rtl_priv(hw); 594 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 595 static u64 last_txok_cnt; 596 static u64 last_rxok_cnt; 597 u64 cur_txok_cnt; 598 u64 cur_rxok_cnt; 599 u32 edca_be_ul = 0x5ea42b; 600 u32 edca_be_dl = 0x5ea42b; 601 602 if (mac->link_state != MAC80211_LINKED) { 603 rtlpriv->dm.current_turbo_edca = false; 604 goto exit; 605 } 606 607 /* Enable BEQ TxOP limit configuration in wireless G-mode. */ 608 /* To check whether we shall force turn on TXOP configuration. */ 609 if ((!rtlpriv->dm.disable_framebursting) && 610 (rtlpriv->sec.pairwise_enc_algorithm == WEP40_ENCRYPTION || 611 rtlpriv->sec.pairwise_enc_algorithm == WEP104_ENCRYPTION || 612 rtlpriv->sec.pairwise_enc_algorithm == TKIP_ENCRYPTION)) { 613 /* Force TxOP limit to 0x005e for UL. */ 614 if (!(edca_be_ul & 0xffff0000)) 615 edca_be_ul |= 0x005e0000; 616 /* Force TxOP limit to 0x005e for DL. */ 617 if (!(edca_be_dl & 0xffff0000)) 618 edca_be_dl |= 0x005e0000; 619 } 620 621 if ((!rtlpriv->dm.is_any_nonbepkts) && 622 (!rtlpriv->dm.disable_framebursting)) { 623 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt; 624 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt; 625 if (cur_rxok_cnt > 4 * cur_txok_cnt) { 626 if (!rtlpriv->dm.is_cur_rdlstate || 627 !rtlpriv->dm.current_turbo_edca) { 628 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, 629 edca_be_dl); 630 rtlpriv->dm.is_cur_rdlstate = true; 631 } 632 } else { 633 if (rtlpriv->dm.is_cur_rdlstate || 634 !rtlpriv->dm.current_turbo_edca) { 635 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, 636 edca_be_ul); 637 rtlpriv->dm.is_cur_rdlstate = false; 638 } 639 } 640 rtlpriv->dm.current_turbo_edca = true; 641 } else { 642 if (rtlpriv->dm.current_turbo_edca) { 643 u8 tmp = AC0_BE; 644 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, 645 &tmp); 646 rtlpriv->dm.current_turbo_edca = false; 647 } 648 } 649 650exit: 651 rtlpriv->dm.is_any_nonbepkts = false; 652 last_txok_cnt = rtlpriv->stats.txbytesunicast; 653 last_rxok_cnt = rtlpriv->stats.rxbytesunicast; 654} 655 656static void rtl92d_dm_rxgain_tracking_thermalmeter(struct ieee80211_hw *hw) 657{ 658 struct rtl_priv *rtlpriv = rtl_priv(hw); 659 u8 index_mapping[RX_INDEX_MAPPING_NUM] = { 660 0x0f, 0x0f, 0x0d, 0x0c, 0x0b, 661 0x0a, 0x09, 0x08, 0x07, 0x06, 662 0x05, 0x04, 0x04, 0x03, 0x02 663 }; 664 int i; 665 u32 u4tmp; 666 667 u4tmp = (index_mapping[(rtlpriv->efuse.eeprom_thermalmeter - 668 rtlpriv->dm.thermalvalue_rxgain)]) << 12; 669 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 670 "===> Rx Gain %x\n", u4tmp); 671 for (i = RF90_PATH_A; i < rtlpriv->phy.num_total_rfpath; i++) 672 rtl_set_rfreg(hw, i, 0x3C, RFREG_OFFSET_MASK, 673 (rtlpriv->phy.reg_rf3c[i] & (~(0xF000))) | u4tmp); 674} 675 676static void rtl92d_bandtype_2_4G(struct ieee80211_hw *hw, long *temp_cckg, 677 u8 *cck_index_old) 678{ 679 struct rtl_priv *rtlpriv = rtl_priv(hw); 680 int i; 681 unsigned long flag = 0; 682 long temp_cck; 683 const u8 *cckswing; 684 685 /* Query CCK default setting From 0xa24 */ 686 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); 687 temp_cck = rtl_get_bbreg(hw, RCCK0_TXFILTER2, 688 MASKDWORD) & MASKCCK; 689 rtl92d_release_cckandrw_pagea_ctl(hw, &flag); 690 for (i = 0; i < CCK_TABLE_LENGTH; i++) { 691 if (rtlpriv->dm.cck_inch14) 692 cckswing = &cckswing_table_ch14[i][2]; 693 else 694 cckswing = &cckswing_table_ch1ch13[i][2]; 695 696 if (temp_cck == le32_to_cpu(*((__le32 *)cckswing))) { 697 *cck_index_old = (u8)i; 698 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 699 "Initial reg0x%x = 0x%lx, cck_index = 0x%x, ch14 %d\n", 700 RCCK0_TXFILTER2, temp_cck, 701 *cck_index_old, 702 rtlpriv->dm.cck_inch14); 703 break; 704 } 705 } 706 *temp_cckg = temp_cck; 707} 708 709static void rtl92d_bandtype_5G(struct rtl_hal *rtlhal, u8 *ofdm_index, 710 bool *internal_pa, u8 thermalvalue, u8 delta, 711 u8 rf, struct rtl_efuse *rtlefuse, 712 struct rtl_priv *rtlpriv, struct rtl_phy *rtlphy, 713 const u8 index_mapping[5][INDEX_MAPPING_NUM], 714 const u8 index_mapping_pa[8][INDEX_MAPPING_NUM]) 715{ 716 int i; 717 u8 index; 718 u8 offset = 0; 719 720 for (i = 0; i < rf; i++) { 721 if (rtlhal->macphymode == DUALMAC_DUALPHY && 722 rtlhal->interfaceindex == 1) /* MAC 1 5G */ 723 *internal_pa = rtlefuse->internal_pa_5g[1]; 724 else 725 *internal_pa = rtlefuse->internal_pa_5g[i]; 726 if (*internal_pa) { 727 if (rtlhal->interfaceindex == 1 || i == rf) 728 offset = 4; 729 else 730 offset = 0; 731 if (rtlphy->current_channel >= 100 && 732 rtlphy->current_channel <= 165) 733 offset += 2; 734 } else { 735 if (rtlhal->interfaceindex == 1 || i == rf) 736 offset = 2; 737 else 738 offset = 0; 739 } 740 if (thermalvalue > rtlefuse->eeprom_thermalmeter) 741 offset++; 742 if (*internal_pa) { 743 if (delta > INDEX_MAPPING_NUM - 1) 744 index = index_mapping_pa[offset] 745 [INDEX_MAPPING_NUM - 1]; 746 else 747 index = 748 index_mapping_pa[offset][delta]; 749 } else { 750 if (delta > INDEX_MAPPING_NUM - 1) 751 index = 752 index_mapping[offset][INDEX_MAPPING_NUM - 1]; 753 else 754 index = index_mapping[offset][delta]; 755 } 756 if (thermalvalue > rtlefuse->eeprom_thermalmeter) { 757 if (*internal_pa && thermalvalue > 0x12) { 758 ofdm_index[i] = rtlpriv->dm.ofdm_index[i] - 759 ((delta / 2) * 3 + (delta % 2)); 760 } else { 761 ofdm_index[i] -= index; 762 } 763 } else { 764 ofdm_index[i] += index; 765 } 766 } 767} 768 769static void rtl92d_dm_txpower_tracking_callback_thermalmeter( 770 struct ieee80211_hw *hw) 771{ 772 struct rtl_priv *rtlpriv = rtl_priv(hw); 773 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 774 struct rtl_phy *rtlphy = &(rtlpriv->phy); 775 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 776 u8 thermalvalue, delta, delta_lck, delta_iqk, delta_rxgain; 777 u8 offset, thermalvalue_avg_count = 0; 778 u32 thermalvalue_avg = 0; 779 bool internal_pa = false; 780 long ele_a = 0, ele_d, temp_cck, val_x, value32; 781 long val_y, ele_c = 0; 782 u8 ofdm_index[2]; 783 s8 cck_index = 0; 784 u8 ofdm_index_old[2] = {0, 0}; 785 s8 cck_index_old = 0; 786 u8 index; 787 int i; 788 bool is2t = IS_92D_SINGLEPHY(rtlhal->version); 789 u8 ofdm_min_index = 6, ofdm_min_index_internal_pa = 3, rf; 790 u8 indexforchannel = 791 rtl92d_get_rightchnlplace_for_iqk(rtlphy->current_channel); 792 static const u8 index_mapping[5][INDEX_MAPPING_NUM] = { 793 /* 5G, path A/MAC 0, decrease power */ 794 {0, 1, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18}, 795 /* 5G, path A/MAC 0, increase power */ 796 {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, 797 /* 5G, path B/MAC 1, decrease power */ 798 {0, 2, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18}, 799 /* 5G, path B/MAC 1, increase power */ 800 {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, 801 /* 2.4G, for decreas power */ 802 {0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10}, 803 }; 804 static const u8 index_mapping_internal_pa[8][INDEX_MAPPING_NUM] = { 805 /* 5G, path A/MAC 0, ch36-64, decrease power */ 806 {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16}, 807 /* 5G, path A/MAC 0, ch36-64, increase power */ 808 {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, 809 /* 5G, path A/MAC 0, ch100-165, decrease power */ 810 {0, 1, 2, 3, 5, 6, 8, 10, 11, 13, 14, 15, 15}, 811 /* 5G, path A/MAC 0, ch100-165, increase power */ 812 {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, 813 /* 5G, path B/MAC 1, ch36-64, decrease power */ 814 {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16}, 815 /* 5G, path B/MAC 1, ch36-64, increase power */ 816 {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, 817 /* 5G, path B/MAC 1, ch100-165, decrease power */ 818 {0, 1, 2, 3, 5, 6, 8, 9, 10, 12, 13, 14, 14}, 819 /* 5G, path B/MAC 1, ch100-165, increase power */ 820 {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, 821 }; 822 823 rtlpriv->dm.txpower_trackinginit = true; 824 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "\n"); 825 thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0xf800); 826 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 827 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n", 828 thermalvalue, 829 rtlpriv->dm.thermalvalue, rtlefuse->eeprom_thermalmeter); 830 rtl92d_phy_ap_calibrate(hw, (thermalvalue - 831 rtlefuse->eeprom_thermalmeter)); 832 833 if (!thermalvalue) 834 goto exit; 835 836 if (is2t) 837 rf = 2; 838 else 839 rf = 1; 840 841 if (rtlpriv->dm.thermalvalue && !rtlhal->reloadtxpowerindex) 842 goto old_index_done; 843 844 ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD) & MASKOFDM_D; 845 for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) { 846 if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) { 847 ofdm_index_old[0] = (u8)i; 848 849 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 850 "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n", 851 ROFDM0_XATXIQIMBALANCE, 852 ele_d, ofdm_index_old[0]); 853 break; 854 } 855 } 856 if (is2t) { 857 ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 858 MASKDWORD) & MASKOFDM_D; 859 for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) { 860 if (ele_d == 861 (ofdmswing_table[i] & MASKOFDM_D)) { 862 ofdm_index_old[1] = (u8)i; 863 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, 864 DBG_LOUD, 865 "Initial pathB ele_d reg 0x%x = 0x%lx, ofdm_index = 0x%x\n", 866 ROFDM0_XBTXIQIMBALANCE, ele_d, 867 ofdm_index_old[1]); 868 break; 869 } 870 } 871 } 872 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 873 rtl92d_bandtype_2_4G(hw, &temp_cck, &cck_index_old); 874 } else { 875 temp_cck = 0x090e1317; 876 cck_index_old = 12; 877 } 878 879 if (!rtlpriv->dm.thermalvalue) { 880 rtlpriv->dm.thermalvalue = rtlefuse->eeprom_thermalmeter; 881 rtlpriv->dm.thermalvalue_lck = thermalvalue; 882 rtlpriv->dm.thermalvalue_iqk = thermalvalue; 883 rtlpriv->dm.thermalvalue_rxgain = rtlefuse->eeprom_thermalmeter; 884 for (i = 0; i < rf; i++) 885 rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i]; 886 rtlpriv->dm.cck_index = cck_index_old; 887 } 888 if (rtlhal->reloadtxpowerindex) { 889 for (i = 0; i < rf; i++) 890 rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i]; 891 rtlpriv->dm.cck_index = cck_index_old; 892 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 893 "reload ofdm index for band switch\n"); 894 } 895old_index_done: 896 for (i = 0; i < rf; i++) 897 ofdm_index[i] = rtlpriv->dm.ofdm_index[i]; 898 899 rtlpriv->dm.thermalvalue_avg 900 [rtlpriv->dm.thermalvalue_avg_index] = thermalvalue; 901 rtlpriv->dm.thermalvalue_avg_index++; 902 if (rtlpriv->dm.thermalvalue_avg_index == AVG_THERMAL_NUM) 903 rtlpriv->dm.thermalvalue_avg_index = 0; 904 for (i = 0; i < AVG_THERMAL_NUM; i++) { 905 if (rtlpriv->dm.thermalvalue_avg[i]) { 906 thermalvalue_avg += rtlpriv->dm.thermalvalue_avg[i]; 907 thermalvalue_avg_count++; 908 } 909 } 910 if (thermalvalue_avg_count) 911 thermalvalue = (u8)(thermalvalue_avg / thermalvalue_avg_count); 912 if (rtlhal->reloadtxpowerindex) { 913 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ? 914 (thermalvalue - rtlefuse->eeprom_thermalmeter) : 915 (rtlefuse->eeprom_thermalmeter - thermalvalue); 916 rtlhal->reloadtxpowerindex = false; 917 rtlpriv->dm.done_txpower = false; 918 } else if (rtlpriv->dm.done_txpower) { 919 delta = (thermalvalue > rtlpriv->dm.thermalvalue) ? 920 (thermalvalue - rtlpriv->dm.thermalvalue) : 921 (rtlpriv->dm.thermalvalue - thermalvalue); 922 } else { 923 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ? 924 (thermalvalue - rtlefuse->eeprom_thermalmeter) : 925 (rtlefuse->eeprom_thermalmeter - thermalvalue); 926 } 927 delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ? 928 (thermalvalue - rtlpriv->dm.thermalvalue_lck) : 929 (rtlpriv->dm.thermalvalue_lck - thermalvalue); 930 delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ? 931 (thermalvalue - rtlpriv->dm.thermalvalue_iqk) : 932 (rtlpriv->dm.thermalvalue_iqk - thermalvalue); 933 delta_rxgain = 934 (thermalvalue > rtlpriv->dm.thermalvalue_rxgain) ? 935 (thermalvalue - rtlpriv->dm.thermalvalue_rxgain) : 936 (rtlpriv->dm.thermalvalue_rxgain - thermalvalue); 937 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 938 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n", 939 thermalvalue, rtlpriv->dm.thermalvalue, 940 rtlefuse->eeprom_thermalmeter, delta, delta_lck, 941 delta_iqk); 942 if (delta_lck > rtlefuse->delta_lck && rtlefuse->delta_lck != 0) { 943 rtlpriv->dm.thermalvalue_lck = thermalvalue; 944 rtl92d_phy_lc_calibrate(hw); 945 } 946 947 if (delta == 0 || !rtlpriv->dm.txpower_track_control) 948 goto check_delta; 949 950 rtlpriv->dm.done_txpower = true; 951 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ? 952 (thermalvalue - rtlefuse->eeprom_thermalmeter) : 953 (rtlefuse->eeprom_thermalmeter - thermalvalue); 954 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 955 offset = 4; 956 if (delta > INDEX_MAPPING_NUM - 1) 957 index = index_mapping[offset][INDEX_MAPPING_NUM - 1]; 958 else 959 index = index_mapping[offset][delta]; 960 if (thermalvalue > rtlpriv->dm.thermalvalue) { 961 for (i = 0; i < rf; i++) 962 ofdm_index[i] -= delta; 963 cck_index -= delta; 964 } else { 965 for (i = 0; i < rf; i++) 966 ofdm_index[i] += index; 967 cck_index += index; 968 } 969 } else if (rtlhal->current_bandtype == BAND_ON_5G) { 970 rtl92d_bandtype_5G(rtlhal, ofdm_index, 971 &internal_pa, thermalvalue, 972 delta, rf, rtlefuse, rtlpriv, 973 rtlphy, index_mapping, 974 index_mapping_internal_pa); 975 } 976 if (is2t) { 977 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 978 "temp OFDM_A_index=0x%x, OFDM_B_index = 0x%x,cck_index=0x%x\n", 979 rtlpriv->dm.ofdm_index[0], 980 rtlpriv->dm.ofdm_index[1], 981 rtlpriv->dm.cck_index); 982 } else { 983 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 984 "temp OFDM_A_index=0x%x,cck_index = 0x%x\n", 985 rtlpriv->dm.ofdm_index[0], 986 rtlpriv->dm.cck_index); 987 } 988 for (i = 0; i < rf; i++) { 989 if (ofdm_index[i] > OFDM_TABLE_SIZE_92D - 1) 990 ofdm_index[i] = OFDM_TABLE_SIZE_92D - 1; 991 else if (ofdm_index[i] < ofdm_min_index) 992 ofdm_index[i] = ofdm_min_index; 993 } 994 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 995 if (cck_index > CCK_TABLE_SIZE - 1) { 996 cck_index = CCK_TABLE_SIZE - 1; 997 } else if (internal_pa || 998 rtlhal->current_bandtype == BAND_ON_2_4G) { 999 if (ofdm_index[i] < ofdm_min_index_internal_pa) 1000 ofdm_index[i] = ofdm_min_index_internal_pa; 1001 } else if (cck_index < 0) { 1002 cck_index = 0; 1003 } 1004 } 1005 if (is2t) { 1006 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 1007 "new OFDM_A_index=0x%x, OFDM_B_index = 0x%x, cck_index=0x%x\n", 1008 ofdm_index[0], ofdm_index[1], 1009 cck_index); 1010 } else { 1011 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 1012 "new OFDM_A_index=0x%x,cck_index = 0x%x\n", 1013 ofdm_index[0], cck_index); 1014 } 1015 ele_d = (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22; 1016 val_x = rtlphy->iqk_matrix[indexforchannel].value[0][0]; 1017 val_y = rtlphy->iqk_matrix[indexforchannel].value[0][1]; 1018 if (val_x != 0) { 1019 if ((val_x & 0x00000200) != 0) 1020 val_x = val_x | 0xFFFFFC00; 1021 ele_a = ((val_x * ele_d) >> 8) & 0x000003FF; 1022 1023 /* new element C = element D x Y */ 1024 if ((val_y & 0x00000200) != 0) 1025 val_y = val_y | 0xFFFFFC00; 1026 ele_c = ((val_y * ele_d) >> 8) & 0x000003FF; 1027 1028 /* write new elements A, C, D to regC80 and 1029 * regC94, element B is always 0 1030 */ 1031 value32 = (ele_d << 22) | ((ele_c & 0x3F) << 16) | ele_a; 1032 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 1033 MASKDWORD, value32); 1034 1035 value32 = (ele_c & 0x000003C0) >> 6; 1036 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, 1037 value32); 1038 1039 value32 = ((val_x * ele_d) >> 7) & 0x01; 1040 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), 1041 value32); 1042 1043 } else { 1044 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 1045 MASKDWORD, 1046 ofdmswing_table[(u8)ofdm_index[0]]); 1047 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, 1048 0x00); 1049 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, 1050 BIT(24), 0x00); 1051 } 1052 1053 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 1054 "TxPwrTracking for interface %d path A: X = 0x%lx, Y = 0x%lx ele_A = 0x%lx ele_C = 0x%lx ele_D = 0x%lx 0xe94 = 0x%lx 0xe9c = 0x%lx\n", 1055 rtlhal->interfaceindex, 1056 val_x, val_y, ele_a, ele_c, ele_d, 1057 val_x, val_y); 1058 1059 if (cck_index >= CCK_TABLE_SIZE) 1060 cck_index = CCK_TABLE_SIZE - 1; 1061 if (cck_index < 0) 1062 cck_index = 0; 1063 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 1064 /* Adjust CCK according to IQK result */ 1065 if (!rtlpriv->dm.cck_inch14) { 1066 rtl_write_byte(rtlpriv, 0xa22, 1067 cckswing_table_ch1ch13[cck_index][0]); 1068 rtl_write_byte(rtlpriv, 0xa23, 1069 cckswing_table_ch1ch13[cck_index][1]); 1070 rtl_write_byte(rtlpriv, 0xa24, 1071 cckswing_table_ch1ch13[cck_index][2]); 1072 rtl_write_byte(rtlpriv, 0xa25, 1073 cckswing_table_ch1ch13[cck_index][3]); 1074 rtl_write_byte(rtlpriv, 0xa26, 1075 cckswing_table_ch1ch13[cck_index][4]); 1076 rtl_write_byte(rtlpriv, 0xa27, 1077 cckswing_table_ch1ch13[cck_index][5]); 1078 rtl_write_byte(rtlpriv, 0xa28, 1079 cckswing_table_ch1ch13[cck_index][6]); 1080 rtl_write_byte(rtlpriv, 0xa29, 1081 cckswing_table_ch1ch13[cck_index][7]); 1082 } else { 1083 rtl_write_byte(rtlpriv, 0xa22, 1084 cckswing_table_ch14[cck_index][0]); 1085 rtl_write_byte(rtlpriv, 0xa23, 1086 cckswing_table_ch14[cck_index][1]); 1087 rtl_write_byte(rtlpriv, 0xa24, 1088 cckswing_table_ch14[cck_index][2]); 1089 rtl_write_byte(rtlpriv, 0xa25, 1090 cckswing_table_ch14[cck_index][3]); 1091 rtl_write_byte(rtlpriv, 0xa26, 1092 cckswing_table_ch14[cck_index][4]); 1093 rtl_write_byte(rtlpriv, 0xa27, 1094 cckswing_table_ch14[cck_index][5]); 1095 rtl_write_byte(rtlpriv, 0xa28, 1096 cckswing_table_ch14[cck_index][6]); 1097 rtl_write_byte(rtlpriv, 0xa29, 1098 cckswing_table_ch14[cck_index][7]); 1099 } 1100 } 1101 if (is2t) { 1102 ele_d = (ofdmswing_table[ofdm_index[1]] & 0xFFC00000) >> 22; 1103 val_x = rtlphy->iqk_matrix[indexforchannel].value[0][4]; 1104 val_y = rtlphy->iqk_matrix[indexforchannel].value[0][5]; 1105 if (val_x != 0) { 1106 if ((val_x & 0x00000200) != 0) 1107 /* consider minus */ 1108 val_x = val_x | 0xFFFFFC00; 1109 ele_a = ((val_x * ele_d) >> 8) & 0x000003FF; 1110 /* new element C = element D x Y */ 1111 if ((val_y & 0x00000200) != 0) 1112 val_y = val_y | 0xFFFFFC00; 1113 ele_c = ((val_y * ele_d) >> 8) & 0x00003FF; 1114 /* write new elements A, C, D to regC88 1115 * and regC9C, element B is always 0 1116 */ 1117 value32 = (ele_d << 22) | ((ele_c & 0x3F) << 16) | ele_a; 1118 rtl_set_bbreg(hw, 1119 ROFDM0_XBTXIQIMBALANCE, 1120 MASKDWORD, value32); 1121 value32 = (ele_c & 0x000003C0) >> 6; 1122 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 1123 MASKH4BITS, value32); 1124 value32 = ((val_x * ele_d) >> 7) & 0x01; 1125 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, 1126 BIT(28), value32); 1127 } else { 1128 rtl_set_bbreg(hw, 1129 ROFDM0_XBTXIQIMBALANCE, 1130 MASKDWORD, 1131 ofdmswing_table[ofdm_index[1]]); 1132 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 1133 MASKH4BITS, 0x00); 1134 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, 1135 BIT(28), 0x00); 1136 } 1137 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 1138 "TxPwrTracking path B: X = 0x%lx, Y = 0x%lx ele_A = 0x%lx ele_C = 0x%lx ele_D = 0x%lx 0xeb4 = 0x%lx 0xebc = 0x%lx\n", 1139 val_x, val_y, ele_a, ele_c, 1140 ele_d, val_x, val_y); 1141 } 1142 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 1143 "TxPwrTracking 0xc80 = 0x%x, 0xc94 = 0x%x RF 0x24 = 0x%x\n", 1144 rtl_get_bbreg(hw, 0xc80, MASKDWORD), 1145 rtl_get_bbreg(hw, 0xc94, MASKDWORD), 1146 rtl_get_rfreg(hw, RF90_PATH_A, 0x24, 1147 RFREG_OFFSET_MASK)); 1148 1149check_delta: 1150 if (delta_iqk > rtlefuse->delta_iqk && rtlefuse->delta_iqk != 0) { 1151 rtl92d_phy_reset_iqk_result(hw); 1152 rtlpriv->dm.thermalvalue_iqk = thermalvalue; 1153 rtl92d_phy_iq_calibrate(hw); 1154 } 1155 if (delta_rxgain > 0 && rtlhal->current_bandtype == BAND_ON_5G && 1156 thermalvalue <= rtlefuse->eeprom_thermalmeter) { 1157 rtlpriv->dm.thermalvalue_rxgain = thermalvalue; 1158 rtl92d_dm_rxgain_tracking_thermalmeter(hw); 1159 } 1160 if (rtlpriv->dm.txpower_track_control) 1161 rtlpriv->dm.thermalvalue = thermalvalue; 1162 1163exit: 1164 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "<===\n"); 1165} 1166 1167static void rtl92d_dm_initialize_txpower_tracking(struct ieee80211_hw *hw) 1168{ 1169 struct rtl_priv *rtlpriv = rtl_priv(hw); 1170 1171 rtlpriv->dm.txpower_tracking = true; 1172 rtlpriv->dm.txpower_trackinginit = false; 1173 rtlpriv->dm.txpower_track_control = true; 1174 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 1175 "pMgntInfo->txpower_tracking = %d\n", 1176 rtlpriv->dm.txpower_tracking); 1177} 1178 1179void rtl92d_dm_check_txpower_tracking_thermal_meter(struct ieee80211_hw *hw) 1180{ 1181 struct rtl_priv *rtlpriv = rtl_priv(hw); 1182 1183 if (!rtlpriv->dm.txpower_tracking) 1184 return; 1185 1186 if (!rtlpriv->dm.tm_trigger) { 1187 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, BIT(17) | 1188 BIT(16), 0x03); 1189 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 1190 "Trigger 92S Thermal Meter!!\n"); 1191 rtlpriv->dm.tm_trigger = 1; 1192 return; 1193 } else { 1194 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 1195 "Schedule TxPowerTracking direct call!!\n"); 1196 rtl92d_dm_txpower_tracking_callback_thermalmeter(hw); 1197 rtlpriv->dm.tm_trigger = 0; 1198 } 1199} 1200 1201void rtl92d_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw) 1202{ 1203 struct rtl_priv *rtlpriv = rtl_priv(hw); 1204 struct rate_adaptive *ra = &(rtlpriv->ra); 1205 1206 ra->ratr_state = DM_RATR_STA_INIT; 1207 ra->pre_ratr_state = DM_RATR_STA_INIT; 1208 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER) 1209 rtlpriv->dm.useramask = true; 1210 else 1211 rtlpriv->dm.useramask = false; 1212} 1213 1214void rtl92d_dm_init(struct ieee80211_hw *hw) 1215{ 1216 struct rtl_priv *rtlpriv = rtl_priv(hw); 1217 1218 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER; 1219 rtl_dm_diginit(hw, 0x20); 1220 rtlpriv->dm_digtable.rx_gain_max = DM_DIG_FA_UPPER; 1221 rtlpriv->dm_digtable.rx_gain_min = DM_DIG_FA_LOWER; 1222 rtl92d_dm_init_dynamic_txpower(hw); 1223 rtl92d_dm_init_edca_turbo(hw); 1224 rtl92d_dm_init_rate_adaptive_mask(hw); 1225 rtl92d_dm_initialize_txpower_tracking(hw); 1226} 1227 1228void rtl92d_dm_watchdog(struct ieee80211_hw *hw) 1229{ 1230 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1231 bool fw_current_inpsmode = false; 1232 bool fwps_awake = true; 1233 1234 /* 1. RF is OFF. (No need to do DM.) 1235 * 2. Fw is under power saving mode for FwLPS. 1236 * (Prevent from SW/FW I/O racing.) 1237 * 3. IPS workitem is scheduled. (Prevent from IPS sequence 1238 * to be swapped with DM. 1239 * 4. RFChangeInProgress is TRUE. 1240 * (Prevent from broken by IPS/HW/SW Rf off.) */ 1241 1242 if ((ppsc->rfpwr_state == ERFON) && ((!fw_current_inpsmode) && 1243 fwps_awake) && (!ppsc->rfchange_inprogress)) { 1244 rtl92d_dm_pwdb_monitor(hw); 1245 rtl92d_dm_false_alarm_counter_statistics(hw); 1246 rtl92d_dm_find_minimum_rssi(hw); 1247 rtl92d_dm_dig(hw); 1248 /* rtl92d_dm_dynamic_bb_powersaving(hw); */ 1249 rtl92d_dm_dynamic_txpower(hw); 1250 /* rtl92d_dm_check_txpower_tracking_thermal_meter(hw); */ 1251 /* rtl92d_dm_refresh_rate_adaptive_mask(hw); */ 1252 /* rtl92d_dm_interrupt_migration(hw); */ 1253 rtl92d_dm_check_edca_turbo(hw); 1254 } 1255} 1256