1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> 4 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com> 5 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> 6 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com> 7 8 Based on the original rt2800pci.c and rt2800usb.c. 9 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 10 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 11 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 12 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> 13 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> 14 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> 15 <http://rt2x00.serialmonkey.com> 16 17 */ 18 19/* 20 Module: rt2800lib 21 Abstract: rt2800 generic device routines. 22 */ 23 24#include <linux/crc-ccitt.h> 25#include <linux/kernel.h> 26#include <linux/module.h> 27#include <linux/slab.h> 28 29#include "rt2x00.h" 30#include "rt2800lib.h" 31#include "rt2800.h" 32 33static bool modparam_watchdog; 34module_param_named(watchdog, modparam_watchdog, bool, S_IRUGO); 35MODULE_PARM_DESC(watchdog, "Enable watchdog to detect tx/rx hangs and reset hardware if detected"); 36 37/* 38 * Register access. 39 * All access to the CSR registers will go through the methods 40 * rt2800_register_read and rt2800_register_write. 41 * BBP and RF register require indirect register access, 42 * and use the CSR registers BBPCSR and RFCSR to achieve this. 43 * These indirect registers work with busy bits, 44 * and we will try maximal REGISTER_BUSY_COUNT times to access 45 * the register while taking a REGISTER_BUSY_DELAY us delay 46 * between each attampt. When the busy bit is still set at that time, 47 * the access attempt is considered to have failed, 48 * and we will print an error. 49 * The _lock versions must be used if you already hold the csr_mutex 50 */ 51#define WAIT_FOR_BBP(__dev, __reg) \ 52 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg)) 53#define WAIT_FOR_RFCSR(__dev, __reg) \ 54 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg)) 55#define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \ 56 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \ 57 (__reg)) 58#define WAIT_FOR_RF(__dev, __reg) \ 59 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg)) 60#define WAIT_FOR_MCU(__dev, __reg) \ 61 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \ 62 H2M_MAILBOX_CSR_OWNER, (__reg)) 63 64static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev) 65{ 66 /* check for rt2872 on SoC */ 67 if (!rt2x00_is_soc(rt2x00dev) || 68 !rt2x00_rt(rt2x00dev, RT2872)) 69 return false; 70 71 /* we know for sure that these rf chipsets are used on rt305x boards */ 72 if (rt2x00_rf(rt2x00dev, RF3020) || 73 rt2x00_rf(rt2x00dev, RF3021) || 74 rt2x00_rf(rt2x00dev, RF3022)) 75 return true; 76 77 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n"); 78 return false; 79} 80 81static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev, 82 const unsigned int word, const u8 value) 83{ 84 u32 reg; 85 86 mutex_lock(&rt2x00dev->csr_mutex); 87 88 /* 89 * Wait until the BBP becomes available, afterwards we 90 * can safely write the new data into the register. 91 */ 92 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 93 reg = 0; 94 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); 95 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 96 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 97 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); 98 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 99 100 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 101 } 102 103 mutex_unlock(&rt2x00dev->csr_mutex); 104} 105 106static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word) 107{ 108 u32 reg; 109 u8 value; 110 111 mutex_lock(&rt2x00dev->csr_mutex); 112 113 /* 114 * Wait until the BBP becomes available, afterwards we 115 * can safely write the read request into the register. 116 * After the data has been written, we wait until hardware 117 * returns the correct value, if at any time the register 118 * doesn't become available in time, reg will be 0xffffffff 119 * which means we return 0xff to the caller. 120 */ 121 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 122 reg = 0; 123 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 124 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 125 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); 126 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 127 128 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 129 130 WAIT_FOR_BBP(rt2x00dev, ®); 131 } 132 133 value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); 134 135 mutex_unlock(&rt2x00dev->csr_mutex); 136 137 return value; 138} 139 140static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev, 141 const unsigned int word, const u8 value) 142{ 143 u32 reg; 144 145 mutex_lock(&rt2x00dev->csr_mutex); 146 147 /* 148 * Wait until the RFCSR becomes available, afterwards we 149 * can safely write the new data into the register. 150 */ 151 switch (rt2x00dev->chip.rt) { 152 case RT6352: 153 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { 154 reg = 0; 155 rt2x00_set_field32(®, RF_CSR_CFG_DATA_MT7620, value); 156 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, 157 word); 158 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 1); 159 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); 160 161 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 162 } 163 break; 164 165 default: 166 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 167 reg = 0; 168 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); 169 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 170 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); 171 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 172 173 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 174 } 175 break; 176 } 177 178 mutex_unlock(&rt2x00dev->csr_mutex); 179} 180 181static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, 182 const unsigned int reg, const u8 value) 183{ 184 rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value); 185} 186 187static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev, 188 const unsigned int reg, const u8 value) 189{ 190 rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value); 191 rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value); 192} 193 194static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev, 195 const unsigned int reg, const u8 value) 196{ 197 rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value); 198 rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value); 199} 200 201static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, 202 const unsigned int word) 203{ 204 u32 reg; 205 u8 value; 206 207 mutex_lock(&rt2x00dev->csr_mutex); 208 209 /* 210 * Wait until the RFCSR becomes available, afterwards we 211 * can safely write the read request into the register. 212 * After the data has been written, we wait until hardware 213 * returns the correct value, if at any time the register 214 * doesn't become available in time, reg will be 0xffffffff 215 * which means we return 0xff to the caller. 216 */ 217 switch (rt2x00dev->chip.rt) { 218 case RT6352: 219 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { 220 reg = 0; 221 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, 222 word); 223 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 0); 224 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); 225 226 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 227 228 WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®); 229 } 230 231 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620); 232 break; 233 234 default: 235 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 236 reg = 0; 237 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 238 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); 239 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 240 241 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 242 243 WAIT_FOR_RFCSR(rt2x00dev, ®); 244 } 245 246 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); 247 break; 248 } 249 250 mutex_unlock(&rt2x00dev->csr_mutex); 251 252 return value; 253} 254 255static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, 256 const unsigned int reg) 257{ 258 return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6))); 259} 260 261static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev, 262 const unsigned int word, const u32 value) 263{ 264 u32 reg; 265 266 mutex_lock(&rt2x00dev->csr_mutex); 267 268 /* 269 * Wait until the RF becomes available, afterwards we 270 * can safely write the new data into the register. 271 */ 272 if (WAIT_FOR_RF(rt2x00dev, ®)) { 273 reg = 0; 274 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); 275 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); 276 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); 277 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); 278 279 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); 280 rt2x00_rf_write(rt2x00dev, word, value); 281 } 282 283 mutex_unlock(&rt2x00dev->csr_mutex); 284} 285 286static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = { 287 [EEPROM_CHIP_ID] = 0x0000, 288 [EEPROM_VERSION] = 0x0001, 289 [EEPROM_MAC_ADDR_0] = 0x0002, 290 [EEPROM_MAC_ADDR_1] = 0x0003, 291 [EEPROM_MAC_ADDR_2] = 0x0004, 292 [EEPROM_NIC_CONF0] = 0x001a, 293 [EEPROM_NIC_CONF1] = 0x001b, 294 [EEPROM_FREQ] = 0x001d, 295 [EEPROM_LED_AG_CONF] = 0x001e, 296 [EEPROM_LED_ACT_CONF] = 0x001f, 297 [EEPROM_LED_POLARITY] = 0x0020, 298 [EEPROM_NIC_CONF2] = 0x0021, 299 [EEPROM_LNA] = 0x0022, 300 [EEPROM_RSSI_BG] = 0x0023, 301 [EEPROM_RSSI_BG2] = 0x0024, 302 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */ 303 [EEPROM_RSSI_A] = 0x0025, 304 [EEPROM_RSSI_A2] = 0x0026, 305 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */ 306 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027, 307 [EEPROM_TXPOWER_DELTA] = 0x0028, 308 [EEPROM_TXPOWER_BG1] = 0x0029, 309 [EEPROM_TXPOWER_BG2] = 0x0030, 310 [EEPROM_TSSI_BOUND_BG1] = 0x0037, 311 [EEPROM_TSSI_BOUND_BG2] = 0x0038, 312 [EEPROM_TSSI_BOUND_BG3] = 0x0039, 313 [EEPROM_TSSI_BOUND_BG4] = 0x003a, 314 [EEPROM_TSSI_BOUND_BG5] = 0x003b, 315 [EEPROM_TXPOWER_A1] = 0x003c, 316 [EEPROM_TXPOWER_A2] = 0x0053, 317 [EEPROM_TXPOWER_INIT] = 0x0068, 318 [EEPROM_TSSI_BOUND_A1] = 0x006a, 319 [EEPROM_TSSI_BOUND_A2] = 0x006b, 320 [EEPROM_TSSI_BOUND_A3] = 0x006c, 321 [EEPROM_TSSI_BOUND_A4] = 0x006d, 322 [EEPROM_TSSI_BOUND_A5] = 0x006e, 323 [EEPROM_TXPOWER_BYRATE] = 0x006f, 324 [EEPROM_BBP_START] = 0x0078, 325}; 326 327static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = { 328 [EEPROM_CHIP_ID] = 0x0000, 329 [EEPROM_VERSION] = 0x0001, 330 [EEPROM_MAC_ADDR_0] = 0x0002, 331 [EEPROM_MAC_ADDR_1] = 0x0003, 332 [EEPROM_MAC_ADDR_2] = 0x0004, 333 [EEPROM_NIC_CONF0] = 0x001a, 334 [EEPROM_NIC_CONF1] = 0x001b, 335 [EEPROM_NIC_CONF2] = 0x001c, 336 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020, 337 [EEPROM_FREQ] = 0x0022, 338 [EEPROM_LED_AG_CONF] = 0x0023, 339 [EEPROM_LED_ACT_CONF] = 0x0024, 340 [EEPROM_LED_POLARITY] = 0x0025, 341 [EEPROM_LNA] = 0x0026, 342 [EEPROM_EXT_LNA2] = 0x0027, 343 [EEPROM_RSSI_BG] = 0x0028, 344 [EEPROM_RSSI_BG2] = 0x0029, 345 [EEPROM_RSSI_A] = 0x002a, 346 [EEPROM_RSSI_A2] = 0x002b, 347 [EEPROM_TXPOWER_BG1] = 0x0030, 348 [EEPROM_TXPOWER_BG2] = 0x0037, 349 [EEPROM_EXT_TXPOWER_BG3] = 0x003e, 350 [EEPROM_TSSI_BOUND_BG1] = 0x0045, 351 [EEPROM_TSSI_BOUND_BG2] = 0x0046, 352 [EEPROM_TSSI_BOUND_BG3] = 0x0047, 353 [EEPROM_TSSI_BOUND_BG4] = 0x0048, 354 [EEPROM_TSSI_BOUND_BG5] = 0x0049, 355 [EEPROM_TXPOWER_A1] = 0x004b, 356 [EEPROM_TXPOWER_A2] = 0x0065, 357 [EEPROM_EXT_TXPOWER_A3] = 0x007f, 358 [EEPROM_TSSI_BOUND_A1] = 0x009a, 359 [EEPROM_TSSI_BOUND_A2] = 0x009b, 360 [EEPROM_TSSI_BOUND_A3] = 0x009c, 361 [EEPROM_TSSI_BOUND_A4] = 0x009d, 362 [EEPROM_TSSI_BOUND_A5] = 0x009e, 363 [EEPROM_TXPOWER_BYRATE] = 0x00a0, 364}; 365 366static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev, 367 const enum rt2800_eeprom_word word) 368{ 369 const unsigned int *map; 370 unsigned int index; 371 372 if (WARN_ONCE(word >= EEPROM_WORD_COUNT, 373 "%s: invalid EEPROM word %d\n", 374 wiphy_name(rt2x00dev->hw->wiphy), word)) 375 return 0; 376 377 if (rt2x00_rt(rt2x00dev, RT3593) || 378 rt2x00_rt(rt2x00dev, RT3883)) 379 map = rt2800_eeprom_map_ext; 380 else 381 map = rt2800_eeprom_map; 382 383 index = map[word]; 384 385 /* Index 0 is valid only for EEPROM_CHIP_ID. 386 * Otherwise it means that the offset of the 387 * given word is not initialized in the map, 388 * or that the field is not usable on the 389 * actual chipset. 390 */ 391 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0, 392 "%s: invalid access of EEPROM word %d\n", 393 wiphy_name(rt2x00dev->hw->wiphy), word); 394 395 return index; 396} 397 398static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev, 399 const enum rt2800_eeprom_word word) 400{ 401 unsigned int index; 402 403 index = rt2800_eeprom_word_index(rt2x00dev, word); 404 return rt2x00_eeprom_addr(rt2x00dev, index); 405} 406 407static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev, 408 const enum rt2800_eeprom_word word) 409{ 410 unsigned int index; 411 412 index = rt2800_eeprom_word_index(rt2x00dev, word); 413 return rt2x00_eeprom_read(rt2x00dev, index); 414} 415 416static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev, 417 const enum rt2800_eeprom_word word, u16 data) 418{ 419 unsigned int index; 420 421 index = rt2800_eeprom_word_index(rt2x00dev, word); 422 rt2x00_eeprom_write(rt2x00dev, index, data); 423} 424 425static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev, 426 const enum rt2800_eeprom_word array, 427 unsigned int offset) 428{ 429 unsigned int index; 430 431 index = rt2800_eeprom_word_index(rt2x00dev, array); 432 return rt2x00_eeprom_read(rt2x00dev, index + offset); 433} 434 435static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev) 436{ 437 u32 reg; 438 int i, count; 439 440 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 441 rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); 442 rt2x00_set_field32(®, FRC_WL_ANT_SET, 1); 443 rt2x00_set_field32(®, WLAN_CLK_EN, 0); 444 rt2x00_set_field32(®, WLAN_EN, 1); 445 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 446 447 udelay(REGISTER_BUSY_DELAY); 448 449 count = 0; 450 do { 451 /* 452 * Check PLL_LD & XTAL_RDY. 453 */ 454 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 455 reg = rt2800_register_read(rt2x00dev, CMB_CTRL); 456 if (rt2x00_get_field32(reg, PLL_LD) && 457 rt2x00_get_field32(reg, XTAL_RDY)) 458 break; 459 udelay(REGISTER_BUSY_DELAY); 460 } 461 462 if (i >= REGISTER_BUSY_COUNT) { 463 464 if (count >= 10) 465 return -EIO; 466 467 rt2800_register_write(rt2x00dev, 0x58, 0x018); 468 udelay(REGISTER_BUSY_DELAY); 469 rt2800_register_write(rt2x00dev, 0x58, 0x418); 470 udelay(REGISTER_BUSY_DELAY); 471 rt2800_register_write(rt2x00dev, 0x58, 0x618); 472 udelay(REGISTER_BUSY_DELAY); 473 count++; 474 } else { 475 count = 0; 476 } 477 478 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 479 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0); 480 rt2x00_set_field32(®, WLAN_CLK_EN, 1); 481 rt2x00_set_field32(®, WLAN_RESET, 1); 482 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 483 udelay(10); 484 rt2x00_set_field32(®, WLAN_RESET, 0); 485 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 486 udelay(10); 487 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff); 488 } while (count != 0); 489 490 return 0; 491} 492 493void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev, 494 const u8 command, const u8 token, 495 const u8 arg0, const u8 arg1) 496{ 497 u32 reg; 498 499 /* 500 * SOC devices don't support MCU requests. 501 */ 502 if (rt2x00_is_soc(rt2x00dev)) 503 return; 504 505 mutex_lock(&rt2x00dev->csr_mutex); 506 507 /* 508 * Wait until the MCU becomes available, afterwards we 509 * can safely write the new data into the register. 510 */ 511 if (WAIT_FOR_MCU(rt2x00dev, ®)) { 512 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); 513 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); 514 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); 515 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); 516 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); 517 518 reg = 0; 519 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); 520 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); 521 } 522 523 mutex_unlock(&rt2x00dev->csr_mutex); 524} 525EXPORT_SYMBOL_GPL(rt2800_mcu_request); 526 527int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev) 528{ 529 unsigned int i = 0; 530 u32 reg; 531 532 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 533 reg = rt2800_register_read(rt2x00dev, MAC_CSR0); 534 if (reg && reg != ~0) 535 return 0; 536 msleep(1); 537 } 538 539 rt2x00_err(rt2x00dev, "Unstable hardware\n"); 540 return -EBUSY; 541} 542EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready); 543 544int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) 545{ 546 unsigned int i; 547 u32 reg; 548 549 /* 550 * Some devices are really slow to respond here. Wait a whole second 551 * before timing out. 552 */ 553 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 554 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 555 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && 556 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) 557 return 0; 558 559 msleep(10); 560 } 561 562 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg); 563 return -EACCES; 564} 565EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready); 566 567void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev) 568{ 569 u32 reg; 570 571 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 572 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 573 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 574 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 575 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 576 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 577 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 578} 579EXPORT_SYMBOL_GPL(rt2800_disable_wpdma); 580 581void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev, 582 unsigned short *txwi_size, 583 unsigned short *rxwi_size) 584{ 585 switch (rt2x00dev->chip.rt) { 586 case RT3593: 587 case RT3883: 588 *txwi_size = TXWI_DESC_SIZE_4WORDS; 589 *rxwi_size = RXWI_DESC_SIZE_5WORDS; 590 break; 591 592 case RT5592: 593 case RT6352: 594 *txwi_size = TXWI_DESC_SIZE_5WORDS; 595 *rxwi_size = RXWI_DESC_SIZE_6WORDS; 596 break; 597 598 default: 599 *txwi_size = TXWI_DESC_SIZE_4WORDS; 600 *rxwi_size = RXWI_DESC_SIZE_4WORDS; 601 break; 602 } 603} 604EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size); 605 606static bool rt2800_check_firmware_crc(const u8 *data, const size_t len) 607{ 608 u16 fw_crc; 609 u16 crc; 610 611 /* 612 * The last 2 bytes in the firmware array are the crc checksum itself, 613 * this means that we should never pass those 2 bytes to the crc 614 * algorithm. 615 */ 616 fw_crc = (data[len - 2] << 8 | data[len - 1]); 617 618 /* 619 * Use the crc ccitt algorithm. 620 * This will return the same value as the legacy driver which 621 * used bit ordering reversion on the both the firmware bytes 622 * before input input as well as on the final output. 623 * Obviously using crc ccitt directly is much more efficient. 624 */ 625 crc = crc_ccitt(~0, data, len - 2); 626 627 /* 628 * There is a small difference between the crc-itu-t + bitrev and 629 * the crc-ccitt crc calculation. In the latter method the 2 bytes 630 * will be swapped, use swab16 to convert the crc to the correct 631 * value. 632 */ 633 crc = swab16(crc); 634 635 return fw_crc == crc; 636} 637 638int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev, 639 const u8 *data, const size_t len) 640{ 641 size_t offset = 0; 642 size_t fw_len; 643 bool multiple; 644 645 /* 646 * PCI(e) & SOC devices require firmware with a length 647 * of 8kb. USB devices require firmware files with a length 648 * of 4kb. Certain USB chipsets however require different firmware, 649 * which Ralink only provides attached to the original firmware 650 * file. Thus for USB devices, firmware files have a length 651 * which is a multiple of 4kb. The firmware for rt3290 chip also 652 * have a length which is a multiple of 4kb. 653 */ 654 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290)) 655 fw_len = 4096; 656 else 657 fw_len = 8192; 658 659 multiple = true; 660 /* 661 * Validate the firmware length 662 */ 663 if (len != fw_len && (!multiple || (len % fw_len) != 0)) 664 return FW_BAD_LENGTH; 665 666 /* 667 * Check if the chipset requires one of the upper parts 668 * of the firmware. 669 */ 670 if (rt2x00_is_usb(rt2x00dev) && 671 !rt2x00_rt(rt2x00dev, RT2860) && 672 !rt2x00_rt(rt2x00dev, RT2872) && 673 !rt2x00_rt(rt2x00dev, RT3070) && 674 ((len / fw_len) == 1)) 675 return FW_BAD_VERSION; 676 677 /* 678 * 8kb firmware files must be checked as if it were 679 * 2 separate firmware files. 680 */ 681 while (offset < len) { 682 if (!rt2800_check_firmware_crc(data + offset, fw_len)) 683 return FW_BAD_CRC; 684 685 offset += fw_len; 686 } 687 688 return FW_OK; 689} 690EXPORT_SYMBOL_GPL(rt2800_check_firmware); 691 692int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev, 693 const u8 *data, const size_t len) 694{ 695 unsigned int i; 696 u32 reg; 697 int retval; 698 699 if (rt2x00_rt(rt2x00dev, RT3290)) { 700 retval = rt2800_enable_wlan_rt3290(rt2x00dev); 701 if (retval) 702 return -EBUSY; 703 } 704 705 /* 706 * If driver doesn't wake up firmware here, 707 * rt2800_load_firmware will hang forever when interface is up again. 708 */ 709 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000); 710 711 /* 712 * Wait for stable hardware. 713 */ 714 if (rt2800_wait_csr_ready(rt2x00dev)) 715 return -EBUSY; 716 717 if (rt2x00_is_pci(rt2x00dev)) { 718 if (rt2x00_rt(rt2x00dev, RT3290) || 719 rt2x00_rt(rt2x00dev, RT3572) || 720 rt2x00_rt(rt2x00dev, RT5390) || 721 rt2x00_rt(rt2x00dev, RT5392)) { 722 reg = rt2800_register_read(rt2x00dev, AUX_CTRL); 723 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); 724 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); 725 rt2800_register_write(rt2x00dev, AUX_CTRL, reg); 726 } 727 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); 728 } 729 730 rt2800_disable_wpdma(rt2x00dev); 731 732 /* 733 * Write firmware to the device. 734 */ 735 rt2800_drv_write_firmware(rt2x00dev, data, len); 736 737 /* 738 * Wait for device to stabilize. 739 */ 740 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 741 reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL); 742 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) 743 break; 744 msleep(1); 745 } 746 747 if (i == REGISTER_BUSY_COUNT) { 748 rt2x00_err(rt2x00dev, "PBF system register not ready\n"); 749 return -EBUSY; 750 } 751 752 /* 753 * Disable DMA, will be reenabled later when enabling 754 * the radio. 755 */ 756 rt2800_disable_wpdma(rt2x00dev); 757 758 /* 759 * Initialize firmware. 760 */ 761 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 762 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 763 if (rt2x00_is_usb(rt2x00dev)) { 764 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 765 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 766 } 767 msleep(1); 768 769 return 0; 770} 771EXPORT_SYMBOL_GPL(rt2800_load_firmware); 772 773void rt2800_write_tx_data(struct queue_entry *entry, 774 struct txentry_desc *txdesc) 775{ 776 __le32 *txwi = rt2800_drv_get_txwi(entry); 777 u32 word; 778 int i; 779 780 /* 781 * Initialize TX Info descriptor 782 */ 783 word = rt2x00_desc_read(txwi, 0); 784 rt2x00_set_field32(&word, TXWI_W0_FRAG, 785 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 786 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 787 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags)); 788 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0); 789 rt2x00_set_field32(&word, TXWI_W0_TS, 790 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 791 rt2x00_set_field32(&word, TXWI_W0_AMPDU, 792 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags)); 793 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, 794 txdesc->u.ht.mpdu_density); 795 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop); 796 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs); 797 rt2x00_set_field32(&word, TXWI_W0_BW, 798 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags)); 799 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, 800 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags)); 801 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc); 802 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); 803 rt2x00_desc_write(txwi, 0, word); 804 805 word = rt2x00_desc_read(txwi, 1); 806 rt2x00_set_field32(&word, TXWI_W1_ACK, 807 test_bit(ENTRY_TXD_ACK, &txdesc->flags)); 808 rt2x00_set_field32(&word, TXWI_W1_NSEQ, 809 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); 810 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size); 811 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 812 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? 813 txdesc->key_idx : txdesc->u.ht.wcid); 814 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, 815 txdesc->length); 816 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid); 817 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1); 818 rt2x00_desc_write(txwi, 1, word); 819 820 /* 821 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert 822 * the IV from the IVEIV register when TXD_W3_WIV is set to 0. 823 * When TXD_W3_WIV is set to 1 it will use the IV data 824 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which 825 * crypto entry in the registers should be used to encrypt the frame. 826 * 827 * Nulify all remaining words as well, we don't know how to program them. 828 */ 829 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++) 830 _rt2x00_desc_write(txwi, i, 0); 831} 832EXPORT_SYMBOL_GPL(rt2800_write_tx_data); 833 834static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2) 835{ 836 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0); 837 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1); 838 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2); 839 u16 eeprom; 840 u8 offset0; 841 u8 offset1; 842 u8 offset2; 843 844 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 845 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG); 846 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0); 847 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1); 848 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 849 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2); 850 } else { 851 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A); 852 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0); 853 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1); 854 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 855 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2); 856 } 857 858 /* 859 * Convert the value from the descriptor into the RSSI value 860 * If the value in the descriptor is 0, it is considered invalid 861 * and the default (extremely low) rssi value is assumed 862 */ 863 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128; 864 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128; 865 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128; 866 867 /* 868 * mac80211 only accepts a single RSSI value. Calculating the 869 * average doesn't deliver a fair answer either since -60:-60 would 870 * be considered equally good as -50:-70 while the second is the one 871 * which gives less energy... 872 */ 873 rssi0 = max(rssi0, rssi1); 874 return (int)max(rssi0, rssi2); 875} 876 877void rt2800_process_rxwi(struct queue_entry *entry, 878 struct rxdone_entry_desc *rxdesc) 879{ 880 __le32 *rxwi = (__le32 *) entry->skb->data; 881 u32 word; 882 883 word = rt2x00_desc_read(rxwi, 0); 884 885 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF); 886 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT); 887 888 word = rt2x00_desc_read(rxwi, 1); 889 890 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI)) 891 rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI; 892 893 if (rt2x00_get_field32(word, RXWI_W1_BW)) 894 rxdesc->bw = RATE_INFO_BW_40; 895 896 /* 897 * Detect RX rate, always use MCS as signal type. 898 */ 899 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS; 900 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS); 901 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE); 902 903 /* 904 * Mask of 0x8 bit to remove the short preamble flag. 905 */ 906 if (rxdesc->rate_mode == RATE_MODE_CCK) 907 rxdesc->signal &= ~0x8; 908 909 word = rt2x00_desc_read(rxwi, 2); 910 911 /* 912 * Convert descriptor AGC value to RSSI value. 913 */ 914 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word); 915 /* 916 * Remove RXWI descriptor from start of the buffer. 917 */ 918 skb_pull(entry->skb, entry->queue->winfo_size); 919} 920EXPORT_SYMBOL_GPL(rt2800_process_rxwi); 921 922static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc, 923 u32 status, enum nl80211_band band) 924{ 925 u8 flags = 0; 926 u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS); 927 928 switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) { 929 case RATE_MODE_HT_GREENFIELD: 930 flags |= IEEE80211_TX_RC_GREEN_FIELD; 931 fallthrough; 932 case RATE_MODE_HT_MIX: 933 flags |= IEEE80211_TX_RC_MCS; 934 break; 935 case RATE_MODE_OFDM: 936 if (band == NL80211_BAND_2GHZ) 937 idx += 4; 938 break; 939 case RATE_MODE_CCK: 940 if (idx >= 8) 941 idx -= 8; 942 break; 943 } 944 945 if (rt2x00_get_field32(status, TX_STA_FIFO_BW)) 946 flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; 947 948 if (rt2x00_get_field32(status, TX_STA_FIFO_SGI)) 949 flags |= IEEE80211_TX_RC_SHORT_GI; 950 951 skbdesc->tx_rate_idx = idx; 952 skbdesc->tx_rate_flags = flags; 953} 954 955static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg) 956{ 957 __le32 *txwi; 958 u32 word; 959 int wcid, ack, pid; 960 int tx_wcid, tx_ack, tx_pid, is_agg; 961 962 /* 963 * This frames has returned with an IO error, 964 * so the status report is not intended for this 965 * frame. 966 */ 967 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) 968 return false; 969 970 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID); 971 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED); 972 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE); 973 is_agg = rt2x00_get_field32(reg, TX_STA_FIFO_TX_AGGRE); 974 975 /* 976 * Validate if this TX status report is intended for 977 * this entry by comparing the WCID/ACK/PID fields. 978 */ 979 txwi = rt2800_drv_get_txwi(entry); 980 981 word = rt2x00_desc_read(txwi, 1); 982 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID); 983 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK); 984 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID); 985 986 if (wcid != tx_wcid || ack != tx_ack || (!is_agg && pid != tx_pid)) { 987 rt2x00_dbg(entry->queue->rt2x00dev, 988 "TX status report missed for queue %d entry %d\n", 989 entry->queue->qid, entry->entry_idx); 990 return false; 991 } 992 993 return true; 994} 995 996void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi, 997 bool match) 998{ 999 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1000 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1001 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1002 struct txdone_entry_desc txdesc; 1003 u32 word; 1004 u16 mcs, real_mcs; 1005 int aggr, ampdu, wcid, ack_req; 1006 1007 /* 1008 * Obtain the status about this packet. 1009 */ 1010 txdesc.flags = 0; 1011 word = rt2x00_desc_read(txwi, 0); 1012 1013 mcs = rt2x00_get_field32(word, TXWI_W0_MCS); 1014 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU); 1015 1016 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS); 1017 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE); 1018 wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID); 1019 ack_req = rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED); 1020 1021 /* 1022 * If a frame was meant to be sent as a single non-aggregated MPDU 1023 * but ended up in an aggregate the used tx rate doesn't correlate 1024 * with the one specified in the TXWI as the whole aggregate is sent 1025 * with the same rate. 1026 * 1027 * For example: two frames are sent to rt2x00, the first one sets 1028 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0 1029 * and requests MCS15. If the hw aggregates both frames into one 1030 * AMDPU the tx status for both frames will contain MCS7 although 1031 * the frame was sent successfully. 1032 * 1033 * Hence, replace the requested rate with the real tx rate to not 1034 * confuse the rate control algortihm by providing clearly wrong 1035 * data. 1036 * 1037 * FIXME: if we do not find matching entry, we tell that frame was 1038 * posted without any retries. We need to find a way to fix that 1039 * and provide retry count. 1040 */ 1041 if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) { 1042 rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band); 1043 mcs = real_mcs; 1044 } 1045 1046 if (aggr == 1 || ampdu == 1) 1047 __set_bit(TXDONE_AMPDU, &txdesc.flags); 1048 1049 if (!ack_req) 1050 __set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags); 1051 1052 /* 1053 * Ralink has a retry mechanism using a global fallback 1054 * table. We setup this fallback table to try the immediate 1055 * lower rate for all rates. In the TX_STA_FIFO, the MCS field 1056 * always contains the MCS used for the last transmission, be 1057 * it successful or not. 1058 */ 1059 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) { 1060 /* 1061 * Transmission succeeded. The number of retries is 1062 * mcs - real_mcs 1063 */ 1064 __set_bit(TXDONE_SUCCESS, &txdesc.flags); 1065 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0); 1066 } else { 1067 /* 1068 * Transmission failed. The number of retries is 1069 * always 7 in this case (for a total number of 8 1070 * frames sent). 1071 */ 1072 __set_bit(TXDONE_FAILURE, &txdesc.flags); 1073 txdesc.retry = rt2x00dev->long_retry; 1074 } 1075 1076 /* 1077 * the frame was retried at least once 1078 * -> hw used fallback rates 1079 */ 1080 if (txdesc.retry) 1081 __set_bit(TXDONE_FALLBACK, &txdesc.flags); 1082 1083 if (!match) { 1084 /* RCU assures non-null sta will not be freed by mac80211. */ 1085 rcu_read_lock(); 1086 if (likely(wcid >= WCID_START && wcid <= WCID_END)) 1087 skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START]; 1088 else 1089 skbdesc->sta = NULL; 1090 rt2x00lib_txdone_nomatch(entry, &txdesc); 1091 rcu_read_unlock(); 1092 } else { 1093 rt2x00lib_txdone(entry, &txdesc); 1094 } 1095} 1096EXPORT_SYMBOL_GPL(rt2800_txdone_entry); 1097 1098void rt2800_txdone(struct rt2x00_dev *rt2x00dev, unsigned int quota) 1099{ 1100 struct data_queue *queue; 1101 struct queue_entry *entry; 1102 u32 reg; 1103 u8 qid; 1104 bool match; 1105 1106 while (quota-- > 0 && kfifo_get(&rt2x00dev->txstatus_fifo, ®)) { 1107 /* 1108 * TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus qid is 1109 * guaranteed to be one of the TX QIDs . 1110 */ 1111 qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE); 1112 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid); 1113 1114 if (unlikely(rt2x00queue_empty(queue))) { 1115 rt2x00_dbg(rt2x00dev, "Got TX status for an empty queue %u, dropping\n", 1116 qid); 1117 break; 1118 } 1119 1120 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1121 1122 if (unlikely(test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) || 1123 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))) { 1124 rt2x00_warn(rt2x00dev, "Data pending for entry %u in queue %u\n", 1125 entry->entry_idx, qid); 1126 break; 1127 } 1128 1129 match = rt2800_txdone_entry_check(entry, reg); 1130 rt2800_txdone_entry(entry, reg, rt2800_drv_get_txwi(entry), match); 1131 } 1132} 1133EXPORT_SYMBOL_GPL(rt2800_txdone); 1134 1135static inline bool rt2800_entry_txstatus_timeout(struct rt2x00_dev *rt2x00dev, 1136 struct queue_entry *entry) 1137{ 1138 bool ret; 1139 unsigned long tout; 1140 1141 if (!test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags)) 1142 return false; 1143 1144 if (test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags)) 1145 tout = msecs_to_jiffies(50); 1146 else 1147 tout = msecs_to_jiffies(2000); 1148 1149 ret = time_after(jiffies, entry->last_action + tout); 1150 if (unlikely(ret)) 1151 rt2x00_dbg(entry->queue->rt2x00dev, 1152 "TX status timeout for entry %d in queue %d\n", 1153 entry->entry_idx, entry->queue->qid); 1154 return ret; 1155} 1156 1157bool rt2800_txstatus_timeout(struct rt2x00_dev *rt2x00dev) 1158{ 1159 struct data_queue *queue; 1160 struct queue_entry *entry; 1161 1162 tx_queue_for_each(rt2x00dev, queue) { 1163 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1164 if (rt2800_entry_txstatus_timeout(rt2x00dev, entry)) 1165 return true; 1166 } 1167 1168 return false; 1169} 1170EXPORT_SYMBOL_GPL(rt2800_txstatus_timeout); 1171 1172/* 1173 * test if there is an entry in any TX queue for which DMA is done 1174 * but the TX status has not been returned yet 1175 */ 1176bool rt2800_txstatus_pending(struct rt2x00_dev *rt2x00dev) 1177{ 1178 struct data_queue *queue; 1179 1180 tx_queue_for_each(rt2x00dev, queue) { 1181 if (rt2x00queue_get_entry(queue, Q_INDEX_DMA_DONE) != 1182 rt2x00queue_get_entry(queue, Q_INDEX_DONE)) 1183 return true; 1184 } 1185 return false; 1186} 1187EXPORT_SYMBOL_GPL(rt2800_txstatus_pending); 1188 1189void rt2800_txdone_nostatus(struct rt2x00_dev *rt2x00dev) 1190{ 1191 struct data_queue *queue; 1192 struct queue_entry *entry; 1193 1194 /* 1195 * Process any trailing TX status reports for IO failures, 1196 * we loop until we find the first non-IO error entry. This 1197 * can either be a frame which is free, is being uploaded, 1198 * or has completed the upload but didn't have an entry 1199 * in the TX_STAT_FIFO register yet. 1200 */ 1201 tx_queue_for_each(rt2x00dev, queue) { 1202 while (!rt2x00queue_empty(queue)) { 1203 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1204 1205 if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) || 1206 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags)) 1207 break; 1208 1209 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags) || 1210 rt2800_entry_txstatus_timeout(rt2x00dev, entry)) 1211 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE); 1212 else 1213 break; 1214 } 1215 } 1216} 1217EXPORT_SYMBOL_GPL(rt2800_txdone_nostatus); 1218 1219static int rt2800_check_hung(struct data_queue *queue) 1220{ 1221 unsigned int cur_idx = rt2800_drv_get_dma_done(queue); 1222 1223 if (queue->wd_idx != cur_idx) 1224 queue->wd_count = 0; 1225 else 1226 queue->wd_count++; 1227 1228 return queue->wd_count > 16; 1229} 1230 1231void rt2800_watchdog(struct rt2x00_dev *rt2x00dev) 1232{ 1233 struct data_queue *queue; 1234 bool hung_tx = false; 1235 bool hung_rx = false; 1236 1237 if (test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) 1238 return; 1239 1240 queue_for_each(rt2x00dev, queue) { 1241 switch (queue->qid) { 1242 case QID_AC_VO: 1243 case QID_AC_VI: 1244 case QID_AC_BE: 1245 case QID_AC_BK: 1246 case QID_MGMT: 1247 if (rt2x00queue_empty(queue)) 1248 continue; 1249 hung_tx = rt2800_check_hung(queue); 1250 break; 1251 case QID_RX: 1252 /* For station mode we should reactive at least 1253 * beacons. TODO: need to find good way detect 1254 * RX hung for AP mode. 1255 */ 1256 if (rt2x00dev->intf_sta_count == 0) 1257 continue; 1258 hung_rx = rt2800_check_hung(queue); 1259 break; 1260 default: 1261 break; 1262 } 1263 } 1264 1265 if (hung_tx) 1266 rt2x00_warn(rt2x00dev, "Watchdog TX hung detected\n"); 1267 1268 if (hung_rx) 1269 rt2x00_warn(rt2x00dev, "Watchdog RX hung detected\n"); 1270 1271 if (hung_tx || hung_rx) 1272 ieee80211_restart_hw(rt2x00dev->hw); 1273} 1274EXPORT_SYMBOL_GPL(rt2800_watchdog); 1275 1276static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev, 1277 unsigned int index) 1278{ 1279 return HW_BEACON_BASE(index); 1280} 1281 1282static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev, 1283 unsigned int index) 1284{ 1285 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index)); 1286} 1287 1288static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev) 1289{ 1290 struct data_queue *queue = rt2x00dev->bcn; 1291 struct queue_entry *entry; 1292 int i, bcn_num = 0; 1293 u64 off, reg = 0; 1294 u32 bssid_dw1; 1295 1296 /* 1297 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers. 1298 */ 1299 for (i = 0; i < queue->limit; i++) { 1300 entry = &queue->entries[i]; 1301 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags)) 1302 continue; 1303 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx); 1304 reg |= off << (8 * bcn_num); 1305 bcn_num++; 1306 } 1307 1308 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg); 1309 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32)); 1310 1311 /* 1312 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons. 1313 */ 1314 bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1); 1315 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM, 1316 bcn_num > 0 ? bcn_num - 1 : 0); 1317 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1); 1318} 1319 1320void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) 1321{ 1322 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1323 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1324 unsigned int beacon_base; 1325 unsigned int padding_len; 1326 u32 orig_reg, reg; 1327 const int txwi_desc_size = entry->queue->winfo_size; 1328 1329 /* 1330 * Disable beaconing while we are reloading the beacon data, 1331 * otherwise we might be sending out invalid data. 1332 */ 1333 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1334 orig_reg = reg; 1335 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1336 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1337 1338 /* 1339 * Add space for the TXWI in front of the skb. 1340 */ 1341 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size); 1342 1343 /* 1344 * Register descriptor details in skb frame descriptor. 1345 */ 1346 skbdesc->flags |= SKBDESC_DESC_IN_SKB; 1347 skbdesc->desc = entry->skb->data; 1348 skbdesc->desc_len = txwi_desc_size; 1349 1350 /* 1351 * Add the TXWI for the beacon to the skb. 1352 */ 1353 rt2800_write_tx_data(entry, txdesc); 1354 1355 /* 1356 * Dump beacon to userspace through debugfs. 1357 */ 1358 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry); 1359 1360 /* 1361 * Write entire beacon with TXWI and padding to register. 1362 */ 1363 padding_len = roundup(entry->skb->len, 4) - entry->skb->len; 1364 if (padding_len && skb_pad(entry->skb, padding_len)) { 1365 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n"); 1366 /* skb freed by skb_pad() on failure */ 1367 entry->skb = NULL; 1368 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1369 return; 1370 } 1371 1372 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx); 1373 1374 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data, 1375 entry->skb->len + padding_len); 1376 __set_bit(ENTRY_BCN_ENABLED, &entry->flags); 1377 1378 /* 1379 * Change global beacons settings. 1380 */ 1381 rt2800_update_beacons_setup(rt2x00dev); 1382 1383 /* 1384 * Restore beaconing state. 1385 */ 1386 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1387 1388 /* 1389 * Clean up beacon skb. 1390 */ 1391 dev_kfree_skb_any(entry->skb); 1392 entry->skb = NULL; 1393} 1394EXPORT_SYMBOL_GPL(rt2800_write_beacon); 1395 1396static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev, 1397 unsigned int index) 1398{ 1399 int i; 1400 const int txwi_desc_size = rt2x00dev->bcn->winfo_size; 1401 unsigned int beacon_base; 1402 1403 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index); 1404 1405 /* 1406 * For the Beacon base registers we only need to clear 1407 * the whole TXWI which (when set to 0) will invalidate 1408 * the entire beacon. 1409 */ 1410 for (i = 0; i < txwi_desc_size; i += sizeof(__le32)) 1411 rt2800_register_write(rt2x00dev, beacon_base + i, 0); 1412} 1413 1414void rt2800_clear_beacon(struct queue_entry *entry) 1415{ 1416 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1417 u32 orig_reg, reg; 1418 1419 /* 1420 * Disable beaconing while we are reloading the beacon data, 1421 * otherwise we might be sending out invalid data. 1422 */ 1423 orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1424 reg = orig_reg; 1425 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1426 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1427 1428 /* 1429 * Clear beacon. 1430 */ 1431 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx); 1432 __clear_bit(ENTRY_BCN_ENABLED, &entry->flags); 1433 1434 /* 1435 * Change global beacons settings. 1436 */ 1437 rt2800_update_beacons_setup(rt2x00dev); 1438 /* 1439 * Restore beaconing state. 1440 */ 1441 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1442} 1443EXPORT_SYMBOL_GPL(rt2800_clear_beacon); 1444 1445#ifdef CONFIG_RT2X00_LIB_DEBUGFS 1446const struct rt2x00debug rt2800_rt2x00debug = { 1447 .owner = THIS_MODULE, 1448 .csr = { 1449 .read = rt2800_register_read, 1450 .write = rt2800_register_write, 1451 .flags = RT2X00DEBUGFS_OFFSET, 1452 .word_base = CSR_REG_BASE, 1453 .word_size = sizeof(u32), 1454 .word_count = CSR_REG_SIZE / sizeof(u32), 1455 }, 1456 .eeprom = { 1457 /* NOTE: The local EEPROM access functions can't 1458 * be used here, use the generic versions instead. 1459 */ 1460 .read = rt2x00_eeprom_read, 1461 .write = rt2x00_eeprom_write, 1462 .word_base = EEPROM_BASE, 1463 .word_size = sizeof(u16), 1464 .word_count = EEPROM_SIZE / sizeof(u16), 1465 }, 1466 .bbp = { 1467 .read = rt2800_bbp_read, 1468 .write = rt2800_bbp_write, 1469 .word_base = BBP_BASE, 1470 .word_size = sizeof(u8), 1471 .word_count = BBP_SIZE / sizeof(u8), 1472 }, 1473 .rf = { 1474 .read = rt2x00_rf_read, 1475 .write = rt2800_rf_write, 1476 .word_base = RF_BASE, 1477 .word_size = sizeof(u32), 1478 .word_count = RF_SIZE / sizeof(u32), 1479 }, 1480 .rfcsr = { 1481 .read = rt2800_rfcsr_read, 1482 .write = rt2800_rfcsr_write, 1483 .word_base = RFCSR_BASE, 1484 .word_size = sizeof(u8), 1485 .word_count = RFCSR_SIZE / sizeof(u8), 1486 }, 1487}; 1488EXPORT_SYMBOL_GPL(rt2800_rt2x00debug); 1489#endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 1490 1491int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev) 1492{ 1493 u32 reg; 1494 1495 if (rt2x00_rt(rt2x00dev, RT3290)) { 1496 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 1497 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0); 1498 } else { 1499 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 1500 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2); 1501 } 1502} 1503EXPORT_SYMBOL_GPL(rt2800_rfkill_poll); 1504 1505#ifdef CONFIG_RT2X00_LIB_LEDS 1506static void rt2800_brightness_set(struct led_classdev *led_cdev, 1507 enum led_brightness brightness) 1508{ 1509 struct rt2x00_led *led = 1510 container_of(led_cdev, struct rt2x00_led, led_dev); 1511 unsigned int enabled = brightness != LED_OFF; 1512 unsigned int bg_mode = 1513 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ); 1514 unsigned int polarity = 1515 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1516 EEPROM_FREQ_LED_POLARITY); 1517 unsigned int ledmode = 1518 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1519 EEPROM_FREQ_LED_MODE); 1520 u32 reg; 1521 1522 /* Check for SoC (SOC devices don't support MCU requests) */ 1523 if (rt2x00_is_soc(led->rt2x00dev)) { 1524 reg = rt2800_register_read(led->rt2x00dev, LED_CFG); 1525 1526 /* Set LED Polarity */ 1527 rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); 1528 1529 /* Set LED Mode */ 1530 if (led->type == LED_TYPE_RADIO) { 1531 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 1532 enabled ? 3 : 0); 1533 } else if (led->type == LED_TYPE_ASSOC) { 1534 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 1535 enabled ? 3 : 0); 1536 } else if (led->type == LED_TYPE_QUALITY) { 1537 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 1538 enabled ? 3 : 0); 1539 } 1540 1541 rt2800_register_write(led->rt2x00dev, LED_CFG, reg); 1542 1543 } else { 1544 if (led->type == LED_TYPE_RADIO) { 1545 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1546 enabled ? 0x20 : 0); 1547 } else if (led->type == LED_TYPE_ASSOC) { 1548 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1549 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20); 1550 } else if (led->type == LED_TYPE_QUALITY) { 1551 /* 1552 * The brightness is divided into 6 levels (0 - 5), 1553 * The specs tell us the following levels: 1554 * 0, 1 ,3, 7, 15, 31 1555 * to determine the level in a simple way we can simply 1556 * work with bitshifting: 1557 * (1 << level) - 1 1558 */ 1559 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, 1560 (1 << brightness / (LED_FULL / 6)) - 1, 1561 polarity); 1562 } 1563 } 1564} 1565 1566static void rt2800_init_led(struct rt2x00_dev *rt2x00dev, 1567 struct rt2x00_led *led, enum led_type type) 1568{ 1569 led->rt2x00dev = rt2x00dev; 1570 led->type = type; 1571 led->led_dev.brightness_set = rt2800_brightness_set; 1572 led->flags = LED_INITIALIZED; 1573} 1574#endif /* CONFIG_RT2X00_LIB_LEDS */ 1575 1576/* 1577 * Configuration handlers. 1578 */ 1579static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev, 1580 const u8 *address, 1581 int wcid) 1582{ 1583 struct mac_wcid_entry wcid_entry; 1584 u32 offset; 1585 1586 offset = MAC_WCID_ENTRY(wcid); 1587 1588 memset(&wcid_entry, 0xff, sizeof(wcid_entry)); 1589 if (address) 1590 memcpy(wcid_entry.mac, address, ETH_ALEN); 1591 1592 rt2800_register_multiwrite(rt2x00dev, offset, 1593 &wcid_entry, sizeof(wcid_entry)); 1594} 1595 1596static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid) 1597{ 1598 u32 offset; 1599 offset = MAC_WCID_ATTR_ENTRY(wcid); 1600 rt2800_register_write(rt2x00dev, offset, 0); 1601} 1602 1603static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev, 1604 int wcid, u32 bssidx) 1605{ 1606 u32 offset = MAC_WCID_ATTR_ENTRY(wcid); 1607 u32 reg; 1608 1609 /* 1610 * The BSS Idx numbers is split in a main value of 3 bits, 1611 * and a extended field for adding one additional bit to the value. 1612 */ 1613 reg = rt2800_register_read(rt2x00dev, offset); 1614 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); 1615 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, 1616 (bssidx & 0x8) >> 3); 1617 rt2800_register_write(rt2x00dev, offset, reg); 1618} 1619 1620static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev, 1621 struct rt2x00lib_crypto *crypto, 1622 struct ieee80211_key_conf *key) 1623{ 1624 struct mac_iveiv_entry iveiv_entry; 1625 u32 offset; 1626 u32 reg; 1627 1628 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx); 1629 1630 if (crypto->cmd == SET_KEY) { 1631 reg = rt2800_register_read(rt2x00dev, offset); 1632 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 1633 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); 1634 /* 1635 * Both the cipher as the BSS Idx numbers are split in a main 1636 * value of 3 bits, and a extended field for adding one additional 1637 * bit to the value. 1638 */ 1639 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 1640 (crypto->cipher & 0x7)); 1641 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 1642 (crypto->cipher & 0x8) >> 3); 1643 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); 1644 rt2800_register_write(rt2x00dev, offset, reg); 1645 } else { 1646 /* Delete the cipher without touching the bssidx */ 1647 reg = rt2800_register_read(rt2x00dev, offset); 1648 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); 1649 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); 1650 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); 1651 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); 1652 rt2800_register_write(rt2x00dev, offset, reg); 1653 } 1654 1655 if (test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags)) 1656 return; 1657 1658 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 1659 1660 memset(&iveiv_entry, 0, sizeof(iveiv_entry)); 1661 if ((crypto->cipher == CIPHER_TKIP) || 1662 (crypto->cipher == CIPHER_TKIP_NO_MIC) || 1663 (crypto->cipher == CIPHER_AES)) 1664 iveiv_entry.iv[3] |= 0x20; 1665 iveiv_entry.iv[3] |= key->keyidx << 6; 1666 rt2800_register_multiwrite(rt2x00dev, offset, 1667 &iveiv_entry, sizeof(iveiv_entry)); 1668} 1669 1670int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, 1671 struct rt2x00lib_crypto *crypto, 1672 struct ieee80211_key_conf *key) 1673{ 1674 struct hw_key_entry key_entry; 1675 struct rt2x00_field32 field; 1676 u32 offset; 1677 u32 reg; 1678 1679 if (crypto->cmd == SET_KEY) { 1680 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx; 1681 1682 memcpy(key_entry.key, crypto->key, 1683 sizeof(key_entry.key)); 1684 memcpy(key_entry.tx_mic, crypto->tx_mic, 1685 sizeof(key_entry.tx_mic)); 1686 memcpy(key_entry.rx_mic, crypto->rx_mic, 1687 sizeof(key_entry.rx_mic)); 1688 1689 offset = SHARED_KEY_ENTRY(key->hw_key_idx); 1690 rt2800_register_multiwrite(rt2x00dev, offset, 1691 &key_entry, sizeof(key_entry)); 1692 } 1693 1694 /* 1695 * The cipher types are stored over multiple registers 1696 * starting with SHARED_KEY_MODE_BASE each word will have 1697 * 32 bits and contains the cipher types for 2 bssidx each. 1698 * Using the correct defines correctly will cause overhead, 1699 * so just calculate the correct offset. 1700 */ 1701 field.bit_offset = 4 * (key->hw_key_idx % 8); 1702 field.bit_mask = 0x7 << field.bit_offset; 1703 1704 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8); 1705 1706 reg = rt2800_register_read(rt2x00dev, offset); 1707 rt2x00_set_field32(®, field, 1708 (crypto->cmd == SET_KEY) * crypto->cipher); 1709 rt2800_register_write(rt2x00dev, offset, reg); 1710 1711 /* 1712 * Update WCID information 1713 */ 1714 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx); 1715 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx, 1716 crypto->bssidx); 1717 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1718 1719 return 0; 1720} 1721EXPORT_SYMBOL_GPL(rt2800_config_shared_key); 1722 1723int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, 1724 struct rt2x00lib_crypto *crypto, 1725 struct ieee80211_key_conf *key) 1726{ 1727 struct hw_key_entry key_entry; 1728 u32 offset; 1729 1730 if (crypto->cmd == SET_KEY) { 1731 /* 1732 * Allow key configuration only for STAs that are 1733 * known by the hw. 1734 */ 1735 if (crypto->wcid > WCID_END) 1736 return -ENOSPC; 1737 key->hw_key_idx = crypto->wcid; 1738 1739 memcpy(key_entry.key, crypto->key, 1740 sizeof(key_entry.key)); 1741 memcpy(key_entry.tx_mic, crypto->tx_mic, 1742 sizeof(key_entry.tx_mic)); 1743 memcpy(key_entry.rx_mic, crypto->rx_mic, 1744 sizeof(key_entry.rx_mic)); 1745 1746 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx); 1747 rt2800_register_multiwrite(rt2x00dev, offset, 1748 &key_entry, sizeof(key_entry)); 1749 } 1750 1751 /* 1752 * Update WCID information 1753 */ 1754 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1755 1756 return 0; 1757} 1758EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key); 1759 1760static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev) 1761{ 1762 u8 i, max_psdu; 1763 u32 reg; 1764 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1765 1766 for (i = 0; i < 3; i++) 1767 if (drv_data->ampdu_factor_cnt[i] > 0) 1768 break; 1769 1770 max_psdu = min(drv_data->max_psdu, i); 1771 1772 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); 1773 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, max_psdu); 1774 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 1775} 1776 1777int rt2800_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1778 struct ieee80211_sta *sta) 1779{ 1780 struct rt2x00_dev *rt2x00dev = hw->priv; 1781 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1782 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1783 int wcid; 1784 1785 /* 1786 * Limit global maximum TX AMPDU length to smallest value of all 1787 * connected stations. In AP mode this can be suboptimal, but we 1788 * do not have a choice if some connected STA is not capable to 1789 * receive the same amount of data like the others. 1790 */ 1791 if (sta->ht_cap.ht_supported) { 1792 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]++; 1793 rt2800_set_max_psdu_len(rt2x00dev); 1794 } 1795 1796 /* 1797 * Search for the first free WCID entry and return the corresponding 1798 * index. 1799 */ 1800 wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START; 1801 1802 /* 1803 * Store selected wcid even if it is invalid so that we can 1804 * later decide if the STA is uploaded into the hw. 1805 */ 1806 sta_priv->wcid = wcid; 1807 1808 /* 1809 * No space left in the device, however, we can still communicate 1810 * with the STA -> No error. 1811 */ 1812 if (wcid > WCID_END) 1813 return 0; 1814 1815 __set_bit(wcid - WCID_START, drv_data->sta_ids); 1816 drv_data->wcid_to_sta[wcid - WCID_START] = sta; 1817 1818 /* 1819 * Clean up WCID attributes and write STA address to the device. 1820 */ 1821 rt2800_delete_wcid_attr(rt2x00dev, wcid); 1822 rt2800_config_wcid(rt2x00dev, sta->addr, wcid); 1823 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid, 1824 rt2x00lib_get_bssidx(rt2x00dev, vif)); 1825 return 0; 1826} 1827EXPORT_SYMBOL_GPL(rt2800_sta_add); 1828 1829int rt2800_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1830 struct ieee80211_sta *sta) 1831{ 1832 struct rt2x00_dev *rt2x00dev = hw->priv; 1833 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1834 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1835 int wcid = sta_priv->wcid; 1836 1837 if (sta->ht_cap.ht_supported) { 1838 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]--; 1839 rt2800_set_max_psdu_len(rt2x00dev); 1840 } 1841 1842 if (wcid > WCID_END) 1843 return 0; 1844 /* 1845 * Remove WCID entry, no need to clean the attributes as they will 1846 * get renewed when the WCID is reused. 1847 */ 1848 rt2800_config_wcid(rt2x00dev, NULL, wcid); 1849 drv_data->wcid_to_sta[wcid - WCID_START] = NULL; 1850 __clear_bit(wcid - WCID_START, drv_data->sta_ids); 1851 1852 return 0; 1853} 1854EXPORT_SYMBOL_GPL(rt2800_sta_remove); 1855 1856void rt2800_pre_reset_hw(struct rt2x00_dev *rt2x00dev) 1857{ 1858 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1859 struct data_queue *queue = rt2x00dev->bcn; 1860 struct queue_entry *entry; 1861 int i, wcid; 1862 1863 for (wcid = WCID_START; wcid < WCID_END; wcid++) { 1864 drv_data->wcid_to_sta[wcid - WCID_START] = NULL; 1865 __clear_bit(wcid - WCID_START, drv_data->sta_ids); 1866 } 1867 1868 for (i = 0; i < queue->limit; i++) { 1869 entry = &queue->entries[i]; 1870 clear_bit(ENTRY_BCN_ASSIGNED, &entry->flags); 1871 } 1872} 1873EXPORT_SYMBOL_GPL(rt2800_pre_reset_hw); 1874 1875void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, 1876 const unsigned int filter_flags) 1877{ 1878 u32 reg; 1879 1880 /* 1881 * Start configuration steps. 1882 * Note that the version error will always be dropped 1883 * and broadcast frames will always be accepted since 1884 * there is no filter for it at this time. 1885 */ 1886 reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG); 1887 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, 1888 !(filter_flags & FIF_FCSFAIL)); 1889 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, 1890 !(filter_flags & FIF_PLCPFAIL)); 1891 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, 1892 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags)); 1893 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); 1894 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); 1895 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, 1896 !(filter_flags & FIF_ALLMULTI)); 1897 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); 1898 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); 1899 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, 1900 !(filter_flags & FIF_CONTROL)); 1901 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, 1902 !(filter_flags & FIF_CONTROL)); 1903 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, 1904 !(filter_flags & FIF_CONTROL)); 1905 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, 1906 !(filter_flags & FIF_CONTROL)); 1907 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, 1908 !(filter_flags & FIF_CONTROL)); 1909 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, 1910 !(filter_flags & FIF_PSPOLL)); 1911 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0); 1912 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, 1913 !(filter_flags & FIF_CONTROL)); 1914 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, 1915 !(filter_flags & FIF_CONTROL)); 1916 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); 1917} 1918EXPORT_SYMBOL_GPL(rt2800_config_filter); 1919 1920void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, 1921 struct rt2x00intf_conf *conf, const unsigned int flags) 1922{ 1923 u32 reg; 1924 bool update_bssid = false; 1925 1926 if (flags & CONFIG_UPDATE_TYPE) { 1927 /* 1928 * Enable synchronisation. 1929 */ 1930 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1931 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); 1932 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1933 1934 if (conf->sync == TSF_SYNC_AP_NONE) { 1935 /* 1936 * Tune beacon queue transmit parameters for AP mode 1937 */ 1938 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); 1939 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); 1940 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); 1941 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1942 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); 1943 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1944 } else { 1945 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); 1946 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); 1947 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); 1948 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1949 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16); 1950 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1951 } 1952 } 1953 1954 if (flags & CONFIG_UPDATE_MAC) { 1955 if (flags & CONFIG_UPDATE_TYPE && 1956 conf->sync == TSF_SYNC_AP_NONE) { 1957 /* 1958 * The BSSID register has to be set to our own mac 1959 * address in AP mode. 1960 */ 1961 memcpy(conf->bssid, conf->mac, sizeof(conf->mac)); 1962 update_bssid = true; 1963 } 1964 1965 if (!is_zero_ether_addr((const u8 *)conf->mac)) { 1966 reg = le32_to_cpu(conf->mac[1]); 1967 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); 1968 conf->mac[1] = cpu_to_le32(reg); 1969 } 1970 1971 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0, 1972 conf->mac, sizeof(conf->mac)); 1973 } 1974 1975 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) { 1976 if (!is_zero_ether_addr((const u8 *)conf->bssid)) { 1977 reg = le32_to_cpu(conf->bssid[1]); 1978 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3); 1979 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0); 1980 conf->bssid[1] = cpu_to_le32(reg); 1981 } 1982 1983 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0, 1984 conf->bssid, sizeof(conf->bssid)); 1985 } 1986} 1987EXPORT_SYMBOL_GPL(rt2800_config_intf); 1988 1989static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev, 1990 struct rt2x00lib_erp *erp) 1991{ 1992 bool any_sta_nongf = !!(erp->ht_opmode & 1993 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); 1994 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION; 1995 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode; 1996 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate; 1997 u32 reg; 1998 1999 /* default protection rate for HT20: OFDM 24M */ 2000 mm20_rate = gf20_rate = 0x4004; 2001 2002 /* default protection rate for HT40: duplicate OFDM 24M */ 2003 mm40_rate = gf40_rate = 0x4084; 2004 2005 switch (protection) { 2006 case IEEE80211_HT_OP_MODE_PROTECTION_NONE: 2007 /* 2008 * All STAs in this BSS are HT20/40 but there might be 2009 * STAs not supporting greenfield mode. 2010 * => Disable protection for HT transmissions. 2011 */ 2012 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0; 2013 2014 break; 2015 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: 2016 /* 2017 * All STAs in this BSS are HT20 or HT20/40 but there 2018 * might be STAs not supporting greenfield mode. 2019 * => Protect all HT40 transmissions. 2020 */ 2021 mm20_mode = gf20_mode = 0; 2022 mm40_mode = gf40_mode = 1; 2023 2024 break; 2025 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER: 2026 /* 2027 * Nonmember protection: 2028 * According to 802.11n we _should_ protect all 2029 * HT transmissions (but we don't have to). 2030 * 2031 * But if cts_protection is enabled we _shall_ protect 2032 * all HT transmissions using a CCK rate. 2033 * 2034 * And if any station is non GF we _shall_ protect 2035 * GF transmissions. 2036 * 2037 * We decide to protect everything 2038 * -> fall through to mixed mode. 2039 */ 2040 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: 2041 /* 2042 * Legacy STAs are present 2043 * => Protect all HT transmissions. 2044 */ 2045 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1; 2046 2047 /* 2048 * If erp protection is needed we have to protect HT 2049 * transmissions with CCK 11M long preamble. 2050 */ 2051 if (erp->cts_protection) { 2052 /* don't duplicate RTS/CTS in CCK mode */ 2053 mm20_rate = mm40_rate = 0x0003; 2054 gf20_rate = gf40_rate = 0x0003; 2055 } 2056 break; 2057 } 2058 2059 /* check for STAs not supporting greenfield mode */ 2060 if (any_sta_nongf) 2061 gf20_mode = gf40_mode = 1; 2062 2063 /* Update HT protection config */ 2064 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 2065 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); 2066 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); 2067 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 2068 2069 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 2070 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); 2071 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); 2072 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 2073 2074 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 2075 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); 2076 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); 2077 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 2078 2079 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 2080 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); 2081 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); 2082 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 2083} 2084 2085void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp, 2086 u32 changed) 2087{ 2088 u32 reg; 2089 2090 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 2091 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); 2092 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 2093 !!erp->short_preamble); 2094 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 2095 } 2096 2097 if (changed & BSS_CHANGED_ERP_CTS_PROT) { 2098 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 2099 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 2100 erp->cts_protection ? 2 : 0); 2101 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 2102 } 2103 2104 if (changed & BSS_CHANGED_BASIC_RATES) { 2105 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 2106 0xff0 | erp->basic_rates); 2107 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 2108 } 2109 2110 if (changed & BSS_CHANGED_ERP_SLOT) { 2111 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); 2112 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 2113 erp->slot_time); 2114 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 2115 2116 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); 2117 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); 2118 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 2119 } 2120 2121 if (changed & BSS_CHANGED_BEACON_INT) { 2122 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 2123 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 2124 erp->beacon_int * 16); 2125 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 2126 } 2127 2128 if (changed & BSS_CHANGED_HT) 2129 rt2800_config_ht_opmode(rt2x00dev, erp); 2130} 2131EXPORT_SYMBOL_GPL(rt2800_config_erp); 2132 2133static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev) 2134{ 2135 u32 reg; 2136 u16 eeprom; 2137 u8 led_ctrl, led_g_mode, led_r_mode; 2138 2139 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 2140 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { 2141 rt2x00_set_field32(®, GPIO_SWITCH_0, 1); 2142 rt2x00_set_field32(®, GPIO_SWITCH_1, 1); 2143 } else { 2144 rt2x00_set_field32(®, GPIO_SWITCH_0, 0); 2145 rt2x00_set_field32(®, GPIO_SWITCH_1, 0); 2146 } 2147 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 2148 2149 reg = rt2800_register_read(rt2x00dev, LED_CFG); 2150 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0; 2151 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3; 2152 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) || 2153 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) { 2154 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 2155 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE); 2156 if (led_ctrl == 0 || led_ctrl > 0x40) { 2157 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); 2158 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode); 2159 rt2800_register_write(rt2x00dev, LED_CFG, reg); 2160 } else { 2161 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff, 2162 (led_g_mode << 2) | led_r_mode, 1); 2163 } 2164 } 2165} 2166 2167static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev, 2168 enum antenna ant) 2169{ 2170 u32 reg; 2171 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0; 2172 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1; 2173 2174 if (rt2x00_is_pci(rt2x00dev)) { 2175 reg = rt2800_register_read(rt2x00dev, E2PROM_CSR); 2176 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); 2177 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); 2178 } else if (rt2x00_is_usb(rt2x00dev)) 2179 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff, 2180 eesk_pin, 0); 2181 2182 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 2183 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 2184 rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3); 2185 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 2186} 2187 2188void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) 2189{ 2190 u8 r1; 2191 u8 r3; 2192 u16 eeprom; 2193 2194 r1 = rt2800_bbp_read(rt2x00dev, 1); 2195 r3 = rt2800_bbp_read(rt2x00dev, 3); 2196 2197 if (rt2x00_rt(rt2x00dev, RT3572) && 2198 rt2x00_has_cap_bt_coexist(rt2x00dev)) 2199 rt2800_config_3572bt_ant(rt2x00dev); 2200 2201 /* 2202 * Configure the TX antenna. 2203 */ 2204 switch (ant->tx_chain_num) { 2205 case 1: 2206 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); 2207 break; 2208 case 2: 2209 if (rt2x00_rt(rt2x00dev, RT3572) && 2210 rt2x00_has_cap_bt_coexist(rt2x00dev)) 2211 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1); 2212 else 2213 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 2214 break; 2215 case 3: 2216 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 2217 break; 2218 } 2219 2220 /* 2221 * Configure the RX antenna. 2222 */ 2223 switch (ant->rx_chain_num) { 2224 case 1: 2225 if (rt2x00_rt(rt2x00dev, RT3070) || 2226 rt2x00_rt(rt2x00dev, RT3090) || 2227 rt2x00_rt(rt2x00dev, RT3352) || 2228 rt2x00_rt(rt2x00dev, RT3390)) { 2229 eeprom = rt2800_eeprom_read(rt2x00dev, 2230 EEPROM_NIC_CONF1); 2231 if (rt2x00_get_field16(eeprom, 2232 EEPROM_NIC_CONF1_ANT_DIVERSITY)) 2233 rt2800_set_ant_diversity(rt2x00dev, 2234 rt2x00dev->default_ant.rx); 2235 } 2236 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); 2237 break; 2238 case 2: 2239 if (rt2x00_rt(rt2x00dev, RT3572) && 2240 rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2241 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1); 2242 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2243 rt2x00dev->curr_band == NL80211_BAND_5GHZ); 2244 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B); 2245 } else { 2246 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1); 2247 } 2248 break; 2249 case 3: 2250 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2); 2251 break; 2252 } 2253 2254 rt2800_bbp_write(rt2x00dev, 3, r3); 2255 rt2800_bbp_write(rt2x00dev, 1, r1); 2256 2257 if (rt2x00_rt(rt2x00dev, RT3593) || 2258 rt2x00_rt(rt2x00dev, RT3883)) { 2259 if (ant->rx_chain_num == 1) 2260 rt2800_bbp_write(rt2x00dev, 86, 0x00); 2261 else 2262 rt2800_bbp_write(rt2x00dev, 86, 0x46); 2263 } 2264} 2265EXPORT_SYMBOL_GPL(rt2800_config_ant); 2266 2267static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev, 2268 struct rt2x00lib_conf *libconf) 2269{ 2270 u16 eeprom; 2271 short lna_gain; 2272 2273 if (libconf->rf.channel <= 14) { 2274 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 2275 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG); 2276 } else if (libconf->rf.channel <= 64) { 2277 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 2278 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0); 2279 } else if (libconf->rf.channel <= 128) { 2280 if (rt2x00_rt(rt2x00dev, RT3593) || 2281 rt2x00_rt(rt2x00dev, RT3883)) { 2282 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 2283 lna_gain = rt2x00_get_field16(eeprom, 2284 EEPROM_EXT_LNA2_A1); 2285 } else { 2286 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 2287 lna_gain = rt2x00_get_field16(eeprom, 2288 EEPROM_RSSI_BG2_LNA_A1); 2289 } 2290 } else { 2291 if (rt2x00_rt(rt2x00dev, RT3593) || 2292 rt2x00_rt(rt2x00dev, RT3883)) { 2293 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 2294 lna_gain = rt2x00_get_field16(eeprom, 2295 EEPROM_EXT_LNA2_A2); 2296 } else { 2297 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 2298 lna_gain = rt2x00_get_field16(eeprom, 2299 EEPROM_RSSI_A2_LNA_A2); 2300 } 2301 } 2302 2303 rt2x00dev->lna_gain = lna_gain; 2304} 2305 2306static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev) 2307{ 2308 return clk_get_rate(rt2x00dev->clk) == 20000000; 2309} 2310 2311#define FREQ_OFFSET_BOUND 0x5f 2312 2313static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev) 2314{ 2315 u8 freq_offset, prev_freq_offset; 2316 u8 rfcsr, prev_rfcsr; 2317 2318 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE); 2319 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND); 2320 2321 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 2322 prev_rfcsr = rfcsr; 2323 2324 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset); 2325 if (rfcsr == prev_rfcsr) 2326 return; 2327 2328 if (rt2x00_is_usb(rt2x00dev)) { 2329 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff, 2330 freq_offset, prev_rfcsr); 2331 return; 2332 } 2333 2334 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE); 2335 while (prev_freq_offset != freq_offset) { 2336 if (prev_freq_offset < freq_offset) 2337 prev_freq_offset++; 2338 else 2339 prev_freq_offset--; 2340 2341 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset); 2342 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 2343 2344 usleep_range(1000, 1500); 2345 } 2346} 2347 2348static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev, 2349 struct ieee80211_conf *conf, 2350 struct rf_channel *rf, 2351 struct channel_info *info) 2352{ 2353 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); 2354 2355 if (rt2x00dev->default_ant.tx_chain_num == 1) 2356 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); 2357 2358 if (rt2x00dev->default_ant.rx_chain_num == 1) { 2359 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); 2360 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 2361 } else if (rt2x00dev->default_ant.rx_chain_num == 2) 2362 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 2363 2364 if (rf->channel > 14) { 2365 /* 2366 * When TX power is below 0, we should increase it by 7 to 2367 * make it a positive value (Minimum value is -7). 2368 * However this means that values between 0 and 7 have 2369 * double meaning, and we should set a 7DBm boost flag. 2370 */ 2371 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, 2372 (info->default_power1 >= 0)); 2373 2374 if (info->default_power1 < 0) 2375 info->default_power1 += 7; 2376 2377 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1); 2378 2379 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, 2380 (info->default_power2 >= 0)); 2381 2382 if (info->default_power2 < 0) 2383 info->default_power2 += 7; 2384 2385 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2); 2386 } else { 2387 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1); 2388 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2); 2389 } 2390 2391 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); 2392 2393 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2394 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2395 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2396 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2397 2398 udelay(200); 2399 2400 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2401 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2402 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); 2403 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2404 2405 udelay(200); 2406 2407 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2408 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2409 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2410 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2411} 2412 2413static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev, 2414 struct ieee80211_conf *conf, 2415 struct rf_channel *rf, 2416 struct channel_info *info) 2417{ 2418 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2419 u8 rfcsr, calib_tx, calib_rx; 2420 2421 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2422 2423 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 2424 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3); 2425 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 2426 2427 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2428 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2429 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2430 2431 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2432 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1); 2433 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2434 2435 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 2436 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2); 2437 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2438 2439 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2440 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2441 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 2442 rt2x00dev->default_ant.rx_chain_num <= 1); 2443 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 2444 rt2x00dev->default_ant.rx_chain_num <= 2); 2445 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2446 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 2447 rt2x00dev->default_ant.tx_chain_num <= 1); 2448 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 2449 rt2x00dev->default_ant.tx_chain_num <= 2); 2450 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2451 2452 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23); 2453 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2454 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2455 2456 if (rt2x00_rt(rt2x00dev, RT3390)) { 2457 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f; 2458 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f; 2459 } else { 2460 if (conf_is_ht40(conf)) { 2461 calib_tx = drv_data->calibration_bw40; 2462 calib_rx = drv_data->calibration_bw40; 2463 } else { 2464 calib_tx = drv_data->calibration_bw20; 2465 calib_rx = drv_data->calibration_bw20; 2466 } 2467 } 2468 2469 rfcsr = rt2800_rfcsr_read(rt2x00dev, 24); 2470 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx); 2471 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr); 2472 2473 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31); 2474 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx); 2475 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2476 2477 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2478 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2479 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2480 2481 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2482 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); 2483 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2484 2485 usleep_range(1000, 1500); 2486 2487 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); 2488 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2489} 2490 2491static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, 2492 struct ieee80211_conf *conf, 2493 struct rf_channel *rf, 2494 struct channel_info *info) 2495{ 2496 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2497 u8 rfcsr; 2498 u32 reg; 2499 2500 if (rf->channel <= 14) { 2501 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2502 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2503 } else { 2504 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2505 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2506 } 2507 2508 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2509 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); 2510 2511 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2512 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2513 if (rf->channel <= 14) 2514 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2); 2515 else 2516 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1); 2517 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2518 2519 rfcsr = rt2800_rfcsr_read(rt2x00dev, 5); 2520 if (rf->channel <= 14) 2521 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1); 2522 else 2523 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2); 2524 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr); 2525 2526 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2527 if (rf->channel <= 14) { 2528 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3); 2529 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2530 info->default_power1); 2531 } else { 2532 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7); 2533 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2534 (info->default_power1 & 0x3) | 2535 ((info->default_power1 & 0xC) << 1)); 2536 } 2537 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2538 2539 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 2540 if (rf->channel <= 14) { 2541 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3); 2542 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2543 info->default_power2); 2544 } else { 2545 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7); 2546 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2547 (info->default_power2 & 0x3) | 2548 ((info->default_power2 & 0xC) << 1)); 2549 } 2550 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2551 2552 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2553 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2554 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2555 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2556 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2557 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2558 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2559 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2560 if (rf->channel <= 14) { 2561 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2562 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2563 } 2564 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2565 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2566 } else { 2567 switch (rt2x00dev->default_ant.tx_chain_num) { 2568 case 1: 2569 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2570 fallthrough; 2571 case 2: 2572 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2573 break; 2574 } 2575 2576 switch (rt2x00dev->default_ant.rx_chain_num) { 2577 case 1: 2578 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2579 fallthrough; 2580 case 2: 2581 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2582 break; 2583 } 2584 } 2585 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2586 2587 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23); 2588 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2589 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2590 2591 if (conf_is_ht40(conf)) { 2592 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40); 2593 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40); 2594 } else { 2595 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20); 2596 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20); 2597 } 2598 2599 if (rf->channel <= 14) { 2600 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 2601 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 2602 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2603 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 2604 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 2605 rfcsr = 0x4c; 2606 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2607 drv_data->txmixer_gain_24g); 2608 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2609 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2610 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 2611 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 2612 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 2613 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 2614 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 2615 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 2616 } else { 2617 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2618 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1); 2619 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0); 2620 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1); 2621 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0); 2622 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2623 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 2624 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2625 rt2800_rfcsr_write(rt2x00dev, 11, 0x00); 2626 rt2800_rfcsr_write(rt2x00dev, 15, 0x43); 2627 rfcsr = 0x7a; 2628 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2629 drv_data->txmixer_gain_5g); 2630 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2631 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2632 if (rf->channel <= 64) { 2633 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7); 2634 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6); 2635 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 2636 } else if (rf->channel <= 128) { 2637 rt2800_rfcsr_write(rt2x00dev, 19, 0x74); 2638 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4); 2639 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2640 } else { 2641 rt2800_rfcsr_write(rt2x00dev, 19, 0x72); 2642 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3); 2643 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2644 } 2645 rt2800_rfcsr_write(rt2x00dev, 26, 0x87); 2646 rt2800_rfcsr_write(rt2x00dev, 27, 0x01); 2647 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f); 2648 } 2649 2650 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 2651 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 2652 if (rf->channel <= 14) 2653 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 2654 else 2655 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0); 2656 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 2657 2658 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2659 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2660 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2661} 2662 2663static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, 2664 struct ieee80211_conf *conf, 2665 struct rf_channel *rf, 2666 struct channel_info *info) 2667{ 2668 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2669 u8 txrx_agc_fc; 2670 u8 txrx_h20m; 2671 u8 rfcsr; 2672 u8 bbp; 2673 const bool txbf_enabled = false; /* TODO */ 2674 2675 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */ 2676 bbp = rt2800_bbp_read(rt2x00dev, 109); 2677 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0); 2678 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0); 2679 rt2800_bbp_write(rt2x00dev, 109, bbp); 2680 2681 bbp = rt2800_bbp_read(rt2x00dev, 110); 2682 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0); 2683 rt2800_bbp_write(rt2x00dev, 110, bbp); 2684 2685 if (rf->channel <= 14) { 2686 /* Restore BBP 25 & 26 for 2.4 GHz */ 2687 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2688 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2689 } else { 2690 /* Hard code BBP 25 & 26 for 5GHz */ 2691 2692 /* Enable IQ Phase correction */ 2693 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2694 /* Setup IQ Phase correction value */ 2695 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2696 } 2697 2698 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2699 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf); 2700 2701 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2702 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3)); 2703 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2704 2705 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2706 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1); 2707 if (rf->channel <= 14) 2708 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1); 2709 else 2710 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2); 2711 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2712 2713 rfcsr = rt2800_rfcsr_read(rt2x00dev, 53); 2714 if (rf->channel <= 14) { 2715 rfcsr = 0; 2716 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2717 info->default_power1 & 0x1f); 2718 } else { 2719 if (rt2x00_is_usb(rt2x00dev)) 2720 rfcsr = 0x40; 2721 2722 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2723 ((info->default_power1 & 0x18) << 1) | 2724 (info->default_power1 & 7)); 2725 } 2726 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr); 2727 2728 rfcsr = rt2800_rfcsr_read(rt2x00dev, 55); 2729 if (rf->channel <= 14) { 2730 rfcsr = 0; 2731 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2732 info->default_power2 & 0x1f); 2733 } else { 2734 if (rt2x00_is_usb(rt2x00dev)) 2735 rfcsr = 0x40; 2736 2737 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2738 ((info->default_power2 & 0x18) << 1) | 2739 (info->default_power2 & 7)); 2740 } 2741 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr); 2742 2743 rfcsr = rt2800_rfcsr_read(rt2x00dev, 54); 2744 if (rf->channel <= 14) { 2745 rfcsr = 0; 2746 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2747 info->default_power3 & 0x1f); 2748 } else { 2749 if (rt2x00_is_usb(rt2x00dev)) 2750 rfcsr = 0x40; 2751 2752 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2753 ((info->default_power3 & 0x18) << 1) | 2754 (info->default_power3 & 7)); 2755 } 2756 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr); 2757 2758 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2759 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2760 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2761 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2762 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2763 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2764 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2765 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 2766 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 2767 2768 switch (rt2x00dev->default_ant.tx_chain_num) { 2769 case 3: 2770 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2771 fallthrough; 2772 case 2: 2773 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2774 fallthrough; 2775 case 1: 2776 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2777 break; 2778 } 2779 2780 switch (rt2x00dev->default_ant.rx_chain_num) { 2781 case 3: 2782 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2783 fallthrough; 2784 case 2: 2785 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2786 fallthrough; 2787 case 1: 2788 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2789 break; 2790 } 2791 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2792 2793 rt2800_freq_cal_mode1(rt2x00dev); 2794 2795 if (conf_is_ht40(conf)) { 2796 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40, 2797 RFCSR24_TX_AGC_FC); 2798 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40, 2799 RFCSR24_TX_H20M); 2800 } else { 2801 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20, 2802 RFCSR24_TX_AGC_FC); 2803 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20, 2804 RFCSR24_TX_H20M); 2805 } 2806 2807 /* NOTE: the reference driver does not writes the new value 2808 * back to RFCSR 32 2809 */ 2810 rfcsr = rt2800_rfcsr_read(rt2x00dev, 32); 2811 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc); 2812 2813 if (rf->channel <= 14) 2814 rfcsr = 0xa0; 2815 else 2816 rfcsr = 0x80; 2817 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2818 2819 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2820 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m); 2821 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m); 2822 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2823 2824 /* Band selection */ 2825 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36); 2826 if (rf->channel <= 14) 2827 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1); 2828 else 2829 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0); 2830 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr); 2831 2832 rfcsr = rt2800_rfcsr_read(rt2x00dev, 34); 2833 if (rf->channel <= 14) 2834 rfcsr = 0x3c; 2835 else 2836 rfcsr = 0x20; 2837 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 2838 2839 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2840 if (rf->channel <= 14) 2841 rfcsr = 0x1a; 2842 else 2843 rfcsr = 0x12; 2844 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2845 2846 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2847 if (rf->channel >= 1 && rf->channel <= 14) 2848 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2849 else if (rf->channel >= 36 && rf->channel <= 64) 2850 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2851 else if (rf->channel >= 100 && rf->channel <= 128) 2852 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2853 else 2854 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2855 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2856 2857 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2858 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 2859 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2860 2861 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 2862 2863 if (rf->channel <= 14) { 2864 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 2865 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 2866 } else { 2867 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8); 2868 rt2800_rfcsr_write(rt2x00dev, 13, 0x23); 2869 } 2870 2871 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 2872 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1); 2873 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2874 2875 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 2876 if (rf->channel <= 14) { 2877 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5); 2878 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3); 2879 } else { 2880 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4); 2881 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2); 2882 } 2883 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2884 2885 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 2886 if (rf->channel <= 14) 2887 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3); 2888 else 2889 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2); 2890 2891 if (txbf_enabled) 2892 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1); 2893 2894 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2895 2896 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 2897 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0); 2898 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 2899 2900 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57); 2901 if (rf->channel <= 14) 2902 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b); 2903 else 2904 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f); 2905 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr); 2906 2907 if (rf->channel <= 14) { 2908 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 2909 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 2910 } else { 2911 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b); 2912 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 2913 } 2914 2915 /* Initiate VCO calibration */ 2916 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 2917 if (rf->channel <= 14) { 2918 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 2919 } else { 2920 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1); 2921 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1); 2922 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1); 2923 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1); 2924 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1); 2925 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 2926 } 2927 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 2928 2929 if (rf->channel >= 1 && rf->channel <= 14) { 2930 rfcsr = 0x23; 2931 if (txbf_enabled) 2932 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2933 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2934 2935 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 2936 } else if (rf->channel >= 36 && rf->channel <= 64) { 2937 rfcsr = 0x36; 2938 if (txbf_enabled) 2939 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2940 rt2800_rfcsr_write(rt2x00dev, 39, 0x36); 2941 2942 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb); 2943 } else if (rf->channel >= 100 && rf->channel <= 128) { 2944 rfcsr = 0x32; 2945 if (txbf_enabled) 2946 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2947 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2948 2949 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3); 2950 } else { 2951 rfcsr = 0x30; 2952 if (txbf_enabled) 2953 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2954 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2955 2956 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b); 2957 } 2958} 2959 2960static void rt2800_config_channel_rf3853(struct rt2x00_dev *rt2x00dev, 2961 struct ieee80211_conf *conf, 2962 struct rf_channel *rf, 2963 struct channel_info *info) 2964{ 2965 u8 rfcsr; 2966 u8 bbp; 2967 u8 pwr1, pwr2, pwr3; 2968 2969 const bool txbf_enabled = false; /* TODO */ 2970 2971 /* TODO: add band selection */ 2972 2973 if (rf->channel <= 14) 2974 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 2975 else if (rf->channel < 132) 2976 rt2800_rfcsr_write(rt2x00dev, 6, 0x80); 2977 else 2978 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 2979 2980 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2981 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 2982 2983 if (rf->channel <= 14) 2984 rt2800_rfcsr_write(rt2x00dev, 11, 0x46); 2985 else 2986 rt2800_rfcsr_write(rt2x00dev, 11, 0x48); 2987 2988 if (rf->channel <= 14) 2989 rt2800_rfcsr_write(rt2x00dev, 12, 0x1a); 2990 else 2991 rt2800_rfcsr_write(rt2x00dev, 12, 0x52); 2992 2993 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 2994 2995 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2996 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2997 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2998 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2999 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 3000 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 3001 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 3002 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 3003 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3004 3005 switch (rt2x00dev->default_ant.tx_chain_num) { 3006 case 3: 3007 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 3008 fallthrough; 3009 case 2: 3010 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 3011 fallthrough; 3012 case 1: 3013 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 3014 break; 3015 } 3016 3017 switch (rt2x00dev->default_ant.rx_chain_num) { 3018 case 3: 3019 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 3020 fallthrough; 3021 case 2: 3022 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 3023 fallthrough; 3024 case 1: 3025 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 3026 break; 3027 } 3028 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3029 3030 rt2800_freq_cal_mode1(rt2x00dev); 3031 3032 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 3033 if (!conf_is_ht40(conf)) 3034 rfcsr &= ~(0x06); 3035 else 3036 rfcsr |= 0x06; 3037 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 3038 3039 if (rf->channel <= 14) 3040 rt2800_rfcsr_write(rt2x00dev, 31, 0xa0); 3041 else 3042 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 3043 3044 if (conf_is_ht40(conf)) 3045 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 3046 else 3047 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8); 3048 3049 if (rf->channel <= 14) 3050 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c); 3051 else 3052 rt2800_rfcsr_write(rt2x00dev, 34, 0x20); 3053 3054 /* loopback RF_BS */ 3055 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36); 3056 if (rf->channel <= 14) 3057 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1); 3058 else 3059 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0); 3060 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr); 3061 3062 if (rf->channel <= 14) 3063 rfcsr = 0x23; 3064 else if (rf->channel < 100) 3065 rfcsr = 0x36; 3066 else if (rf->channel < 132) 3067 rfcsr = 0x32; 3068 else 3069 rfcsr = 0x30; 3070 3071 if (txbf_enabled) 3072 rfcsr |= 0x40; 3073 3074 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 3075 3076 if (rf->channel <= 14) 3077 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 3078 else 3079 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b); 3080 3081 if (rf->channel <= 14) 3082 rfcsr = 0xbb; 3083 else if (rf->channel < 100) 3084 rfcsr = 0xeb; 3085 else if (rf->channel < 132) 3086 rfcsr = 0xb3; 3087 else 3088 rfcsr = 0x9b; 3089 rt2800_rfcsr_write(rt2x00dev, 45, rfcsr); 3090 3091 if (rf->channel <= 14) 3092 rfcsr = 0x8e; 3093 else 3094 rfcsr = 0x8a; 3095 3096 if (txbf_enabled) 3097 rfcsr |= 0x20; 3098 3099 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3100 3101 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 3102 3103 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 3104 if (rf->channel <= 14) 3105 rt2800_rfcsr_write(rt2x00dev, 51, 0x75); 3106 else 3107 rt2800_rfcsr_write(rt2x00dev, 51, 0x51); 3108 3109 rfcsr = rt2800_rfcsr_read(rt2x00dev, 52); 3110 if (rf->channel <= 14) 3111 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 3112 else 3113 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 3114 3115 if (rf->channel <= 14) { 3116 pwr1 = info->default_power1 & 0x1f; 3117 pwr2 = info->default_power2 & 0x1f; 3118 pwr3 = info->default_power3 & 0x1f; 3119 } else { 3120 pwr1 = 0x48 | ((info->default_power1 & 0x18) << 1) | 3121 (info->default_power1 & 0x7); 3122 pwr2 = 0x48 | ((info->default_power2 & 0x18) << 1) | 3123 (info->default_power2 & 0x7); 3124 pwr3 = 0x48 | ((info->default_power3 & 0x18) << 1) | 3125 (info->default_power3 & 0x7); 3126 } 3127 3128 rt2800_rfcsr_write(rt2x00dev, 53, pwr1); 3129 rt2800_rfcsr_write(rt2x00dev, 54, pwr2); 3130 rt2800_rfcsr_write(rt2x00dev, 55, pwr3); 3131 3132 rt2x00_dbg(rt2x00dev, "Channel:%d, pwr1:%02x, pwr2:%02x, pwr3:%02x\n", 3133 rf->channel, pwr1, pwr2, pwr3); 3134 3135 bbp = (info->default_power1 >> 5) | 3136 ((info->default_power2 & 0xe0) >> 1); 3137 rt2800_bbp_write(rt2x00dev, 109, bbp); 3138 3139 bbp = rt2800_bbp_read(rt2x00dev, 110); 3140 bbp &= 0x0f; 3141 bbp |= (info->default_power3 & 0xe0) >> 1; 3142 rt2800_bbp_write(rt2x00dev, 110, bbp); 3143 3144 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57); 3145 if (rf->channel <= 14) 3146 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e); 3147 else 3148 rt2800_rfcsr_write(rt2x00dev, 57, 0x3e); 3149 3150 /* Enable RF tuning */ 3151 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 3152 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3153 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3154 3155 udelay(2000); 3156 3157 bbp = rt2800_bbp_read(rt2x00dev, 49); 3158 /* clear update flag */ 3159 rt2800_bbp_write(rt2x00dev, 49, bbp & 0xfe); 3160 rt2800_bbp_write(rt2x00dev, 49, bbp); 3161 3162 /* TODO: add calibration for TxBF */ 3163} 3164 3165#define POWER_BOUND 0x27 3166#define POWER_BOUND_5G 0x2b 3167 3168static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev, 3169 struct ieee80211_conf *conf, 3170 struct rf_channel *rf, 3171 struct channel_info *info) 3172{ 3173 u8 rfcsr; 3174 3175 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 3176 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 3177 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 3178 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 3179 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 3180 3181 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 3182 if (info->default_power1 > POWER_BOUND) 3183 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 3184 else 3185 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 3186 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3187 3188 rt2800_freq_cal_mode1(rt2x00dev); 3189 3190 if (rf->channel <= 14) { 3191 if (rf->channel == 6) 3192 rt2800_bbp_write(rt2x00dev, 68, 0x0c); 3193 else 3194 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 3195 3196 if (rf->channel >= 1 && rf->channel <= 6) 3197 rt2800_bbp_write(rt2x00dev, 59, 0x0f); 3198 else if (rf->channel >= 7 && rf->channel <= 11) 3199 rt2800_bbp_write(rt2x00dev, 59, 0x0e); 3200 else if (rf->channel >= 12 && rf->channel <= 14) 3201 rt2800_bbp_write(rt2x00dev, 59, 0x0d); 3202 } 3203} 3204 3205static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev, 3206 struct ieee80211_conf *conf, 3207 struct rf_channel *rf, 3208 struct channel_info *info) 3209{ 3210 u8 rfcsr; 3211 3212 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 3213 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 3214 3215 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 3216 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 3217 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 3218 3219 if (info->default_power1 > POWER_BOUND) 3220 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND); 3221 else 3222 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1); 3223 3224 if (info->default_power2 > POWER_BOUND) 3225 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND); 3226 else 3227 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2); 3228 3229 rt2800_freq_cal_mode1(rt2x00dev); 3230 3231 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3232 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 3233 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 3234 3235 if ( rt2x00dev->default_ant.tx_chain_num == 2 ) 3236 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 3237 else 3238 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 3239 3240 if ( rt2x00dev->default_ant.rx_chain_num == 2 ) 3241 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 3242 else 3243 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 3244 3245 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 3246 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 3247 3248 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3249 3250 rt2800_rfcsr_write(rt2x00dev, 31, 80); 3251} 3252 3253static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, 3254 struct ieee80211_conf *conf, 3255 struct rf_channel *rf, 3256 struct channel_info *info) 3257{ 3258 u8 rfcsr; 3259 int idx = rf->channel-1; 3260 3261 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 3262 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 3263 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 3264 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 3265 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 3266 3267 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 3268 if (info->default_power1 > POWER_BOUND) 3269 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 3270 else 3271 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 3272 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3273 3274 if (rt2x00_rt(rt2x00dev, RT5392)) { 3275 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 3276 if (info->default_power2 > POWER_BOUND) 3277 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND); 3278 else 3279 rt2x00_set_field8(&rfcsr, RFCSR50_TX, 3280 info->default_power2); 3281 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 3282 } 3283 3284 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3285 if (rt2x00_rt(rt2x00dev, RT5392)) { 3286 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 3287 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 3288 } 3289 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 3290 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3291 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 3292 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 3293 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3294 3295 rt2800_freq_cal_mode1(rt2x00dev); 3296 3297 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 3298 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 3299 /* r55/r59 value array of channel 1~14 */ 3300 static const char r55_bt_rev[] = {0x83, 0x83, 3301 0x83, 0x73, 0x73, 0x63, 0x53, 0x53, 3302 0x53, 0x43, 0x43, 0x43, 0x43, 0x43}; 3303 static const char r59_bt_rev[] = {0x0e, 0x0e, 3304 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09, 3305 0x07, 0x07, 0x07, 0x07, 0x07, 0x07}; 3306 3307 rt2800_rfcsr_write(rt2x00dev, 55, 3308 r55_bt_rev[idx]); 3309 rt2800_rfcsr_write(rt2x00dev, 59, 3310 r59_bt_rev[idx]); 3311 } else { 3312 static const char r59_bt[] = {0x8b, 0x8b, 0x8b, 3313 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89, 3314 0x88, 0x88, 0x86, 0x85, 0x84}; 3315 3316 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]); 3317 } 3318 } else { 3319 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 3320 static const char r55_nonbt_rev[] = {0x23, 0x23, 3321 0x23, 0x23, 0x13, 0x13, 0x03, 0x03, 3322 0x03, 0x03, 0x03, 0x03, 0x03, 0x03}; 3323 static const char r59_nonbt_rev[] = {0x07, 0x07, 3324 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 3325 0x07, 0x07, 0x06, 0x05, 0x04, 0x04}; 3326 3327 rt2800_rfcsr_write(rt2x00dev, 55, 3328 r55_nonbt_rev[idx]); 3329 rt2800_rfcsr_write(rt2x00dev, 59, 3330 r59_nonbt_rev[idx]); 3331 } else if (rt2x00_rt(rt2x00dev, RT5390) || 3332 rt2x00_rt(rt2x00dev, RT5392) || 3333 rt2x00_rt(rt2x00dev, RT6352)) { 3334 static const char r59_non_bt[] = {0x8f, 0x8f, 3335 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d, 3336 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86}; 3337 3338 rt2800_rfcsr_write(rt2x00dev, 59, 3339 r59_non_bt[idx]); 3340 } else if (rt2x00_rt(rt2x00dev, RT5350)) { 3341 static const char r59_non_bt[] = {0x0b, 0x0b, 3342 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a, 3343 0x0a, 0x09, 0x08, 0x07, 0x07, 0x06}; 3344 3345 rt2800_rfcsr_write(rt2x00dev, 59, 3346 r59_non_bt[idx]); 3347 } 3348 } 3349} 3350 3351static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev, 3352 struct ieee80211_conf *conf, 3353 struct rf_channel *rf, 3354 struct channel_info *info) 3355{ 3356 u8 rfcsr, ep_reg; 3357 u32 reg; 3358 int power_bound; 3359 3360 /* TODO */ 3361 const bool is_11b = false; 3362 const bool is_type_ep = false; 3363 3364 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 3365 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3366 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0); 3367 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 3368 3369 /* Order of values on rf_channel entry: N, K, mod, R */ 3370 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff); 3371 3372 rfcsr = rt2800_rfcsr_read(rt2x00dev, 9); 3373 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf); 3374 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8); 3375 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2); 3376 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr); 3377 3378 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 3379 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1); 3380 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3); 3381 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 3382 3383 if (rf->channel <= 14) { 3384 rt2800_rfcsr_write(rt2x00dev, 10, 0x90); 3385 /* FIXME: RF11 owerwrite ? */ 3386 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A); 3387 rt2800_rfcsr_write(rt2x00dev, 12, 0x52); 3388 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 3389 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 3390 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A); 3391 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 3392 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 3393 rt2800_rfcsr_write(rt2x00dev, 36, 0x80); 3394 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 3395 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 3396 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B); 3397 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D); 3398 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B); 3399 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5); 3400 rt2800_rfcsr_write(rt2x00dev, 43, 0x72); 3401 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E); 3402 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2); 3403 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B); 3404 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 3405 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E); 3406 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 3407 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 3408 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1); 3409 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 3410 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 3411 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 3412 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 3413 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 3414 3415 /* TODO RF27 <- tssi */ 3416 3417 rfcsr = rf->channel <= 10 ? 0x07 : 0x06; 3418 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 3419 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr); 3420 3421 if (is_11b) { 3422 /* CCK */ 3423 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8); 3424 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0); 3425 if (is_type_ep) 3426 rt2800_rfcsr_write(rt2x00dev, 55, 0x06); 3427 else 3428 rt2800_rfcsr_write(rt2x00dev, 55, 0x47); 3429 } else { 3430 /* OFDM */ 3431 if (is_type_ep) 3432 rt2800_rfcsr_write(rt2x00dev, 55, 0x03); 3433 else 3434 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 3435 } 3436 3437 power_bound = POWER_BOUND; 3438 ep_reg = 0x2; 3439 } else { 3440 rt2800_rfcsr_write(rt2x00dev, 10, 0x97); 3441 /* FIMXE: RF11 overwrite */ 3442 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 3443 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF); 3444 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 3445 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 3446 rt2800_rfcsr_write(rt2x00dev, 37, 0x04); 3447 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 3448 rt2800_rfcsr_write(rt2x00dev, 40, 0x42); 3449 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB); 3450 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7); 3451 rt2800_rfcsr_write(rt2x00dev, 45, 0x41); 3452 rt2800_rfcsr_write(rt2x00dev, 48, 0x00); 3453 rt2800_rfcsr_write(rt2x00dev, 57, 0x77); 3454 rt2800_rfcsr_write(rt2x00dev, 60, 0x05); 3455 rt2800_rfcsr_write(rt2x00dev, 61, 0x01); 3456 3457 /* TODO RF27 <- tssi */ 3458 3459 if (rf->channel >= 36 && rf->channel <= 64) { 3460 3461 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E); 3462 rt2800_rfcsr_write(rt2x00dev, 13, 0x22); 3463 rt2800_rfcsr_write(rt2x00dev, 22, 0x60); 3464 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F); 3465 if (rf->channel <= 50) 3466 rt2800_rfcsr_write(rt2x00dev, 24, 0x09); 3467 else if (rf->channel >= 52) 3468 rt2800_rfcsr_write(rt2x00dev, 24, 0x07); 3469 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C); 3470 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B); 3471 rt2800_rfcsr_write(rt2x00dev, 44, 0X40); 3472 rt2800_rfcsr_write(rt2x00dev, 46, 0X00); 3473 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE); 3474 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C); 3475 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8); 3476 if (rf->channel <= 50) { 3477 rt2800_rfcsr_write(rt2x00dev, 55, 0x06), 3478 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3); 3479 } else if (rf->channel >= 52) { 3480 rt2800_rfcsr_write(rt2x00dev, 55, 0x04); 3481 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 3482 } 3483 3484 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 3485 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F); 3486 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 3487 3488 } else if (rf->channel >= 100 && rf->channel <= 165) { 3489 3490 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E); 3491 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 3492 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 3493 if (rf->channel <= 153) { 3494 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C); 3495 rt2800_rfcsr_write(rt2x00dev, 24, 0x06); 3496 } else if (rf->channel >= 155) { 3497 rt2800_rfcsr_write(rt2x00dev, 23, 0x38); 3498 rt2800_rfcsr_write(rt2x00dev, 24, 0x05); 3499 } 3500 if (rf->channel <= 138) { 3501 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A); 3502 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B); 3503 rt2800_rfcsr_write(rt2x00dev, 44, 0x20); 3504 rt2800_rfcsr_write(rt2x00dev, 46, 0x18); 3505 } else if (rf->channel >= 140) { 3506 rt2800_rfcsr_write(rt2x00dev, 39, 0x18); 3507 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B); 3508 rt2800_rfcsr_write(rt2x00dev, 44, 0x10); 3509 rt2800_rfcsr_write(rt2x00dev, 46, 0X08); 3510 } 3511 if (rf->channel <= 124) 3512 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC); 3513 else if (rf->channel >= 126) 3514 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC); 3515 if (rf->channel <= 138) 3516 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 3517 else if (rf->channel >= 140) 3518 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 3519 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB); 3520 if (rf->channel <= 138) 3521 rt2800_rfcsr_write(rt2x00dev, 55, 0x01); 3522 else if (rf->channel >= 140) 3523 rt2800_rfcsr_write(rt2x00dev, 55, 0x00); 3524 if (rf->channel <= 128) 3525 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 3526 else if (rf->channel >= 130) 3527 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB); 3528 if (rf->channel <= 116) 3529 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D); 3530 else if (rf->channel >= 118) 3531 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 3532 if (rf->channel <= 138) 3533 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F); 3534 else if (rf->channel >= 140) 3535 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C); 3536 if (rf->channel <= 116) 3537 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D); 3538 else if (rf->channel >= 118) 3539 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 3540 } 3541 3542 power_bound = POWER_BOUND_5G; 3543 ep_reg = 0x3; 3544 } 3545 3546 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 3547 if (info->default_power1 > power_bound) 3548 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound); 3549 else 3550 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 3551 if (is_type_ep) 3552 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg); 3553 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3554 3555 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 3556 if (info->default_power2 > power_bound) 3557 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound); 3558 else 3559 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2); 3560 if (is_type_ep) 3561 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg); 3562 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 3563 3564 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3565 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 3566 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3567 3568 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 3569 rt2x00dev->default_ant.tx_chain_num >= 1); 3570 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 3571 rt2x00dev->default_ant.tx_chain_num == 2); 3572 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 3573 3574 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 3575 rt2x00dev->default_ant.rx_chain_num >= 1); 3576 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 3577 rt2x00dev->default_ant.rx_chain_num == 2); 3578 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 3579 3580 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3581 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4); 3582 3583 if (conf_is_ht40(conf)) 3584 rt2800_rfcsr_write(rt2x00dev, 30, 0x16); 3585 else 3586 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 3587 3588 if (!is_11b) { 3589 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 3590 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 3591 } 3592 3593 /* TODO proper frequency adjustment */ 3594 rt2800_freq_cal_mode1(rt2x00dev); 3595 3596 /* TODO merge with others */ 3597 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 3598 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3599 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3600 3601 /* BBP settings */ 3602 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3603 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3604 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3605 3606 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18); 3607 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08); 3608 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38); 3609 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92); 3610 3611 /* GLRT band configuration */ 3612 rt2800_bbp_write(rt2x00dev, 195, 128); 3613 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0); 3614 rt2800_bbp_write(rt2x00dev, 195, 129); 3615 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E); 3616 rt2800_bbp_write(rt2x00dev, 195, 130); 3617 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28); 3618 rt2800_bbp_write(rt2x00dev, 195, 131); 3619 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20); 3620 rt2800_bbp_write(rt2x00dev, 195, 133); 3621 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F); 3622 rt2800_bbp_write(rt2x00dev, 195, 124); 3623 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F); 3624} 3625 3626static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev, 3627 struct ieee80211_conf *conf, 3628 struct rf_channel *rf, 3629 struct channel_info *info) 3630{ 3631 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 3632 u8 rx_agc_fc, tx_agc_fc; 3633 u8 rfcsr; 3634 3635 /* Frequeny plan setting */ 3636 /* Rdiv setting (set 0x03 if Xtal==20) 3637 * R13[1:0] 3638 */ 3639 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 3640 rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620, 3641 rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0); 3642 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 3643 3644 /* N setting 3645 * R20[7:0] in rf->rf1 3646 * R21[0] always 0 3647 */ 3648 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 3649 rfcsr = (rf->rf1 & 0x00ff); 3650 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 3651 3652 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 3653 rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0); 3654 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 3655 3656 /* K setting (always 0) 3657 * R16[3:0] (RF PLL freq selection) 3658 */ 3659 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16); 3660 rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0); 3661 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 3662 3663 /* D setting (always 0) 3664 * R22[2:0] (D=15, R22[2:0]=<111>) 3665 */ 3666 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 3667 rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0); 3668 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 3669 3670 /* Ksd setting 3671 * Ksd: R17<7:0> in rf->rf2 3672 * R18<7:0> in rf->rf3 3673 * R19<1:0> in rf->rf4 3674 */ 3675 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 3676 rfcsr = rf->rf2; 3677 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 3678 3679 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18); 3680 rfcsr = rf->rf3; 3681 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); 3682 3683 rfcsr = rt2800_rfcsr_read(rt2x00dev, 19); 3684 rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4); 3685 rt2800_rfcsr_write(rt2x00dev, 19, rfcsr); 3686 3687 /* Default: XO=20MHz , SDM mode */ 3688 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16); 3689 rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80); 3690 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 3691 3692 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 3693 rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1); 3694 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 3695 3696 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3697 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620, 3698 rt2x00dev->default_ant.tx_chain_num != 1); 3699 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3700 3701 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 3702 rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620, 3703 rt2x00dev->default_ant.tx_chain_num != 1); 3704 rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620, 3705 rt2x00dev->default_ant.rx_chain_num != 1); 3706 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 3707 3708 rfcsr = rt2800_rfcsr_read(rt2x00dev, 42); 3709 rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620, 3710 rt2x00dev->default_ant.tx_chain_num != 1); 3711 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); 3712 3713 /* RF for DC Cal BW */ 3714 if (conf_is_ht40(conf)) { 3715 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10); 3716 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10); 3717 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04); 3718 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10); 3719 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10); 3720 } else { 3721 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20); 3722 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20); 3723 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00); 3724 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20); 3725 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20); 3726 } 3727 3728 if (conf_is_ht40(conf)) { 3729 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08); 3730 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08); 3731 } else { 3732 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28); 3733 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28); 3734 } 3735 3736 rfcsr = rt2800_rfcsr_read(rt2x00dev, 28); 3737 rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40, 3738 conf_is_ht40(conf) && (rf->channel == 11)); 3739 rt2800_rfcsr_write(rt2x00dev, 28, rfcsr); 3740 3741 if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) { 3742 if (conf_is_ht40(conf)) { 3743 rx_agc_fc = drv_data->rx_calibration_bw40; 3744 tx_agc_fc = drv_data->tx_calibration_bw40; 3745 } else { 3746 rx_agc_fc = drv_data->rx_calibration_bw20; 3747 tx_agc_fc = drv_data->tx_calibration_bw20; 3748 } 3749 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 3750 rfcsr &= (~0x3F); 3751 rfcsr |= rx_agc_fc; 3752 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr); 3753 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 3754 rfcsr &= (~0x3F); 3755 rfcsr |= rx_agc_fc; 3756 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr); 3757 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6); 3758 rfcsr &= (~0x3F); 3759 rfcsr |= rx_agc_fc; 3760 rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr); 3761 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7); 3762 rfcsr &= (~0x3F); 3763 rfcsr |= rx_agc_fc; 3764 rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr); 3765 3766 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 3767 rfcsr &= (~0x3F); 3768 rfcsr |= tx_agc_fc; 3769 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr); 3770 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 3771 rfcsr &= (~0x3F); 3772 rfcsr |= tx_agc_fc; 3773 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr); 3774 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58); 3775 rfcsr &= (~0x3F); 3776 rfcsr |= tx_agc_fc; 3777 rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr); 3778 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59); 3779 rfcsr &= (~0x3F); 3780 rfcsr |= tx_agc_fc; 3781 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr); 3782 } 3783} 3784 3785static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev, 3786 struct ieee80211_channel *chan, 3787 int power_level) { 3788 u16 eeprom, target_power, max_power; 3789 u32 mac_sys_ctrl, mac_status; 3790 u32 reg; 3791 u8 bbp; 3792 int i; 3793 3794 /* hardware unit is 0.5dBm, limited to 23.5dBm */ 3795 power_level *= 2; 3796 if (power_level > 0x2f) 3797 power_level = 0x2f; 3798 3799 max_power = chan->max_power * 2; 3800 if (max_power > 0x2f) 3801 max_power = 0x2f; 3802 3803 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0); 3804 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, power_level); 3805 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, power_level); 3806 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_0, max_power); 3807 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_1, max_power); 3808 3809 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 3810 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) { 3811 /* init base power by eeprom target power */ 3812 target_power = rt2800_eeprom_read(rt2x00dev, 3813 EEPROM_TXPOWER_INIT); 3814 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, target_power); 3815 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, target_power); 3816 } 3817 rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg); 3818 3819 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); 3820 rt2x00_set_field32(®, TX_ALC_CFG_1_TX_TEMP_COMP, 0); 3821 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); 3822 3823 /* Save MAC SYS CTRL registers */ 3824 mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 3825 /* Disable Tx/Rx */ 3826 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0); 3827 /* Check MAC Tx/Rx idle */ 3828 for (i = 0; i < 10000; i++) { 3829 mac_status = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG); 3830 if (mac_status & 0x3) 3831 usleep_range(50, 200); 3832 else 3833 break; 3834 } 3835 3836 if (i == 10000) 3837 rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n"); 3838 3839 if (chan->center_freq > 2457) { 3840 bbp = rt2800_bbp_read(rt2x00dev, 30); 3841 bbp = 0x40; 3842 rt2800_bbp_write(rt2x00dev, 30, bbp); 3843 rt2800_rfcsr_write(rt2x00dev, 39, 0); 3844 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) 3845 rt2800_rfcsr_write(rt2x00dev, 42, 0xfb); 3846 else 3847 rt2800_rfcsr_write(rt2x00dev, 42, 0x7b); 3848 } else { 3849 bbp = rt2800_bbp_read(rt2x00dev, 30); 3850 bbp = 0x1f; 3851 rt2800_bbp_write(rt2x00dev, 30, bbp); 3852 rt2800_rfcsr_write(rt2x00dev, 39, 0x80); 3853 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) 3854 rt2800_rfcsr_write(rt2x00dev, 42, 0xdb); 3855 else 3856 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b); 3857 } 3858 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl); 3859 3860 rt2800_vco_calibration(rt2x00dev); 3861} 3862 3863static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev, 3864 const unsigned int word, 3865 const u8 value) 3866{ 3867 u8 chain, reg; 3868 3869 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) { 3870 reg = rt2800_bbp_read(rt2x00dev, 27); 3871 rt2x00_set_field8(®, BBP27_RX_CHAIN_SEL, chain); 3872 rt2800_bbp_write(rt2x00dev, 27, reg); 3873 3874 rt2800_bbp_write(rt2x00dev, word, value); 3875 } 3876} 3877 3878static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel) 3879{ 3880 u8 cal; 3881 3882 /* TX0 IQ Gain */ 3883 rt2800_bbp_write(rt2x00dev, 158, 0x2c); 3884 if (channel <= 14) 3885 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G); 3886 else if (channel >= 36 && channel <= 64) 3887 cal = rt2x00_eeprom_byte(rt2x00dev, 3888 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G); 3889 else if (channel >= 100 && channel <= 138) 3890 cal = rt2x00_eeprom_byte(rt2x00dev, 3891 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G); 3892 else if (channel >= 140 && channel <= 165) 3893 cal = rt2x00_eeprom_byte(rt2x00dev, 3894 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G); 3895 else 3896 cal = 0; 3897 rt2800_bbp_write(rt2x00dev, 159, cal); 3898 3899 /* TX0 IQ Phase */ 3900 rt2800_bbp_write(rt2x00dev, 158, 0x2d); 3901 if (channel <= 14) 3902 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G); 3903 else if (channel >= 36 && channel <= 64) 3904 cal = rt2x00_eeprom_byte(rt2x00dev, 3905 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G); 3906 else if (channel >= 100 && channel <= 138) 3907 cal = rt2x00_eeprom_byte(rt2x00dev, 3908 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G); 3909 else if (channel >= 140 && channel <= 165) 3910 cal = rt2x00_eeprom_byte(rt2x00dev, 3911 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G); 3912 else 3913 cal = 0; 3914 rt2800_bbp_write(rt2x00dev, 159, cal); 3915 3916 /* TX1 IQ Gain */ 3917 rt2800_bbp_write(rt2x00dev, 158, 0x4a); 3918 if (channel <= 14) 3919 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G); 3920 else if (channel >= 36 && channel <= 64) 3921 cal = rt2x00_eeprom_byte(rt2x00dev, 3922 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G); 3923 else if (channel >= 100 && channel <= 138) 3924 cal = rt2x00_eeprom_byte(rt2x00dev, 3925 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G); 3926 else if (channel >= 140 && channel <= 165) 3927 cal = rt2x00_eeprom_byte(rt2x00dev, 3928 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G); 3929 else 3930 cal = 0; 3931 rt2800_bbp_write(rt2x00dev, 159, cal); 3932 3933 /* TX1 IQ Phase */ 3934 rt2800_bbp_write(rt2x00dev, 158, 0x4b); 3935 if (channel <= 14) 3936 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G); 3937 else if (channel >= 36 && channel <= 64) 3938 cal = rt2x00_eeprom_byte(rt2x00dev, 3939 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G); 3940 else if (channel >= 100 && channel <= 138) 3941 cal = rt2x00_eeprom_byte(rt2x00dev, 3942 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G); 3943 else if (channel >= 140 && channel <= 165) 3944 cal = rt2x00_eeprom_byte(rt2x00dev, 3945 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G); 3946 else 3947 cal = 0; 3948 rt2800_bbp_write(rt2x00dev, 159, cal); 3949 3950 /* FIXME: possible RX0, RX1 callibration ? */ 3951 3952 /* RF IQ compensation control */ 3953 rt2800_bbp_write(rt2x00dev, 158, 0x04); 3954 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL); 3955 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 3956 3957 /* RF IQ imbalance compensation control */ 3958 rt2800_bbp_write(rt2x00dev, 158, 0x03); 3959 cal = rt2x00_eeprom_byte(rt2x00dev, 3960 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL); 3961 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 3962} 3963 3964static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev, 3965 unsigned int channel, 3966 char txpower) 3967{ 3968 if (rt2x00_rt(rt2x00dev, RT3593) || 3969 rt2x00_rt(rt2x00dev, RT3883)) 3970 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC); 3971 3972 if (channel <= 14) 3973 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER); 3974 3975 if (rt2x00_rt(rt2x00dev, RT3593) || 3976 rt2x00_rt(rt2x00dev, RT3883)) 3977 return clamp_t(char, txpower, MIN_A_TXPOWER_3593, 3978 MAX_A_TXPOWER_3593); 3979 else 3980 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER); 3981} 3982 3983static void rt3883_bbp_adjust(struct rt2x00_dev *rt2x00dev, 3984 struct rf_channel *rf) 3985{ 3986 u8 bbp; 3987 3988 bbp = (rf->channel > 14) ? 0x48 : 0x38; 3989 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp); 3990 3991 rt2800_bbp_write(rt2x00dev, 69, 0x12); 3992 3993 if (rf->channel <= 14) { 3994 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 3995 } else { 3996 /* Disable CCK packet detection */ 3997 rt2800_bbp_write(rt2x00dev, 70, 0x00); 3998 } 3999 4000 rt2800_bbp_write(rt2x00dev, 73, 0x10); 4001 4002 if (rf->channel > 14) { 4003 rt2800_bbp_write(rt2x00dev, 62, 0x1d); 4004 rt2800_bbp_write(rt2x00dev, 63, 0x1d); 4005 rt2800_bbp_write(rt2x00dev, 64, 0x1d); 4006 } else { 4007 rt2800_bbp_write(rt2x00dev, 62, 0x2d); 4008 rt2800_bbp_write(rt2x00dev, 63, 0x2d); 4009 rt2800_bbp_write(rt2x00dev, 64, 0x2d); 4010 } 4011} 4012 4013static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, 4014 struct ieee80211_conf *conf, 4015 struct rf_channel *rf, 4016 struct channel_info *info) 4017{ 4018 u32 reg; 4019 u32 tx_pin; 4020 u8 bbp, rfcsr; 4021 4022 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 4023 info->default_power1); 4024 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 4025 info->default_power2); 4026 if (rt2x00dev->default_ant.tx_chain_num > 2) 4027 info->default_power3 = 4028 rt2800_txpower_to_dev(rt2x00dev, rf->channel, 4029 info->default_power3); 4030 4031 switch (rt2x00dev->chip.rt) { 4032 case RT3883: 4033 rt3883_bbp_adjust(rt2x00dev, rf); 4034 break; 4035 } 4036 4037 switch (rt2x00dev->chip.rf) { 4038 case RF2020: 4039 case RF3020: 4040 case RF3021: 4041 case RF3022: 4042 case RF3320: 4043 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); 4044 break; 4045 case RF3052: 4046 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info); 4047 break; 4048 case RF3053: 4049 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info); 4050 break; 4051 case RF3290: 4052 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info); 4053 break; 4054 case RF3322: 4055 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info); 4056 break; 4057 case RF3853: 4058 rt2800_config_channel_rf3853(rt2x00dev, conf, rf, info); 4059 break; 4060 case RF3070: 4061 case RF5350: 4062 case RF5360: 4063 case RF5362: 4064 case RF5370: 4065 case RF5372: 4066 case RF5390: 4067 case RF5392: 4068 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info); 4069 break; 4070 case RF5592: 4071 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info); 4072 break; 4073 case RF7620: 4074 rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info); 4075 break; 4076 default: 4077 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); 4078 } 4079 4080 if (rt2x00_rf(rt2x00dev, RF3070) || 4081 rt2x00_rf(rt2x00dev, RF3290) || 4082 rt2x00_rf(rt2x00dev, RF3322) || 4083 rt2x00_rf(rt2x00dev, RF5350) || 4084 rt2x00_rf(rt2x00dev, RF5360) || 4085 rt2x00_rf(rt2x00dev, RF5362) || 4086 rt2x00_rf(rt2x00dev, RF5370) || 4087 rt2x00_rf(rt2x00dev, RF5372) || 4088 rt2x00_rf(rt2x00dev, RF5390) || 4089 rt2x00_rf(rt2x00dev, RF5392)) { 4090 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 4091 if (rt2x00_rf(rt2x00dev, RF3322)) { 4092 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M, 4093 conf_is_ht40(conf)); 4094 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M, 4095 conf_is_ht40(conf)); 4096 } else { 4097 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 4098 conf_is_ht40(conf)); 4099 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 4100 conf_is_ht40(conf)); 4101 } 4102 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 4103 4104 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 4105 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 4106 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 4107 } 4108 4109 /* 4110 * Change BBP settings 4111 */ 4112 4113 if (rt2x00_rt(rt2x00dev, RT3352)) { 4114 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4115 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4116 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4117 4118 rt2800_bbp_write(rt2x00dev, 27, 0x0); 4119 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 4120 rt2800_bbp_write(rt2x00dev, 27, 0x20); 4121 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 4122 rt2800_bbp_write(rt2x00dev, 86, 0x38); 4123 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 4124 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 4125 if (rf->channel > 14) { 4126 /* Disable CCK Packet detection on 5GHz */ 4127 rt2800_bbp_write(rt2x00dev, 70, 0x00); 4128 } else { 4129 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 4130 } 4131 4132 if (conf_is_ht40(conf)) 4133 rt2800_bbp_write(rt2x00dev, 105, 0x04); 4134 else 4135 rt2800_bbp_write(rt2x00dev, 105, 0x34); 4136 4137 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4138 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4139 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4140 rt2800_bbp_write(rt2x00dev, 77, 0x98); 4141 } else if (rt2x00_rt(rt2x00dev, RT3883)) { 4142 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4143 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4144 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4145 4146 if (rt2x00dev->default_ant.rx_chain_num > 1) 4147 rt2800_bbp_write(rt2x00dev, 86, 0x46); 4148 else 4149 rt2800_bbp_write(rt2x00dev, 86, 0); 4150 } else { 4151 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4152 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4153 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4154 if (rt2x00_rt(rt2x00dev, RT6352)) 4155 rt2800_bbp_write(rt2x00dev, 86, 0x38); 4156 else 4157 rt2800_bbp_write(rt2x00dev, 86, 0); 4158 } 4159 4160 if (rf->channel <= 14) { 4161 if (!rt2x00_rt(rt2x00dev, RT5390) && 4162 !rt2x00_rt(rt2x00dev, RT5392) && 4163 !rt2x00_rt(rt2x00dev, RT6352)) { 4164 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 4165 rt2800_bbp_write(rt2x00dev, 82, 0x62); 4166 rt2800_bbp_write(rt2x00dev, 82, 0x62); 4167 rt2800_bbp_write(rt2x00dev, 75, 0x46); 4168 } else { 4169 if (rt2x00_rt(rt2x00dev, RT3593)) 4170 rt2800_bbp_write(rt2x00dev, 82, 0x62); 4171 else 4172 rt2800_bbp_write(rt2x00dev, 82, 0x84); 4173 rt2800_bbp_write(rt2x00dev, 75, 0x50); 4174 } 4175 if (rt2x00_rt(rt2x00dev, RT3593) || 4176 rt2x00_rt(rt2x00dev, RT3883)) 4177 rt2800_bbp_write(rt2x00dev, 83, 0x8a); 4178 } 4179 4180 } else { 4181 if (rt2x00_rt(rt2x00dev, RT3572)) 4182 rt2800_bbp_write(rt2x00dev, 82, 0x94); 4183 else if (rt2x00_rt(rt2x00dev, RT3593) || 4184 rt2x00_rt(rt2x00dev, RT3883)) 4185 rt2800_bbp_write(rt2x00dev, 82, 0x82); 4186 else if (!rt2x00_rt(rt2x00dev, RT6352)) 4187 rt2800_bbp_write(rt2x00dev, 82, 0xf2); 4188 4189 if (rt2x00_rt(rt2x00dev, RT3593) || 4190 rt2x00_rt(rt2x00dev, RT3883)) 4191 rt2800_bbp_write(rt2x00dev, 83, 0x9a); 4192 4193 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) 4194 rt2800_bbp_write(rt2x00dev, 75, 0x46); 4195 else 4196 rt2800_bbp_write(rt2x00dev, 75, 0x50); 4197 } 4198 4199 reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG); 4200 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); 4201 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); 4202 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); 4203 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); 4204 4205 if (rt2x00_rt(rt2x00dev, RT3572)) 4206 rt2800_rfcsr_write(rt2x00dev, 8, 0); 4207 4208 if (rt2x00_rt(rt2x00dev, RT6352)) { 4209 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 4210 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); 4211 } else { 4212 tx_pin = 0; 4213 } 4214 4215 switch (rt2x00dev->default_ant.tx_chain_num) { 4216 case 3: 4217 /* Turn on tertiary PAs */ 4218 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 4219 rf->channel > 14); 4220 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 4221 rf->channel <= 14); 4222 fallthrough; 4223 case 2: 4224 /* Turn on secondary PAs */ 4225 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 4226 rf->channel > 14); 4227 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 4228 rf->channel <= 14); 4229 fallthrough; 4230 case 1: 4231 /* Turn on primary PAs */ 4232 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 4233 rf->channel > 14); 4234 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) 4235 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 4236 else 4237 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 4238 rf->channel <= 14); 4239 break; 4240 } 4241 4242 switch (rt2x00dev->default_ant.rx_chain_num) { 4243 case 3: 4244 /* Turn on tertiary LNAs */ 4245 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1); 4246 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1); 4247 fallthrough; 4248 case 2: 4249 /* Turn on secondary LNAs */ 4250 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1); 4251 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1); 4252 fallthrough; 4253 case 1: 4254 /* Turn on primary LNAs */ 4255 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1); 4256 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); 4257 break; 4258 } 4259 4260 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); 4261 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); 4262 4263 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 4264 4265 if (rt2x00_rt(rt2x00dev, RT3572)) { 4266 rt2800_rfcsr_write(rt2x00dev, 8, 0x80); 4267 4268 /* AGC init */ 4269 if (rf->channel <= 14) 4270 reg = 0x1c + (2 * rt2x00dev->lna_gain); 4271 else 4272 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 4273 4274 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4275 } 4276 4277 if (rt2x00_rt(rt2x00dev, RT3593)) { 4278 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 4279 4280 /* Band selection */ 4281 if (rt2x00_is_usb(rt2x00dev) || 4282 rt2x00_is_pcie(rt2x00dev)) { 4283 /* GPIO #8 controls all paths */ 4284 rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0); 4285 if (rf->channel <= 14) 4286 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1); 4287 else 4288 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0); 4289 } 4290 4291 /* LNA PE control. */ 4292 if (rt2x00_is_usb(rt2x00dev)) { 4293 /* GPIO #4 controls PE0 and PE1, 4294 * GPIO #7 controls PE2 4295 */ 4296 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 4297 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 4298 4299 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 4300 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 4301 } else if (rt2x00_is_pcie(rt2x00dev)) { 4302 /* GPIO #4 controls PE0, PE1 and PE2 */ 4303 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 4304 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 4305 } 4306 4307 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 4308 4309 /* AGC init */ 4310 if (rf->channel <= 14) 4311 reg = 0x1c + 2 * rt2x00dev->lna_gain; 4312 else 4313 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 4314 4315 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4316 4317 usleep_range(1000, 1500); 4318 } 4319 4320 if (rt2x00_rt(rt2x00dev, RT3883)) { 4321 if (!conf_is_ht40(conf)) 4322 rt2800_bbp_write(rt2x00dev, 105, 0x34); 4323 else 4324 rt2800_bbp_write(rt2x00dev, 105, 0x04); 4325 4326 /* AGC init */ 4327 if (rf->channel <= 14) 4328 reg = 0x2e + rt2x00dev->lna_gain; 4329 else 4330 reg = 0x20 + ((rt2x00dev->lna_gain * 5) / 3); 4331 4332 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4333 4334 usleep_range(1000, 1500); 4335 } 4336 4337 if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) { 4338 reg = 0x10; 4339 if (!conf_is_ht40(conf)) { 4340 if (rt2x00_rt(rt2x00dev, RT6352) && 4341 rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 4342 reg |= 0x5; 4343 } else { 4344 reg |= 0xa; 4345 } 4346 } 4347 rt2800_bbp_write(rt2x00dev, 195, 141); 4348 rt2800_bbp_write(rt2x00dev, 196, reg); 4349 4350 /* AGC init. 4351 * Despite the vendor driver using different values here for 4352 * RT6352 chip, we use 0x1c for now. This may have to be changed 4353 * once TSSI got implemented. 4354 */ 4355 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain; 4356 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4357 4358 if (rt2x00_rt(rt2x00dev, RT5592)) 4359 rt2800_iq_calibrate(rt2x00dev, rf->channel); 4360 } 4361 4362 bbp = rt2800_bbp_read(rt2x00dev, 4); 4363 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); 4364 rt2800_bbp_write(rt2x00dev, 4, bbp); 4365 4366 bbp = rt2800_bbp_read(rt2x00dev, 3); 4367 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf)); 4368 rt2800_bbp_write(rt2x00dev, 3, bbp); 4369 4370 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 4371 if (conf_is_ht40(conf)) { 4372 rt2800_bbp_write(rt2x00dev, 69, 0x1a); 4373 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 4374 rt2800_bbp_write(rt2x00dev, 73, 0x16); 4375 } else { 4376 rt2800_bbp_write(rt2x00dev, 69, 0x16); 4377 rt2800_bbp_write(rt2x00dev, 70, 0x08); 4378 rt2800_bbp_write(rt2x00dev, 73, 0x11); 4379 } 4380 } 4381 4382 usleep_range(1000, 1500); 4383 4384 /* 4385 * Clear channel statistic counters 4386 */ 4387 reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA); 4388 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA); 4389 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); 4390 4391 /* 4392 * Clear update flag 4393 */ 4394 if (rt2x00_rt(rt2x00dev, RT3352) || 4395 rt2x00_rt(rt2x00dev, RT5350)) { 4396 bbp = rt2800_bbp_read(rt2x00dev, 49); 4397 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0); 4398 rt2800_bbp_write(rt2x00dev, 49, bbp); 4399 } 4400} 4401 4402static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev) 4403{ 4404 u8 tssi_bounds[9]; 4405 u8 current_tssi; 4406 u16 eeprom; 4407 u8 step; 4408 int i; 4409 4410 /* 4411 * First check if temperature compensation is supported. 4412 */ 4413 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 4414 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC)) 4415 return 0; 4416 4417 /* 4418 * Read TSSI boundaries for temperature compensation from 4419 * the EEPROM. 4420 * 4421 * Array idx 0 1 2 3 4 5 6 7 8 4422 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4 4423 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00 4424 */ 4425 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 4426 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1); 4427 tssi_bounds[0] = rt2x00_get_field16(eeprom, 4428 EEPROM_TSSI_BOUND_BG1_MINUS4); 4429 tssi_bounds[1] = rt2x00_get_field16(eeprom, 4430 EEPROM_TSSI_BOUND_BG1_MINUS3); 4431 4432 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2); 4433 tssi_bounds[2] = rt2x00_get_field16(eeprom, 4434 EEPROM_TSSI_BOUND_BG2_MINUS2); 4435 tssi_bounds[3] = rt2x00_get_field16(eeprom, 4436 EEPROM_TSSI_BOUND_BG2_MINUS1); 4437 4438 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3); 4439 tssi_bounds[4] = rt2x00_get_field16(eeprom, 4440 EEPROM_TSSI_BOUND_BG3_REF); 4441 tssi_bounds[5] = rt2x00_get_field16(eeprom, 4442 EEPROM_TSSI_BOUND_BG3_PLUS1); 4443 4444 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4); 4445 tssi_bounds[6] = rt2x00_get_field16(eeprom, 4446 EEPROM_TSSI_BOUND_BG4_PLUS2); 4447 tssi_bounds[7] = rt2x00_get_field16(eeprom, 4448 EEPROM_TSSI_BOUND_BG4_PLUS3); 4449 4450 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5); 4451 tssi_bounds[8] = rt2x00_get_field16(eeprom, 4452 EEPROM_TSSI_BOUND_BG5_PLUS4); 4453 4454 step = rt2x00_get_field16(eeprom, 4455 EEPROM_TSSI_BOUND_BG5_AGC_STEP); 4456 } else { 4457 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1); 4458 tssi_bounds[0] = rt2x00_get_field16(eeprom, 4459 EEPROM_TSSI_BOUND_A1_MINUS4); 4460 tssi_bounds[1] = rt2x00_get_field16(eeprom, 4461 EEPROM_TSSI_BOUND_A1_MINUS3); 4462 4463 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2); 4464 tssi_bounds[2] = rt2x00_get_field16(eeprom, 4465 EEPROM_TSSI_BOUND_A2_MINUS2); 4466 tssi_bounds[3] = rt2x00_get_field16(eeprom, 4467 EEPROM_TSSI_BOUND_A2_MINUS1); 4468 4469 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3); 4470 tssi_bounds[4] = rt2x00_get_field16(eeprom, 4471 EEPROM_TSSI_BOUND_A3_REF); 4472 tssi_bounds[5] = rt2x00_get_field16(eeprom, 4473 EEPROM_TSSI_BOUND_A3_PLUS1); 4474 4475 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4); 4476 tssi_bounds[6] = rt2x00_get_field16(eeprom, 4477 EEPROM_TSSI_BOUND_A4_PLUS2); 4478 tssi_bounds[7] = rt2x00_get_field16(eeprom, 4479 EEPROM_TSSI_BOUND_A4_PLUS3); 4480 4481 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5); 4482 tssi_bounds[8] = rt2x00_get_field16(eeprom, 4483 EEPROM_TSSI_BOUND_A5_PLUS4); 4484 4485 step = rt2x00_get_field16(eeprom, 4486 EEPROM_TSSI_BOUND_A5_AGC_STEP); 4487 } 4488 4489 /* 4490 * Check if temperature compensation is supported. 4491 */ 4492 if (tssi_bounds[4] == 0xff || step == 0xff) 4493 return 0; 4494 4495 /* 4496 * Read current TSSI (BBP 49). 4497 */ 4498 current_tssi = rt2800_bbp_read(rt2x00dev, 49); 4499 4500 /* 4501 * Compare TSSI value (BBP49) with the compensation boundaries 4502 * from the EEPROM and increase or decrease tx power. 4503 */ 4504 for (i = 0; i <= 3; i++) { 4505 if (current_tssi > tssi_bounds[i]) 4506 break; 4507 } 4508 4509 if (i == 4) { 4510 for (i = 8; i >= 5; i--) { 4511 if (current_tssi < tssi_bounds[i]) 4512 break; 4513 } 4514 } 4515 4516 return (i - 4) * step; 4517} 4518 4519static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev, 4520 enum nl80211_band band) 4521{ 4522 u16 eeprom; 4523 u8 comp_en; 4524 u8 comp_type; 4525 int comp_value = 0; 4526 4527 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA); 4528 4529 /* 4530 * HT40 compensation not required. 4531 */ 4532 if (eeprom == 0xffff || 4533 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 4534 return 0; 4535 4536 if (band == NL80211_BAND_2GHZ) { 4537 comp_en = rt2x00_get_field16(eeprom, 4538 EEPROM_TXPOWER_DELTA_ENABLE_2G); 4539 if (comp_en) { 4540 comp_type = rt2x00_get_field16(eeprom, 4541 EEPROM_TXPOWER_DELTA_TYPE_2G); 4542 comp_value = rt2x00_get_field16(eeprom, 4543 EEPROM_TXPOWER_DELTA_VALUE_2G); 4544 if (!comp_type) 4545 comp_value = -comp_value; 4546 } 4547 } else { 4548 comp_en = rt2x00_get_field16(eeprom, 4549 EEPROM_TXPOWER_DELTA_ENABLE_5G); 4550 if (comp_en) { 4551 comp_type = rt2x00_get_field16(eeprom, 4552 EEPROM_TXPOWER_DELTA_TYPE_5G); 4553 comp_value = rt2x00_get_field16(eeprom, 4554 EEPROM_TXPOWER_DELTA_VALUE_5G); 4555 if (!comp_type) 4556 comp_value = -comp_value; 4557 } 4558 } 4559 4560 return comp_value; 4561} 4562 4563static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev, 4564 int power_level, int max_power) 4565{ 4566 int delta; 4567 4568 if (rt2x00_has_cap_power_limit(rt2x00dev)) 4569 return 0; 4570 4571 /* 4572 * XXX: We don't know the maximum transmit power of our hardware since 4573 * the EEPROM doesn't expose it. We only know that we are calibrated 4574 * to 100% tx power. 4575 * 4576 * Hence, we assume the regulatory limit that cfg80211 calulated for 4577 * the current channel is our maximum and if we are requested to lower 4578 * the value we just reduce our tx power accordingly. 4579 */ 4580 delta = power_level - max_power; 4581 return min(delta, 0); 4582} 4583 4584static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b, 4585 enum nl80211_band band, int power_level, 4586 u8 txpower, int delta) 4587{ 4588 u16 eeprom; 4589 u8 criterion; 4590 u8 eirp_txpower; 4591 u8 eirp_txpower_criterion; 4592 u8 reg_limit; 4593 4594 if (rt2x00_rt(rt2x00dev, RT3593)) 4595 return min_t(u8, txpower, 0xc); 4596 4597 if (rt2x00_rt(rt2x00dev, RT3883)) 4598 return min_t(u8, txpower, 0xf); 4599 4600 if (rt2x00_has_cap_power_limit(rt2x00dev)) { 4601 /* 4602 * Check if eirp txpower exceed txpower_limit. 4603 * We use OFDM 6M as criterion and its eirp txpower 4604 * is stored at EEPROM_EIRP_MAX_TX_POWER. 4605 * .11b data rate need add additional 4dbm 4606 * when calculating eirp txpower. 4607 */ 4608 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4609 EEPROM_TXPOWER_BYRATE, 4610 1); 4611 criterion = rt2x00_get_field16(eeprom, 4612 EEPROM_TXPOWER_BYRATE_RATE0); 4613 4614 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER); 4615 4616 if (band == NL80211_BAND_2GHZ) 4617 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 4618 EEPROM_EIRP_MAX_TX_POWER_2GHZ); 4619 else 4620 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 4621 EEPROM_EIRP_MAX_TX_POWER_5GHZ); 4622 4623 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) + 4624 (is_rate_b ? 4 : 0) + delta; 4625 4626 reg_limit = (eirp_txpower > power_level) ? 4627 (eirp_txpower - power_level) : 0; 4628 } else 4629 reg_limit = 0; 4630 4631 txpower = max(0, txpower + delta - reg_limit); 4632 return min_t(u8, txpower, 0xc); 4633} 4634 4635 4636enum { 4637 TX_PWR_CFG_0_IDX, 4638 TX_PWR_CFG_1_IDX, 4639 TX_PWR_CFG_2_IDX, 4640 TX_PWR_CFG_3_IDX, 4641 TX_PWR_CFG_4_IDX, 4642 TX_PWR_CFG_5_IDX, 4643 TX_PWR_CFG_6_IDX, 4644 TX_PWR_CFG_7_IDX, 4645 TX_PWR_CFG_8_IDX, 4646 TX_PWR_CFG_9_IDX, 4647 TX_PWR_CFG_0_EXT_IDX, 4648 TX_PWR_CFG_1_EXT_IDX, 4649 TX_PWR_CFG_2_EXT_IDX, 4650 TX_PWR_CFG_3_EXT_IDX, 4651 TX_PWR_CFG_4_EXT_IDX, 4652 TX_PWR_CFG_IDX_COUNT, 4653}; 4654 4655static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev, 4656 struct ieee80211_channel *chan, 4657 int power_level) 4658{ 4659 u8 txpower; 4660 u16 eeprom; 4661 u32 regs[TX_PWR_CFG_IDX_COUNT]; 4662 unsigned int offset; 4663 enum nl80211_band band = chan->band; 4664 int delta; 4665 int i; 4666 4667 memset(regs, '\0', sizeof(regs)); 4668 4669 /* TODO: adapt TX power reduction from the rt28xx code */ 4670 4671 /* calculate temperature compensation delta */ 4672 delta = rt2800_get_gain_calibration_delta(rt2x00dev); 4673 4674 if (band == NL80211_BAND_5GHZ) 4675 offset = 16; 4676 else 4677 offset = 0; 4678 4679 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 4680 offset += 8; 4681 4682 /* read the next four txpower values */ 4683 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4684 offset); 4685 4686 /* CCK 1MBS,2MBS */ 4687 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4688 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 4689 txpower, delta); 4690 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4691 TX_PWR_CFG_0_CCK1_CH0, txpower); 4692 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4693 TX_PWR_CFG_0_CCK1_CH1, txpower); 4694 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4695 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower); 4696 4697 /* CCK 5.5MBS,11MBS */ 4698 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4699 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 4700 txpower, delta); 4701 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4702 TX_PWR_CFG_0_CCK5_CH0, txpower); 4703 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4704 TX_PWR_CFG_0_CCK5_CH1, txpower); 4705 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4706 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower); 4707 4708 /* OFDM 6MBS,9MBS */ 4709 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4710 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4711 txpower, delta); 4712 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4713 TX_PWR_CFG_0_OFDM6_CH0, txpower); 4714 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4715 TX_PWR_CFG_0_OFDM6_CH1, txpower); 4716 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4717 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower); 4718 4719 /* OFDM 12MBS,18MBS */ 4720 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4721 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4722 txpower, delta); 4723 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4724 TX_PWR_CFG_0_OFDM12_CH0, txpower); 4725 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4726 TX_PWR_CFG_0_OFDM12_CH1, txpower); 4727 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4728 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower); 4729 4730 /* read the next four txpower values */ 4731 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4732 offset + 1); 4733 4734 /* OFDM 24MBS,36MBS */ 4735 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4736 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4737 txpower, delta); 4738 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4739 TX_PWR_CFG_1_OFDM24_CH0, txpower); 4740 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4741 TX_PWR_CFG_1_OFDM24_CH1, txpower); 4742 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4743 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower); 4744 4745 /* OFDM 48MBS */ 4746 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4747 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4748 txpower, delta); 4749 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4750 TX_PWR_CFG_1_OFDM48_CH0, txpower); 4751 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4752 TX_PWR_CFG_1_OFDM48_CH1, txpower); 4753 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4754 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower); 4755 4756 /* OFDM 54MBS */ 4757 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4758 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4759 txpower, delta); 4760 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4761 TX_PWR_CFG_7_OFDM54_CH0, txpower); 4762 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4763 TX_PWR_CFG_7_OFDM54_CH1, txpower); 4764 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4765 TX_PWR_CFG_7_OFDM54_CH2, txpower); 4766 4767 /* read the next four txpower values */ 4768 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4769 offset + 2); 4770 4771 /* MCS 0,1 */ 4772 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4773 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4774 txpower, delta); 4775 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4776 TX_PWR_CFG_1_MCS0_CH0, txpower); 4777 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4778 TX_PWR_CFG_1_MCS0_CH1, txpower); 4779 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4780 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower); 4781 4782 /* MCS 2,3 */ 4783 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4784 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4785 txpower, delta); 4786 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4787 TX_PWR_CFG_1_MCS2_CH0, txpower); 4788 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4789 TX_PWR_CFG_1_MCS2_CH1, txpower); 4790 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4791 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower); 4792 4793 /* MCS 4,5 */ 4794 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4795 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4796 txpower, delta); 4797 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4798 TX_PWR_CFG_2_MCS4_CH0, txpower); 4799 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4800 TX_PWR_CFG_2_MCS4_CH1, txpower); 4801 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4802 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower); 4803 4804 /* MCS 6 */ 4805 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4806 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4807 txpower, delta); 4808 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4809 TX_PWR_CFG_2_MCS6_CH0, txpower); 4810 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4811 TX_PWR_CFG_2_MCS6_CH1, txpower); 4812 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4813 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower); 4814 4815 /* read the next four txpower values */ 4816 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4817 offset + 3); 4818 4819 /* MCS 7 */ 4820 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4821 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4822 txpower, delta); 4823 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4824 TX_PWR_CFG_7_MCS7_CH0, txpower); 4825 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4826 TX_PWR_CFG_7_MCS7_CH1, txpower); 4827 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4828 TX_PWR_CFG_7_MCS7_CH2, txpower); 4829 4830 /* MCS 8,9 */ 4831 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4832 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4833 txpower, delta); 4834 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4835 TX_PWR_CFG_2_MCS8_CH0, txpower); 4836 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4837 TX_PWR_CFG_2_MCS8_CH1, txpower); 4838 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4839 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower); 4840 4841 /* MCS 10,11 */ 4842 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4843 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4844 txpower, delta); 4845 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4846 TX_PWR_CFG_2_MCS10_CH0, txpower); 4847 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4848 TX_PWR_CFG_2_MCS10_CH1, txpower); 4849 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4850 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower); 4851 4852 /* MCS 12,13 */ 4853 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4854 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4855 txpower, delta); 4856 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4857 TX_PWR_CFG_3_MCS12_CH0, txpower); 4858 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4859 TX_PWR_CFG_3_MCS12_CH1, txpower); 4860 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4861 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower); 4862 4863 /* read the next four txpower values */ 4864 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4865 offset + 4); 4866 4867 /* MCS 14 */ 4868 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4869 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4870 txpower, delta); 4871 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4872 TX_PWR_CFG_3_MCS14_CH0, txpower); 4873 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4874 TX_PWR_CFG_3_MCS14_CH1, txpower); 4875 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4876 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower); 4877 4878 /* MCS 15 */ 4879 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4880 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4881 txpower, delta); 4882 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4883 TX_PWR_CFG_8_MCS15_CH0, txpower); 4884 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4885 TX_PWR_CFG_8_MCS15_CH1, txpower); 4886 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4887 TX_PWR_CFG_8_MCS15_CH2, txpower); 4888 4889 /* MCS 16,17 */ 4890 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4891 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4892 txpower, delta); 4893 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4894 TX_PWR_CFG_5_MCS16_CH0, txpower); 4895 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4896 TX_PWR_CFG_5_MCS16_CH1, txpower); 4897 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4898 TX_PWR_CFG_5_MCS16_CH2, txpower); 4899 4900 /* MCS 18,19 */ 4901 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4902 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4903 txpower, delta); 4904 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4905 TX_PWR_CFG_5_MCS18_CH0, txpower); 4906 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4907 TX_PWR_CFG_5_MCS18_CH1, txpower); 4908 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4909 TX_PWR_CFG_5_MCS18_CH2, txpower); 4910 4911 /* read the next four txpower values */ 4912 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4913 offset + 5); 4914 4915 /* MCS 20,21 */ 4916 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4917 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4918 txpower, delta); 4919 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4920 TX_PWR_CFG_6_MCS20_CH0, txpower); 4921 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4922 TX_PWR_CFG_6_MCS20_CH1, txpower); 4923 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4924 TX_PWR_CFG_6_MCS20_CH2, txpower); 4925 4926 /* MCS 22 */ 4927 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4928 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4929 txpower, delta); 4930 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4931 TX_PWR_CFG_6_MCS22_CH0, txpower); 4932 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4933 TX_PWR_CFG_6_MCS22_CH1, txpower); 4934 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4935 TX_PWR_CFG_6_MCS22_CH2, txpower); 4936 4937 /* MCS 23 */ 4938 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4939 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4940 txpower, delta); 4941 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4942 TX_PWR_CFG_8_MCS23_CH0, txpower); 4943 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4944 TX_PWR_CFG_8_MCS23_CH1, txpower); 4945 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4946 TX_PWR_CFG_8_MCS23_CH2, txpower); 4947 4948 /* read the next four txpower values */ 4949 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4950 offset + 6); 4951 4952 /* STBC, MCS 0,1 */ 4953 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4954 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4955 txpower, delta); 4956 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4957 TX_PWR_CFG_3_STBC0_CH0, txpower); 4958 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4959 TX_PWR_CFG_3_STBC0_CH1, txpower); 4960 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4961 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower); 4962 4963 /* STBC, MCS 2,3 */ 4964 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4965 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4966 txpower, delta); 4967 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4968 TX_PWR_CFG_3_STBC2_CH0, txpower); 4969 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4970 TX_PWR_CFG_3_STBC2_CH1, txpower); 4971 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4972 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower); 4973 4974 /* STBC, MCS 4,5 */ 4975 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4976 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4977 txpower, delta); 4978 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower); 4979 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower); 4980 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0, 4981 txpower); 4982 4983 /* STBC, MCS 6 */ 4984 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4985 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4986 txpower, delta); 4987 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower); 4988 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower); 4989 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2, 4990 txpower); 4991 4992 /* read the next four txpower values */ 4993 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4994 offset + 7); 4995 4996 /* STBC, MCS 7 */ 4997 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4998 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4999 txpower, delta); 5000 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 5001 TX_PWR_CFG_9_STBC7_CH0, txpower); 5002 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 5003 TX_PWR_CFG_9_STBC7_CH1, txpower); 5004 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 5005 TX_PWR_CFG_9_STBC7_CH2, txpower); 5006 5007 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]); 5008 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]); 5009 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]); 5010 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]); 5011 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]); 5012 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]); 5013 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]); 5014 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]); 5015 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]); 5016 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]); 5017 5018 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT, 5019 regs[TX_PWR_CFG_0_EXT_IDX]); 5020 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT, 5021 regs[TX_PWR_CFG_1_EXT_IDX]); 5022 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT, 5023 regs[TX_PWR_CFG_2_EXT_IDX]); 5024 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT, 5025 regs[TX_PWR_CFG_3_EXT_IDX]); 5026 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT, 5027 regs[TX_PWR_CFG_4_EXT_IDX]); 5028 5029 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++) 5030 rt2x00_dbg(rt2x00dev, 5031 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n", 5032 (band == NL80211_BAND_5GHZ) ? '5' : '2', 5033 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ? 5034 '4' : '2', 5035 (i > TX_PWR_CFG_9_IDX) ? 5036 (i - TX_PWR_CFG_9_IDX - 1) : i, 5037 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "", 5038 (unsigned long) regs[i]); 5039} 5040 5041static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev, 5042 struct ieee80211_channel *chan, 5043 int power_level) 5044{ 5045 u32 reg, pwreg; 5046 u16 eeprom; 5047 u32 data, gdata; 5048 u8 t, i; 5049 enum nl80211_band band = chan->band; 5050 int delta; 5051 5052 /* Warn user if bw_comp is set in EEPROM */ 5053 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); 5054 5055 if (delta) 5056 rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n", 5057 delta); 5058 5059 /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit 5060 * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor 5061 * driver does as well, though it looks kinda wrong. 5062 * Maybe some misunderstanding of what a signed 8-bit value is? Maybe 5063 * the hardware has a problem handling 0x20, and as the code initially 5064 * used a fixed offset between HT20 and HT40 rates they had to work- 5065 * around that issue and most likely just forgot about it later on. 5066 * Maybe we should use rt2800_get_txpower_bw_comp() here as well, 5067 * however, the corresponding EEPROM value is not respected by the 5068 * vendor driver, so maybe this is rather being taken care of the 5069 * TXALC and the driver doesn't need to handle it...? 5070 * Though this is all very awkward, just do as they did, as that's what 5071 * board vendors expected when they populated the EEPROM... 5072 */ 5073 for (i = 0; i < 5; i++) { 5074 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5075 EEPROM_TXPOWER_BYRATE, 5076 i * 2); 5077 5078 data = eeprom; 5079 5080 t = eeprom & 0x3f; 5081 if (t == 32) 5082 t++; 5083 5084 gdata = t; 5085 5086 t = (eeprom & 0x3f00) >> 8; 5087 if (t == 32) 5088 t++; 5089 5090 gdata |= (t << 8); 5091 5092 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5093 EEPROM_TXPOWER_BYRATE, 5094 (i * 2) + 1); 5095 5096 t = eeprom & 0x3f; 5097 if (t == 32) 5098 t++; 5099 5100 gdata |= (t << 16); 5101 5102 t = (eeprom & 0x3f00) >> 8; 5103 if (t == 32) 5104 t++; 5105 5106 gdata |= (t << 24); 5107 data |= (eeprom << 16); 5108 5109 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) { 5110 /* HT20 */ 5111 if (data != 0xffffffff) 5112 rt2800_register_write(rt2x00dev, 5113 TX_PWR_CFG_0 + (i * 4), 5114 data); 5115 } else { 5116 /* HT40 */ 5117 if (gdata != 0xffffffff) 5118 rt2800_register_write(rt2x00dev, 5119 TX_PWR_CFG_0 + (i * 4), 5120 gdata); 5121 } 5122 } 5123 5124 /* Aparently Ralink ran out of space in the BYRATE calibration section 5125 * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x 5126 * registers. As recent 2T chips use 8-bit instead of 4-bit values for 5127 * power-offsets more space would be needed. Ralink decided to keep the 5128 * EEPROM layout untouched and rather have some shared values covering 5129 * multiple bitrates. 5130 * Populate the registers not covered by the EEPROM in the same way the 5131 * vendor driver does. 5132 */ 5133 5134 /* For OFDM 54MBS use value from OFDM 48MBS */ 5135 pwreg = 0; 5136 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1); 5137 t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS); 5138 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t); 5139 5140 /* For MCS 7 use value from MCS 6 */ 5141 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2); 5142 t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7); 5143 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t); 5144 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg); 5145 5146 /* For MCS 15 use value from MCS 14 */ 5147 pwreg = 0; 5148 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3); 5149 t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14); 5150 rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t); 5151 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg); 5152 5153 /* For STBC MCS 7 use value from STBC MCS 6 */ 5154 pwreg = 0; 5155 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4); 5156 t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6); 5157 rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t); 5158 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg); 5159 5160 rt2800_config_alc(rt2x00dev, chan, power_level); 5161 5162 /* TODO: temperature compensation code! */ 5163} 5164 5165/* 5166 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and 5167 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values, 5168 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power 5169 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm. 5170 * Reference per rate transmit power values are located in the EEPROM at 5171 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to 5172 * current conditions (i.e. band, bandwidth, temperature, user settings). 5173 */ 5174static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev, 5175 struct ieee80211_channel *chan, 5176 int power_level) 5177{ 5178 u8 txpower, r1; 5179 u16 eeprom; 5180 u32 reg, offset; 5181 int i, is_rate_b, delta, power_ctrl; 5182 enum nl80211_band band = chan->band; 5183 5184 /* 5185 * Calculate HT40 compensation. For 40MHz we need to add or subtract 5186 * value read from EEPROM (different for 2GHz and for 5GHz). 5187 */ 5188 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); 5189 5190 /* 5191 * Calculate temperature compensation. Depends on measurement of current 5192 * TSSI (Transmitter Signal Strength Indication) we know TX power (due 5193 * to temperature or maybe other factors) is smaller or bigger than 5194 * expected. We adjust it, based on TSSI reference and boundaries values 5195 * provided in EEPROM. 5196 */ 5197 switch (rt2x00dev->chip.rt) { 5198 case RT2860: 5199 case RT2872: 5200 case RT2883: 5201 case RT3070: 5202 case RT3071: 5203 case RT3090: 5204 case RT3572: 5205 delta += rt2800_get_gain_calibration_delta(rt2x00dev); 5206 break; 5207 default: 5208 /* TODO: temperature compensation code for other chips. */ 5209 break; 5210 } 5211 5212 /* 5213 * Decrease power according to user settings, on devices with unknown 5214 * maximum tx power. For other devices we take user power_level into 5215 * consideration on rt2800_compensate_txpower(). 5216 */ 5217 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level, 5218 chan->max_power); 5219 5220 /* 5221 * BBP_R1 controls TX power for all rates, it allow to set the following 5222 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively. 5223 * 5224 * TODO: we do not use +6 dBm option to do not increase power beyond 5225 * regulatory limit, however this could be utilized for devices with 5226 * CAPABILITY_POWER_LIMIT. 5227 */ 5228 if (delta <= -12) { 5229 power_ctrl = 2; 5230 delta += 12; 5231 } else if (delta <= -6) { 5232 power_ctrl = 1; 5233 delta += 6; 5234 } else { 5235 power_ctrl = 0; 5236 } 5237 r1 = rt2800_bbp_read(rt2x00dev, 1); 5238 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl); 5239 rt2800_bbp_write(rt2x00dev, 1, r1); 5240 5241 offset = TX_PWR_CFG_0; 5242 5243 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) { 5244 /* just to be safe */ 5245 if (offset > TX_PWR_CFG_4) 5246 break; 5247 5248 reg = rt2800_register_read(rt2x00dev, offset); 5249 5250 /* read the next four txpower values */ 5251 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5252 EEPROM_TXPOWER_BYRATE, 5253 i); 5254 5255 is_rate_b = i ? 0 : 1; 5256 /* 5257 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS, 5258 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12, 5259 * TX_PWR_CFG_4: unknown 5260 */ 5261 txpower = rt2x00_get_field16(eeprom, 5262 EEPROM_TXPOWER_BYRATE_RATE0); 5263 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5264 power_level, txpower, delta); 5265 rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower); 5266 5267 /* 5268 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS, 5269 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13, 5270 * TX_PWR_CFG_4: unknown 5271 */ 5272 txpower = rt2x00_get_field16(eeprom, 5273 EEPROM_TXPOWER_BYRATE_RATE1); 5274 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5275 power_level, txpower, delta); 5276 rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower); 5277 5278 /* 5279 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS, 5280 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14, 5281 * TX_PWR_CFG_4: unknown 5282 */ 5283 txpower = rt2x00_get_field16(eeprom, 5284 EEPROM_TXPOWER_BYRATE_RATE2); 5285 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5286 power_level, txpower, delta); 5287 rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower); 5288 5289 /* 5290 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS, 5291 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15, 5292 * TX_PWR_CFG_4: unknown 5293 */ 5294 txpower = rt2x00_get_field16(eeprom, 5295 EEPROM_TXPOWER_BYRATE_RATE3); 5296 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5297 power_level, txpower, delta); 5298 rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower); 5299 5300 /* read the next four txpower values */ 5301 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5302 EEPROM_TXPOWER_BYRATE, 5303 i + 1); 5304 5305 is_rate_b = 0; 5306 /* 5307 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0, 5308 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown, 5309 * TX_PWR_CFG_4: unknown 5310 */ 5311 txpower = rt2x00_get_field16(eeprom, 5312 EEPROM_TXPOWER_BYRATE_RATE0); 5313 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5314 power_level, txpower, delta); 5315 rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower); 5316 5317 /* 5318 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1, 5319 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown, 5320 * TX_PWR_CFG_4: unknown 5321 */ 5322 txpower = rt2x00_get_field16(eeprom, 5323 EEPROM_TXPOWER_BYRATE_RATE1); 5324 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5325 power_level, txpower, delta); 5326 rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower); 5327 5328 /* 5329 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2, 5330 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown, 5331 * TX_PWR_CFG_4: unknown 5332 */ 5333 txpower = rt2x00_get_field16(eeprom, 5334 EEPROM_TXPOWER_BYRATE_RATE2); 5335 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5336 power_level, txpower, delta); 5337 rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower); 5338 5339 /* 5340 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3, 5341 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown, 5342 * TX_PWR_CFG_4: unknown 5343 */ 5344 txpower = rt2x00_get_field16(eeprom, 5345 EEPROM_TXPOWER_BYRATE_RATE3); 5346 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5347 power_level, txpower, delta); 5348 rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower); 5349 5350 rt2800_register_write(rt2x00dev, offset, reg); 5351 5352 /* next TX_PWR_CFG register */ 5353 offset += 4; 5354 } 5355} 5356 5357static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev, 5358 struct ieee80211_channel *chan, 5359 int power_level) 5360{ 5361 if (rt2x00_rt(rt2x00dev, RT3593) || 5362 rt2x00_rt(rt2x00dev, RT3883)) 5363 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level); 5364 else if (rt2x00_rt(rt2x00dev, RT6352)) 5365 rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level); 5366 else 5367 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level); 5368} 5369 5370void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev) 5371{ 5372 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan, 5373 rt2x00dev->tx_power); 5374} 5375EXPORT_SYMBOL_GPL(rt2800_gain_calibration); 5376 5377void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev) 5378{ 5379 u32 tx_pin; 5380 u8 rfcsr; 5381 unsigned long min_sleep = 0; 5382 5383 /* 5384 * A voltage-controlled oscillator(VCO) is an electronic oscillator 5385 * designed to be controlled in oscillation frequency by a voltage 5386 * input. Maybe the temperature will affect the frequency of 5387 * oscillation to be shifted. The VCO calibration will be called 5388 * periodically to adjust the frequency to be precision. 5389 */ 5390 5391 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 5392 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE; 5393 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 5394 5395 switch (rt2x00dev->chip.rf) { 5396 case RF2020: 5397 case RF3020: 5398 case RF3021: 5399 case RF3022: 5400 case RF3320: 5401 case RF3052: 5402 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 5403 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 5404 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 5405 break; 5406 case RF3053: 5407 case RF3070: 5408 case RF3290: 5409 case RF3853: 5410 case RF5350: 5411 case RF5360: 5412 case RF5362: 5413 case RF5370: 5414 case RF5372: 5415 case RF5390: 5416 case RF5392: 5417 case RF5592: 5418 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 5419 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 5420 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 5421 min_sleep = 1000; 5422 break; 5423 case RF7620: 5424 rt2800_rfcsr_write(rt2x00dev, 5, 0x40); 5425 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C); 5426 rfcsr = rt2800_rfcsr_read(rt2x00dev, 4); 5427 rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1); 5428 rt2800_rfcsr_write(rt2x00dev, 4, rfcsr); 5429 min_sleep = 2000; 5430 break; 5431 default: 5432 WARN_ONCE(1, "Not supported RF chipset %x for VCO recalibration", 5433 rt2x00dev->chip.rf); 5434 return; 5435 } 5436 5437 if (min_sleep > 0) 5438 usleep_range(min_sleep, min_sleep * 2); 5439 5440 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 5441 if (rt2x00dev->rf_channel <= 14) { 5442 switch (rt2x00dev->default_ant.tx_chain_num) { 5443 case 3: 5444 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1); 5445 fallthrough; 5446 case 2: 5447 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); 5448 fallthrough; 5449 case 1: 5450 default: 5451 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 5452 break; 5453 } 5454 } else { 5455 switch (rt2x00dev->default_ant.tx_chain_num) { 5456 case 3: 5457 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1); 5458 fallthrough; 5459 case 2: 5460 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); 5461 fallthrough; 5462 case 1: 5463 default: 5464 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1); 5465 break; 5466 } 5467 } 5468 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 5469 5470 if (rt2x00_rt(rt2x00dev, RT6352)) { 5471 if (rt2x00dev->default_ant.rx_chain_num == 1) { 5472 rt2800_bbp_write(rt2x00dev, 91, 0x07); 5473 rt2800_bbp_write(rt2x00dev, 95, 0x1A); 5474 rt2800_bbp_write(rt2x00dev, 195, 128); 5475 rt2800_bbp_write(rt2x00dev, 196, 0xA0); 5476 rt2800_bbp_write(rt2x00dev, 195, 170); 5477 rt2800_bbp_write(rt2x00dev, 196, 0x12); 5478 rt2800_bbp_write(rt2x00dev, 195, 171); 5479 rt2800_bbp_write(rt2x00dev, 196, 0x10); 5480 } else { 5481 rt2800_bbp_write(rt2x00dev, 91, 0x06); 5482 rt2800_bbp_write(rt2x00dev, 95, 0x9A); 5483 rt2800_bbp_write(rt2x00dev, 195, 128); 5484 rt2800_bbp_write(rt2x00dev, 196, 0xE0); 5485 rt2800_bbp_write(rt2x00dev, 195, 170); 5486 rt2800_bbp_write(rt2x00dev, 196, 0x30); 5487 rt2800_bbp_write(rt2x00dev, 195, 171); 5488 rt2800_bbp_write(rt2x00dev, 196, 0x30); 5489 } 5490 5491 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 5492 rt2800_bbp_write(rt2x00dev, 75, 0x68); 5493 rt2800_bbp_write(rt2x00dev, 76, 0x4C); 5494 rt2800_bbp_write(rt2x00dev, 79, 0x1C); 5495 rt2800_bbp_write(rt2x00dev, 80, 0x0C); 5496 rt2800_bbp_write(rt2x00dev, 82, 0xB6); 5497 } 5498 5499 /* On 11A, We should delay and wait RF/BBP to be stable 5500 * and the appropriate time should be 1000 micro seconds 5501 * 2005/06/05 - On 11G, we also need this delay time. 5502 * Otherwise it's difficult to pass the WHQL. 5503 */ 5504 usleep_range(1000, 1500); 5505 } 5506} 5507EXPORT_SYMBOL_GPL(rt2800_vco_calibration); 5508 5509static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev, 5510 struct rt2x00lib_conf *libconf) 5511{ 5512 u32 reg; 5513 5514 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); 5515 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 5516 libconf->conf->short_frame_max_tx_count); 5517 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 5518 libconf->conf->long_frame_max_tx_count); 5519 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 5520} 5521 5522static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev, 5523 struct rt2x00lib_conf *libconf) 5524{ 5525 enum dev_state state = 5526 (libconf->conf->flags & IEEE80211_CONF_PS) ? 5527 STATE_SLEEP : STATE_AWAKE; 5528 u32 reg; 5529 5530 if (state == STATE_SLEEP) { 5531 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0); 5532 5533 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); 5534 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); 5535 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 5536 libconf->conf->listen_interval - 1); 5537 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); 5538 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 5539 5540 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 5541 } else { 5542 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); 5543 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); 5544 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); 5545 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); 5546 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 5547 5548 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 5549 } 5550} 5551 5552void rt2800_config(struct rt2x00_dev *rt2x00dev, 5553 struct rt2x00lib_conf *libconf, 5554 const unsigned int flags) 5555{ 5556 /* Always recalculate LNA gain before changing configuration */ 5557 rt2800_config_lna_gain(rt2x00dev, libconf); 5558 5559 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) { 5560 rt2800_config_channel(rt2x00dev, libconf->conf, 5561 &libconf->rf, &libconf->channel); 5562 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 5563 libconf->conf->power_level); 5564 } 5565 if (flags & IEEE80211_CONF_CHANGE_POWER) 5566 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 5567 libconf->conf->power_level); 5568 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 5569 rt2800_config_retry_limit(rt2x00dev, libconf); 5570 if (flags & IEEE80211_CONF_CHANGE_PS) 5571 rt2800_config_ps(rt2x00dev, libconf); 5572} 5573EXPORT_SYMBOL_GPL(rt2800_config); 5574 5575/* 5576 * Link tuning 5577 */ 5578void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 5579{ 5580 u32 reg; 5581 5582 /* 5583 * Update FCS error count from register. 5584 */ 5585 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); 5586 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); 5587} 5588EXPORT_SYMBOL_GPL(rt2800_link_stats); 5589 5590static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) 5591{ 5592 u8 vgc; 5593 5594 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 5595 if (rt2x00_rt(rt2x00dev, RT3070) || 5596 rt2x00_rt(rt2x00dev, RT3071) || 5597 rt2x00_rt(rt2x00dev, RT3090) || 5598 rt2x00_rt(rt2x00dev, RT3290) || 5599 rt2x00_rt(rt2x00dev, RT3390) || 5600 rt2x00_rt(rt2x00dev, RT3572) || 5601 rt2x00_rt(rt2x00dev, RT3593) || 5602 rt2x00_rt(rt2x00dev, RT5390) || 5603 rt2x00_rt(rt2x00dev, RT5392) || 5604 rt2x00_rt(rt2x00dev, RT5592) || 5605 rt2x00_rt(rt2x00dev, RT6352)) 5606 vgc = 0x1c + (2 * rt2x00dev->lna_gain); 5607 else 5608 vgc = 0x2e + rt2x00dev->lna_gain; 5609 } else { /* 5GHZ band */ 5610 if (rt2x00_rt(rt2x00dev, RT3593) || 5611 rt2x00_rt(rt2x00dev, RT3883)) 5612 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3; 5613 else if (rt2x00_rt(rt2x00dev, RT5592)) 5614 vgc = 0x24 + (2 * rt2x00dev->lna_gain); 5615 else { 5616 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 5617 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3; 5618 else 5619 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3; 5620 } 5621 } 5622 5623 return vgc; 5624} 5625 5626static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev, 5627 struct link_qual *qual, u8 vgc_level) 5628{ 5629 if (qual->vgc_level != vgc_level) { 5630 if (rt2x00_rt(rt2x00dev, RT3572) || 5631 rt2x00_rt(rt2x00dev, RT3593) || 5632 rt2x00_rt(rt2x00dev, RT3883) || 5633 rt2x00_rt(rt2x00dev, RT6352)) { 5634 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, 5635 vgc_level); 5636 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 5637 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a); 5638 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level); 5639 } else { 5640 rt2800_bbp_write(rt2x00dev, 66, vgc_level); 5641 } 5642 5643 qual->vgc_level = vgc_level; 5644 qual->vgc_level_reg = vgc_level; 5645 } 5646} 5647 5648void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 5649{ 5650 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev)); 5651} 5652EXPORT_SYMBOL_GPL(rt2800_reset_tuner); 5653 5654void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, 5655 const u32 count) 5656{ 5657 u8 vgc; 5658 5659 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) 5660 return; 5661 5662 /* When RSSI is better than a certain threshold, increase VGC 5663 * with a chip specific value in order to improve the balance 5664 * between sensibility and noise isolation. 5665 */ 5666 5667 vgc = rt2800_get_default_vgc(rt2x00dev); 5668 5669 switch (rt2x00dev->chip.rt) { 5670 case RT3572: 5671 case RT3593: 5672 if (qual->rssi > -65) { 5673 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) 5674 vgc += 0x20; 5675 else 5676 vgc += 0x10; 5677 } 5678 break; 5679 5680 case RT3883: 5681 if (qual->rssi > -65) 5682 vgc += 0x10; 5683 break; 5684 5685 case RT5592: 5686 if (qual->rssi > -65) 5687 vgc += 0x20; 5688 break; 5689 5690 default: 5691 if (qual->rssi > -80) 5692 vgc += 0x10; 5693 break; 5694 } 5695 5696 rt2800_set_vgc(rt2x00dev, qual, vgc); 5697} 5698EXPORT_SYMBOL_GPL(rt2800_link_tuner); 5699 5700/* 5701 * Initialization functions. 5702 */ 5703static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 5704{ 5705 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 5706 u32 reg; 5707 u16 eeprom; 5708 unsigned int i; 5709 int ret; 5710 5711 rt2800_disable_wpdma(rt2x00dev); 5712 5713 ret = rt2800_drv_init_registers(rt2x00dev); 5714 if (ret) 5715 return ret; 5716 5717 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f); 5718 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 5719 5720 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); 5721 5722 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 5723 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); 5724 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); 5725 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); 5726 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); 5727 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 5728 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); 5729 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 5730 5731 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI); 5732 5733 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); 5734 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); 5735 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); 5736 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 5737 5738 if (rt2x00_rt(rt2x00dev, RT3290)) { 5739 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 5740 if (rt2x00_get_field32(reg, WLAN_EN) == 1) { 5741 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1); 5742 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 5743 } 5744 5745 reg = rt2800_register_read(rt2x00dev, CMB_CTRL); 5746 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) { 5747 rt2x00_set_field32(®, LDO0_EN, 1); 5748 rt2x00_set_field32(®, LDO_BGSEL, 3); 5749 rt2800_register_write(rt2x00dev, CMB_CTRL, reg); 5750 } 5751 5752 reg = rt2800_register_read(rt2x00dev, OSC_CTRL); 5753 rt2x00_set_field32(®, OSC_ROSC_EN, 1); 5754 rt2x00_set_field32(®, OSC_CAL_REQ, 1); 5755 rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27); 5756 rt2800_register_write(rt2x00dev, OSC_CTRL, reg); 5757 5758 reg = rt2800_register_read(rt2x00dev, COEX_CFG0); 5759 rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e); 5760 rt2800_register_write(rt2x00dev, COEX_CFG0, reg); 5761 5762 reg = rt2800_register_read(rt2x00dev, COEX_CFG2); 5763 rt2x00_set_field32(®, BT_COEX_CFG1, 0x00); 5764 rt2x00_set_field32(®, BT_COEX_CFG0, 0x17); 5765 rt2x00_set_field32(®, WL_COEX_CFG1, 0x93); 5766 rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f); 5767 rt2800_register_write(rt2x00dev, COEX_CFG2, reg); 5768 5769 reg = rt2800_register_read(rt2x00dev, PLL_CTRL); 5770 rt2x00_set_field32(®, PLL_CONTROL, 1); 5771 rt2800_register_write(rt2x00dev, PLL_CTRL, reg); 5772 } 5773 5774 if (rt2x00_rt(rt2x00dev, RT3071) || 5775 rt2x00_rt(rt2x00dev, RT3090) || 5776 rt2x00_rt(rt2x00dev, RT3290) || 5777 rt2x00_rt(rt2x00dev, RT3390)) { 5778 5779 if (rt2x00_rt(rt2x00dev, RT3290)) 5780 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 5781 0x00000404); 5782 else 5783 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 5784 0x00000400); 5785 5786 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5787 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 5788 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 5789 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 5790 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 5791 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 5792 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5793 0x0000002c); 5794 else 5795 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5796 0x0000000f); 5797 } else { 5798 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5799 } 5800 } else if (rt2x00_rt(rt2x00dev, RT3070)) { 5801 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5802 5803 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 5804 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5805 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c); 5806 } else { 5807 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5808 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5809 } 5810 } else if (rt2800_is_305x_soc(rt2x00dev)) { 5811 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5812 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5813 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030); 5814 } else if (rt2x00_rt(rt2x00dev, RT3352)) { 5815 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5816 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5817 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5818 } else if (rt2x00_rt(rt2x00dev, RT3572)) { 5819 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5820 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5821 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 5822 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5823 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5824 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) { 5825 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 5826 if (rt2x00_get_field16(eeprom, 5827 EEPROM_NIC_CONF1_DAC_TEST)) 5828 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5829 0x0000001f); 5830 else 5831 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5832 0x0000000f); 5833 } else { 5834 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5835 0x00000000); 5836 } 5837 } else if (rt2x00_rt(rt2x00dev, RT3883)) { 5838 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5839 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5840 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00040000); 5841 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_0, 0x8000fc21); 5842 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_3, 0x00009c40); 5843 } else if (rt2x00_rt(rt2x00dev, RT5390) || 5844 rt2x00_rt(rt2x00dev, RT5392)) { 5845 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5846 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5847 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5848 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 5849 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5850 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5851 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5852 } else if (rt2x00_rt(rt2x00dev, RT5350)) { 5853 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5854 } else if (rt2x00_rt(rt2x00dev, RT6352)) { 5855 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401); 5856 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0001); 5857 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5858 rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000); 5859 rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0); 5860 rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0); 5861 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C); 5862 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C); 5863 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 5864 0x3630363A); 5865 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT, 5866 0x3630363A); 5867 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); 5868 rt2x00_set_field32(®, TX_ALC_CFG_1_ROS_BUSY_EN, 0); 5869 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); 5870 } else { 5871 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 5872 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5873 } 5874 5875 reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG); 5876 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); 5877 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); 5878 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); 5879 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); 5880 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); 5881 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); 5882 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); 5883 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); 5884 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); 5885 5886 reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG); 5887 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); 5888 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); 5889 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); 5890 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); 5891 5892 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); 5893 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); 5894 if (rt2x00_is_usb(rt2x00dev)) { 5895 drv_data->max_psdu = 3; 5896 } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) || 5897 rt2x00_rt(rt2x00dev, RT2883) || 5898 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) { 5899 drv_data->max_psdu = 2; 5900 } else { 5901 drv_data->max_psdu = 1; 5902 } 5903 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu); 5904 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 10); 5905 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 10); 5906 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 5907 5908 reg = rt2800_register_read(rt2x00dev, LED_CFG); 5909 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); 5910 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); 5911 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); 5912 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); 5913 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); 5914 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); 5915 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); 5916 rt2800_register_write(rt2x00dev, LED_CFG, reg); 5917 5918 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); 5919 5920 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); 5921 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 2); 5922 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 2); 5923 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); 5924 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); 5925 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); 5926 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); 5927 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 5928 5929 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); 5930 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); 5931 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); 5932 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 1); 5933 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); 5934 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 0); 5935 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); 5936 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); 5937 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 5938 5939 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); 5940 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); 5941 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); 5942 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); 5943 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); 5944 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5945 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5946 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5947 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5948 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5949 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); 5950 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 5951 5952 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 5953 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); 5954 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); 5955 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); 5956 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); 5957 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5958 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5959 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5960 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5961 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5962 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); 5963 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 5964 5965 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 5966 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); 5967 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 1); 5968 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); 5969 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5970 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5971 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5972 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5973 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5974 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5975 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); 5976 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 5977 5978 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 5979 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); 5980 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 1); 5981 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); 5982 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5983 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5984 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5985 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 5986 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5987 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 5988 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); 5989 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 5990 5991 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 5992 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); 5993 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 1); 5994 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); 5995 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5996 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5997 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5998 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5999 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6000 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 6001 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); 6002 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 6003 6004 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 6005 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); 6006 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 1); 6007 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); 6008 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 6009 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6010 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6011 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 6012 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6013 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 6014 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0); 6015 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 6016 6017 if (rt2x00_is_usb(rt2x00dev)) { 6018 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006); 6019 6020 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 6021 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 6022 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 6023 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 6024 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 6025 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); 6026 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); 6027 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); 6028 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); 6029 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); 6030 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 6031 } 6032 6033 /* 6034 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1 6035 * although it is reserved. 6036 */ 6037 reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG); 6038 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); 6039 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); 6040 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); 6041 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); 6042 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); 6043 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); 6044 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); 6045 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0); 6046 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); 6047 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0); 6048 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg); 6049 6050 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002; 6051 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg); 6052 6053 if (rt2x00_rt(rt2x00dev, RT3883)) { 6054 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_0, 0x12111008); 6055 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_1, 0x16151413); 6056 } 6057 6058 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); 6059 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7); 6060 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, 6061 IEEE80211_MAX_RTS_THRESHOLD); 6062 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 1); 6063 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 6064 6065 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); 6066 6067 /* 6068 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS 6069 * time should be set to 16. However, the original Ralink driver uses 6070 * 16 for both and indeed using a value of 10 for CCK SIFS results in 6071 * connection problems with 11g + CTS protection. Hence, use the same 6072 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS. 6073 */ 6074 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); 6075 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); 6076 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); 6077 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); 6078 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314); 6079 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); 6080 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 6081 6082 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 6083 6084 /* 6085 * ASIC will keep garbage value after boot, clear encryption keys. 6086 */ 6087 for (i = 0; i < 4; i++) 6088 rt2800_register_write(rt2x00dev, SHARED_KEY_MODE_ENTRY(i), 0); 6089 6090 for (i = 0; i < 256; i++) { 6091 rt2800_config_wcid(rt2x00dev, NULL, i); 6092 rt2800_delete_wcid_attr(rt2x00dev, i); 6093 } 6094 6095 /* 6096 * Clear encryption initialization vectors on start, but keep them 6097 * for watchdog reset. Otherwise we will have wrong IVs and not be 6098 * able to keep connections after reset. 6099 */ 6100 if (!test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags)) 6101 for (i = 0; i < 256; i++) 6102 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); 6103 6104 /* 6105 * Clear all beacons 6106 */ 6107 for (i = 0; i < 8; i++) 6108 rt2800_clear_beacon_register(rt2x00dev, i); 6109 6110 if (rt2x00_is_usb(rt2x00dev)) { 6111 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 6112 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); 6113 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 6114 } else if (rt2x00_is_pcie(rt2x00dev)) { 6115 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 6116 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); 6117 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 6118 } else if (rt2x00_is_soc(rt2x00dev)) { 6119 struct clk *clk = clk_get_sys("bus", NULL); 6120 int rate; 6121 6122 if (IS_ERR(clk)) { 6123 clk = clk_get_sys("cpu", NULL); 6124 6125 if (IS_ERR(clk)) { 6126 rate = 125; 6127 } else { 6128 rate = clk_get_rate(clk) / 3000000; 6129 clk_put(clk); 6130 } 6131 } else { 6132 rate = clk_get_rate(clk) / 1000000; 6133 clk_put(clk); 6134 } 6135 6136 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 6137 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, rate); 6138 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 6139 } 6140 6141 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0); 6142 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); 6143 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); 6144 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); 6145 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); 6146 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); 6147 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); 6148 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); 6149 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); 6150 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); 6151 6152 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1); 6153 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); 6154 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); 6155 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); 6156 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); 6157 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); 6158 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); 6159 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); 6160 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); 6161 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); 6162 6163 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0); 6164 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); 6165 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); 6166 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); 6167 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); 6168 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); 6169 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); 6170 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); 6171 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); 6172 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); 6173 6174 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1); 6175 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); 6176 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); 6177 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); 6178 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); 6179 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); 6180 6181 /* 6182 * Do not force the BA window size, we use the TXWI to set it 6183 */ 6184 reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE); 6185 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); 6186 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); 6187 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg); 6188 6189 /* 6190 * We must clear the error counters. 6191 * These registers are cleared on read, 6192 * so we may pass a useless variable to store the value. 6193 */ 6194 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); 6195 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1); 6196 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2); 6197 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0); 6198 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1); 6199 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2); 6200 6201 /* 6202 * Setup leadtime for pre tbtt interrupt to 6ms 6203 */ 6204 reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG); 6205 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); 6206 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg); 6207 6208 /* 6209 * Set up channel statistics timer 6210 */ 6211 reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG); 6212 rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); 6213 rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); 6214 rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); 6215 rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1); 6216 rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1); 6217 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg); 6218 6219 return 0; 6220} 6221 6222static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev) 6223{ 6224 unsigned int i; 6225 u32 reg; 6226 6227 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 6228 reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG); 6229 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY)) 6230 return 0; 6231 6232 udelay(REGISTER_BUSY_DELAY); 6233 } 6234 6235 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n"); 6236 return -EACCES; 6237} 6238 6239static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) 6240{ 6241 unsigned int i; 6242 u8 value; 6243 6244 /* 6245 * BBP was enabled after firmware was loaded, 6246 * but we need to reactivate it now. 6247 */ 6248 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 6249 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 6250 msleep(1); 6251 6252 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 6253 value = rt2800_bbp_read(rt2x00dev, 0); 6254 if ((value != 0xff) && (value != 0x00)) 6255 return 0; 6256 udelay(REGISTER_BUSY_DELAY); 6257 } 6258 6259 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); 6260 return -EACCES; 6261} 6262 6263static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev) 6264{ 6265 u8 value; 6266 6267 value = rt2800_bbp_read(rt2x00dev, 4); 6268 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1); 6269 rt2800_bbp_write(rt2x00dev, 4, value); 6270} 6271 6272static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev) 6273{ 6274 rt2800_bbp_write(rt2x00dev, 142, 1); 6275 rt2800_bbp_write(rt2x00dev, 143, 57); 6276} 6277 6278static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev) 6279{ 6280 static const u8 glrt_table[] = { 6281 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */ 6282 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */ 6283 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */ 6284 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */ 6285 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */ 6286 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */ 6287 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */ 6288 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */ 6289 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */ 6290 }; 6291 int i; 6292 6293 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) { 6294 rt2800_bbp_write(rt2x00dev, 195, 128 + i); 6295 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]); 6296 } 6297}; 6298 6299static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev) 6300{ 6301 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 6302 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6303 rt2800_bbp_write(rt2x00dev, 68, 0x0B); 6304 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6305 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6306 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6307 rt2800_bbp_write(rt2x00dev, 81, 0x37); 6308 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6309 rt2800_bbp_write(rt2x00dev, 83, 0x6A); 6310 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6311 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6312 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6313 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6314 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6315 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6316 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6317} 6318 6319static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev) 6320{ 6321 u16 eeprom; 6322 u8 value; 6323 6324 value = rt2800_bbp_read(rt2x00dev, 138); 6325 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 6326 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 6327 value |= 0x20; 6328 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 6329 value &= ~0x02; 6330 rt2800_bbp_write(rt2x00dev, 138, value); 6331} 6332 6333static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev) 6334{ 6335 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6336 6337 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6338 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6339 6340 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6341 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6342 6343 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6344 6345 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 6346 rt2800_bbp_write(rt2x00dev, 80, 0x08); 6347 6348 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6349 6350 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6351 6352 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6353 6354 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6355 6356 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6357 6358 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6359 6360 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6361 6362 rt2800_bbp_write(rt2x00dev, 105, 0x01); 6363 6364 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6365} 6366 6367static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev) 6368{ 6369 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6370 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6371 6372 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 6373 rt2800_bbp_write(rt2x00dev, 69, 0x16); 6374 rt2800_bbp_write(rt2x00dev, 73, 0x12); 6375 } else { 6376 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6377 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6378 } 6379 6380 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6381 6382 rt2800_bbp_write(rt2x00dev, 81, 0x37); 6383 6384 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6385 6386 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6387 6388 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D)) 6389 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6390 else 6391 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6392 6393 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6394 6395 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6396 6397 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6398 6399 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6400 6401 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6402 6403 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6404} 6405 6406static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev) 6407{ 6408 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6409 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6410 6411 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6412 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6413 6414 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6415 6416 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6417 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6418 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6419 6420 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6421 6422 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6423 6424 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6425 6426 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6427 6428 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6429 6430 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6431 6432 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) || 6433 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || 6434 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E)) 6435 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6436 else 6437 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6438 6439 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6440 6441 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6442 6443 if (rt2x00_rt(rt2x00dev, RT3071) || 6444 rt2x00_rt(rt2x00dev, RT3090)) 6445 rt2800_disable_unused_dac_adc(rt2x00dev); 6446} 6447 6448static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev) 6449{ 6450 u8 value; 6451 6452 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6453 6454 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6455 6456 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6457 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6458 6459 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6460 6461 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6462 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6463 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6464 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6465 6466 rt2800_bbp_write(rt2x00dev, 77, 0x58); 6467 6468 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6469 6470 rt2800_bbp_write(rt2x00dev, 74, 0x0b); 6471 rt2800_bbp_write(rt2x00dev, 79, 0x18); 6472 rt2800_bbp_write(rt2x00dev, 80, 0x09); 6473 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6474 6475 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6476 6477 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6478 6479 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6480 6481 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6482 6483 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6484 6485 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6486 6487 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6488 6489 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6490 6491 rt2800_bbp_write(rt2x00dev, 105, 0x1c); 6492 6493 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6494 6495 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6496 6497 rt2800_bbp_write(rt2x00dev, 67, 0x24); 6498 rt2800_bbp_write(rt2x00dev, 143, 0x04); 6499 rt2800_bbp_write(rt2x00dev, 142, 0x99); 6500 rt2800_bbp_write(rt2x00dev, 150, 0x30); 6501 rt2800_bbp_write(rt2x00dev, 151, 0x2e); 6502 rt2800_bbp_write(rt2x00dev, 152, 0x20); 6503 rt2800_bbp_write(rt2x00dev, 153, 0x34); 6504 rt2800_bbp_write(rt2x00dev, 154, 0x40); 6505 rt2800_bbp_write(rt2x00dev, 155, 0x3b); 6506 rt2800_bbp_write(rt2x00dev, 253, 0x04); 6507 6508 value = rt2800_bbp_read(rt2x00dev, 47); 6509 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1); 6510 rt2800_bbp_write(rt2x00dev, 47, value); 6511 6512 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */ 6513 value = rt2800_bbp_read(rt2x00dev, 3); 6514 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1); 6515 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1); 6516 rt2800_bbp_write(rt2x00dev, 3, value); 6517} 6518 6519static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev) 6520{ 6521 rt2800_bbp_write(rt2x00dev, 3, 0x00); 6522 rt2800_bbp_write(rt2x00dev, 4, 0x50); 6523 6524 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6525 6526 rt2800_bbp_write(rt2x00dev, 47, 0x48); 6527 6528 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6529 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6530 6531 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6532 6533 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6534 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6535 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6536 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6537 6538 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6539 6540 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6541 6542 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 6543 rt2800_bbp_write(rt2x00dev, 80, 0x08); 6544 rt2800_bbp_write(rt2x00dev, 81, 0x37); 6545 6546 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6547 6548 if (rt2x00_rt(rt2x00dev, RT5350)) { 6549 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6550 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6551 } else { 6552 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6553 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6554 } 6555 6556 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6557 6558 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6559 6560 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6561 6562 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6563 6564 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6565 6566 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6567 6568 if (rt2x00_rt(rt2x00dev, RT5350)) { 6569 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 6570 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6571 } else { 6572 rt2800_bbp_write(rt2x00dev, 105, 0x34); 6573 rt2800_bbp_write(rt2x00dev, 106, 0x05); 6574 } 6575 6576 rt2800_bbp_write(rt2x00dev, 120, 0x50); 6577 6578 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6579 6580 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 6581 /* Set ITxBF timeout to 0x9c40=1000msec */ 6582 rt2800_bbp_write(rt2x00dev, 179, 0x02); 6583 rt2800_bbp_write(rt2x00dev, 180, 0x00); 6584 rt2800_bbp_write(rt2x00dev, 182, 0x40); 6585 rt2800_bbp_write(rt2x00dev, 180, 0x01); 6586 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 6587 rt2800_bbp_write(rt2x00dev, 179, 0x00); 6588 /* Reprogram the inband interface to put right values in RXWI */ 6589 rt2800_bbp_write(rt2x00dev, 142, 0x04); 6590 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 6591 rt2800_bbp_write(rt2x00dev, 142, 0x06); 6592 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 6593 rt2800_bbp_write(rt2x00dev, 142, 0x07); 6594 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 6595 rt2800_bbp_write(rt2x00dev, 142, 0x08); 6596 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 6597 6598 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 6599 6600 if (rt2x00_rt(rt2x00dev, RT5350)) { 6601 /* Antenna Software OFDM */ 6602 rt2800_bbp_write(rt2x00dev, 150, 0x40); 6603 /* Antenna Software CCK */ 6604 rt2800_bbp_write(rt2x00dev, 151, 0x30); 6605 rt2800_bbp_write(rt2x00dev, 152, 0xa3); 6606 /* Clear previously selected antenna */ 6607 rt2800_bbp_write(rt2x00dev, 154, 0); 6608 } 6609} 6610 6611static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev) 6612{ 6613 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6614 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6615 6616 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6617 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6618 6619 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6620 6621 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6622 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6623 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6624 6625 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6626 6627 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6628 6629 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6630 6631 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6632 6633 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6634 6635 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6636 6637 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E)) 6638 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6639 else 6640 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6641 6642 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6643 6644 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6645 6646 rt2800_disable_unused_dac_adc(rt2x00dev); 6647} 6648 6649static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev) 6650{ 6651 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6652 6653 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6654 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6655 6656 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6657 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6658 6659 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6660 6661 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6662 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6663 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6664 6665 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6666 6667 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6668 6669 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6670 6671 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6672 6673 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6674 6675 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6676 6677 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6678 6679 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6680 6681 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6682 6683 rt2800_disable_unused_dac_adc(rt2x00dev); 6684} 6685 6686static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev) 6687{ 6688 rt2800_init_bbp_early(rt2x00dev); 6689 6690 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6691 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6692 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6693 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6694 6695 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6696 6697 /* Enable DC filter */ 6698 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E)) 6699 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6700} 6701 6702static void rt2800_init_bbp_3883(struct rt2x00_dev *rt2x00dev) 6703{ 6704 rt2800_init_bbp_early(rt2x00dev); 6705 6706 rt2800_bbp_write(rt2x00dev, 4, 0x50); 6707 rt2800_bbp_write(rt2x00dev, 47, 0x48); 6708 6709 rt2800_bbp_write(rt2x00dev, 86, 0x46); 6710 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6711 6712 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6713 6714 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6715 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6716 rt2800_bbp_write(rt2x00dev, 105, 0x34); 6717 rt2800_bbp_write(rt2x00dev, 106, 0x12); 6718 rt2800_bbp_write(rt2x00dev, 120, 0x50); 6719 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6720 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 6721 6722 /* Set ITxBF timeout to 0x9C40=1000msec */ 6723 rt2800_bbp_write(rt2x00dev, 179, 0x02); 6724 rt2800_bbp_write(rt2x00dev, 180, 0x00); 6725 rt2800_bbp_write(rt2x00dev, 182, 0x40); 6726 rt2800_bbp_write(rt2x00dev, 180, 0x01); 6727 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 6728 6729 rt2800_bbp_write(rt2x00dev, 179, 0x00); 6730 6731 /* Reprogram the inband interface to put right values in RXWI */ 6732 rt2800_bbp_write(rt2x00dev, 142, 0x04); 6733 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 6734 rt2800_bbp_write(rt2x00dev, 142, 0x06); 6735 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 6736 rt2800_bbp_write(rt2x00dev, 142, 0x07); 6737 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 6738 rt2800_bbp_write(rt2x00dev, 142, 0x08); 6739 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 6740 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 6741} 6742 6743static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev) 6744{ 6745 int ant, div_mode; 6746 u16 eeprom; 6747 u8 value; 6748 6749 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6750 6751 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6752 6753 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6754 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6755 6756 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6757 6758 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6759 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6760 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6761 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6762 6763 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6764 6765 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6766 6767 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6768 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6769 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6770 6771 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6772 6773 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6774 6775 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6776 6777 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6778 6779 if (rt2x00_rt(rt2x00dev, RT5392)) 6780 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6781 6782 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6783 6784 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6785 6786 if (rt2x00_rt(rt2x00dev, RT5392)) { 6787 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 6788 rt2800_bbp_write(rt2x00dev, 98, 0x12); 6789 } 6790 6791 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6792 6793 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6794 6795 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 6796 6797 if (rt2x00_rt(rt2x00dev, RT5390)) 6798 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6799 else if (rt2x00_rt(rt2x00dev, RT5392)) 6800 rt2800_bbp_write(rt2x00dev, 106, 0x12); 6801 else 6802 WARN_ON(1); 6803 6804 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6805 6806 if (rt2x00_rt(rt2x00dev, RT5392)) { 6807 rt2800_bbp_write(rt2x00dev, 134, 0xd0); 6808 rt2800_bbp_write(rt2x00dev, 135, 0xf6); 6809 } 6810 6811 rt2800_disable_unused_dac_adc(rt2x00dev); 6812 6813 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 6814 div_mode = rt2x00_get_field16(eeprom, 6815 EEPROM_NIC_CONF1_ANT_DIVERSITY); 6816 ant = (div_mode == 3) ? 1 : 0; 6817 6818 /* check if this is a Bluetooth combo card */ 6819 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 6820 u32 reg; 6821 6822 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 6823 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 6824 rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0); 6825 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0); 6826 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 0); 6827 if (ant == 0) 6828 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 1); 6829 else if (ant == 1) 6830 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 1); 6831 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 6832 } 6833 6834 /* These chips have hardware RX antenna diversity */ 6835 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) || 6836 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) { 6837 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */ 6838 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */ 6839 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */ 6840 } 6841 6842 value = rt2800_bbp_read(rt2x00dev, 152); 6843 if (ant == 0) 6844 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 6845 else 6846 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 6847 rt2800_bbp_write(rt2x00dev, 152, value); 6848 6849 rt2800_init_freq_calibration(rt2x00dev); 6850} 6851 6852static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev) 6853{ 6854 int ant, div_mode; 6855 u16 eeprom; 6856 u8 value; 6857 6858 rt2800_init_bbp_early(rt2x00dev); 6859 6860 value = rt2800_bbp_read(rt2x00dev, 105); 6861 rt2x00_set_field8(&value, BBP105_MLD, 6862 rt2x00dev->default_ant.rx_chain_num == 2); 6863 rt2800_bbp_write(rt2x00dev, 105, value); 6864 6865 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6866 6867 rt2800_bbp_write(rt2x00dev, 20, 0x06); 6868 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6869 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 6870 rt2800_bbp_write(rt2x00dev, 68, 0xDD); 6871 rt2800_bbp_write(rt2x00dev, 69, 0x1A); 6872 rt2800_bbp_write(rt2x00dev, 70, 0x05); 6873 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6874 rt2800_bbp_write(rt2x00dev, 74, 0x0F); 6875 rt2800_bbp_write(rt2x00dev, 75, 0x4F); 6876 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6877 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6878 rt2800_bbp_write(rt2x00dev, 84, 0x9A); 6879 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6880 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6881 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6882 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6883 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 6884 rt2800_bbp_write(rt2x00dev, 98, 0x12); 6885 rt2800_bbp_write(rt2x00dev, 103, 0xC0); 6886 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6887 /* FIXME BBP105 owerwrite */ 6888 rt2800_bbp_write(rt2x00dev, 105, 0x3C); 6889 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6890 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6891 rt2800_bbp_write(rt2x00dev, 134, 0xD0); 6892 rt2800_bbp_write(rt2x00dev, 135, 0xF6); 6893 rt2800_bbp_write(rt2x00dev, 137, 0x0F); 6894 6895 /* Initialize GLRT (Generalized Likehood Radio Test) */ 6896 rt2800_init_bbp_5592_glrt(rt2x00dev); 6897 6898 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6899 6900 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 6901 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY); 6902 ant = (div_mode == 3) ? 1 : 0; 6903 value = rt2800_bbp_read(rt2x00dev, 152); 6904 if (ant == 0) { 6905 /* Main antenna */ 6906 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 6907 } else { 6908 /* Auxiliary antenna */ 6909 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 6910 } 6911 rt2800_bbp_write(rt2x00dev, 152, value); 6912 6913 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) { 6914 value = rt2800_bbp_read(rt2x00dev, 254); 6915 rt2x00_set_field8(&value, BBP254_BIT7, 1); 6916 rt2800_bbp_write(rt2x00dev, 254, value); 6917 } 6918 6919 rt2800_init_freq_calibration(rt2x00dev); 6920 6921 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6922 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 6923 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6924} 6925 6926static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev, 6927 const u8 reg, const u8 value) 6928{ 6929 rt2800_bbp_write(rt2x00dev, 195, reg); 6930 rt2800_bbp_write(rt2x00dev, 196, value); 6931} 6932 6933static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev, 6934 const u8 reg, const u8 value) 6935{ 6936 rt2800_bbp_write(rt2x00dev, 158, reg); 6937 rt2800_bbp_write(rt2x00dev, 159, value); 6938} 6939 6940static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg) 6941{ 6942 rt2800_bbp_write(rt2x00dev, 158, reg); 6943 return rt2800_bbp_read(rt2x00dev, 159); 6944} 6945 6946static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev) 6947{ 6948 u8 bbp; 6949 6950 /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */ 6951 bbp = rt2800_bbp_read(rt2x00dev, 105); 6952 rt2x00_set_field8(&bbp, BBP105_MLD, 6953 rt2x00dev->default_ant.rx_chain_num == 2); 6954 rt2800_bbp_write(rt2x00dev, 105, bbp); 6955 6956 /* Avoid data loss and CRC errors */ 6957 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6958 6959 /* Fix I/Q swap issue */ 6960 bbp = rt2800_bbp_read(rt2x00dev, 1); 6961 bbp |= 0x04; 6962 rt2800_bbp_write(rt2x00dev, 1, bbp); 6963 6964 /* BBP for G band */ 6965 rt2800_bbp_write(rt2x00dev, 3, 0x08); 6966 rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */ 6967 rt2800_bbp_write(rt2x00dev, 6, 0x08); 6968 rt2800_bbp_write(rt2x00dev, 14, 0x09); 6969 rt2800_bbp_write(rt2x00dev, 15, 0xFF); 6970 rt2800_bbp_write(rt2x00dev, 16, 0x01); 6971 rt2800_bbp_write(rt2x00dev, 20, 0x06); 6972 rt2800_bbp_write(rt2x00dev, 21, 0x00); 6973 rt2800_bbp_write(rt2x00dev, 22, 0x00); 6974 rt2800_bbp_write(rt2x00dev, 27, 0x00); 6975 rt2800_bbp_write(rt2x00dev, 28, 0x00); 6976 rt2800_bbp_write(rt2x00dev, 30, 0x00); 6977 rt2800_bbp_write(rt2x00dev, 31, 0x48); 6978 rt2800_bbp_write(rt2x00dev, 47, 0x40); 6979 rt2800_bbp_write(rt2x00dev, 62, 0x00); 6980 rt2800_bbp_write(rt2x00dev, 63, 0x00); 6981 rt2800_bbp_write(rt2x00dev, 64, 0x00); 6982 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 6983 rt2800_bbp_write(rt2x00dev, 66, 0x1C); 6984 rt2800_bbp_write(rt2x00dev, 67, 0x20); 6985 rt2800_bbp_write(rt2x00dev, 68, 0xDD); 6986 rt2800_bbp_write(rt2x00dev, 69, 0x10); 6987 rt2800_bbp_write(rt2x00dev, 70, 0x05); 6988 rt2800_bbp_write(rt2x00dev, 73, 0x18); 6989 rt2800_bbp_write(rt2x00dev, 74, 0x0F); 6990 rt2800_bbp_write(rt2x00dev, 75, 0x60); 6991 rt2800_bbp_write(rt2x00dev, 76, 0x44); 6992 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6993 rt2800_bbp_write(rt2x00dev, 78, 0x1E); 6994 rt2800_bbp_write(rt2x00dev, 79, 0x1C); 6995 rt2800_bbp_write(rt2x00dev, 80, 0x0C); 6996 rt2800_bbp_write(rt2x00dev, 81, 0x3A); 6997 rt2800_bbp_write(rt2x00dev, 82, 0xB6); 6998 rt2800_bbp_write(rt2x00dev, 83, 0x9A); 6999 rt2800_bbp_write(rt2x00dev, 84, 0x9A); 7000 rt2800_bbp_write(rt2x00dev, 86, 0x38); 7001 rt2800_bbp_write(rt2x00dev, 88, 0x90); 7002 rt2800_bbp_write(rt2x00dev, 91, 0x04); 7003 rt2800_bbp_write(rt2x00dev, 92, 0x02); 7004 rt2800_bbp_write(rt2x00dev, 95, 0x9A); 7005 rt2800_bbp_write(rt2x00dev, 96, 0x00); 7006 rt2800_bbp_write(rt2x00dev, 103, 0xC0); 7007 rt2800_bbp_write(rt2x00dev, 104, 0x92); 7008 /* FIXME BBP105 owerwrite */ 7009 rt2800_bbp_write(rt2x00dev, 105, 0x3C); 7010 rt2800_bbp_write(rt2x00dev, 106, 0x12); 7011 rt2800_bbp_write(rt2x00dev, 109, 0x00); 7012 rt2800_bbp_write(rt2x00dev, 134, 0x10); 7013 rt2800_bbp_write(rt2x00dev, 135, 0xA6); 7014 rt2800_bbp_write(rt2x00dev, 137, 0x04); 7015 rt2800_bbp_write(rt2x00dev, 142, 0x30); 7016 rt2800_bbp_write(rt2x00dev, 143, 0xF7); 7017 rt2800_bbp_write(rt2x00dev, 160, 0xEC); 7018 rt2800_bbp_write(rt2x00dev, 161, 0xC4); 7019 rt2800_bbp_write(rt2x00dev, 162, 0x77); 7020 rt2800_bbp_write(rt2x00dev, 163, 0xF9); 7021 rt2800_bbp_write(rt2x00dev, 164, 0x00); 7022 rt2800_bbp_write(rt2x00dev, 165, 0x00); 7023 rt2800_bbp_write(rt2x00dev, 186, 0x00); 7024 rt2800_bbp_write(rt2x00dev, 187, 0x00); 7025 rt2800_bbp_write(rt2x00dev, 188, 0x00); 7026 rt2800_bbp_write(rt2x00dev, 186, 0x00); 7027 rt2800_bbp_write(rt2x00dev, 187, 0x01); 7028 rt2800_bbp_write(rt2x00dev, 188, 0x00); 7029 rt2800_bbp_write(rt2x00dev, 189, 0x00); 7030 7031 rt2800_bbp_write(rt2x00dev, 91, 0x06); 7032 rt2800_bbp_write(rt2x00dev, 92, 0x04); 7033 rt2800_bbp_write(rt2x00dev, 93, 0x54); 7034 rt2800_bbp_write(rt2x00dev, 99, 0x50); 7035 rt2800_bbp_write(rt2x00dev, 148, 0x84); 7036 rt2800_bbp_write(rt2x00dev, 167, 0x80); 7037 rt2800_bbp_write(rt2x00dev, 178, 0xFF); 7038 rt2800_bbp_write(rt2x00dev, 106, 0x13); 7039 7040 /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */ 7041 rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00); 7042 rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14); 7043 rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20); 7044 rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A); 7045 rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16); 7046 rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06); 7047 rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02); 7048 rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07); 7049 rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05); 7050 rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09); 7051 rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20); 7052 rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08); 7053 rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A); 7054 rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00); 7055 rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00); 7056 rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0); 7057 rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F); 7058 rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F); 7059 rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32); 7060 rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08); 7061 rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28); 7062 rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19); 7063 rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A); 7064 rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16); 7065 rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10); 7066 rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10); 7067 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A); 7068 rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36); 7069 rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C); 7070 rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26); 7071 rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24); 7072 rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42); 7073 rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40); 7074 rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30); 7075 rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29); 7076 rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C); 7077 rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46); 7078 rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D); 7079 rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40); 7080 rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E); 7081 rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38); 7082 rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D); 7083 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F); 7084 rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C); 7085 rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34); 7086 rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C); 7087 rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F); 7088 rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C); 7089 rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35); 7090 rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E); 7091 rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F); 7092 rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49); 7093 rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41); 7094 rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36); 7095 rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39); 7096 rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30); 7097 rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30); 7098 rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E); 7099 rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D); 7100 rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28); 7101 rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21); 7102 rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C); 7103 rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16); 7104 rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50); 7105 rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A); 7106 rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43); 7107 rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50); 7108 rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10); 7109 rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10); 7110 rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10); 7111 rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10); 7112 rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D); 7113 rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14); 7114 rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32); 7115 rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C); 7116 rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36); 7117 rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C); 7118 rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43); 7119 rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C); 7120 rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E); 7121 rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36); 7122 rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30); 7123 rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E); 7124 7125 /* BBP for G band DCOC function */ 7126 rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C); 7127 rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00); 7128 rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10); 7129 rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10); 7130 rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10); 7131 rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10); 7132 rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08); 7133 rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40); 7134 rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04); 7135 rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04); 7136 rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08); 7137 rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08); 7138 rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03); 7139 rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03); 7140 rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03); 7141 rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02); 7142 rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40); 7143 rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40); 7144 rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64); 7145 rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64); 7146 7147 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7148} 7149 7150static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) 7151{ 7152 unsigned int i; 7153 u16 eeprom; 7154 u8 reg_id; 7155 u8 value; 7156 7157 if (rt2800_is_305x_soc(rt2x00dev)) 7158 rt2800_init_bbp_305x_soc(rt2x00dev); 7159 7160 switch (rt2x00dev->chip.rt) { 7161 case RT2860: 7162 case RT2872: 7163 case RT2883: 7164 rt2800_init_bbp_28xx(rt2x00dev); 7165 break; 7166 case RT3070: 7167 case RT3071: 7168 case RT3090: 7169 rt2800_init_bbp_30xx(rt2x00dev); 7170 break; 7171 case RT3290: 7172 rt2800_init_bbp_3290(rt2x00dev); 7173 break; 7174 case RT3352: 7175 case RT5350: 7176 rt2800_init_bbp_3352(rt2x00dev); 7177 break; 7178 case RT3390: 7179 rt2800_init_bbp_3390(rt2x00dev); 7180 break; 7181 case RT3572: 7182 rt2800_init_bbp_3572(rt2x00dev); 7183 break; 7184 case RT3593: 7185 rt2800_init_bbp_3593(rt2x00dev); 7186 return; 7187 case RT3883: 7188 rt2800_init_bbp_3883(rt2x00dev); 7189 return; 7190 case RT5390: 7191 case RT5392: 7192 rt2800_init_bbp_53xx(rt2x00dev); 7193 break; 7194 case RT5592: 7195 rt2800_init_bbp_5592(rt2x00dev); 7196 return; 7197 case RT6352: 7198 rt2800_init_bbp_6352(rt2x00dev); 7199 break; 7200 } 7201 7202 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 7203 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 7204 EEPROM_BBP_START, i); 7205 7206 if (eeprom != 0xffff && eeprom != 0x0000) { 7207 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); 7208 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); 7209 rt2800_bbp_write(rt2x00dev, reg_id, value); 7210 } 7211 } 7212} 7213 7214static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev) 7215{ 7216 u32 reg; 7217 7218 reg = rt2800_register_read(rt2x00dev, OPT_14_CSR); 7219 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); 7220 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); 7221} 7222 7223static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40, 7224 u8 filter_target) 7225{ 7226 unsigned int i; 7227 u8 bbp; 7228 u8 rfcsr; 7229 u8 passband; 7230 u8 stopband; 7231 u8 overtuned = 0; 7232 u8 rfcsr24 = (bw40) ? 0x27 : 0x07; 7233 7234 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 7235 7236 bbp = rt2800_bbp_read(rt2x00dev, 4); 7237 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40); 7238 rt2800_bbp_write(rt2x00dev, 4, bbp); 7239 7240 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31); 7241 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40); 7242 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 7243 7244 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 7245 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1); 7246 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 7247 7248 /* 7249 * Set power & frequency of passband test tone 7250 */ 7251 rt2800_bbp_write(rt2x00dev, 24, 0); 7252 7253 for (i = 0; i < 100; i++) { 7254 rt2800_bbp_write(rt2x00dev, 25, 0x90); 7255 msleep(1); 7256 7257 passband = rt2800_bbp_read(rt2x00dev, 55); 7258 if (passband) 7259 break; 7260 } 7261 7262 /* 7263 * Set power & frequency of stopband test tone 7264 */ 7265 rt2800_bbp_write(rt2x00dev, 24, 0x06); 7266 7267 for (i = 0; i < 100; i++) { 7268 rt2800_bbp_write(rt2x00dev, 25, 0x90); 7269 msleep(1); 7270 7271 stopband = rt2800_bbp_read(rt2x00dev, 55); 7272 7273 if ((passband - stopband) <= filter_target) { 7274 rfcsr24++; 7275 overtuned += ((passband - stopband) == filter_target); 7276 } else 7277 break; 7278 7279 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 7280 } 7281 7282 rfcsr24 -= !!overtuned; 7283 7284 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 7285 return rfcsr24; 7286} 7287 7288static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev, 7289 const unsigned int rf_reg) 7290{ 7291 u8 rfcsr; 7292 7293 rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg); 7294 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1); 7295 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 7296 msleep(1); 7297 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0); 7298 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 7299} 7300 7301static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev) 7302{ 7303 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7304 u8 filter_tgt_bw20; 7305 u8 filter_tgt_bw40; 7306 u8 rfcsr, bbp; 7307 7308 /* 7309 * TODO: sync filter_tgt values with vendor driver 7310 */ 7311 if (rt2x00_rt(rt2x00dev, RT3070)) { 7312 filter_tgt_bw20 = 0x16; 7313 filter_tgt_bw40 = 0x19; 7314 } else { 7315 filter_tgt_bw20 = 0x13; 7316 filter_tgt_bw40 = 0x15; 7317 } 7318 7319 drv_data->calibration_bw20 = 7320 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20); 7321 drv_data->calibration_bw40 = 7322 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40); 7323 7324 /* 7325 * Save BBP 25 & 26 values for later use in channel switching (for 3052) 7326 */ 7327 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25); 7328 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26); 7329 7330 /* 7331 * Set back to initial state 7332 */ 7333 rt2800_bbp_write(rt2x00dev, 24, 0); 7334 7335 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 7336 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); 7337 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 7338 7339 /* 7340 * Set BBP back to BW20 7341 */ 7342 bbp = rt2800_bbp_read(rt2x00dev, 4); 7343 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); 7344 rt2800_bbp_write(rt2x00dev, 4, bbp); 7345} 7346 7347static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev) 7348{ 7349 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7350 u8 min_gain, rfcsr, bbp; 7351 u16 eeprom; 7352 7353 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 7354 7355 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0); 7356 if (rt2x00_rt(rt2x00dev, RT3070) || 7357 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7358 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 7359 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 7360 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev)) 7361 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1); 7362 } 7363 7364 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2; 7365 if (drv_data->txmixer_gain_24g >= min_gain) { 7366 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN, 7367 drv_data->txmixer_gain_24g); 7368 } 7369 7370 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 7371 7372 if (rt2x00_rt(rt2x00dev, RT3090)) { 7373 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 7374 bbp = rt2800_bbp_read(rt2x00dev, 138); 7375 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 7376 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 7377 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0); 7378 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 7379 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1); 7380 rt2800_bbp_write(rt2x00dev, 138, bbp); 7381 } 7382 7383 if (rt2x00_rt(rt2x00dev, RT3070)) { 7384 rfcsr = rt2800_rfcsr_read(rt2x00dev, 27); 7385 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) 7386 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3); 7387 else 7388 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0); 7389 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0); 7390 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0); 7391 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0); 7392 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr); 7393 } else if (rt2x00_rt(rt2x00dev, RT3071) || 7394 rt2x00_rt(rt2x00dev, RT3090) || 7395 rt2x00_rt(rt2x00dev, RT3390)) { 7396 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 7397 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 7398 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 7399 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 7400 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 7401 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 7402 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 7403 7404 rfcsr = rt2800_rfcsr_read(rt2x00dev, 15); 7405 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0); 7406 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr); 7407 7408 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 7409 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0); 7410 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 7411 7412 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 7413 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0); 7414 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 7415 } 7416} 7417 7418static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev) 7419{ 7420 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7421 u8 rfcsr; 7422 u8 tx_gain; 7423 7424 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 7425 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0); 7426 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 7427 7428 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 7429 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g, 7430 RFCSR17_TXMIXER_GAIN); 7431 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain); 7432 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 7433 7434 rfcsr = rt2800_rfcsr_read(rt2x00dev, 38); 7435 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0); 7436 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr); 7437 7438 rfcsr = rt2800_rfcsr_read(rt2x00dev, 39); 7439 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0); 7440 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 7441 7442 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 7443 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 7444 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 7445 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 7446 7447 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 7448 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 7449 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 7450 7451 /* TODO: enable stream mode */ 7452} 7453 7454static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev) 7455{ 7456 u8 reg; 7457 u16 eeprom; 7458 7459 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 7460 reg = rt2800_bbp_read(rt2x00dev, 138); 7461 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 7462 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 7463 rt2x00_set_field8(®, BBP138_RX_ADC1, 0); 7464 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 7465 rt2x00_set_field8(®, BBP138_TX_DAC1, 1); 7466 rt2800_bbp_write(rt2x00dev, 138, reg); 7467 7468 reg = rt2800_rfcsr_read(rt2x00dev, 38); 7469 rt2x00_set_field8(®, RFCSR38_RX_LO1_EN, 0); 7470 rt2800_rfcsr_write(rt2x00dev, 38, reg); 7471 7472 reg = rt2800_rfcsr_read(rt2x00dev, 39); 7473 rt2x00_set_field8(®, RFCSR39_RX_LO2_EN, 0); 7474 rt2800_rfcsr_write(rt2x00dev, 39, reg); 7475 7476 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7477 7478 reg = rt2800_rfcsr_read(rt2x00dev, 30); 7479 rt2x00_set_field8(®, RFCSR30_RX_VCM, 2); 7480 rt2800_rfcsr_write(rt2x00dev, 30, reg); 7481} 7482 7483static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev) 7484{ 7485 rt2800_rf_init_calibration(rt2x00dev, 30); 7486 7487 rt2800_rfcsr_write(rt2x00dev, 0, 0x50); 7488 rt2800_rfcsr_write(rt2x00dev, 1, 0x01); 7489 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); 7490 rt2800_rfcsr_write(rt2x00dev, 3, 0x75); 7491 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7492 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 7493 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 7494 rt2800_rfcsr_write(rt2x00dev, 7, 0x50); 7495 rt2800_rfcsr_write(rt2x00dev, 8, 0x39); 7496 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 7497 rt2800_rfcsr_write(rt2x00dev, 10, 0x60); 7498 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7499 rt2800_rfcsr_write(rt2x00dev, 12, 0x75); 7500 rt2800_rfcsr_write(rt2x00dev, 13, 0x75); 7501 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7502 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 7503 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 7504 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 7505 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 7506 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7507 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 7508 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 7509 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7510 rt2800_rfcsr_write(rt2x00dev, 23, 0x31); 7511 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 7512 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 7513 rt2800_rfcsr_write(rt2x00dev, 26, 0x25); 7514 rt2800_rfcsr_write(rt2x00dev, 27, 0x23); 7515 rt2800_rfcsr_write(rt2x00dev, 28, 0x13); 7516 rt2800_rfcsr_write(rt2x00dev, 29, 0x83); 7517 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 7518 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 7519} 7520 7521static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev) 7522{ 7523 u8 rfcsr; 7524 u16 eeprom; 7525 u32 reg; 7526 7527 /* XXX vendor driver do this only for 3070 */ 7528 rt2800_rf_init_calibration(rt2x00dev, 30); 7529 7530 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7531 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 7532 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 7533 rt2800_rfcsr_write(rt2x00dev, 7, 0x60); 7534 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 7535 rt2800_rfcsr_write(rt2x00dev, 10, 0x41); 7536 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7537 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); 7538 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7539 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 7540 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 7541 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 7542 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 7543 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7544 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 7545 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 7546 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 7547 rt2800_rfcsr_write(rt2x00dev, 25, 0x03); 7548 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); 7549 7550 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 7551 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7552 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7553 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7554 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7555 } else if (rt2x00_rt(rt2x00dev, RT3071) || 7556 rt2x00_rt(rt2x00dev, RT3090)) { 7557 rt2800_rfcsr_write(rt2x00dev, 31, 0x14); 7558 7559 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 7560 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 7561 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 7562 7563 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7564 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7565 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7566 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) { 7567 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 7568 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 7569 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7570 else 7571 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7572 } 7573 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7574 7575 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7576 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 7577 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7578 } 7579 7580 rt2800_rx_filter_calibration(rt2x00dev); 7581 7582 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || 7583 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7584 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) 7585 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7586 7587 rt2800_led_open_drain_enable(rt2x00dev); 7588 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7589} 7590 7591static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev) 7592{ 7593 u8 rfcsr; 7594 7595 rt2800_rf_init_calibration(rt2x00dev, 2); 7596 7597 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 7598 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 7599 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 7600 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 7601 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 7602 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3); 7603 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7604 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 7605 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 7606 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 7607 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 7608 rt2800_rfcsr_write(rt2x00dev, 18, 0x02); 7609 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7610 rt2800_rfcsr_write(rt2x00dev, 25, 0x83); 7611 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 7612 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 7613 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 7614 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7615 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7616 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7617 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7618 rt2800_rfcsr_write(rt2x00dev, 34, 0x05); 7619 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7620 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 7621 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 7622 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 7623 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 7624 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 7625 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 7626 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b); 7627 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 7628 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 7629 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 7630 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 7631 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 7632 rt2800_rfcsr_write(rt2x00dev, 49, 0x98); 7633 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 7634 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 7635 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 7636 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 7637 rt2800_rfcsr_write(rt2x00dev, 56, 0x02); 7638 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 7639 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 7640 rt2800_rfcsr_write(rt2x00dev, 59, 0x09); 7641 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 7642 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1); 7643 7644 rfcsr = rt2800_rfcsr_read(rt2x00dev, 29); 7645 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3); 7646 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr); 7647 7648 rt2800_led_open_drain_enable(rt2x00dev); 7649 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7650} 7651 7652static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev) 7653{ 7654 int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0, 7655 &rt2x00dev->cap_flags); 7656 int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1, 7657 &rt2x00dev->cap_flags); 7658 u8 rfcsr; 7659 7660 rt2800_rf_init_calibration(rt2x00dev, 30); 7661 7662 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 7663 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 7664 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 7665 rt2800_rfcsr_write(rt2x00dev, 3, 0x18); 7666 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 7667 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 7668 rt2800_rfcsr_write(rt2x00dev, 6, 0x33); 7669 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7670 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7671 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7672 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2); 7673 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 7674 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 7675 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 7676 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a); 7677 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7678 rt2800_rfcsr_write(rt2x00dev, 16, 0x01); 7679 rt2800_rfcsr_write(rt2x00dev, 18, 0x45); 7680 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7681 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7682 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 7683 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7684 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 7685 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 7686 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 7687 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 7688 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7689 rt2800_rfcsr_write(rt2x00dev, 28, 0x03); 7690 rt2800_rfcsr_write(rt2x00dev, 29, 0x00); 7691 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7692 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7693 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7694 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7695 rfcsr = 0x01; 7696 if (tx0_ext_pa) 7697 rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1); 7698 if (tx1_ext_pa) 7699 rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1); 7700 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 7701 rt2800_rfcsr_write(rt2x00dev, 35, 0x03); 7702 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd); 7703 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c); 7704 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f); 7705 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5); 7706 rt2800_rfcsr_write(rt2x00dev, 40, 0x33); 7707 rfcsr = 0x52; 7708 if (!tx0_ext_pa) { 7709 rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1); 7710 rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1); 7711 } 7712 rt2800_rfcsr_write(rt2x00dev, 41, rfcsr); 7713 rfcsr = 0x52; 7714 if (!tx1_ext_pa) { 7715 rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1); 7716 rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1); 7717 } 7718 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); 7719 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb); 7720 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb); 7721 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb); 7722 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd); 7723 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d); 7724 rt2800_rfcsr_write(rt2x00dev, 48, 0x14); 7725 rt2800_rfcsr_write(rt2x00dev, 49, 0x00); 7726 rfcsr = 0x2d; 7727 if (tx0_ext_pa) 7728 rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1); 7729 if (tx1_ext_pa) 7730 rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1); 7731 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 7732 rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f)); 7733 rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00)); 7734 rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52)); 7735 rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b)); 7736 rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f)); 7737 rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00)); 7738 rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52)); 7739 rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b)); 7740 rt2800_rfcsr_write(rt2x00dev, 59, 0x00); 7741 rt2800_rfcsr_write(rt2x00dev, 60, 0x00); 7742 rt2800_rfcsr_write(rt2x00dev, 61, 0x00); 7743 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 7744 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 7745 7746 rt2800_rx_filter_calibration(rt2x00dev); 7747 rt2800_led_open_drain_enable(rt2x00dev); 7748 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7749} 7750 7751static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev) 7752{ 7753 u32 reg; 7754 7755 rt2800_rf_init_calibration(rt2x00dev, 30); 7756 7757 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0); 7758 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1); 7759 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 7760 rt2800_rfcsr_write(rt2x00dev, 3, 0x62); 7761 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7762 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b); 7763 rt2800_rfcsr_write(rt2x00dev, 6, 0x42); 7764 rt2800_rfcsr_write(rt2x00dev, 7, 0x34); 7765 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 7766 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 7767 rt2800_rfcsr_write(rt2x00dev, 10, 0x61); 7768 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7769 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b); 7770 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0); 7771 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7772 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 7773 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0); 7774 rt2800_rfcsr_write(rt2x00dev, 17, 0x94); 7775 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c); 7776 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a); 7777 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2); 7778 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6); 7779 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7780 rt2800_rfcsr_write(rt2x00dev, 23, 0x14); 7781 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 7782 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 7783 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 7784 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 7785 rt2800_rfcsr_write(rt2x00dev, 28, 0x41); 7786 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f); 7787 rt2800_rfcsr_write(rt2x00dev, 30, 0x20); 7788 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); 7789 7790 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7791 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 7792 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7793 7794 rt2800_rx_filter_calibration(rt2x00dev); 7795 7796 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) 7797 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7798 7799 rt2800_led_open_drain_enable(rt2x00dev); 7800 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7801} 7802 7803static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev) 7804{ 7805 u8 rfcsr; 7806 u32 reg; 7807 7808 rt2800_rf_init_calibration(rt2x00dev, 30); 7809 7810 rt2800_rfcsr_write(rt2x00dev, 0, 0x70); 7811 rt2800_rfcsr_write(rt2x00dev, 1, 0x81); 7812 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 7813 rt2800_rfcsr_write(rt2x00dev, 3, 0x02); 7814 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c); 7815 rt2800_rfcsr_write(rt2x00dev, 5, 0x05); 7816 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a); 7817 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 7818 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 7819 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 7820 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 7821 rt2800_rfcsr_write(rt2x00dev, 12, 0x70); 7822 rt2800_rfcsr_write(rt2x00dev, 13, 0x65); 7823 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0); 7824 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 7825 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c); 7826 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 7827 rt2800_rfcsr_write(rt2x00dev, 18, 0xac); 7828 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 7829 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 7830 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0); 7831 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7832 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c); 7833 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 7834 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 7835 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 7836 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 7837 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7838 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 7839 rt2800_rfcsr_write(rt2x00dev, 30, 0x09); 7840 rt2800_rfcsr_write(rt2x00dev, 31, 0x10); 7841 7842 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 7843 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 7844 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 7845 7846 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7847 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7848 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7849 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7850 msleep(1); 7851 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7852 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7853 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7854 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7855 7856 rt2800_rx_filter_calibration(rt2x00dev); 7857 rt2800_led_open_drain_enable(rt2x00dev); 7858 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7859} 7860 7861static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev) 7862{ 7863 u8 bbp; 7864 bool txbf_enabled = false; /* FIXME */ 7865 7866 bbp = rt2800_bbp_read(rt2x00dev, 105); 7867 if (rt2x00dev->default_ant.rx_chain_num == 1) 7868 rt2x00_set_field8(&bbp, BBP105_MLD, 0); 7869 else 7870 rt2x00_set_field8(&bbp, BBP105_MLD, 1); 7871 rt2800_bbp_write(rt2x00dev, 105, bbp); 7872 7873 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7874 7875 rt2800_bbp_write(rt2x00dev, 92, 0x02); 7876 rt2800_bbp_write(rt2x00dev, 82, 0x82); 7877 rt2800_bbp_write(rt2x00dev, 106, 0x05); 7878 rt2800_bbp_write(rt2x00dev, 104, 0x92); 7879 rt2800_bbp_write(rt2x00dev, 88, 0x90); 7880 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 7881 rt2800_bbp_write(rt2x00dev, 47, 0x48); 7882 rt2800_bbp_write(rt2x00dev, 120, 0x50); 7883 7884 if (txbf_enabled) 7885 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 7886 else 7887 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 7888 7889 /* SNR mapping */ 7890 rt2800_bbp_write(rt2x00dev, 142, 6); 7891 rt2800_bbp_write(rt2x00dev, 143, 160); 7892 rt2800_bbp_write(rt2x00dev, 142, 7); 7893 rt2800_bbp_write(rt2x00dev, 143, 161); 7894 rt2800_bbp_write(rt2x00dev, 142, 8); 7895 rt2800_bbp_write(rt2x00dev, 143, 162); 7896 7897 /* ADC/DAC control */ 7898 rt2800_bbp_write(rt2x00dev, 31, 0x08); 7899 7900 /* RX AGC energy lower bound in log2 */ 7901 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 7902 7903 /* FIXME: BBP 105 owerwrite? */ 7904 rt2800_bbp_write(rt2x00dev, 105, 0x04); 7905 7906} 7907 7908static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev) 7909{ 7910 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7911 u32 reg; 7912 u8 rfcsr; 7913 7914 /* Disable GPIO #4 and #7 function for LAN PE control */ 7915 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7916 rt2x00_set_field32(®, GPIO_SWITCH_4, 0); 7917 rt2x00_set_field32(®, GPIO_SWITCH_7, 0); 7918 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7919 7920 /* Initialize default register values */ 7921 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 7922 rt2800_rfcsr_write(rt2x00dev, 3, 0x80); 7923 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 7924 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 7925 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7926 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7927 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 7928 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 7929 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e); 7930 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 7931 rt2800_rfcsr_write(rt2x00dev, 18, 0x40); 7932 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7933 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7934 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7935 rt2800_rfcsr_write(rt2x00dev, 32, 0x78); 7936 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b); 7937 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c); 7938 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0); 7939 rt2800_rfcsr_write(rt2x00dev, 38, 0x86); 7940 rt2800_rfcsr_write(rt2x00dev, 39, 0x23); 7941 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3); 7942 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 7943 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 7944 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e); 7945 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 7946 rt2800_rfcsr_write(rt2x00dev, 51, 0x75); 7947 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 7948 rt2800_rfcsr_write(rt2x00dev, 53, 0x18); 7949 rt2800_rfcsr_write(rt2x00dev, 54, 0x18); 7950 rt2800_rfcsr_write(rt2x00dev, 55, 0x18); 7951 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb); 7952 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e); 7953 7954 /* Initiate calibration */ 7955 /* TODO: use rt2800_rf_init_calibration ? */ 7956 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 7957 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); 7958 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 7959 7960 rt2800_freq_cal_mode1(rt2x00dev); 7961 7962 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18); 7963 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1); 7964 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); 7965 7966 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7967 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7968 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7969 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7970 usleep_range(1000, 1500); 7971 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7972 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7973 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7974 7975 /* Set initial values for RX filter calibration */ 7976 drv_data->calibration_bw20 = 0x1f; 7977 drv_data->calibration_bw40 = 0x2f; 7978 7979 /* Save BBP 25 & 26 values for later use in channel switching */ 7980 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25); 7981 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26); 7982 7983 rt2800_led_open_drain_enable(rt2x00dev); 7984 rt2800_normal_mode_setup_3593(rt2x00dev); 7985 7986 rt3593_post_bbp_init(rt2x00dev); 7987 7988 /* TODO: enable stream mode support */ 7989} 7990 7991static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev) 7992{ 7993 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 7994 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 7995 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 7996 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 7997 rt2800_rfcsr_write(rt2x00dev, 4, 0x49); 7998 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 7999 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 8000 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8001 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 8002 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 8003 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 8004 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 8005 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 8006 if (rt2800_clk_is_20mhz(rt2x00dev)) 8007 rt2800_rfcsr_write(rt2x00dev, 13, 0x1f); 8008 else 8009 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 8010 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8011 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8012 rt2800_rfcsr_write(rt2x00dev, 16, 0xc0); 8013 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8014 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 8015 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 8016 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 8017 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8018 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 8019 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 8020 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 8021 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 8022 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 8023 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8024 rt2800_rfcsr_write(rt2x00dev, 29, 0xd0); 8025 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8026 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8027 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 8028 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8029 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8030 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8031 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8032 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 8033 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 8034 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 8035 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 8036 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 8037 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 8038 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 8039 rt2800_rfcsr_write(rt2x00dev, 44, 0x0c); 8040 rt2800_rfcsr_write(rt2x00dev, 45, 0xa6); 8041 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 8042 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 8043 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 8044 rt2800_rfcsr_write(rt2x00dev, 49, 0x80); 8045 rt2800_rfcsr_write(rt2x00dev, 50, 0x00); 8046 rt2800_rfcsr_write(rt2x00dev, 51, 0x00); 8047 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 8048 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 8049 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 8050 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 8051 rt2800_rfcsr_write(rt2x00dev, 56, 0x82); 8052 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 8053 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 8054 rt2800_rfcsr_write(rt2x00dev, 59, 0x0b); 8055 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 8056 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 8057 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 8058 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 8059} 8060 8061static void rt2800_init_rfcsr_3883(struct rt2x00_dev *rt2x00dev) 8062{ 8063 u8 rfcsr; 8064 8065 /* TODO: get the actual ECO value from the SoC */ 8066 const unsigned int eco = 5; 8067 8068 rt2800_rf_init_calibration(rt2x00dev, 2); 8069 8070 rt2800_rfcsr_write(rt2x00dev, 0, 0xe0); 8071 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 8072 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 8073 rt2800_rfcsr_write(rt2x00dev, 3, 0x20); 8074 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 8075 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 8076 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 8077 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8078 rt2800_rfcsr_write(rt2x00dev, 8, 0x5b); 8079 rt2800_rfcsr_write(rt2x00dev, 9, 0x08); 8080 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 8081 rt2800_rfcsr_write(rt2x00dev, 11, 0x48); 8082 rt2800_rfcsr_write(rt2x00dev, 12, 0x1a); 8083 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 8084 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8085 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8086 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8087 8088 /* RFCSR 17 will be initialized later based on the 8089 * frequency offset stored in the EEPROM 8090 */ 8091 8092 rt2800_rfcsr_write(rt2x00dev, 18, 0x40); 8093 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 8094 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 8095 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 8096 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8097 rt2800_rfcsr_write(rt2x00dev, 23, 0xc0); 8098 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 8099 rt2800_rfcsr_write(rt2x00dev, 25, 0x00); 8100 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 8101 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 8102 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8103 rt2800_rfcsr_write(rt2x00dev, 29, 0x00); 8104 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8105 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8106 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 8107 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8108 rt2800_rfcsr_write(rt2x00dev, 34, 0x20); 8109 rt2800_rfcsr_write(rt2x00dev, 35, 0x00); 8110 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8111 rt2800_rfcsr_write(rt2x00dev, 37, 0x00); 8112 rt2800_rfcsr_write(rt2x00dev, 38, 0x86); 8113 rt2800_rfcsr_write(rt2x00dev, 39, 0x23); 8114 rt2800_rfcsr_write(rt2x00dev, 40, 0x00); 8115 rt2800_rfcsr_write(rt2x00dev, 41, 0x00); 8116 rt2800_rfcsr_write(rt2x00dev, 42, 0x00); 8117 rt2800_rfcsr_write(rt2x00dev, 43, 0x00); 8118 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 8119 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 8120 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 8121 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 8122 rt2800_rfcsr_write(rt2x00dev, 48, 0x00); 8123 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e); 8124 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 8125 rt2800_rfcsr_write(rt2x00dev, 51, 0x51); 8126 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 8127 rt2800_rfcsr_write(rt2x00dev, 53, 0x76); 8128 rt2800_rfcsr_write(rt2x00dev, 54, 0x76); 8129 rt2800_rfcsr_write(rt2x00dev, 55, 0x76); 8130 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb); 8131 rt2800_rfcsr_write(rt2x00dev, 57, 0x3e); 8132 rt2800_rfcsr_write(rt2x00dev, 58, 0x00); 8133 rt2800_rfcsr_write(rt2x00dev, 59, 0x00); 8134 rt2800_rfcsr_write(rt2x00dev, 60, 0x00); 8135 rt2800_rfcsr_write(rt2x00dev, 61, 0x00); 8136 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 8137 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 8138 8139 /* TODO: rx filter calibration? */ 8140 8141 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 8142 8143 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 8144 8145 rt2800_bbp_write(rt2x00dev, 105, 0x05); 8146 8147 rt2800_bbp_write(rt2x00dev, 179, 0x02); 8148 rt2800_bbp_write(rt2x00dev, 180, 0x00); 8149 rt2800_bbp_write(rt2x00dev, 182, 0x40); 8150 rt2800_bbp_write(rt2x00dev, 180, 0x01); 8151 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 8152 8153 rt2800_bbp_write(rt2x00dev, 179, 0x00); 8154 8155 rt2800_bbp_write(rt2x00dev, 142, 0x04); 8156 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 8157 rt2800_bbp_write(rt2x00dev, 142, 0x06); 8158 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 8159 rt2800_bbp_write(rt2x00dev, 142, 0x07); 8160 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 8161 rt2800_bbp_write(rt2x00dev, 142, 0x08); 8162 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 8163 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 8164 8165 if (eco == 5) { 8166 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8); 8167 rt2800_rfcsr_write(rt2x00dev, 33, 0x32); 8168 } 8169 8170 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 8171 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_BP, 0); 8172 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); 8173 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 8174 msleep(1); 8175 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0); 8176 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 8177 8178 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 8179 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 8180 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 8181 8182 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 8183 rfcsr |= 0xc0; 8184 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 8185 8186 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 8187 rfcsr |= 0x20; 8188 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 8189 8190 rfcsr = rt2800_rfcsr_read(rt2x00dev, 46); 8191 rfcsr |= 0x20; 8192 rt2800_rfcsr_write(rt2x00dev, 46, rfcsr); 8193 8194 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 8195 rfcsr &= ~0xee; 8196 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 8197} 8198 8199static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev) 8200{ 8201 rt2800_rf_init_calibration(rt2x00dev, 2); 8202 8203 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 8204 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 8205 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 8206 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 8207 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8208 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 8209 else 8210 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 8211 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8212 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 8213 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 8214 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 8215 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 8216 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8217 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8218 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8219 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8220 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 8221 8222 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 8223 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 8224 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8225 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 8226 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 8227 if (rt2x00_is_usb(rt2x00dev) && 8228 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8229 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 8230 else 8231 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0); 8232 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 8233 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 8234 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8235 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 8236 8237 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8238 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8239 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 8240 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8241 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8242 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8243 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8244 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 8245 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 8246 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 8247 8248 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 8249 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 8250 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2); 8251 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a); 8252 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 8253 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 8254 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8255 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 8256 else 8257 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b); 8258 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 8259 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 8260 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 8261 8262 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 8263 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8264 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 8265 else 8266 rt2800_rfcsr_write(rt2x00dev, 53, 0x84); 8267 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 8268 rt2800_rfcsr_write(rt2x00dev, 55, 0x44); 8269 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8270 rt2800_rfcsr_write(rt2x00dev, 56, 0x42); 8271 else 8272 rt2800_rfcsr_write(rt2x00dev, 56, 0x22); 8273 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 8274 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 8275 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f); 8276 8277 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 8278 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 8279 if (rt2x00_is_usb(rt2x00dev)) 8280 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 8281 else 8282 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5); 8283 } else { 8284 if (rt2x00_is_usb(rt2x00dev)) 8285 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd); 8286 else 8287 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5); 8288 } 8289 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 8290 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 8291 8292 rt2800_normal_mode_setup_5xxx(rt2x00dev); 8293 8294 rt2800_led_open_drain_enable(rt2x00dev); 8295} 8296 8297static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev) 8298{ 8299 rt2800_rf_init_calibration(rt2x00dev, 2); 8300 8301 rt2800_rfcsr_write(rt2x00dev, 1, 0x17); 8302 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 8303 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 8304 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 8305 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8306 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 8307 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 8308 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 8309 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 8310 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8311 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8312 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8313 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8314 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d); 8315 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 8316 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d); 8317 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8318 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b); 8319 rt2800_rfcsr_write(rt2x00dev, 24, 0x44); 8320 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 8321 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 8322 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 8323 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8324 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 8325 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8326 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8327 rt2800_rfcsr_write(rt2x00dev, 32, 0x20); 8328 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 8329 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8330 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8331 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8332 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 8333 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 8334 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 8335 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f); 8336 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 8337 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 8338 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 8339 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 8340 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 8341 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 8342 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c); 8343 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 8344 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 8345 rt2800_rfcsr_write(rt2x00dev, 50, 0x94); 8346 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a); 8347 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 8348 rt2800_rfcsr_write(rt2x00dev, 53, 0x44); 8349 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 8350 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 8351 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1); 8352 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 8353 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 8354 rt2800_rfcsr_write(rt2x00dev, 59, 0x07); 8355 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 8356 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 8357 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 8358 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 8359 8360 rt2800_normal_mode_setup_5xxx(rt2x00dev); 8361 8362 rt2800_led_open_drain_enable(rt2x00dev); 8363} 8364 8365static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev) 8366{ 8367 rt2800_rf_init_calibration(rt2x00dev, 30); 8368 8369 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F); 8370 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 8371 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 8372 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4); 8373 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8374 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8375 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8376 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8377 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8378 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D); 8379 rt2800_rfcsr_write(rt2x00dev, 20, 0x10); 8380 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D); 8381 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 8382 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8383 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 8384 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 8385 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8386 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8387 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C); 8388 rt2800_rfcsr_write(rt2x00dev, 53, 0x22); 8389 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 8390 8391 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 8392 msleep(1); 8393 8394 rt2800_freq_cal_mode1(rt2x00dev); 8395 8396 /* Enable DC filter */ 8397 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 8398 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 8399 8400 rt2800_normal_mode_setup_5xxx(rt2x00dev); 8401 8402 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C)) 8403 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 8404 8405 rt2800_led_open_drain_enable(rt2x00dev); 8406} 8407 8408static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev, 8409 bool set_bw, bool is_ht40) 8410{ 8411 u8 bbp_val; 8412 8413 bbp_val = rt2800_bbp_read(rt2x00dev, 21); 8414 bbp_val |= 0x1; 8415 rt2800_bbp_write(rt2x00dev, 21, bbp_val); 8416 usleep_range(100, 200); 8417 8418 if (set_bw) { 8419 bbp_val = rt2800_bbp_read(rt2x00dev, 4); 8420 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40); 8421 rt2800_bbp_write(rt2x00dev, 4, bbp_val); 8422 usleep_range(100, 200); 8423 } 8424 8425 bbp_val = rt2800_bbp_read(rt2x00dev, 21); 8426 bbp_val &= (~0x1); 8427 rt2800_bbp_write(rt2x00dev, 21, bbp_val); 8428 usleep_range(100, 200); 8429} 8430 8431static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal) 8432{ 8433 u8 rf_val; 8434 8435 if (btxcal) 8436 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04); 8437 else 8438 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02); 8439 8440 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06); 8441 8442 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 8443 rf_val |= 0x80; 8444 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val); 8445 8446 if (btxcal) { 8447 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1); 8448 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20); 8449 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); 8450 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 8451 rf_val &= (~0x3F); 8452 rf_val |= 0x3F; 8453 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); 8454 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 8455 rf_val &= (~0x3F); 8456 rf_val |= 0x3F; 8457 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); 8458 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31); 8459 } else { 8460 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1); 8461 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18); 8462 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); 8463 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 8464 rf_val &= (~0x3F); 8465 rf_val |= 0x34; 8466 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); 8467 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 8468 rf_val &= (~0x3F); 8469 rf_val |= 0x34; 8470 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); 8471 } 8472 8473 return 0; 8474} 8475 8476static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev) 8477{ 8478 unsigned int cnt; 8479 u8 bbp_val; 8480 char cal_val; 8481 8482 rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82); 8483 8484 cnt = 0; 8485 do { 8486 usleep_range(500, 2000); 8487 bbp_val = rt2800_bbp_read(rt2x00dev, 159); 8488 if (bbp_val == 0x02 || cnt == 20) 8489 break; 8490 8491 cnt++; 8492 } while (cnt < 20); 8493 8494 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39); 8495 cal_val = bbp_val & 0x7F; 8496 if (cal_val >= 0x40) 8497 cal_val -= 128; 8498 8499 return cal_val; 8500} 8501 8502static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev, 8503 bool btxcal) 8504{ 8505 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 8506 u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc; 8507 u8 filter_target; 8508 u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02; 8509 u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31; 8510 int loop = 0, is_ht40, cnt; 8511 u8 bbp_val, rf_val; 8512 char cal_r32_init, cal_r32_val, cal_diff; 8513 u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05; 8514 u8 saverfb5r06, saverfb5r07; 8515 u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20; 8516 u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41; 8517 u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46; 8518 u8 saverfb5r58, saverfb5r59; 8519 u8 savebbp159r0, savebbp159r2, savebbpr23; 8520 u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0; 8521 8522 /* Save MAC registers */ 8523 MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 8524 MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 8525 8526 /* save BBP registers */ 8527 savebbpr23 = rt2800_bbp_read(rt2x00dev, 23); 8528 8529 savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0); 8530 savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2); 8531 8532 /* Save RF registers */ 8533 saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 8534 saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 8535 saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 8536 saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 8537 saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5); 8538 saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 8539 saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 8540 saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8); 8541 saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 8542 saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18); 8543 saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19); 8544 saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20); 8545 8546 saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37); 8547 saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38); 8548 saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39); 8549 saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40); 8550 saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41); 8551 saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42); 8552 saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43); 8553 saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44); 8554 saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45); 8555 saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46); 8556 8557 saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 8558 saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 8559 8560 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 8561 rf_val |= 0x3; 8562 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); 8563 8564 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 8565 rf_val |= 0x1; 8566 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val); 8567 8568 cnt = 0; 8569 do { 8570 usleep_range(500, 2000); 8571 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 8572 if (((rf_val & 0x1) == 0x00) || (cnt == 40)) 8573 break; 8574 cnt++; 8575 } while (cnt < 40); 8576 8577 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 8578 rf_val &= (~0x3); 8579 rf_val |= 0x1; 8580 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); 8581 8582 /* I-3 */ 8583 bbp_val = rt2800_bbp_read(rt2x00dev, 23); 8584 bbp_val &= (~0x1F); 8585 bbp_val |= 0x10; 8586 rt2800_bbp_write(rt2x00dev, 23, bbp_val); 8587 8588 do { 8589 /* I-4,5,6,7,8,9 */ 8590 if (loop == 0) { 8591 is_ht40 = false; 8592 8593 if (btxcal) 8594 filter_target = tx_filter_target_20m; 8595 else 8596 filter_target = rx_filter_target_20m; 8597 } else { 8598 is_ht40 = true; 8599 8600 if (btxcal) 8601 filter_target = tx_filter_target_40m; 8602 else 8603 filter_target = rx_filter_target_40m; 8604 } 8605 8606 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8); 8607 rf_val &= (~0x04); 8608 if (loop == 1) 8609 rf_val |= 0x4; 8610 8611 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val); 8612 8613 rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40); 8614 8615 rt2800_rf_lp_config(rt2x00dev, btxcal); 8616 if (btxcal) { 8617 tx_agc_fc = 0; 8618 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 8619 rf_val &= (~0x7F); 8620 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); 8621 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 8622 rf_val &= (~0x7F); 8623 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); 8624 } else { 8625 rx_agc_fc = 0; 8626 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 8627 rf_val &= (~0x7F); 8628 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); 8629 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 8630 rf_val &= (~0x7F); 8631 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); 8632 } 8633 8634 usleep_range(1000, 2000); 8635 8636 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2); 8637 bbp_val &= (~0x6); 8638 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); 8639 8640 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); 8641 8642 cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev); 8643 8644 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2); 8645 bbp_val |= 0x6; 8646 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); 8647do_cal: 8648 if (btxcal) { 8649 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 8650 rf_val &= (~0x7F); 8651 rf_val |= tx_agc_fc; 8652 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); 8653 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 8654 rf_val &= (~0x7F); 8655 rf_val |= tx_agc_fc; 8656 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); 8657 } else { 8658 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 8659 rf_val &= (~0x7F); 8660 rf_val |= rx_agc_fc; 8661 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); 8662 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 8663 rf_val &= (~0x7F); 8664 rf_val |= rx_agc_fc; 8665 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); 8666 } 8667 8668 usleep_range(500, 1000); 8669 8670 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); 8671 8672 cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev); 8673 8674 cal_diff = cal_r32_init - cal_r32_val; 8675 8676 if (btxcal) 8677 cmm_agc_fc = tx_agc_fc; 8678 else 8679 cmm_agc_fc = rx_agc_fc; 8680 8681 if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) || 8682 ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) { 8683 if (btxcal) 8684 tx_agc_fc = 0; 8685 else 8686 rx_agc_fc = 0; 8687 } else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) { 8688 if (btxcal) 8689 tx_agc_fc++; 8690 else 8691 rx_agc_fc++; 8692 goto do_cal; 8693 } 8694 8695 if (btxcal) { 8696 if (loop == 0) 8697 drv_data->tx_calibration_bw20 = tx_agc_fc; 8698 else 8699 drv_data->tx_calibration_bw40 = tx_agc_fc; 8700 } else { 8701 if (loop == 0) 8702 drv_data->rx_calibration_bw20 = rx_agc_fc; 8703 else 8704 drv_data->rx_calibration_bw40 = rx_agc_fc; 8705 } 8706 8707 loop++; 8708 } while (loop <= 1); 8709 8710 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00); 8711 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01); 8712 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03); 8713 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04); 8714 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05); 8715 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06); 8716 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07); 8717 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08); 8718 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17); 8719 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18); 8720 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19); 8721 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20); 8722 8723 rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37); 8724 rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38); 8725 rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39); 8726 rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40); 8727 rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41); 8728 rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42); 8729 rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43); 8730 rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44); 8731 rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45); 8732 rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46); 8733 8734 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58); 8735 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59); 8736 8737 rt2800_bbp_write(rt2x00dev, 23, savebbpr23); 8738 8739 rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0); 8740 rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2); 8741 8742 bbp_val = rt2800_bbp_read(rt2x00dev, 4); 8743 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 8744 2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)); 8745 rt2800_bbp_write(rt2x00dev, 4, bbp_val); 8746 8747 rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0); 8748 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0); 8749} 8750 8751static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev) 8752{ 8753 /* Initialize RF central register to default value */ 8754 rt2800_rfcsr_write(rt2x00dev, 0, 0x02); 8755 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 8756 rt2800_rfcsr_write(rt2x00dev, 2, 0x33); 8757 rt2800_rfcsr_write(rt2x00dev, 3, 0xFF); 8758 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C); 8759 rt2800_rfcsr_write(rt2x00dev, 5, 0x40); 8760 rt2800_rfcsr_write(rt2x00dev, 6, 0x00); 8761 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8762 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 8763 rt2800_rfcsr_write(rt2x00dev, 9, 0x00); 8764 rt2800_rfcsr_write(rt2x00dev, 10, 0x00); 8765 rt2800_rfcsr_write(rt2x00dev, 11, 0x00); 8766 rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset); 8767 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 8768 rt2800_rfcsr_write(rt2x00dev, 14, 0x40); 8769 rt2800_rfcsr_write(rt2x00dev, 15, 0x22); 8770 rt2800_rfcsr_write(rt2x00dev, 16, 0x4C); 8771 rt2800_rfcsr_write(rt2x00dev, 17, 0x00); 8772 rt2800_rfcsr_write(rt2x00dev, 18, 0x00); 8773 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 8774 rt2800_rfcsr_write(rt2x00dev, 20, 0xA0); 8775 rt2800_rfcsr_write(rt2x00dev, 21, 0x12); 8776 rt2800_rfcsr_write(rt2x00dev, 22, 0x07); 8777 rt2800_rfcsr_write(rt2x00dev, 23, 0x13); 8778 rt2800_rfcsr_write(rt2x00dev, 24, 0xFE); 8779 rt2800_rfcsr_write(rt2x00dev, 25, 0x24); 8780 rt2800_rfcsr_write(rt2x00dev, 26, 0x7A); 8781 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 8782 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8783 rt2800_rfcsr_write(rt2x00dev, 29, 0x05); 8784 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 8785 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 8786 rt2800_rfcsr_write(rt2x00dev, 32, 0x00); 8787 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8788 rt2800_rfcsr_write(rt2x00dev, 34, 0x00); 8789 rt2800_rfcsr_write(rt2x00dev, 35, 0x00); 8790 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8791 rt2800_rfcsr_write(rt2x00dev, 37, 0x00); 8792 rt2800_rfcsr_write(rt2x00dev, 38, 0x00); 8793 rt2800_rfcsr_write(rt2x00dev, 39, 0x00); 8794 rt2800_rfcsr_write(rt2x00dev, 40, 0x00); 8795 rt2800_rfcsr_write(rt2x00dev, 41, 0xD0); 8796 rt2800_rfcsr_write(rt2x00dev, 42, 0x5B); 8797 rt2800_rfcsr_write(rt2x00dev, 43, 0x00); 8798 8799 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 8800 if (rt2800_clk_is_20mhz(rt2x00dev)) 8801 rt2800_rfcsr_write(rt2x00dev, 13, 0x03); 8802 else 8803 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 8804 rt2800_rfcsr_write(rt2x00dev, 14, 0x7C); 8805 rt2800_rfcsr_write(rt2x00dev, 16, 0x80); 8806 rt2800_rfcsr_write(rt2x00dev, 17, 0x99); 8807 rt2800_rfcsr_write(rt2x00dev, 18, 0x99); 8808 rt2800_rfcsr_write(rt2x00dev, 19, 0x09); 8809 rt2800_rfcsr_write(rt2x00dev, 20, 0x50); 8810 rt2800_rfcsr_write(rt2x00dev, 21, 0xB0); 8811 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 8812 rt2800_rfcsr_write(rt2x00dev, 23, 0x06); 8813 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 8814 rt2800_rfcsr_write(rt2x00dev, 25, 0x00); 8815 rt2800_rfcsr_write(rt2x00dev, 26, 0x5D); 8816 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 8817 rt2800_rfcsr_write(rt2x00dev, 28, 0x61); 8818 rt2800_rfcsr_write(rt2x00dev, 29, 0xB5); 8819 rt2800_rfcsr_write(rt2x00dev, 43, 0x02); 8820 8821 rt2800_rfcsr_write(rt2x00dev, 28, 0x62); 8822 rt2800_rfcsr_write(rt2x00dev, 29, 0xAD); 8823 rt2800_rfcsr_write(rt2x00dev, 39, 0x80); 8824 8825 /* Initialize RF channel register to default value */ 8826 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03); 8827 rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00); 8828 rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00); 8829 rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00); 8830 rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00); 8831 rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08); 8832 rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00); 8833 rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51); 8834 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53); 8835 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16); 8836 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61); 8837 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); 8838 rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22); 8839 rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D); 8840 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); 8841 rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13); 8842 rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22); 8843 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27); 8844 rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02); 8845 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); 8846 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01); 8847 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52); 8848 rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80); 8849 rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3); 8850 rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00); 8851 rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00); 8852 rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00); 8853 rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00); 8854 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C); 8855 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B); 8856 rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B); 8857 rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31); 8858 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D); 8859 rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00); 8860 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6); 8861 rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55); 8862 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00); 8863 rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB); 8864 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3); 8865 rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3); 8866 rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03); 8867 rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00); 8868 rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00); 8869 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3); 8870 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3); 8871 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5); 8872 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07); 8873 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68); 8874 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF); 8875 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C); 8876 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07); 8877 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8); 8878 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85); 8879 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10); 8880 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07); 8881 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A); 8882 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85); 8883 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10); 8884 rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C); 8885 rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00); 8886 8887 rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5); 8888 8889 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47); 8890 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71); 8891 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33); 8892 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E); 8893 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23); 8894 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4); 8895 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02); 8896 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12); 8897 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C); 8898 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB); 8899 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D); 8900 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6); 8901 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08); 8902 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4); 8903 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); 8904 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3); 8905 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5); 8906 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27); 8907 rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67); 8908 rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69); 8909 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF); 8910 rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27); 8911 rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20); 8912 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); 8913 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF); 8914 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C); 8915 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20); 8916 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); 8917 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7); 8918 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09); 8919 8920 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51); 8921 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); 8922 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); 8923 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C); 8924 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64); 8925 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51); 8926 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36); 8927 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); 8928 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16); 8929 8930 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C); 8931 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC); 8932 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F); 8933 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27); 8934 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); 8935 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); 8936 8937 /* Initialize RF channel register for DRQFN */ 8938 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); 8939 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3); 8940 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5); 8941 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28); 8942 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68); 8943 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7); 8944 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02); 8945 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7); 8946 8947 /* Initialize RF DC calibration register to default value */ 8948 rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47); 8949 rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00); 8950 rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00); 8951 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00); 8952 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00); 8953 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); 8954 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10); 8955 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10); 8956 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04); 8957 rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00); 8958 rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07); 8959 rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01); 8960 rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07); 8961 rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07); 8962 rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07); 8963 rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20); 8964 rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22); 8965 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00); 8966 rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00); 8967 rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00); 8968 rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00); 8969 rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1); 8970 rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11); 8971 rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02); 8972 rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41); 8973 rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20); 8974 rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00); 8975 rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7); 8976 rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2); 8977 rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20); 8978 rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49); 8979 rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20); 8980 rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04); 8981 rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1); 8982 rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1); 8983 rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01); 8984 rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00); 8985 rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00); 8986 rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00); 8987 rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00); 8988 rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00); 8989 rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00); 8990 rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E); 8991 rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D); 8992 rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E); 8993 rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D); 8994 rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E); 8995 rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D); 8996 rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00); 8997 rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00); 8998 rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00); 8999 rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00); 9000 rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00); 9001 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10); 9002 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10); 9003 rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A); 9004 rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00); 9005 rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00); 9006 rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00); 9007 9008 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08); 9009 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04); 9010 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20); 9011 9012 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); 9013 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C); 9014 9015 rt2800_bw_filter_calibration(rt2x00dev, true); 9016 rt2800_bw_filter_calibration(rt2x00dev, false); 9017} 9018 9019static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) 9020{ 9021 if (rt2800_is_305x_soc(rt2x00dev)) { 9022 rt2800_init_rfcsr_305x_soc(rt2x00dev); 9023 return; 9024 } 9025 9026 switch (rt2x00dev->chip.rt) { 9027 case RT3070: 9028 case RT3071: 9029 case RT3090: 9030 rt2800_init_rfcsr_30xx(rt2x00dev); 9031 break; 9032 case RT3290: 9033 rt2800_init_rfcsr_3290(rt2x00dev); 9034 break; 9035 case RT3352: 9036 rt2800_init_rfcsr_3352(rt2x00dev); 9037 break; 9038 case RT3390: 9039 rt2800_init_rfcsr_3390(rt2x00dev); 9040 break; 9041 case RT3883: 9042 rt2800_init_rfcsr_3883(rt2x00dev); 9043 break; 9044 case RT3572: 9045 rt2800_init_rfcsr_3572(rt2x00dev); 9046 break; 9047 case RT3593: 9048 rt2800_init_rfcsr_3593(rt2x00dev); 9049 break; 9050 case RT5350: 9051 rt2800_init_rfcsr_5350(rt2x00dev); 9052 break; 9053 case RT5390: 9054 rt2800_init_rfcsr_5390(rt2x00dev); 9055 break; 9056 case RT5392: 9057 rt2800_init_rfcsr_5392(rt2x00dev); 9058 break; 9059 case RT5592: 9060 rt2800_init_rfcsr_5592(rt2x00dev); 9061 break; 9062 case RT6352: 9063 rt2800_init_rfcsr_6352(rt2x00dev); 9064 break; 9065 } 9066} 9067 9068int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev) 9069{ 9070 u32 reg; 9071 u16 word; 9072 9073 /* 9074 * Initialize MAC registers. 9075 */ 9076 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) || 9077 rt2800_init_registers(rt2x00dev))) 9078 return -EIO; 9079 9080 /* 9081 * Wait BBP/RF to wake up. 9082 */ 9083 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev))) 9084 return -EIO; 9085 9086 /* 9087 * Send signal during boot time to initialize firmware. 9088 */ 9089 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 9090 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 9091 if (rt2x00_is_usb(rt2x00dev)) 9092 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 9093 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 9094 msleep(1); 9095 9096 /* 9097 * Make sure BBP is up and running. 9098 */ 9099 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev))) 9100 return -EIO; 9101 9102 /* 9103 * Initialize BBP/RF registers. 9104 */ 9105 rt2800_init_bbp(rt2x00dev); 9106 rt2800_init_rfcsr(rt2x00dev); 9107 9108 if (rt2x00_is_usb(rt2x00dev) && 9109 (rt2x00_rt(rt2x00dev, RT3070) || 9110 rt2x00_rt(rt2x00dev, RT3071) || 9111 rt2x00_rt(rt2x00dev, RT3572))) { 9112 udelay(200); 9113 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0); 9114 udelay(10); 9115 } 9116 9117 /* 9118 * Enable RX. 9119 */ 9120 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9121 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 9122 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 9123 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 9124 9125 udelay(50); 9126 9127 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 9128 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); 9129 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); 9130 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 9131 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 9132 9133 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9134 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 9135 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); 9136 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 9137 9138 /* 9139 * Initialize LED control 9140 */ 9141 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF); 9142 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff, 9143 word & 0xff, (word >> 8) & 0xff); 9144 9145 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF); 9146 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff, 9147 word & 0xff, (word >> 8) & 0xff); 9148 9149 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY); 9150 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff, 9151 word & 0xff, (word >> 8) & 0xff); 9152 9153 return 0; 9154} 9155EXPORT_SYMBOL_GPL(rt2800_enable_radio); 9156 9157void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev) 9158{ 9159 u32 reg; 9160 9161 rt2800_disable_wpdma(rt2x00dev); 9162 9163 /* Wait for DMA, ignore error */ 9164 rt2800_wait_wpdma_ready(rt2x00dev); 9165 9166 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9167 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); 9168 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 9169 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 9170} 9171EXPORT_SYMBOL_GPL(rt2800_disable_radio); 9172 9173int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev) 9174{ 9175 u32 reg; 9176 u16 efuse_ctrl_reg; 9177 9178 if (rt2x00_rt(rt2x00dev, RT3290)) 9179 efuse_ctrl_reg = EFUSE_CTRL_3290; 9180 else 9181 efuse_ctrl_reg = EFUSE_CTRL; 9182 9183 reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg); 9184 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); 9185} 9186EXPORT_SYMBOL_GPL(rt2800_efuse_detect); 9187 9188static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) 9189{ 9190 u32 reg; 9191 u16 efuse_ctrl_reg; 9192 u16 efuse_data0_reg; 9193 u16 efuse_data1_reg; 9194 u16 efuse_data2_reg; 9195 u16 efuse_data3_reg; 9196 9197 if (rt2x00_rt(rt2x00dev, RT3290)) { 9198 efuse_ctrl_reg = EFUSE_CTRL_3290; 9199 efuse_data0_reg = EFUSE_DATA0_3290; 9200 efuse_data1_reg = EFUSE_DATA1_3290; 9201 efuse_data2_reg = EFUSE_DATA2_3290; 9202 efuse_data3_reg = EFUSE_DATA3_3290; 9203 } else { 9204 efuse_ctrl_reg = EFUSE_CTRL; 9205 efuse_data0_reg = EFUSE_DATA0; 9206 efuse_data1_reg = EFUSE_DATA1; 9207 efuse_data2_reg = EFUSE_DATA2; 9208 efuse_data3_reg = EFUSE_DATA3; 9209 } 9210 mutex_lock(&rt2x00dev->csr_mutex); 9211 9212 reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg); 9213 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); 9214 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); 9215 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); 9216 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg); 9217 9218 /* Wait until the EEPROM has been loaded */ 9219 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®); 9220 /* Apparently the data is read from end to start */ 9221 reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg); 9222 /* The returned value is in CPU order, but eeprom is le */ 9223 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg); 9224 reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg); 9225 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg); 9226 reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg); 9227 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg); 9228 reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg); 9229 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg); 9230 9231 mutex_unlock(&rt2x00dev->csr_mutex); 9232} 9233 9234int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) 9235{ 9236 unsigned int i; 9237 9238 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8) 9239 rt2800_efuse_read(rt2x00dev, i); 9240 9241 return 0; 9242} 9243EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse); 9244 9245static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev) 9246{ 9247 u16 word; 9248 9249 if (rt2x00_rt(rt2x00dev, RT3593) || 9250 rt2x00_rt(rt2x00dev, RT3883)) 9251 return 0; 9252 9253 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG); 9254 if ((word & 0x00ff) != 0x00ff) 9255 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL); 9256 9257 return 0; 9258} 9259 9260static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev) 9261{ 9262 u16 word; 9263 9264 if (rt2x00_rt(rt2x00dev, RT3593) || 9265 rt2x00_rt(rt2x00dev, RT3883)) 9266 return 0; 9267 9268 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A); 9269 if ((word & 0x00ff) != 0x00ff) 9270 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL); 9271 9272 return 0; 9273} 9274 9275static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) 9276{ 9277 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 9278 u16 word; 9279 u8 *mac; 9280 u8 default_lna_gain; 9281 int retval; 9282 9283 /* 9284 * Read the EEPROM. 9285 */ 9286 retval = rt2800_read_eeprom(rt2x00dev); 9287 if (retval) 9288 return retval; 9289 9290 /* 9291 * Start validation of the data that has been read. 9292 */ 9293 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); 9294 rt2x00lib_set_mac_address(rt2x00dev, mac); 9295 9296 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 9297 if (word == 0xffff) { 9298 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 9299 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1); 9300 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820); 9301 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 9302 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); 9303 } else if (rt2x00_rt(rt2x00dev, RT2860) || 9304 rt2x00_rt(rt2x00dev, RT2872)) { 9305 /* 9306 * There is a max of 2 RX streams for RT28x0 series 9307 */ 9308 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2) 9309 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 9310 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 9311 } 9312 9313 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 9314 if (word == 0xffff) { 9315 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0); 9316 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0); 9317 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0); 9318 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0); 9319 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0); 9320 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0); 9321 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0); 9322 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0); 9323 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0); 9324 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0); 9325 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0); 9326 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0); 9327 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0); 9328 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0); 9329 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0); 9330 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word); 9331 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); 9332 } 9333 9334 word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 9335 if ((word & 0x00ff) == 0x00ff) { 9336 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); 9337 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 9338 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word); 9339 } 9340 if ((word & 0xff00) == 0xff00) { 9341 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE, 9342 LED_MODE_TXRX_ACTIVITY); 9343 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0); 9344 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 9345 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555); 9346 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221); 9347 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8); 9348 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word); 9349 } 9350 9351 /* 9352 * During the LNA validation we are going to use 9353 * lna0 as correct value. Note that EEPROM_LNA 9354 * is never validated. 9355 */ 9356 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 9357 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0); 9358 9359 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG); 9360 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10) 9361 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0); 9362 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10) 9363 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0); 9364 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word); 9365 9366 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev); 9367 9368 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 9369 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10) 9370 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0); 9371 if (!rt2x00_rt(rt2x00dev, RT3593) && 9372 !rt2x00_rt(rt2x00dev, RT3883)) { 9373 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 || 9374 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff) 9375 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1, 9376 default_lna_gain); 9377 } 9378 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word); 9379 9380 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev); 9381 9382 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A); 9383 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10) 9384 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0); 9385 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10) 9386 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0); 9387 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word); 9388 9389 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 9390 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10) 9391 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0); 9392 if (!rt2x00_rt(rt2x00dev, RT3593) && 9393 !rt2x00_rt(rt2x00dev, RT3883)) { 9394 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 || 9395 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff) 9396 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2, 9397 default_lna_gain); 9398 } 9399 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word); 9400 9401 if (rt2x00_rt(rt2x00dev, RT3593) || 9402 rt2x00_rt(rt2x00dev, RT3883)) { 9403 word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 9404 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 || 9405 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff) 9406 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 9407 default_lna_gain); 9408 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 || 9409 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff) 9410 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 9411 default_lna_gain); 9412 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word); 9413 } 9414 9415 return 0; 9416} 9417 9418static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) 9419{ 9420 u16 value; 9421 u16 eeprom; 9422 u16 rf; 9423 9424 /* 9425 * Read EEPROM word for configuration. 9426 */ 9427 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 9428 9429 /* 9430 * Identify RF chipset by EEPROM value 9431 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field 9432 * RT53xx: defined in "EEPROM_CHIP_ID" field 9433 */ 9434 if (rt2x00_rt(rt2x00dev, RT3290) || 9435 rt2x00_rt(rt2x00dev, RT5390) || 9436 rt2x00_rt(rt2x00dev, RT5392) || 9437 rt2x00_rt(rt2x00dev, RT6352)) 9438 rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID); 9439 else if (rt2x00_rt(rt2x00dev, RT3352)) 9440 rf = RF3322; 9441 else if (rt2x00_rt(rt2x00dev, RT3883)) 9442 rf = RF3853; 9443 else if (rt2x00_rt(rt2x00dev, RT5350)) 9444 rf = RF5350; 9445 else 9446 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE); 9447 9448 switch (rf) { 9449 case RF2820: 9450 case RF2850: 9451 case RF2720: 9452 case RF2750: 9453 case RF3020: 9454 case RF2020: 9455 case RF3021: 9456 case RF3022: 9457 case RF3052: 9458 case RF3053: 9459 case RF3070: 9460 case RF3290: 9461 case RF3320: 9462 case RF3322: 9463 case RF3853: 9464 case RF5350: 9465 case RF5360: 9466 case RF5362: 9467 case RF5370: 9468 case RF5372: 9469 case RF5390: 9470 case RF5392: 9471 case RF5592: 9472 case RF7620: 9473 break; 9474 default: 9475 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n", 9476 rf); 9477 return -ENODEV; 9478 } 9479 9480 rt2x00_set_rf(rt2x00dev, rf); 9481 9482 /* 9483 * Identify default antenna configuration. 9484 */ 9485 rt2x00dev->default_ant.tx_chain_num = 9486 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH); 9487 rt2x00dev->default_ant.rx_chain_num = 9488 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH); 9489 9490 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 9491 9492 if (rt2x00_rt(rt2x00dev, RT3070) || 9493 rt2x00_rt(rt2x00dev, RT3090) || 9494 rt2x00_rt(rt2x00dev, RT3352) || 9495 rt2x00_rt(rt2x00dev, RT3390)) { 9496 value = rt2x00_get_field16(eeprom, 9497 EEPROM_NIC_CONF1_ANT_DIVERSITY); 9498 switch (value) { 9499 case 0: 9500 case 1: 9501 case 2: 9502 rt2x00dev->default_ant.tx = ANTENNA_A; 9503 rt2x00dev->default_ant.rx = ANTENNA_A; 9504 break; 9505 case 3: 9506 rt2x00dev->default_ant.tx = ANTENNA_A; 9507 rt2x00dev->default_ant.rx = ANTENNA_B; 9508 break; 9509 } 9510 } else { 9511 rt2x00dev->default_ant.tx = ANTENNA_A; 9512 rt2x00dev->default_ant.rx = ANTENNA_A; 9513 } 9514 9515 /* These chips have hardware RX antenna diversity */ 9516 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) || 9517 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) { 9518 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */ 9519 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */ 9520 } 9521 9522 /* 9523 * Determine external LNA informations. 9524 */ 9525 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G)) 9526 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); 9527 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G)) 9528 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); 9529 9530 /* 9531 * Detect if this device has an hardware controlled radio. 9532 */ 9533 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO)) 9534 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); 9535 9536 /* 9537 * Detect if this device has Bluetooth co-existence. 9538 */ 9539 if (!rt2x00_rt(rt2x00dev, RT3352) && 9540 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) 9541 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags); 9542 9543 /* 9544 * Read frequency offset and RF programming sequence. 9545 */ 9546 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 9547 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); 9548 9549 /* 9550 * Store led settings, for correct led behaviour. 9551 */ 9552#ifdef CONFIG_RT2X00_LIB_LEDS 9553 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); 9554 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); 9555 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); 9556 9557 rt2x00dev->led_mcu_reg = eeprom; 9558#endif /* CONFIG_RT2X00_LIB_LEDS */ 9559 9560 /* 9561 * Check if support EIRP tx power limit feature. 9562 */ 9563 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER); 9564 9565 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) < 9566 EIRP_MAX_TX_POWER_LIMIT) 9567 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags); 9568 9569 /* 9570 * Detect if device uses internal or external PA 9571 */ 9572 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 9573 9574 if (rt2x00_rt(rt2x00dev, RT3352)) { 9575 if (rt2x00_get_field16(eeprom, 9576 EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352)) 9577 __set_bit(CAPABILITY_EXTERNAL_PA_TX0, 9578 &rt2x00dev->cap_flags); 9579 if (rt2x00_get_field16(eeprom, 9580 EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352)) 9581 __set_bit(CAPABILITY_EXTERNAL_PA_TX1, 9582 &rt2x00dev->cap_flags); 9583 } 9584 9585 return 0; 9586} 9587 9588/* 9589 * RF value list for rt28xx 9590 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750) 9591 */ 9592static const struct rf_channel rf_vals[] = { 9593 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b }, 9594 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f }, 9595 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b }, 9596 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f }, 9597 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b }, 9598 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f }, 9599 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b }, 9600 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f }, 9601 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b }, 9602 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f }, 9603 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b }, 9604 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f }, 9605 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b }, 9606 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 }, 9607 9608 /* 802.11 UNI / HyperLan 2 */ 9609 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 }, 9610 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 }, 9611 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 }, 9612 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 }, 9613 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b }, 9614 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b }, 9615 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 }, 9616 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 }, 9617 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b }, 9618 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 }, 9619 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 }, 9620 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 }, 9621 9622 /* 802.11 HyperLan 2 */ 9623 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 }, 9624 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 }, 9625 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 }, 9626 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 }, 9627 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 }, 9628 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b }, 9629 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 }, 9630 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 }, 9631 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 }, 9632 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 }, 9633 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b }, 9634 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 }, 9635 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b }, 9636 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 }, 9637 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b }, 9638 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 }, 9639 9640 /* 802.11 UNII */ 9641 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 }, 9642 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 }, 9643 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f }, 9644 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f }, 9645 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 }, 9646 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 }, 9647 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 }, 9648 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f }, 9649 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 }, 9650 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 }, 9651 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f }, 9652 9653 /* 802.11 Japan */ 9654 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b }, 9655 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 }, 9656 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b }, 9657 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 }, 9658 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 }, 9659 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b }, 9660 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 }, 9661}; 9662 9663/* 9664 * RF value list for rt3xxx 9665 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053) 9666 */ 9667static const struct rf_channel rf_vals_3x[] = { 9668 {1, 241, 2, 2 }, 9669 {2, 241, 2, 7 }, 9670 {3, 242, 2, 2 }, 9671 {4, 242, 2, 7 }, 9672 {5, 243, 2, 2 }, 9673 {6, 243, 2, 7 }, 9674 {7, 244, 2, 2 }, 9675 {8, 244, 2, 7 }, 9676 {9, 245, 2, 2 }, 9677 {10, 245, 2, 7 }, 9678 {11, 246, 2, 2 }, 9679 {12, 246, 2, 7 }, 9680 {13, 247, 2, 2 }, 9681 {14, 248, 2, 4 }, 9682 9683 /* 802.11 UNI / HyperLan 2 */ 9684 {36, 0x56, 0, 4}, 9685 {38, 0x56, 0, 6}, 9686 {40, 0x56, 0, 8}, 9687 {44, 0x57, 0, 0}, 9688 {46, 0x57, 0, 2}, 9689 {48, 0x57, 0, 4}, 9690 {52, 0x57, 0, 8}, 9691 {54, 0x57, 0, 10}, 9692 {56, 0x58, 0, 0}, 9693 {60, 0x58, 0, 4}, 9694 {62, 0x58, 0, 6}, 9695 {64, 0x58, 0, 8}, 9696 9697 /* 802.11 HyperLan 2 */ 9698 {100, 0x5b, 0, 8}, 9699 {102, 0x5b, 0, 10}, 9700 {104, 0x5c, 0, 0}, 9701 {108, 0x5c, 0, 4}, 9702 {110, 0x5c, 0, 6}, 9703 {112, 0x5c, 0, 8}, 9704 {116, 0x5d, 0, 0}, 9705 {118, 0x5d, 0, 2}, 9706 {120, 0x5d, 0, 4}, 9707 {124, 0x5d, 0, 8}, 9708 {126, 0x5d, 0, 10}, 9709 {128, 0x5e, 0, 0}, 9710 {132, 0x5e, 0, 4}, 9711 {134, 0x5e, 0, 6}, 9712 {136, 0x5e, 0, 8}, 9713 {140, 0x5f, 0, 0}, 9714 9715 /* 802.11 UNII */ 9716 {149, 0x5f, 0, 9}, 9717 {151, 0x5f, 0, 11}, 9718 {153, 0x60, 0, 1}, 9719 {157, 0x60, 0, 5}, 9720 {159, 0x60, 0, 7}, 9721 {161, 0x60, 0, 9}, 9722 {165, 0x61, 0, 1}, 9723 {167, 0x61, 0, 3}, 9724 {169, 0x61, 0, 5}, 9725 {171, 0x61, 0, 7}, 9726 {173, 0x61, 0, 9}, 9727}; 9728 9729/* 9730 * RF value list for rt3xxx with Xtal20MHz 9731 * Supports: 2.4 GHz (all) (RF3322) 9732 */ 9733static const struct rf_channel rf_vals_3x_xtal20[] = { 9734 {1, 0xE2, 2, 0x14}, 9735 {2, 0xE3, 2, 0x14}, 9736 {3, 0xE4, 2, 0x14}, 9737 {4, 0xE5, 2, 0x14}, 9738 {5, 0xE6, 2, 0x14}, 9739 {6, 0xE7, 2, 0x14}, 9740 {7, 0xE8, 2, 0x14}, 9741 {8, 0xE9, 2, 0x14}, 9742 {9, 0xEA, 2, 0x14}, 9743 {10, 0xEB, 2, 0x14}, 9744 {11, 0xEC, 2, 0x14}, 9745 {12, 0xED, 2, 0x14}, 9746 {13, 0xEE, 2, 0x14}, 9747 {14, 0xF0, 2, 0x18}, 9748}; 9749 9750static const struct rf_channel rf_vals_3853[] = { 9751 {1, 241, 6, 2}, 9752 {2, 241, 6, 7}, 9753 {3, 242, 6, 2}, 9754 {4, 242, 6, 7}, 9755 {5, 243, 6, 2}, 9756 {6, 243, 6, 7}, 9757 {7, 244, 6, 2}, 9758 {8, 244, 6, 7}, 9759 {9, 245, 6, 2}, 9760 {10, 245, 6, 7}, 9761 {11, 246, 6, 2}, 9762 {12, 246, 6, 7}, 9763 {13, 247, 6, 2}, 9764 {14, 248, 6, 4}, 9765 9766 {36, 0x56, 8, 4}, 9767 {38, 0x56, 8, 6}, 9768 {40, 0x56, 8, 8}, 9769 {44, 0x57, 8, 0}, 9770 {46, 0x57, 8, 2}, 9771 {48, 0x57, 8, 4}, 9772 {52, 0x57, 8, 8}, 9773 {54, 0x57, 8, 10}, 9774 {56, 0x58, 8, 0}, 9775 {60, 0x58, 8, 4}, 9776 {62, 0x58, 8, 6}, 9777 {64, 0x58, 8, 8}, 9778 9779 {100, 0x5b, 8, 8}, 9780 {102, 0x5b, 8, 10}, 9781 {104, 0x5c, 8, 0}, 9782 {108, 0x5c, 8, 4}, 9783 {110, 0x5c, 8, 6}, 9784 {112, 0x5c, 8, 8}, 9785 {114, 0x5c, 8, 10}, 9786 {116, 0x5d, 8, 0}, 9787 {118, 0x5d, 8, 2}, 9788 {120, 0x5d, 8, 4}, 9789 {124, 0x5d, 8, 8}, 9790 {126, 0x5d, 8, 10}, 9791 {128, 0x5e, 8, 0}, 9792 {132, 0x5e, 8, 4}, 9793 {134, 0x5e, 8, 6}, 9794 {136, 0x5e, 8, 8}, 9795 {140, 0x5f, 8, 0}, 9796 9797 {149, 0x5f, 8, 9}, 9798 {151, 0x5f, 8, 11}, 9799 {153, 0x60, 8, 1}, 9800 {157, 0x60, 8, 5}, 9801 {159, 0x60, 8, 7}, 9802 {161, 0x60, 8, 9}, 9803 {165, 0x61, 8, 1}, 9804 {167, 0x61, 8, 3}, 9805 {169, 0x61, 8, 5}, 9806 {171, 0x61, 8, 7}, 9807 {173, 0x61, 8, 9}, 9808}; 9809 9810static const struct rf_channel rf_vals_5592_xtal20[] = { 9811 /* Channel, N, K, mod, R */ 9812 {1, 482, 4, 10, 3}, 9813 {2, 483, 4, 10, 3}, 9814 {3, 484, 4, 10, 3}, 9815 {4, 485, 4, 10, 3}, 9816 {5, 486, 4, 10, 3}, 9817 {6, 487, 4, 10, 3}, 9818 {7, 488, 4, 10, 3}, 9819 {8, 489, 4, 10, 3}, 9820 {9, 490, 4, 10, 3}, 9821 {10, 491, 4, 10, 3}, 9822 {11, 492, 4, 10, 3}, 9823 {12, 493, 4, 10, 3}, 9824 {13, 494, 4, 10, 3}, 9825 {14, 496, 8, 10, 3}, 9826 {36, 172, 8, 12, 1}, 9827 {38, 173, 0, 12, 1}, 9828 {40, 173, 4, 12, 1}, 9829 {42, 173, 8, 12, 1}, 9830 {44, 174, 0, 12, 1}, 9831 {46, 174, 4, 12, 1}, 9832 {48, 174, 8, 12, 1}, 9833 {50, 175, 0, 12, 1}, 9834 {52, 175, 4, 12, 1}, 9835 {54, 175, 8, 12, 1}, 9836 {56, 176, 0, 12, 1}, 9837 {58, 176, 4, 12, 1}, 9838 {60, 176, 8, 12, 1}, 9839 {62, 177, 0, 12, 1}, 9840 {64, 177, 4, 12, 1}, 9841 {100, 183, 4, 12, 1}, 9842 {102, 183, 8, 12, 1}, 9843 {104, 184, 0, 12, 1}, 9844 {106, 184, 4, 12, 1}, 9845 {108, 184, 8, 12, 1}, 9846 {110, 185, 0, 12, 1}, 9847 {112, 185, 4, 12, 1}, 9848 {114, 185, 8, 12, 1}, 9849 {116, 186, 0, 12, 1}, 9850 {118, 186, 4, 12, 1}, 9851 {120, 186, 8, 12, 1}, 9852 {122, 187, 0, 12, 1}, 9853 {124, 187, 4, 12, 1}, 9854 {126, 187, 8, 12, 1}, 9855 {128, 188, 0, 12, 1}, 9856 {130, 188, 4, 12, 1}, 9857 {132, 188, 8, 12, 1}, 9858 {134, 189, 0, 12, 1}, 9859 {136, 189, 4, 12, 1}, 9860 {138, 189, 8, 12, 1}, 9861 {140, 190, 0, 12, 1}, 9862 {149, 191, 6, 12, 1}, 9863 {151, 191, 10, 12, 1}, 9864 {153, 192, 2, 12, 1}, 9865 {155, 192, 6, 12, 1}, 9866 {157, 192, 10, 12, 1}, 9867 {159, 193, 2, 12, 1}, 9868 {161, 193, 6, 12, 1}, 9869 {165, 194, 2, 12, 1}, 9870 {184, 164, 0, 12, 1}, 9871 {188, 164, 4, 12, 1}, 9872 {192, 165, 8, 12, 1}, 9873 {196, 166, 0, 12, 1}, 9874}; 9875 9876static const struct rf_channel rf_vals_5592_xtal40[] = { 9877 /* Channel, N, K, mod, R */ 9878 {1, 241, 2, 10, 3}, 9879 {2, 241, 7, 10, 3}, 9880 {3, 242, 2, 10, 3}, 9881 {4, 242, 7, 10, 3}, 9882 {5, 243, 2, 10, 3}, 9883 {6, 243, 7, 10, 3}, 9884 {7, 244, 2, 10, 3}, 9885 {8, 244, 7, 10, 3}, 9886 {9, 245, 2, 10, 3}, 9887 {10, 245, 7, 10, 3}, 9888 {11, 246, 2, 10, 3}, 9889 {12, 246, 7, 10, 3}, 9890 {13, 247, 2, 10, 3}, 9891 {14, 248, 4, 10, 3}, 9892 {36, 86, 4, 12, 1}, 9893 {38, 86, 6, 12, 1}, 9894 {40, 86, 8, 12, 1}, 9895 {42, 86, 10, 12, 1}, 9896 {44, 87, 0, 12, 1}, 9897 {46, 87, 2, 12, 1}, 9898 {48, 87, 4, 12, 1}, 9899 {50, 87, 6, 12, 1}, 9900 {52, 87, 8, 12, 1}, 9901 {54, 87, 10, 12, 1}, 9902 {56, 88, 0, 12, 1}, 9903 {58, 88, 2, 12, 1}, 9904 {60, 88, 4, 12, 1}, 9905 {62, 88, 6, 12, 1}, 9906 {64, 88, 8, 12, 1}, 9907 {100, 91, 8, 12, 1}, 9908 {102, 91, 10, 12, 1}, 9909 {104, 92, 0, 12, 1}, 9910 {106, 92, 2, 12, 1}, 9911 {108, 92, 4, 12, 1}, 9912 {110, 92, 6, 12, 1}, 9913 {112, 92, 8, 12, 1}, 9914 {114, 92, 10, 12, 1}, 9915 {116, 93, 0, 12, 1}, 9916 {118, 93, 2, 12, 1}, 9917 {120, 93, 4, 12, 1}, 9918 {122, 93, 6, 12, 1}, 9919 {124, 93, 8, 12, 1}, 9920 {126, 93, 10, 12, 1}, 9921 {128, 94, 0, 12, 1}, 9922 {130, 94, 2, 12, 1}, 9923 {132, 94, 4, 12, 1}, 9924 {134, 94, 6, 12, 1}, 9925 {136, 94, 8, 12, 1}, 9926 {138, 94, 10, 12, 1}, 9927 {140, 95, 0, 12, 1}, 9928 {149, 95, 9, 12, 1}, 9929 {151, 95, 11, 12, 1}, 9930 {153, 96, 1, 12, 1}, 9931 {155, 96, 3, 12, 1}, 9932 {157, 96, 5, 12, 1}, 9933 {159, 96, 7, 12, 1}, 9934 {161, 96, 9, 12, 1}, 9935 {165, 97, 1, 12, 1}, 9936 {184, 82, 0, 12, 1}, 9937 {188, 82, 4, 12, 1}, 9938 {192, 82, 8, 12, 1}, 9939 {196, 83, 0, 12, 1}, 9940}; 9941 9942static const struct rf_channel rf_vals_7620[] = { 9943 {1, 0x50, 0x99, 0x99, 1}, 9944 {2, 0x50, 0x44, 0x44, 2}, 9945 {3, 0x50, 0xEE, 0xEE, 2}, 9946 {4, 0x50, 0x99, 0x99, 3}, 9947 {5, 0x51, 0x44, 0x44, 0}, 9948 {6, 0x51, 0xEE, 0xEE, 0}, 9949 {7, 0x51, 0x99, 0x99, 1}, 9950 {8, 0x51, 0x44, 0x44, 2}, 9951 {9, 0x51, 0xEE, 0xEE, 2}, 9952 {10, 0x51, 0x99, 0x99, 3}, 9953 {11, 0x52, 0x44, 0x44, 0}, 9954 {12, 0x52, 0xEE, 0xEE, 0}, 9955 {13, 0x52, 0x99, 0x99, 1}, 9956 {14, 0x52, 0x33, 0x33, 3}, 9957}; 9958 9959static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) 9960{ 9961 struct hw_mode_spec *spec = &rt2x00dev->spec; 9962 struct channel_info *info; 9963 char *default_power1; 9964 char *default_power2; 9965 char *default_power3; 9966 unsigned int i, tx_chains, rx_chains; 9967 u32 reg; 9968 9969 /* 9970 * Disable powersaving as default. 9971 */ 9972 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 9973 9974 /* 9975 * Change default retry settings to values corresponding more closely 9976 * to rate[0].count setting of minstrel rate control algorithm. 9977 */ 9978 rt2x00dev->hw->wiphy->retry_short = 2; 9979 rt2x00dev->hw->wiphy->retry_long = 2; 9980 9981 /* 9982 * Initialize all hw fields. 9983 */ 9984 ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS); 9985 ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION); 9986 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); 9987 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); 9988 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); 9989 9990 /* 9991 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices 9992 * unless we are capable of sending the buffered frames out after the 9993 * DTIM transmission using rt2x00lib_beacondone. This will send out 9994 * multicast and broadcast traffic immediately instead of buffering it 9995 * infinitly and thus dropping it after some time. 9996 */ 9997 if (!rt2x00_is_usb(rt2x00dev)) 9998 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING); 9999 10000 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE); 10001 10002 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 10003 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 10004 rt2800_eeprom_addr(rt2x00dev, 10005 EEPROM_MAC_ADDR_0)); 10006 10007 /* 10008 * As rt2800 has a global fallback table we cannot specify 10009 * more then one tx rate per frame but since the hw will 10010 * try several rates (based on the fallback table) we should 10011 * initialize max_report_rates to the maximum number of rates 10012 * we are going to try. Otherwise mac80211 will truncate our 10013 * reported tx rates and the rc algortihm will end up with 10014 * incorrect data. 10015 */ 10016 rt2x00dev->hw->max_rates = 1; 10017 rt2x00dev->hw->max_report_rates = 7; 10018 rt2x00dev->hw->max_rate_tries = 1; 10019 10020 /* 10021 * Initialize hw_mode information. 10022 */ 10023 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 10024 10025 switch (rt2x00dev->chip.rf) { 10026 case RF2720: 10027 case RF2820: 10028 spec->num_channels = 14; 10029 spec->channels = rf_vals; 10030 break; 10031 10032 case RF2750: 10033 case RF2850: 10034 spec->num_channels = ARRAY_SIZE(rf_vals); 10035 spec->channels = rf_vals; 10036 break; 10037 10038 case RF2020: 10039 case RF3020: 10040 case RF3021: 10041 case RF3022: 10042 case RF3070: 10043 case RF3290: 10044 case RF3320: 10045 case RF3322: 10046 case RF5350: 10047 case RF5360: 10048 case RF5362: 10049 case RF5370: 10050 case RF5372: 10051 case RF5390: 10052 case RF5392: 10053 spec->num_channels = 14; 10054 if (rt2800_clk_is_20mhz(rt2x00dev)) 10055 spec->channels = rf_vals_3x_xtal20; 10056 else 10057 spec->channels = rf_vals_3x; 10058 break; 10059 10060 case RF7620: 10061 spec->num_channels = ARRAY_SIZE(rf_vals_7620); 10062 spec->channels = rf_vals_7620; 10063 break; 10064 10065 case RF3052: 10066 case RF3053: 10067 spec->num_channels = ARRAY_SIZE(rf_vals_3x); 10068 spec->channels = rf_vals_3x; 10069 break; 10070 10071 case RF3853: 10072 spec->num_channels = ARRAY_SIZE(rf_vals_3853); 10073 spec->channels = rf_vals_3853; 10074 break; 10075 10076 case RF5592: 10077 reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX); 10078 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) { 10079 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40); 10080 spec->channels = rf_vals_5592_xtal40; 10081 } else { 10082 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20); 10083 spec->channels = rf_vals_5592_xtal20; 10084 } 10085 break; 10086 } 10087 10088 if (WARN_ON_ONCE(!spec->channels)) 10089 return -ENODEV; 10090 10091 spec->supported_bands = SUPPORT_BAND_2GHZ; 10092 if (spec->num_channels > 14) 10093 spec->supported_bands |= SUPPORT_BAND_5GHZ; 10094 10095 /* 10096 * Initialize HT information. 10097 */ 10098 if (!rt2x00_rf(rt2x00dev, RF2020)) 10099 spec->ht.ht_supported = true; 10100 else 10101 spec->ht.ht_supported = false; 10102 10103 spec->ht.cap = 10104 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 10105 IEEE80211_HT_CAP_GRN_FLD | 10106 IEEE80211_HT_CAP_SGI_20 | 10107 IEEE80211_HT_CAP_SGI_40; 10108 10109 tx_chains = rt2x00dev->default_ant.tx_chain_num; 10110 rx_chains = rt2x00dev->default_ant.rx_chain_num; 10111 10112 if (tx_chains >= 2) 10113 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC; 10114 10115 spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT; 10116 10117 spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2; 10118 spec->ht.ampdu_density = 4; 10119 spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 10120 if (tx_chains != rx_chains) { 10121 spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 10122 spec->ht.mcs.tx_params |= 10123 (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT; 10124 } 10125 10126 switch (rx_chains) { 10127 case 3: 10128 spec->ht.mcs.rx_mask[2] = 0xff; 10129 fallthrough; 10130 case 2: 10131 spec->ht.mcs.rx_mask[1] = 0xff; 10132 fallthrough; 10133 case 1: 10134 spec->ht.mcs.rx_mask[0] = 0xff; 10135 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */ 10136 break; 10137 } 10138 10139 /* 10140 * Create channel information array 10141 */ 10142 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); 10143 if (!info) 10144 return -ENOMEM; 10145 10146 spec->channels_info = info; 10147 10148 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); 10149 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); 10150 10151 if (rt2x00dev->default_ant.tx_chain_num > 2) 10152 default_power3 = rt2800_eeprom_addr(rt2x00dev, 10153 EEPROM_EXT_TXPOWER_BG3); 10154 else 10155 default_power3 = NULL; 10156 10157 for (i = 0; i < 14; i++) { 10158 info[i].default_power1 = default_power1[i]; 10159 info[i].default_power2 = default_power2[i]; 10160 if (default_power3) 10161 info[i].default_power3 = default_power3[i]; 10162 } 10163 10164 if (spec->num_channels > 14) { 10165 default_power1 = rt2800_eeprom_addr(rt2x00dev, 10166 EEPROM_TXPOWER_A1); 10167 default_power2 = rt2800_eeprom_addr(rt2x00dev, 10168 EEPROM_TXPOWER_A2); 10169 10170 if (rt2x00dev->default_ant.tx_chain_num > 2) 10171 default_power3 = 10172 rt2800_eeprom_addr(rt2x00dev, 10173 EEPROM_EXT_TXPOWER_A3); 10174 else 10175 default_power3 = NULL; 10176 10177 for (i = 14; i < spec->num_channels; i++) { 10178 info[i].default_power1 = default_power1[i - 14]; 10179 info[i].default_power2 = default_power2[i - 14]; 10180 if (default_power3) 10181 info[i].default_power3 = default_power3[i - 14]; 10182 } 10183 } 10184 10185 switch (rt2x00dev->chip.rf) { 10186 case RF2020: 10187 case RF3020: 10188 case RF3021: 10189 case RF3022: 10190 case RF3320: 10191 case RF3052: 10192 case RF3053: 10193 case RF3070: 10194 case RF3290: 10195 case RF3853: 10196 case RF5350: 10197 case RF5360: 10198 case RF5362: 10199 case RF5370: 10200 case RF5372: 10201 case RF5390: 10202 case RF5392: 10203 case RF5592: 10204 case RF7620: 10205 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags); 10206 break; 10207 } 10208 10209 return 0; 10210} 10211 10212static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev) 10213{ 10214 u32 reg; 10215 u32 rt; 10216 u32 rev; 10217 10218 if (rt2x00_rt(rt2x00dev, RT3290)) 10219 reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290); 10220 else 10221 reg = rt2800_register_read(rt2x00dev, MAC_CSR0); 10222 10223 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET); 10224 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION); 10225 10226 switch (rt) { 10227 case RT2860: 10228 case RT2872: 10229 case RT2883: 10230 case RT3070: 10231 case RT3071: 10232 case RT3090: 10233 case RT3290: 10234 case RT3352: 10235 case RT3390: 10236 case RT3572: 10237 case RT3593: 10238 case RT3883: 10239 case RT5350: 10240 case RT5390: 10241 case RT5392: 10242 case RT5592: 10243 break; 10244 default: 10245 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n", 10246 rt, rev); 10247 return -ENODEV; 10248 } 10249 10250 if (rt == RT5390 && rt2x00_is_soc(rt2x00dev)) 10251 rt = RT6352; 10252 10253 rt2x00_set_rt(rt2x00dev, rt, rev); 10254 10255 return 0; 10256} 10257 10258int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev) 10259{ 10260 int retval; 10261 u32 reg; 10262 10263 retval = rt2800_probe_rt(rt2x00dev); 10264 if (retval) 10265 return retval; 10266 10267 /* 10268 * Allocate eeprom data. 10269 */ 10270 retval = rt2800_validate_eeprom(rt2x00dev); 10271 if (retval) 10272 return retval; 10273 10274 retval = rt2800_init_eeprom(rt2x00dev); 10275 if (retval) 10276 return retval; 10277 10278 /* 10279 * Enable rfkill polling by setting GPIO direction of the 10280 * rfkill switch GPIO pin correctly. 10281 */ 10282 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 10283 rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1); 10284 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 10285 10286 /* 10287 * Initialize hw specifications. 10288 */ 10289 retval = rt2800_probe_hw_mode(rt2x00dev); 10290 if (retval) 10291 return retval; 10292 10293 /* 10294 * Set device capabilities. 10295 */ 10296 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags); 10297 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags); 10298 if (!rt2x00_is_usb(rt2x00dev)) 10299 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags); 10300 10301 /* 10302 * Set device requirements. 10303 */ 10304 if (!rt2x00_is_soc(rt2x00dev)) 10305 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags); 10306 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags); 10307 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags); 10308 if (!rt2800_hwcrypt_disabled(rt2x00dev)) 10309 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags); 10310 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); 10311 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags); 10312 if (rt2x00_is_usb(rt2x00dev)) 10313 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags); 10314 else { 10315 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); 10316 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags); 10317 } 10318 10319 if (modparam_watchdog) { 10320 __set_bit(CAPABILITY_RESTART_HW, &rt2x00dev->cap_flags); 10321 rt2x00dev->link.watchdog_interval = msecs_to_jiffies(100); 10322 } else { 10323 rt2x00dev->link.watchdog_disabled = true; 10324 } 10325 10326 /* 10327 * Set the rssi offset. 10328 */ 10329 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; 10330 10331 return 0; 10332} 10333EXPORT_SYMBOL_GPL(rt2800_probe_hw); 10334 10335/* 10336 * IEEE80211 stack callback functions. 10337 */ 10338void rt2800_get_key_seq(struct ieee80211_hw *hw, 10339 struct ieee80211_key_conf *key, 10340 struct ieee80211_key_seq *seq) 10341{ 10342 struct rt2x00_dev *rt2x00dev = hw->priv; 10343 struct mac_iveiv_entry iveiv_entry; 10344 u32 offset; 10345 10346 if (key->cipher != WLAN_CIPHER_SUITE_TKIP) 10347 return; 10348 10349 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 10350 rt2800_register_multiread(rt2x00dev, offset, 10351 &iveiv_entry, sizeof(iveiv_entry)); 10352 10353 memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2); 10354 memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4); 10355} 10356EXPORT_SYMBOL_GPL(rt2800_get_key_seq); 10357 10358int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value) 10359{ 10360 struct rt2x00_dev *rt2x00dev = hw->priv; 10361 u32 reg; 10362 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD); 10363 10364 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); 10365 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); 10366 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 10367 10368 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); 10369 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); 10370 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 10371 10372 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 10373 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); 10374 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 10375 10376 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 10377 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); 10378 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 10379 10380 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 10381 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); 10382 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 10383 10384 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 10385 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); 10386 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 10387 10388 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 10389 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); 10390 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 10391 10392 return 0; 10393} 10394EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold); 10395 10396int rt2800_conf_tx(struct ieee80211_hw *hw, 10397 struct ieee80211_vif *vif, u16 queue_idx, 10398 const struct ieee80211_tx_queue_params *params) 10399{ 10400 struct rt2x00_dev *rt2x00dev = hw->priv; 10401 struct data_queue *queue; 10402 struct rt2x00_field32 field; 10403 int retval; 10404 u32 reg; 10405 u32 offset; 10406 10407 /* 10408 * First pass the configuration through rt2x00lib, that will 10409 * update the queue settings and validate the input. After that 10410 * we are free to update the registers based on the value 10411 * in the queue parameter. 10412 */ 10413 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params); 10414 if (retval) 10415 return retval; 10416 10417 /* 10418 * We only need to perform additional register initialization 10419 * for WMM queues/ 10420 */ 10421 if (queue_idx >= 4) 10422 return 0; 10423 10424 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); 10425 10426 /* Update WMM TXOP register */ 10427 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2))); 10428 field.bit_offset = (queue_idx & 1) * 16; 10429 field.bit_mask = 0xffff << field.bit_offset; 10430 10431 reg = rt2800_register_read(rt2x00dev, offset); 10432 rt2x00_set_field32(®, field, queue->txop); 10433 rt2800_register_write(rt2x00dev, offset, reg); 10434 10435 /* Update WMM registers */ 10436 field.bit_offset = queue_idx * 4; 10437 field.bit_mask = 0xf << field.bit_offset; 10438 10439 reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG); 10440 rt2x00_set_field32(®, field, queue->aifs); 10441 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); 10442 10443 reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG); 10444 rt2x00_set_field32(®, field, queue->cw_min); 10445 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); 10446 10447 reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG); 10448 rt2x00_set_field32(®, field, queue->cw_max); 10449 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); 10450 10451 /* Update EDCA registers */ 10452 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx); 10453 10454 reg = rt2800_register_read(rt2x00dev, offset); 10455 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); 10456 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); 10457 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); 10458 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); 10459 rt2800_register_write(rt2x00dev, offset, reg); 10460 10461 return 0; 10462} 10463EXPORT_SYMBOL_GPL(rt2800_conf_tx); 10464 10465u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 10466{ 10467 struct rt2x00_dev *rt2x00dev = hw->priv; 10468 u64 tsf; 10469 u32 reg; 10470 10471 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1); 10472 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; 10473 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0); 10474 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); 10475 10476 return tsf; 10477} 10478EXPORT_SYMBOL_GPL(rt2800_get_tsf); 10479 10480int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 10481 struct ieee80211_ampdu_params *params) 10482{ 10483 struct ieee80211_sta *sta = params->sta; 10484 enum ieee80211_ampdu_mlme_action action = params->action; 10485 u16 tid = params->tid; 10486 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv; 10487 int ret = 0; 10488 10489 /* 10490 * Don't allow aggregation for stations the hardware isn't aware 10491 * of because tx status reports for frames to an unknown station 10492 * always contain wcid=WCID_END+1 and thus we can't distinguish 10493 * between multiple stations which leads to unwanted situations 10494 * when the hw reorders frames due to aggregation. 10495 */ 10496 if (sta_priv->wcid > WCID_END) 10497 return -ENOSPC; 10498 10499 switch (action) { 10500 case IEEE80211_AMPDU_RX_START: 10501 case IEEE80211_AMPDU_RX_STOP: 10502 /* 10503 * The hw itself takes care of setting up BlockAck mechanisms. 10504 * So, we only have to allow mac80211 to nagotiate a BlockAck 10505 * agreement. Once that is done, the hw will BlockAck incoming 10506 * AMPDUs without further setup. 10507 */ 10508 break; 10509 case IEEE80211_AMPDU_TX_START: 10510 ret = IEEE80211_AMPDU_TX_START_IMMEDIATE; 10511 break; 10512 case IEEE80211_AMPDU_TX_STOP_CONT: 10513 case IEEE80211_AMPDU_TX_STOP_FLUSH: 10514 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 10515 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 10516 break; 10517 case IEEE80211_AMPDU_TX_OPERATIONAL: 10518 break; 10519 default: 10520 rt2x00_warn((struct rt2x00_dev *)hw->priv, 10521 "Unknown AMPDU action\n"); 10522 } 10523 10524 return ret; 10525} 10526EXPORT_SYMBOL_GPL(rt2800_ampdu_action); 10527 10528int rt2800_get_survey(struct ieee80211_hw *hw, int idx, 10529 struct survey_info *survey) 10530{ 10531 struct rt2x00_dev *rt2x00dev = hw->priv; 10532 struct ieee80211_conf *conf = &hw->conf; 10533 u32 idle, busy, busy_ext; 10534 10535 if (idx != 0) 10536 return -ENOENT; 10537 10538 survey->channel = conf->chandef.chan; 10539 10540 idle = rt2800_register_read(rt2x00dev, CH_IDLE_STA); 10541 busy = rt2800_register_read(rt2x00dev, CH_BUSY_STA); 10542 busy_ext = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); 10543 10544 if (idle || busy) { 10545 survey->filled = SURVEY_INFO_TIME | 10546 SURVEY_INFO_TIME_BUSY | 10547 SURVEY_INFO_TIME_EXT_BUSY; 10548 10549 survey->time = (idle + busy) / 1000; 10550 survey->time_busy = busy / 1000; 10551 survey->time_ext_busy = busy_ext / 1000; 10552 } 10553 10554 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) 10555 survey->filled |= SURVEY_INFO_IN_USE; 10556 10557 return 0; 10558 10559} 10560EXPORT_SYMBOL_GPL(rt2800_get_survey); 10561 10562MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz"); 10563MODULE_VERSION(DRV_VERSION); 10564MODULE_DESCRIPTION("Ralink RT2800 library"); 10565MODULE_LICENSE("GPL"); 10566