1/* SPDX-License-Identifier: ISC */
2/* Copyright (C) 2020 MediaTek Inc. */
3
4#ifndef __MT7915_MCU_H
5#define __MT7915_MCU_H
6
7struct mt7915_mcu_txd {
8	__le32 txd[8];
9
10	__le16 len;
11	__le16 pq_id;
12
13	u8 cid;
14	u8 pkt_type;
15	u8 set_query; /* FW don't care */
16	u8 seq;
17
18	u8 uc_d2b0_rev;
19	u8 ext_cid;
20	u8 s2d_index;
21	u8 ext_cid_ack;
22
23	u32 reserved[5];
24} __packed __aligned(4);
25
26/* event table */
27enum {
28	MCU_EVENT_TARGET_ADDRESS_LEN = 0x01,
29	MCU_EVENT_FW_START = 0x01,
30	MCU_EVENT_GENERIC = 0x01,
31	MCU_EVENT_ACCESS_REG = 0x02,
32	MCU_EVENT_MT_PATCH_SEM = 0x04,
33	MCU_EVENT_CH_PRIVILEGE = 0x18,
34	MCU_EVENT_EXT = 0xed,
35	MCU_EVENT_RESTART_DL = 0xef,
36};
37
38/* ext event table */
39enum {
40	MCU_EXT_EVENT_PS_SYNC = 0x5,
41	MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13,
42	MCU_EXT_EVENT_THERMAL_PROTECT = 0x22,
43	MCU_EXT_EVENT_ASSERT_DUMP = 0x23,
44	MCU_EXT_EVENT_RDD_REPORT = 0x3a,
45	MCU_EXT_EVENT_CSA_NOTIFY = 0x4f,
46	MCU_EXT_EVENT_RATE_REPORT = 0x87,
47};
48
49struct mt7915_mcu_rxd {
50	__le32 rxd[6];
51
52	__le16 len;
53	__le16 pkt_type_id;
54
55	u8 eid;
56	u8 seq;
57	__le16 __rsv;
58
59	u8 ext_eid;
60	u8 __rsv1[2];
61	u8 s2d_index;
62};
63
64struct mt7915_mcu_rdd_report {
65	struct mt7915_mcu_rxd rxd;
66
67	u8 idx;
68	u8 long_detected;
69	u8 constant_prf_detected;
70	u8 staggered_prf_detected;
71	u8 radar_type_idx;
72	u8 periodic_pulse_num;
73	u8 long_pulse_num;
74	u8 hw_pulse_num;
75
76	u8 out_lpn;
77	u8 out_spn;
78	u8 out_crpn;
79	u8 out_crpw;
80	u8 out_crbn;
81	u8 out_stgpn;
82	u8 out_stgpw;
83
84	u8 rsv;
85
86	__le32 out_pri_const;
87	__le32 out_pri_stg[3];
88
89	struct {
90		__le32 start;
91		__le16 pulse_width;
92		__le16 pulse_power;
93		u8 mdrdy_flag;
94		u8 rsv[3];
95	} long_pulse[32];
96
97	struct {
98		__le32 start;
99		__le16 pulse_width;
100		__le16 pulse_power;
101		u8 mdrdy_flag;
102		u8 rsv[3];
103	} periodic_pulse[32];
104
105	struct {
106		__le32 start;
107		__le16 pulse_width;
108		__le16 pulse_power;
109		u8 sc_pass;
110		u8 sw_reset;
111		u8 mdrdy_flag;
112		u8 tx_active;
113	} hw_pulse[32];
114} __packed;
115
116struct mt7915_mcu_eeprom_info {
117	__le32 addr;
118	__le32 valid;
119	u8 data[16];
120} __packed;
121
122struct mt7915_mcu_ra_info {
123	struct mt7915_mcu_rxd rxd;
124
125	__le32 event_id;
126	__le16 wlan_idx;
127	__le16 ru_idx;
128	__le16 direction;
129	__le16 dump_group;
130
131	__le32 suggest_rate;
132	__le32 min_rate;	/* for dynamic sounding */
133	__le32 max_rate;	/* for dynamic sounding */
134	__le32 init_rate_down_rate;
135
136	__le16 curr_rate;
137	__le16 init_rate_down_total;
138	__le16 init_rate_down_succ;
139	__le16 success;
140	__le16 attempts;
141
142	__le16 prev_rate;
143	__le16 prob_up_rate;
144	u8 no_rate_up_cnt;
145	u8 ppdu_cnt;
146	u8 gi;
147
148	u8 try_up_fail;
149	u8 try_up_total;
150	u8 suggest_wf;
151	u8 try_up_check;
152	u8 prob_up_period;
153	u8 prob_down_pending;
154} __packed;
155
156#define MT_RA_RATE_NSS			GENMASK(8, 6)
157#define MT_RA_RATE_MCS			GENMASK(3, 0)
158#define MT_RA_RATE_TX_MODE		GENMASK(12, 9)
159#define MT_RA_RATE_DCM_EN		BIT(4)
160#define MT_RA_RATE_BW			GENMASK(14, 13)
161
162#define MCU_PQ_ID(p, q)			(((p) << 15) | ((q) << 10))
163#define MCU_PKT_ID			0xa0
164
165enum {
166	MCU_Q_QUERY,
167	MCU_Q_SET,
168	MCU_Q_RESERVED,
169	MCU_Q_NA
170};
171
172enum {
173	MCU_S2D_H2N,
174	MCU_S2D_C2N,
175	MCU_S2D_H2C,
176	MCU_S2D_H2CN
177};
178
179enum {
180	MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01,
181	MCU_CMD_FW_START_REQ = 0x02,
182	MCU_CMD_INIT_ACCESS_REG = 0x3,
183	MCU_CMD_NIC_POWER_CTRL = 0x4,
184	MCU_CMD_PATCH_START_REQ = 0x05,
185	MCU_CMD_PATCH_FINISH_REQ = 0x07,
186	MCU_CMD_PATCH_SEM_CONTROL = 0x10,
187	MCU_CMD_EXT_CID = 0xED,
188	MCU_CMD_FW_SCATTER = 0xEE,
189	MCU_CMD_RESTART_DL_REQ = 0xEF,
190};
191
192enum {
193	MCU_EXT_CMD_EFUSE_ACCESS = 0x01,
194	MCU_EXT_CMD_PM_STATE_CTRL = 0x07,
195	MCU_EXT_CMD_CHANNEL_SWITCH = 0x08,
196	MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
197	MCU_EXT_CMD_TXBF_ACTION = 0x1e,
198	MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
199	MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
200	MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26,
201	MCU_EXT_CMD_EDCA_UPDATE = 0x27,
202	MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A,
203	MCU_EXT_CMD_THERMAL_CTRL = 0x2c,
204	MCU_EXT_CMD_SET_DRR_CTRL = 0x36,
205	MCU_EXT_CMD_SET_RDD_CTRL = 0x3a,
206	MCU_EXT_CMD_PROTECT_CTRL = 0x3e,
207	MCU_EXT_CMD_MAC_INIT_CTRL = 0x46,
208	MCU_EXT_CMD_RX_HDR_TRANS = 0x47,
209	MCU_EXT_CMD_SET_RX_PATH = 0x4e,
210	MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
211	MCU_EXT_CMD_SET_SER_TRIGGER = 0x81,
212	MCU_EXT_CMD_SCS_CTRL = 0x82,
213	MCU_EXT_CMD_RATE_CTRL = 0x87,
214	MCU_EXT_CMD_FW_DBG_CTRL = 0x95,
215	MCU_EXT_CMD_SET_RDD_TH = 0x9d,
216	MCU_EXT_CMD_SET_SPR = 0xa8,
217};
218
219enum {
220	PATCH_SEM_RELEASE,
221	PATCH_SEM_GET
222};
223
224enum {
225	PATCH_NOT_DL_SEM_FAIL,
226	PATCH_IS_DL,
227	PATCH_NOT_DL_SEM_SUCCESS,
228	PATCH_REL_SEM_SUCCESS
229};
230
231enum {
232	FW_STATE_INITIAL,
233	FW_STATE_FW_DOWNLOAD,
234	FW_STATE_NORMAL_OPERATION,
235	FW_STATE_NORMAL_TRX,
236	FW_STATE_WACPU_RDY        = 7
237};
238
239enum {
240	EE_MODE_EFUSE,
241	EE_MODE_BUFFER,
242};
243
244enum {
245	EE_FORMAT_BIN,
246	EE_FORMAT_WHOLE,
247	EE_FORMAT_MULTIPLE,
248};
249
250#define STA_TYPE_STA			BIT(0)
251#define STA_TYPE_AP			BIT(1)
252#define STA_TYPE_ADHOC			BIT(2)
253#define STA_TYPE_WDS			BIT(4)
254#define STA_TYPE_BC			BIT(5)
255
256#define NETWORK_INFRA			BIT(16)
257#define NETWORK_P2P			BIT(17)
258#define NETWORK_IBSS			BIT(18)
259#define NETWORK_WDS			BIT(21)
260
261#define CONNECTION_INFRA_STA		(STA_TYPE_STA | NETWORK_INFRA)
262#define CONNECTION_INFRA_AP		(STA_TYPE_AP | NETWORK_INFRA)
263#define CONNECTION_P2P_GC		(STA_TYPE_STA | NETWORK_P2P)
264#define CONNECTION_P2P_GO		(STA_TYPE_AP | NETWORK_P2P)
265#define CONNECTION_IBSS_ADHOC		(STA_TYPE_ADHOC | NETWORK_IBSS)
266#define CONNECTION_WDS			(STA_TYPE_WDS | NETWORK_WDS)
267#define CONNECTION_INFRA_BC		(STA_TYPE_BC | NETWORK_INFRA)
268
269#define CONN_STATE_DISCONNECT		0
270#define CONN_STATE_CONNECT		1
271#define CONN_STATE_PORT_SECURE		2
272
273enum {
274	DEV_INFO_ACTIVE,
275	DEV_INFO_MAX_NUM
276};
277
278enum {
279	SCS_SEND_DATA,
280	SCS_SET_MANUAL_PD_TH,
281	SCS_CONFIG,
282	SCS_ENABLE,
283	SCS_SHOW_INFO,
284	SCS_GET_GLO_ADDR,
285	SCS_GET_GLO_ADDR_EVENT,
286};
287
288enum {
289	CMD_CBW_20MHZ = IEEE80211_STA_RX_BW_20,
290	CMD_CBW_40MHZ = IEEE80211_STA_RX_BW_40,
291	CMD_CBW_80MHZ = IEEE80211_STA_RX_BW_80,
292	CMD_CBW_160MHZ = IEEE80211_STA_RX_BW_160,
293	CMD_CBW_10MHZ,
294	CMD_CBW_5MHZ,
295	CMD_CBW_8080MHZ,
296
297	CMD_HE_MCS_BW80 = 0,
298	CMD_HE_MCS_BW160,
299	CMD_HE_MCS_BW8080,
300	CMD_HE_MCS_BW_NUM
301};
302
303struct tlv {
304	__le16 tag;
305	__le16 len;
306} __packed;
307
308struct bss_info_omac {
309	__le16 tag;
310	__le16 len;
311	u8 hw_bss_idx;
312	u8 omac_idx;
313	u8 band_idx;
314	u8 rsv0;
315	__le32 conn_type;
316	u32 rsv1;
317} __packed;
318
319struct bss_info_basic {
320	__le16 tag;
321	__le16 len;
322	__le32 network_type;
323	u8 active;
324	u8 rsv0;
325	__le16 bcn_interval;
326	u8 bssid[ETH_ALEN];
327	u8 wmm_idx;
328	u8 dtim_period;
329	u8 bmc_wcid_lo;
330	u8 cipher;
331	u8 phy_mode;
332	u8 max_bssid;	/* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */
333	u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */
334	u8 bmc_wcid_hi;	/* high Byte and version */
335	u8 rsv[2];
336} __packed;
337
338struct bss_info_rf_ch {
339	__le16 tag;
340	__le16 len;
341	u8 pri_ch;
342	u8 center_ch0;
343	u8 center_ch1;
344	u8 bw;
345	u8 he_ru26_block;	/* 1: don't send HETB in RU26, 0: allow */
346	u8 he_all_disable;	/* 1: disallow all HETB, 0: allow */
347	u8 rsv[2];
348} __packed;
349
350struct bss_info_ext_bss {
351	__le16 tag;
352	__le16 len;
353	__le32 mbss_tsf_offset; /* in unit of us */
354	u8 rsv[8];
355} __packed;
356
357struct bss_info_sync_mode {
358	__le16 tag;
359	__le16 len;
360	__le16 bcn_interval;
361	u8 enable;
362	u8 dtim_period;
363	u8 rsv[8];
364} __packed;
365
366struct bss_info_bmc_rate {
367	__le16 tag;
368	__le16 len;
369	__le16 bc_trans;
370	__le16 mc_trans;
371	u8 short_preamble;
372	u8 rsv[7];
373} __packed;
374
375struct bss_info_ra {
376	__le16 tag;
377	__le16 len;
378	u8 op_mode;
379	u8 adhoc_en;
380	u8 short_preamble;
381	u8 tx_streams;
382	u8 rx_streams;
383	u8 algo;
384	u8 force_sgi;
385	u8 force_gf;
386	u8 ht_mode;
387	u8 has_20_sta;		/* Check if any sta support GF. */
388	u8 bss_width_trigger_events;
389	u8 vht_nss_cap;
390	u8 vht_bw_signal;	/* not use */
391	u8 vht_force_sgi;	/* not use */
392	u8 se_off;
393	u8 antenna_idx;
394	u8 train_up_rule;
395	u8 rsv[3];
396	unsigned short train_up_high_thres;
397	short train_up_rule_rssi;
398	unsigned short low_traffic_thres;
399	__le16 max_phyrate;
400	__le32 phy_cap;
401	__le32 interval;
402	__le32 fast_interval;
403} __packed;
404
405struct bss_info_hw_amsdu {
406	__le16 tag;
407	__le16 len;
408	__le32 cmp_bitmap_0;
409	__le32 cmp_bitmap_1;
410	__le16 trig_thres;
411	u8 enable;
412	u8 rsv;
413} __packed;
414
415struct bss_info_he {
416	__le16 tag;
417	__le16 len;
418	u8 he_pe_duration;
419	u8 vht_op_info_present;
420	__le16 he_rts_thres;
421	__le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
422	u8 rsv[6];
423} __packed;
424
425struct bss_info_bcn {
426	__le16 tag;
427	__le16 len;
428	u8 ver;
429	u8 enable;
430	__le16 sub_ntlv;
431} __packed __aligned(4);
432
433struct bss_info_bcn_csa {
434	__le16 tag;
435	__le16 len;
436	u8 cnt;
437	u8 rsv[3];
438} __packed __aligned(4);
439
440struct bss_info_bcn_bcc {
441	__le16 tag;
442	__le16 len;
443	u8 cnt;
444	u8 rsv[3];
445} __packed __aligned(4);
446
447struct bss_info_bcn_mbss {
448#define MAX_BEACON_NUM	32
449	__le16 tag;
450	__le16 len;
451	__le32 bitmap;
452	__le16 offset[MAX_BEACON_NUM];
453	u8 rsv[8];
454} __packed __aligned(4);
455
456struct bss_info_bcn_cont {
457	__le16 tag;
458	__le16 len;
459	__le16 tim_ofs;
460	__le16 csa_ofs;
461	__le16 bcc_ofs;
462	__le16 pkt_len;
463} __packed __aligned(4);
464
465enum {
466	BSS_INFO_BCN_CSA,
467	BSS_INFO_BCN_BCC,
468	BSS_INFO_BCN_MBSSID,
469	BSS_INFO_BCN_CONTENT,
470	BSS_INFO_BCN_MAX
471};
472
473enum {
474	BSS_INFO_OMAC,
475	BSS_INFO_BASIC,
476	BSS_INFO_RF_CH,		/* optional, for BT/LTE coex */
477	BSS_INFO_PM,		/* sta only */
478	BSS_INFO_UAPSD,		/* sta only */
479	BSS_INFO_ROAM_DETECT,	/* obsoleted */
480	BSS_INFO_LQ_RM,		/* obsoleted */
481	BSS_INFO_EXT_BSS,
482	BSS_INFO_BMC_RATE,	/* for bmc rate control in CR4 */
483	BSS_INFO_SYNC_MODE,
484	BSS_INFO_RA,
485	BSS_INFO_HW_AMSDU,
486	BSS_INFO_BSS_COLOR,
487	BSS_INFO_HE_BASIC,
488	BSS_INFO_PROTECT_INFO,
489	BSS_INFO_OFFLOAD,
490	BSS_INFO_11V_MBSSID,
491	BSS_INFO_MAX_NUM
492};
493
494enum {
495	WTBL_RESET_AND_SET = 1,
496	WTBL_SET,
497	WTBL_QUERY,
498	WTBL_RESET_ALL
499};
500
501struct wtbl_req_hdr {
502	u8 wlan_idx_lo;
503	u8 operation;
504	__le16 tlv_num;
505	u8 wlan_idx_hi;
506	u8 rsv[3];
507} __packed;
508
509struct wtbl_generic {
510	__le16 tag;
511	__le16 len;
512	u8 peer_addr[ETH_ALEN];
513	u8 muar_idx;
514	u8 skip_tx;
515	u8 cf_ack;
516	u8 qos;
517	u8 mesh;
518	u8 adm;
519	__le16 partial_aid;
520	u8 baf_en;
521	u8 aad_om;
522} __packed;
523
524struct wtbl_rx {
525	__le16 tag;
526	__le16 len;
527	u8 rcid;
528	u8 rca1;
529	u8 rca2;
530	u8 rv;
531	u8 rsv[4];
532} __packed;
533
534struct wtbl_ht {
535	__le16 tag;
536	__le16 len;
537	u8 ht;
538	u8 ldpc;
539	u8 af;
540	u8 mm;
541	u8 rsv[4];
542} __packed;
543
544struct wtbl_vht {
545	__le16 tag;
546	__le16 len;
547	u8 ldpc;
548	u8 dyn_bw;
549	u8 vht;
550	u8 txop_ps;
551	u8 rsv[4];
552} __packed;
553
554enum {
555	MT_BA_TYPE_INVALID,
556	MT_BA_TYPE_ORIGINATOR,
557	MT_BA_TYPE_RECIPIENT
558};
559
560enum {
561	RST_BA_MAC_TID_MATCH,
562	RST_BA_MAC_MATCH,
563	RST_BA_NO_MATCH
564};
565
566struct wtbl_ba {
567	__le16 tag;
568	__le16 len;
569	/* common */
570	u8 tid;
571	u8 ba_type;
572	u8 rsv0[2];
573	/* originator only */
574	__le16 sn;
575	u8 ba_en;
576	u8 ba_winsize_idx;
577	__le16 ba_winsize;
578	/* recipient only */
579	u8 peer_addr[ETH_ALEN];
580	u8 rst_ba_tid;
581	u8 rst_ba_sel;
582	u8 rst_ba_sb;
583	u8 band_idx;
584	u8 rsv1[4];
585} __packed;
586
587struct wtbl_smps {
588	__le16 tag;
589	__le16 len;
590	u8 smps;
591	u8 rsv[3];
592} __packed;
593
594enum {
595	WTBL_GENERIC,
596	WTBL_RX,
597	WTBL_HT,
598	WTBL_VHT,
599	WTBL_PEER_PS,		/* not used */
600	WTBL_TX_PS,
601	WTBL_HDR_TRANS,
602	WTBL_SEC_KEY,
603	WTBL_BA,
604	WTBL_RDG,		/* obsoleted */
605	WTBL_PROTECT,		/* not used */
606	WTBL_CLEAR,		/* not used */
607	WTBL_BF,
608	WTBL_SMPS,
609	WTBL_RAW_DATA,		/* debug only */
610	WTBL_PN,
611	WTBL_SPE,
612	WTBL_MAX_NUM
613};
614
615struct sta_ntlv_hdr {
616	u8 rsv[2];
617	__le16 tlv_num;
618} __packed;
619
620struct sta_req_hdr {
621	u8 bss_idx;
622	u8 wlan_idx_lo;
623	__le16 tlv_num;
624	u8 is_tlv_append;
625	u8 muar_idx;
626	u8 wlan_idx_hi;
627	u8 rsv;
628} __packed;
629
630struct sta_rec_basic {
631	__le16 tag;
632	__le16 len;
633	__le32 conn_type;
634	u8 conn_state;
635	u8 qos;
636	__le16 aid;
637	u8 peer_addr[ETH_ALEN];
638	__le16 extra_info;
639} __packed;
640
641struct sta_rec_ht {
642	__le16 tag;
643	__le16 len;
644	__le16 ht_cap;
645	u16 rsv;
646} __packed;
647
648struct sta_rec_vht {
649	__le16 tag;
650	__le16 len;
651	__le32 vht_cap;
652	__le16 vht_rx_mcs_map;
653	__le16 vht_tx_mcs_map;
654	u8 rts_bw_sig;
655	u8 rsv[3];
656} __packed;
657
658struct sta_rec_uapsd {
659	__le16 tag;
660	__le16 len;
661	u8 dac_map;
662	u8 tac_map;
663	u8 max_sp;
664	u8 rsv0;
665	__le16 listen_interval;
666	u8 rsv1[2];
667} __packed;
668
669struct sta_rec_muru {
670	__le16 tag;
671	__le16 len;
672
673	struct {
674		bool ofdma_dl_en;
675		bool ofdma_ul_en;
676		bool mimo_dl_en;
677		bool mimo_ul_en;
678		u8 rsv[4];
679	} cfg;
680
681	struct {
682		u8 punc_pream_rx;
683		bool he_20m_in_40m_2g;
684		bool he_20m_in_160m;
685		bool he_80m_in_160m;
686		bool lt16_sigb;
687		bool rx_su_comp_sigb;
688		bool rx_su_non_comp_sigb;
689		u8 rsv;
690	} ofdma_dl;
691
692	struct {
693		u8 t_frame_dur;
694		u8 mu_cascading;
695		u8 uo_ra;
696		u8 he_2x996_tone;
697		u8 rx_t_frame_11ac;
698		u8 rsv[3];
699	} ofdma_ul;
700
701	struct {
702		bool vht_mu_bfee;
703		bool partial_bw_dl_mimo;
704		u8 rsv[2];
705	} mimo_dl;
706
707	struct {
708		bool full_ul_mimo;
709		bool partial_ul_mimo;
710		u8 rsv[2];
711	} mimo_ul;
712} __packed;
713
714struct sta_rec_he {
715	__le16 tag;
716	__le16 len;
717
718	__le32 he_cap;
719
720	u8 t_frame_dur;
721	u8 max_ampdu_exp;
722	u8 bw_set;
723	u8 device_class;
724	u8 dcm_tx_mode;
725	u8 dcm_tx_max_nss;
726	u8 dcm_rx_mode;
727	u8 dcm_rx_max_nss;
728	u8 dcm_max_ru;
729	u8 punc_pream_rx;
730	u8 pkt_ext;
731	u8 rsv1;
732
733	__le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
734
735	u8 rsv2[2];
736} __packed;
737
738struct sta_rec_ba {
739	__le16 tag;
740	__le16 len;
741	u8 tid;
742	u8 ba_type;
743	u8 amsdu;
744	u8 ba_en;
745	__le16 ssn;
746	__le16 winsize;
747} __packed;
748
749struct sta_rec_amsdu {
750	__le16 tag;
751	__le16 len;
752	u8 max_amsdu_num;
753	u8 max_mpdu_size;
754	u8 amsdu_en;
755	u8 rsv;
756} __packed;
757
758struct sec_key {
759	u8 cipher_id;
760	u8 cipher_len;
761	u8 key_id;
762	u8 key_len;
763	u8 key[32];
764} __packed;
765
766struct sta_rec_sec {
767	__le16 tag;
768	__le16 len;
769	u8 add;
770	u8 n_cipher;
771	u8 rsv[2];
772
773	struct sec_key key[2];
774} __packed;
775
776struct ra_phy {
777	u8 type;
778	u8 flag;
779	u8 stbc;
780	u8 sgi;
781	u8 bw;
782	u8 ldpc;
783	u8 mcs;
784	u8 nss;
785	u8 he_ltf;
786};
787
788struct sta_rec_ra {
789	__le16 tag;
790	__le16 len;
791
792	u8 valid;
793	u8 auto_rate;
794	u8 phy_mode;
795	u8 channel;
796	u8 bw;
797	u8 disable_cck;
798	u8 ht_mcs32;
799	u8 ht_gf;
800	u8 ht_mcs[4];
801	u8 mmps_mode;
802	u8 gband_256;
803	u8 af;
804	u8 auth_wapi_mode;
805	u8 rate_len;
806
807	u8 supp_mode;
808	u8 supp_cck_rate;
809	u8 supp_ofdm_rate;
810	__le32 supp_ht_mcs;
811	__le16 supp_vht_mcs[4];
812
813	u8 op_mode;
814	u8 op_vht_chan_width;
815	u8 op_vht_rx_nss;
816	u8 op_vht_rx_nss_type;
817
818	__le32 sta_status;
819
820	struct ra_phy phy;
821} __packed;
822
823struct sta_rec_ra_fixed {
824	__le16 tag;
825	__le16 len;
826
827	__le32 field;
828	u8 op_mode;
829	u8 op_vht_chan_width;
830	u8 op_vht_rx_nss;
831	u8 op_vht_rx_nss_type;
832
833	struct ra_phy phy;
834
835	u8 spe_en;
836	u8 short_preamble;
837	u8 is_5g;
838	u8 mmps_mode;
839} __packed;
840
841#define RATE_PARAM_FIXED		3
842#define RATE_PARAM_AUTO			20
843#define RATE_CFG_MCS			GENMASK(3, 0)
844#define RATE_CFG_NSS			GENMASK(7, 4)
845#define RATE_CFG_GI			GENMASK(11, 8)
846#define RATE_CFG_BW			GENMASK(15, 12)
847#define RATE_CFG_STBC			GENMASK(19, 16)
848#define RATE_CFG_LDPC			GENMASK(23, 20)
849#define RATE_CFG_PHY_TYPE		GENMASK(27, 24)
850
851struct sta_rec_bf {
852	__le16 tag;
853	__le16 len;
854
855	__le16 pfmu;		/* 0xffff: no access right for PFMU */
856	bool su_mu;		/* 0: SU, 1: MU */
857	u8 bf_cap;		/* 0: iBF, 1: eBF */
858	u8 sounding_phy;	/* 0: legacy, 1: OFDM, 2: HT, 4: VHT */
859	u8 ndpa_rate;
860	u8 ndp_rate;
861	u8 rept_poll_rate;
862	u8 tx_mode;		/* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */
863	u8 nc;
864	u8 nr;
865	u8 bw;			/* 0: 20M, 1: 40M, 2: 80M, 3: 160M */
866
867	u8 mem_total;
868	u8 mem_20m;
869	struct {
870		u8 row;
871		u8 col: 6, row_msb: 2;
872	} mem[4];
873
874	__le16 smart_ant;
875	u8 se_idx;
876	u8 auto_sounding;	/* b7: low traffic indicator
877				 * b6: Stop sounding for this entry
878				 * b5 ~ b0: postpone sounding
879				 */
880	u8 ibf_timeout;
881	u8 ibf_dbw;
882	u8 ibf_ncol;
883	u8 ibf_nrow;
884	u8 nr_bw160;
885	u8 nc_bw160;
886	u8 ru_start_idx;
887	u8 ru_end_idx;
888
889	bool trigger_su;
890	bool trigger_mu;
891	bool ng16_su;
892	bool ng16_mu;
893	bool codebook42_su;
894	bool codebook75_mu;
895
896	u8 he_ltf;
897	u8 rsv[2];
898} __packed;
899
900struct sta_rec_bfee {
901	__le16 tag;
902	__le16 len;
903	bool fb_identity_matrix;	/* 1: feedback identity matrix */
904	bool ignore_feedback;		/* 1: ignore */
905	u8 rsv[2];
906} __packed;
907
908enum {
909	STA_REC_BASIC,
910	STA_REC_RA,
911	STA_REC_RA_CMM_INFO,
912	STA_REC_RA_UPDATE,
913	STA_REC_BF,
914	STA_REC_AMSDU,
915	STA_REC_BA,
916	STA_REC_RED,		/* not used */
917	STA_REC_TX_PROC,	/* for hdr trans and CSO in CR4 */
918	STA_REC_HT,
919	STA_REC_VHT,
920	STA_REC_APPS,
921	STA_REC_KEY,
922	STA_REC_WTBL,
923	STA_REC_HE,
924	STA_REC_HW_AMSDU,
925	STA_REC_WTBL_AADOM,
926	STA_REC_KEY_V2,
927	STA_REC_MURU,
928	STA_REC_MUEDCA,
929	STA_REC_BFEE,
930	STA_REC_MAX_NUM
931};
932
933enum mt7915_cipher_type {
934	MT_CIPHER_NONE,
935	MT_CIPHER_WEP40,
936	MT_CIPHER_WEP104,
937	MT_CIPHER_WEP128,
938	MT_CIPHER_TKIP,
939	MT_CIPHER_AES_CCMP,
940	MT_CIPHER_CCMP_256,
941	MT_CIPHER_GCMP,
942	MT_CIPHER_GCMP_256,
943	MT_CIPHER_WAPI,
944	MT_CIPHER_BIP_CMAC_128,
945};
946
947enum {
948	CH_SWITCH_NORMAL = 0,
949	CH_SWITCH_SCAN = 3,
950	CH_SWITCH_MCC = 4,
951	CH_SWITCH_DFS = 5,
952	CH_SWITCH_BACKGROUND_SCAN_START = 6,
953	CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7,
954	CH_SWITCH_BACKGROUND_SCAN_STOP = 8,
955	CH_SWITCH_SCAN_BYPASS_DPD = 9
956};
957
958enum {
959	THERMAL_SENSOR_TEMP_QUERY,
960	THERMAL_SENSOR_MANUAL_CTRL,
961	THERMAL_SENSOR_INFO_QUERY,
962	THERMAL_SENSOR_TASK_CTRL,
963};
964
965enum {
966	MT_EBF = BIT(0),	/* explicit beamforming */
967	MT_IBF = BIT(1)		/* implicit beamforming */
968};
969
970#define MT7915_WTBL_UPDATE_MAX_SIZE	(sizeof(struct wtbl_req_hdr) +	\
971					 sizeof(struct wtbl_generic) +	\
972					 sizeof(struct wtbl_rx) +	\
973					 sizeof(struct wtbl_ht) +	\
974					 sizeof(struct wtbl_vht) +	\
975					 sizeof(struct wtbl_ba) +	\
976					 sizeof(struct wtbl_smps))
977
978#define MT7915_STA_UPDATE_MAX_SIZE	(sizeof(struct sta_req_hdr) +	\
979					 sizeof(struct sta_rec_basic) +	\
980					 sizeof(struct sta_rec_ht) +	\
981					 sizeof(struct sta_rec_he) +	\
982					 sizeof(struct sta_rec_ba) +	\
983					 sizeof(struct sta_rec_vht) +	\
984					 sizeof(struct sta_rec_uapsd) + \
985					 sizeof(struct sta_rec_amsdu) +	\
986					 sizeof(struct tlv) +		\
987					 MT7915_WTBL_UPDATE_MAX_SIZE)
988
989#define MT7915_WTBL_UPDATE_BA_SIZE	(sizeof(struct wtbl_req_hdr) +	\
990					 sizeof(struct wtbl_ba))
991
992#define MT7915_BSS_UPDATE_MAX_SIZE	(sizeof(struct sta_req_hdr) +	\
993					 sizeof(struct bss_info_omac) +	\
994					 sizeof(struct bss_info_basic) +\
995					 sizeof(struct bss_info_rf_ch) +\
996					 sizeof(struct bss_info_ra) +	\
997					 sizeof(struct bss_info_hw_amsdu) +\
998					 sizeof(struct bss_info_he) +	\
999					 sizeof(struct bss_info_bmc_rate) +\
1000					 sizeof(struct bss_info_ext_bss) +\
1001					 sizeof(struct bss_info_sync_mode))
1002
1003#define MT7915_BEACON_UPDATE_SIZE	(sizeof(struct sta_req_hdr) +	\
1004					 sizeof(struct bss_info_bcn_csa) + \
1005					 sizeof(struct bss_info_bcn_bcc) + \
1006					 sizeof(struct bss_info_bcn_mbss) + \
1007					 sizeof(struct bss_info_bcn_cont))
1008
1009#define PHY_MODE_A			BIT(0)
1010#define PHY_MODE_B			BIT(1)
1011#define PHY_MODE_G			BIT(2)
1012#define PHY_MODE_GN			BIT(3)
1013#define PHY_MODE_AN			BIT(4)
1014#define PHY_MODE_AC			BIT(5)
1015#define PHY_MODE_AX_24G			BIT(6)
1016#define PHY_MODE_AX_5G			BIT(7)
1017#define PHY_MODE_AX_6G			BIT(8)
1018
1019#define MODE_CCK			BIT(0)
1020#define MODE_OFDM			BIT(1)
1021#define MODE_HT				BIT(2)
1022#define MODE_VHT			BIT(3)
1023#define MODE_HE				BIT(4)
1024
1025#define STA_CAP_WMM			BIT(0)
1026#define STA_CAP_SGI_20			BIT(4)
1027#define STA_CAP_SGI_40			BIT(5)
1028#define STA_CAP_TX_STBC			BIT(6)
1029#define STA_CAP_RX_STBC			BIT(7)
1030#define STA_CAP_VHT_SGI_80		BIT(16)
1031#define STA_CAP_VHT_SGI_160		BIT(17)
1032#define STA_CAP_VHT_TX_STBC		BIT(18)
1033#define STA_CAP_VHT_RX_STBC		BIT(19)
1034#define STA_CAP_VHT_LDPC		BIT(23)
1035#define STA_CAP_LDPC			BIT(24)
1036#define STA_CAP_HT			BIT(26)
1037#define STA_CAP_VHT			BIT(27)
1038#define STA_CAP_HE			BIT(28)
1039
1040/* HE MAC */
1041#define STA_REC_HE_CAP_HTC			BIT(0)
1042#define STA_REC_HE_CAP_BQR			BIT(1)
1043#define STA_REC_HE_CAP_BSR			BIT(2)
1044#define STA_REC_HE_CAP_OM			BIT(3)
1045#define STA_REC_HE_CAP_AMSDU_IN_AMPDU		BIT(4)
1046/* HE PHY */
1047#define STA_REC_HE_CAP_DUAL_BAND		BIT(5)
1048#define STA_REC_HE_CAP_LDPC			BIT(6)
1049#define STA_REC_HE_CAP_TRIG_CQI_FK		BIT(7)
1050#define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE	BIT(8)
1051/* STBC */
1052#define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC	BIT(9)
1053#define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC	BIT(10)
1054#define STA_REC_HE_CAP_GT_80M_TX_STBC		BIT(11)
1055#define STA_REC_HE_CAP_GT_80M_RX_STBC		BIT(12)
1056/* GI */
1057#define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI	BIT(13)
1058#define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI	BIT(14)
1059#define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI	BIT(15)
1060#define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI	BIT(16)
1061#define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI	BIT(17)
1062/* 242 TONE */
1063#define STA_REC_HE_CAP_BW20_RU242_SUPPORT	BIT(18)
1064#define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242	BIT(19)
1065#define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242	BIT(20)
1066
1067#endif
1068