1// SPDX-License-Identifier: ISC
2/*
3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
4 * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
5 */
6
7#include "mt76x2.h"
8#include "eeprom.h"
9#include "../mt76x02_phy.h"
10
11static void
12mt76x2_set_wlan_state(struct mt76x02_dev *dev, bool enable)
13{
14	u32 val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
15
16	if (enable)
17		val |= (MT_WLAN_FUN_CTRL_WLAN_EN |
18			MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
19	else
20		val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN |
21			 MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
22
23	mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
24	udelay(20);
25}
26
27void mt76x2_reset_wlan(struct mt76x02_dev *dev, bool enable)
28{
29	u32 val;
30
31	if (!enable)
32		goto out;
33
34	val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
35
36	val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL;
37
38	if (val & MT_WLAN_FUN_CTRL_WLAN_EN) {
39		val |= MT_WLAN_FUN_CTRL_WLAN_RESET_RF;
40		mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
41		udelay(20);
42
43		val &= ~MT_WLAN_FUN_CTRL_WLAN_RESET_RF;
44	}
45
46	mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
47	udelay(20);
48
49out:
50	mt76x2_set_wlan_state(dev, enable);
51}
52EXPORT_SYMBOL_GPL(mt76x2_reset_wlan);
53
54void mt76_write_mac_initvals(struct mt76x02_dev *dev)
55{
56#define DEFAULT_PROT_CFG_CCK				\
57	(FIELD_PREP(MT_PROT_CFG_RATE, 0x3) |		\
58	 FIELD_PREP(MT_PROT_CFG_NAV, 1) |		\
59	 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) |	\
60	 MT_PROT_CFG_RTS_THRESH)
61
62#define DEFAULT_PROT_CFG_OFDM				\
63	(FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) |		\
64	 FIELD_PREP(MT_PROT_CFG_NAV, 1) |			\
65	 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) |	\
66	 MT_PROT_CFG_RTS_THRESH)
67
68#define DEFAULT_PROT_CFG_20				\
69	(FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) |		\
70	 FIELD_PREP(MT_PROT_CFG_CTRL, 1) |		\
71	 FIELD_PREP(MT_PROT_CFG_NAV, 1) |			\
72	 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x17))
73
74#define DEFAULT_PROT_CFG_40				\
75	(FIELD_PREP(MT_PROT_CFG_RATE, 0x2084) |		\
76	 FIELD_PREP(MT_PROT_CFG_CTRL, 1) |		\
77	 FIELD_PREP(MT_PROT_CFG_NAV, 1) |			\
78	 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f))
79
80	static const struct mt76_reg_pair vals[] = {
81		/* Copied from MediaTek reference source */
82		{ MT_PBF_SYS_CTRL,		0x00080c00 },
83		{ MT_PBF_CFG,			0x1efebcff },
84		{ MT_FCE_PSE_CTRL,		0x00000001 },
85		{ MT_MAC_SYS_CTRL,		0x00000000 },
86		{ MT_MAX_LEN_CFG,		0x003e3f00 },
87		{ MT_AMPDU_MAX_LEN_20M1S,	0xaaa99887 },
88		{ MT_AMPDU_MAX_LEN_20M2S,	0x000000aa },
89		{ MT_XIFS_TIME_CFG,		0x33a40d0a },
90		{ MT_BKOFF_SLOT_CFG,		0x00000209 },
91		{ MT_TBTT_SYNC_CFG,		0x00422010 },
92		{ MT_PWR_PIN_CFG,		0x00000000 },
93		{ 0x1238,			0x001700c8 },
94		{ MT_TX_SW_CFG0,		0x00101001 },
95		{ MT_TX_SW_CFG1,		0x00010000 },
96		{ MT_TX_SW_CFG2,		0x00000000 },
97		{ MT_TXOP_CTRL_CFG,		0x0400583f },
98		{ MT_TX_RTS_CFG,		0x00ffff20 },
99		{ MT_TX_TIMEOUT_CFG,		0x000a2290 },
100		{ MT_TX_RETRY_CFG,		0x47f01f0f },
101		{ MT_EXP_ACK_TIME,		0x002c00dc },
102		{ MT_TX_PROT_CFG6,		0xe3f42004 },
103		{ MT_TX_PROT_CFG7,		0xe3f42084 },
104		{ MT_TX_PROT_CFG8,		0xe3f42104 },
105		{ MT_PIFS_TX_CFG,		0x00060fff },
106		{ MT_RX_FILTR_CFG,		0x00015f97 },
107		{ MT_LEGACY_BASIC_RATE,		0x0000017f },
108		{ MT_HT_BASIC_RATE,		0x00004003 },
109		{ MT_PN_PAD_MODE,		0x00000003 },
110		{ MT_TXOP_HLDR_ET,		0x00000002 },
111		{ 0xa44,			0x00000000 },
112		{ MT_HEADER_TRANS_CTRL_REG,	0x00000000 },
113		{ MT_TSO_CTRL,			0x00000000 },
114		{ MT_AUX_CLK_CFG,		0x00000000 },
115		{ MT_DACCLK_EN_DLY_CFG,		0x00000000 },
116		{ MT_TX_ALC_CFG_4,		0x00000000 },
117		{ MT_TX_ALC_VGA3,		0x00000000 },
118		{ MT_TX_PWR_CFG_0,		0x3a3a3a3a },
119		{ MT_TX_PWR_CFG_1,		0x3a3a3a3a },
120		{ MT_TX_PWR_CFG_2,		0x3a3a3a3a },
121		{ MT_TX_PWR_CFG_3,		0x3a3a3a3a },
122		{ MT_TX_PWR_CFG_4,		0x3a3a3a3a },
123		{ MT_TX_PWR_CFG_7,		0x3a3a3a3a },
124		{ MT_TX_PWR_CFG_8,		0x0000003a },
125		{ MT_TX_PWR_CFG_9,		0x0000003a },
126		{ MT_EFUSE_CTRL,		0x0000d000 },
127		{ MT_PAUSE_ENABLE_CONTROL1,	0x0000000a },
128		{ MT_FCE_WLAN_FLOW_CONTROL1,	0x60401c18 },
129		{ MT_WPDMA_DELAY_INT_CFG,	0x94ff0000 },
130		{ MT_TX_SW_CFG3,		0x00000004 },
131		{ MT_HT_FBK_TO_LEGACY,		0x00001818 },
132		{ MT_VHT_HT_FBK_CFG1,		0xedcba980 },
133		{ MT_PROT_AUTO_TX_CFG,		0x00830083 },
134		{ MT_HT_CTRL_CFG,		0x000001ff },
135		{ MT_TX_LINK_CFG,		0x00001020 },
136	};
137	struct mt76_reg_pair prot_vals[] = {
138		{ MT_CCK_PROT_CFG,		DEFAULT_PROT_CFG_CCK },
139		{ MT_OFDM_PROT_CFG,		DEFAULT_PROT_CFG_OFDM },
140		{ MT_MM20_PROT_CFG,		DEFAULT_PROT_CFG_20 },
141		{ MT_MM40_PROT_CFG,		DEFAULT_PROT_CFG_40 },
142		{ MT_GF20_PROT_CFG,		DEFAULT_PROT_CFG_20 },
143		{ MT_GF40_PROT_CFG,		DEFAULT_PROT_CFG_40 },
144	};
145
146	mt76_wr_rp(dev, 0, vals, ARRAY_SIZE(vals));
147	mt76_wr_rp(dev, 0, prot_vals, ARRAY_SIZE(prot_vals));
148}
149EXPORT_SYMBOL_GPL(mt76_write_mac_initvals);
150
151void mt76x2_init_txpower(struct mt76x02_dev *dev,
152			 struct ieee80211_supported_band *sband)
153{
154	struct ieee80211_channel *chan;
155	struct mt76x2_tx_power_info txp;
156	struct mt76_rate_power t = {};
157	int i;
158
159	for (i = 0; i < sband->n_channels; i++) {
160		chan = &sband->channels[i];
161
162		mt76x2_get_power_info(dev, &txp, chan);
163		mt76x2_get_rate_power(dev, &t, chan);
164
165		chan->orig_mpwr = mt76x02_get_max_rate_power(&t) +
166				  txp.target_power;
167		chan->orig_mpwr = DIV_ROUND_UP(chan->orig_mpwr, 2);
168
169		/* convert to combined output power on 2x2 devices */
170		chan->orig_mpwr += 3;
171		chan->max_power = min_t(int, chan->max_reg_power,
172					chan->orig_mpwr);
173	}
174}
175EXPORT_SYMBOL_GPL(mt76x2_init_txpower);
176